JP5473398B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device formed using silicon carbide (SiC) and a method for manufacturing the same, and more particularly, to a device structure that stably generates avalanche breakdown at a pn junction, and ion implantation for forming the pn junction. It is about technology.

  In recent years, there has been an increasing demand for improving the characteristics of power devices from the viewpoint of energy saving, and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), pn junction diodes, and Schottkys formed using SiC as the next generation high voltage and low loss switching elements. Barrier diodes are promising.

  Generally, these elements have a p-type region selectively formed in an n-type region, and a pn junction is formed therebetween. The p-type region is formed by ion implantation of an element serving as an acceptor and subsequent activation heat treatment. Further, a technique is known in which a termination structure in which the doping concentration is gradually reduced is provided at the termination portion of the p-type region, and the electric field concentration at that portion is reduced (for example, Patent Document 1).

  A technique for obtaining a desired doping concentration distribution by performing ion implantation from two directions with different implantation angles using a taper-shaped mask with respect to the formation of the breakdown voltage holding region and the channel formation region of the MOSFET. Is known (for example, Patent Document 2).

  Conventionally, as a SiC substrate used for forming a semiconductor element, a substrate whose surface is inclined by a certain angle (off angle) with respect to a crystal plane of a reference plane has been used for controlling crystal polymorphism. However, the off-angle tends to be reduced from the conventional 8 ° to 4 ° by increasing the wafer diameter and improving the crystal growth technique (for example, Patent Document 3).

JP 2000-516767 JP 2004-39744 A Special table 2008-542181 gazette

  In the manufacture of a semiconductor device (SiC device) using a normal Si substrate, when forming a p-type region such as a MOSFET body region, the angle of ion implantation may be considered for the purpose of preventing channeling. It was. However, no consideration has been given to the formation of the termination structure of the p-type region. Therefore, it cannot be said that the device structure is sufficient in that avalanche breakdown is stably generated when a breakdown voltage is applied to a MOSFET or a pn junction diode.

  In particular, in a semiconductor device using a SiC substrate, conventionally, the off-angle of the substrate is large (8 °), and there is no problem of channeling or the like even if ion implantation is performed from a direction perpendicular to the substrate surface. Even in this case, the angle of ion implantation was not considered. In other words, in the manufacture of the conventional SiC device, the influence of the ion implantation angle on the characteristics of the SiC device was small, so there was no need to consider it.

  However, when the off-angle of the SiC substrate is reduced as in recent years, it is considered that the ion implantation angle has a considerable influence on the characteristics of the SiC device. Therefore, if the angle is appropriately controlled, improvement in the characteristics of the SiC device can be expected.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which avalanche breakdown is stably generated at a pn junction when a breakdown voltage is applied, and a method for manufacturing the same. To do.

A semiconductor device according to the present invention includes a first conductivity type drift layer formed on a silicon carbide substrate, and a second conductivity type region selectively formed on the drift layer. A semiconductor device comprising a non-punch-through type semiconductor element in which a depletion layer extending from a pn junction does not penetrate the drift layer when a breakdown voltage is applied to a pn junction at a boundary between a two-conductivity type region and the drift layer The second conductivity type region has a portion with a longer tail at the end of 10 ¹⁵ cm ^{−3 in} the depth direction of the drift layer of the second conductivity type impurity concentration profile than the center portion at the end. It is what.

  According to the present invention, in the pn junction at the boundary between the second conductivity type region of the non-punch through type semiconductor element and the drift layer, the characteristics of the inclined junction strongly appear at the end. Therefore, since the breakdown voltage at the end of the pn junction increases, the avalanche breakdown starts first (at a low voltage) at the center of the pn junction. This stabilizes the avalanche breakdown that occurs at the pn junction.

It is sectional drawing which shows the structure of MOSFET which is a semiconductor device which concerns on this invention. It is a graph which shows the relationship between the doping concentration of the drift layer of the semiconductor device which concerns on this invention, the maximum electric field value, and the depletion layer width. It is sectional drawing which shows another example of a structure of MOSFET which concerns on this invention. It is sectional drawing which shows another example of a structure of MOSFET which concerns on this invention. It is a figure which shows the relationship between the implantation angle and ion concentration distribution in ion implantation to 4H-SiC. 6 is a diagram showing an ion implantation step in Embodiment 1. FIG. 6 is a diagram showing an ion implantation step in Embodiment 1. FIG. 10 is a diagram showing an ion implantation step in Embodiment 2. FIG. 10 is a diagram showing an ion implantation step in Embodiment 2. FIG. FIG. 10 is a diagram illustrating an ion implantation process in a third embodiment. FIG. 10 is a diagram illustrating an ion implantation process in a third embodiment. FIG. 10 is a diagram showing an ion implantation step in a fourth embodiment. FIG. 10 is a diagram showing an ion implantation step in a fourth embodiment. FIG. 10 is a diagram showing a configuration of a diode that is a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing an ion implantation step in a sixth embodiment. FIG. 10 is a diagram showing an ion implantation step in a sixth embodiment. FIG. 10 is a diagram showing an ion implantation step in a seventh embodiment. FIG. 10 is a diagram showing an ion implantation step in a seventh embodiment. FIG. 10 is a diagram illustrating an ion implantation process in an eighth embodiment. FIG. 10 is a diagram illustrating an ion implantation process in an eighth embodiment. FIG. 10 is a diagram showing an ion implantation step in the ninth embodiment. FIG. 10 is a diagram showing an ion implantation step in the ninth embodiment. FIG. 22 is a cross-sectional view showing a configuration of a MOSFET according to the tenth embodiment. FIG. 11 is a cross-sectional view showing a configuration of a diode according to a tenth embodiment.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a MOSFET which is a semiconductor device according to the present invention. Each of the regions between the alternate long and short dash lines in the figure corresponds to a unit region (minimum unit of the MOSFET structure) that functions as a MOSFET. Actually, the structure of the unit region is repeated in the horizontal direction, and is continuous in a comb shape or a polygonal structure. On the other hand, both ends (outside the one-dot chain line) of FIG. 1 show the outer peripheral portion (termination portion) of the MOSFET formation region.

As shown in FIG. 1, the MOSFET is formed on an n-type low-resistance SiC substrate 1 (hereinafter “n-type substrate 1”) and an n-type drift layer 2 thereon. The n-type drift layer 2 is formed by epitaxial growth on the n-type substrate 1 and functions to hold the voltage applied to the MOSFET. The drift layer 2 has a thickness of about 3 to 150 μm and a doping concentration of about 0.5 to 15 × 10 ¹⁵ / cm ³ . In order to obtain a kV class breakdown voltage, the thickness of the n-type drift layer 2 is preferably about 5 to 20 μm, and the doping concentration is preferably about 5 to 15 × 10 ¹⁵ / cm ³ .

  A p-type body layer 3 (the p-type body layer 3 is composed of regions 3a, 3b, and 3c described later) is formed on the n-type drift layer 2, and is near the upper surface in the p-type body layer 3 Then, the n-type source region 4 is formed.

The body region 3 has a layer thickness of about 0.5 to 2 μm and a doping concentration of about 3 to 20 × 10 ¹⁷ / cm ³ , but the doping concentration is low near the surface of the p-type body layer 3 where the channel is formed. It may be made to become. When the doping concentration in the vicinity of the surface is lowered, scattering due to impurities can be reduced, the carrier mobility in the formed channel can be increased, and the on-resistance of the MOSFET can be reduced. The source region 4 has a layer thickness of about 0.3 to 1 μm and a doping concentration of about 5 to 50 × 10 ¹⁸ / cm ³ .

  On the upper surface of the n-type drift layer 2, a gate electrode 8 is disposed via a gate insulating film 7 so as to straddle the n-type drift layer 2, the p-type body layer 3 and the n-type source region 4. . The gate insulating film 7 is formed by patterning an insulating film (silicon oxide film, silicon oxynitride film, etc.) having a thickness of about 10 to 100 nm formed on the n-type drift layer 2. As a method of forming the insulating film, there are a method of thermally oxidizing or nitriding the upper surface of the n-type drift layer 2, a method of depositing a predetermined insulating film on the n-type drift layer 2, or a method using them together. is there. The gate electrode 8 is formed by patterning a polycrystalline silicon film or a metal film formed on the gate insulating film 7.

  The gate electrode 8 is covered with an interlayer insulating film 9. A source electrode 10 connected to the n-type source region 4 and the p-type body layer 3 is disposed next to the gate electrode 8, and the source electrode 10 passes through a contact hole formed in the interlayer insulating film 9. The upper wiring 12 is connected to the interlayer insulating film 9. A drain electrode 11 is provided on the lower surface of the n-type substrate 1. Although illustration is omitted, the interlayer insulating film 9 and the wiring 12 are removed in a part of the region on the gate electrode 8, and the portion becomes a pad portion for connecting the wiring to the gate electrode 8.

In the present embodiment, when the p-type body layer 3 is formed, a channel formation region 3b located under the gate electrode 8, a contact region 3c connected to the source electrode 10, and a region 3a excluding them (hereinafter referred to as “a”). It is divided into three parts (referred to as “body region 3a”) (contact region 3c is formed so as to overlap in body region 3a), and is formed by ion implantation in different steps. N-type source region 4 is formed on top of body region 3a. Note that the contact region 3c may be doped at a high concentration only (for example, about 5 to 50 × 10 ¹⁸ / cm ³ ) only in order to reduce the connection resistance with the source electrode 10.

  Further, in the p-type body layer 3 serving as the outer peripheral portion (termination portion) of the MOSFET formation region, the p-type termination region 5 is formed in the outermost peripheral portion. The p-type termination region 5 is formed in parallel with the p-type body layer 3. A specific method for forming the p-type body layer 3 (body region 3a, channel forming region 3b, contact region 3c), p-type termination region 5 and n-type source region 4 will be described later.

  As shown in FIG. 1, the p-type body layer 3 (in the center of FIG. 1) straddling the unit regions of the two MOSFETs is shared by the two MOSFETs. Therefore, in the p-type body layer 3, the contact region 3c is located at the center, the body region 3a is located outside, and the channel formation regions 3b are located at both ends.

  Further, since the p-type body layer 3 at the terminal end (both ends in FIG. 1) extends over the MOSFET adjacent to the terminal end, the p-type body layer 3 has a contact region 3c at the center and a body region 3a at the outside. However, the channel formation region 3b is located at the end on the MOSFET side, and the p-type termination region 5 is located at the end on the termination side.

  In the MOSFET according to the present invention, when a breakdown voltage is applied to the pn junction at the boundary between the p-type body layer 3 and the n-type drift layer 2, the depletion layer extending from the pn junction does not penetrate the n-type drift layer 2 ( Non-punch-through type which does not reach the bottom surface of the n-type drift layer 2).

The present inventor conducted a device simulation using the impact ionization value of 4H—SiC according to a report by Konstantinov et al. (Materials Science Forum vols. 264-268 (1998) pp. 1211-1214). / Cm ³ ] and the calculation result of the relationship between the electric field maximum value Emax [V / cm] are shown in the graph of FIG. From this result, the relationship of the following formula (1) is obtained.

Emax = 4.69 · 10 ⁴ · N ^0.1082 (1)
The relationship between the depletion layer width d [μm], the electric field maximum value Emax, and the doping concentration N of the drift layer is given by the following formula (2) using the dielectric constant e and the elementary charge q.

d = (e · Emax) / (q · N) (2)
From the equations (1) and (2), the depletion layer width d is given by the following equation (3) using the doping concentration N.

d = 2.507 · 10 ¹⁵ · N ^-0.8918 (3)
Therefore, when the drift layer thickness t [μm] (distance between the lower surface of the p-type body layer 3 and the lower surface of the n-type drift layer 2) satisfies the following formula (4), Become.

t> 2.507 · 10 ¹⁵ · N ^-0.8918 (4)
Although omitted in the configuration of FIG. 1, in the MOSFET according to the present invention, as shown in FIG. 3 or FIG. 4, the n-type source region 4 and the p-type body layer 3 (channel formation region 3 b) are provided below the gate electrode 8. ) And the channel layer 6 over the n-type drift layer 2 may be provided. FIG. 3 shows an example in which the channel layer 6 is formed on the surface of the n-type drift layer 2 by epitaxial growth. FIG. 4 shows the channel layer 6 formed on the surface portion in the n-type drift layer 2 by ion implantation. It is an example.

  The conductivity type of the channel layer 6 may be n-type or p-type, and the configuration of FIG. 3 is desirable to improve the surface roughness of the n-type drift layer 2 caused by the activation heat treatment of ions implanted into the n-type drift layer 2. If the surface roughness is small, the structure shown in FIG. 4 may be used.

  In forming the p-type body layer 3, it is necessary to perform a heat treatment (activation heat treatment) for activating the implanted ion species after ion implantation of the p-type dopant. In the case of adopting the configuration of FIG. In the case of adopting the configuration of FIG. 3, it is performed before the formation of the channel layer 6, but may be performed collectively after the ion implantation process to the n-type drift layer 2 is completed, You may perform for every ion implantation process.

  FIG. 5 is a diagram showing the relationship between the implantation angle and the doping concentration distribution in the ion implantation, and is a result of the process simulation by the present inventor. This simulation is performed with the setting that Al ions are implanted into the (0001) plane of 4H—SiC, and the ion implantation direction is tilted from the direction perpendicular to the (0001) plane to the <11-20> direction. The doping concentration distribution in the depth direction in SiC was calculated. Here, an angle formed by the direction of ion implantation and the direction perpendicular to the (0001) plane is defined as an “implantation angle”.

  Referring to FIG. 5, comparing the case where the implantation angle is 4 ° and the case where the implantation angle is 4 ° with the same implantation energy, the region where the doping concentration is lower is a region (region deeper from the surface of SiC). It can be seen that the doping concentration profile has a tail. Thus, the closer the ion implantation direction is to the direction perpendicular to the crystal plane, the more the doping concentration profile becomes tailed in the depth direction of SiC.

  In the MOSFET having the configuration of FIG. 1, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8, a channel is formed in the channel formation region 3 b of the p-type body layer 3, and between the source electrode 10 and the drain electrode 11. Is conducted, and a current flows between both electrodes (ON state). When the voltage of the gate electrode 8 is lower than the threshold voltage, no channel is formed in the channel formation region 3b, and the current is cut off because the source electrode 10 and the drain electrode 11 are not conductive. State). On the other hand, when a high voltage is applied between the source and the drain, the pn junction between the body region 3 and the drift layer 2 is avalanche breakdown, but the avalanche breakdown is not at the end of the pn junction but at the center. It is desirable to occur at.

  In particular, in the case of a non-punch through type MOSFET, if the concentration profile of the p-type impurity is long in the depth direction of the n-type drift layer 2 at the end of the p-type body layer 3, the avalanche breakdown is stable. Can be generated. The characteristics of the inclined junction strongly appear at the end of the pn junction between the p-type body layer 3 and the n-type drift layer 2, and the breakdown voltage at that portion increases. Avalanche surrender will begin.

  Therefore, in the present embodiment, in the ion implantation process for forming p-type body layer 3 and p-type termination region 5, channel forming region 3 b and p-type termination region 5 serving as end portions of p-type body layer 3, and the central portion The contact region 3c and the body region 3a there between are formed by ion implantation with different tails of the doping concentration profile, whereby the concentration profile of the p-type impurity is increased at the end of the p-type body layer 3. Try to draw a long hem. Here, the ion implantation for forming the body region 3a is “first ion implantation”, the ion implantation for forming the channel forming region 3b and the p-type termination region 5 is “second ion implantation”, and the contact region 3c is formed. The ion implantation for forming is defined as “third ion implantation”.

  As can be seen from FIG. 5, the doping concentration profile of the implanted ions has a longer tail in the depth direction as the angle formed by the implantation direction and the perpendicular to the crystal plane is smaller. Therefore, in order to lengthen the tail of the concentration profile of the p-type impurity at the center of the p-type body layer 3, the second ion implantation is performed with a small inclination from the normal of the crystal plane, and the first and third ions The implantation may be performed with a large inclination from the perpendicular to the crystal plane. As a result, the tailing of the doping concentration profile can be made longer in the channel formation region 3b and the p-type termination region 5, and can be made shorter in the body region 3a and the contact region 3c. However, since the contact region 3c is formed inside the body region 3a, it hardly contributes to the impurity concentration profile in the pn junction portion.

  Subsequently, an ion implantation process for forming the p-type body layer 3 and the p-type termination region 5 of the MOSFET according to the present invention will be specifically described.

  In the following description, the 4H—SiC n-type substrate 1 has a (0001) plane as a reference plane, and the surface is tilted from the (0001) plane in the <11-20> direction by a predetermined off angle. And Each ion implantation is performed by tilting the implantation direction from the direction perpendicular to the (0001) plane (namely, the <0001> direction) from the direction <11-20> by a specific angle. The injection direction is expressed using an angle, and an angle formed in the <11-20> direction from the reference direction (the <0001> direction or the normal direction of the surface of the n-type drift layer 2) is a positive (+) value, The reverse is represented by a negative (-) value (in each drawing, clockwise is a positive angle and counterclockwise is a negative angle).

  Further, as described above, the contact region 3c formed in the body region 3a hardly contributes to the impurity concentration profile of the pn junction portion and is not related to the feature of the present invention. The illustration and description of the region 3c and the third ion implantation are omitted. Even in an actual device structure, the contact region 3c may be omitted if it is not necessary.

  6 and 7 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the first embodiment. FIG. 6A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. As shown in the figure, the off-angle of the n-type substrate 1 used in the present embodiment is 8 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure. In each ion implantation step, a mask is formed on the upper surface of the n-type drift layer 2 in order to selectively implant ions only in a specific region, but the mask is not shown for simplicity.

  First, as shown in FIG. 6B, the first ion implantation for forming the body region 3a is inclined by + 8 ° with respect to the direction (<0001> direction) perpendicular to the surface of the n-type drift layer 2 (the surface of the n-type substrate 1). From the direction). Subsequently, as shown in FIG. 7A, the second ion implantation for forming the channel formation region 3b and the p-type termination region 5 is inclined in a direction tilted by −4 ° with respect to the normal to the surface of the n-type drift layer 2 (<0001). > Direction tilted by + 4 ° with respect to the direction).

  The first and second ion implantations are performed with substantially the same implantation energy and dose amount, respectively. Each of the first and second ion implantations may be performed once, or may be performed in multiple steps (the same applies to the third ion implantation whose description is omitted). In the case of performing the treatment in a large number of times, the implantation energy and the dose may be changed every time as necessary, but in principle, the implantation direction is made constant. The same applies to the following embodiments.

  Thereafter, as shown in FIG. 7B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined by + 8 ° with respect to the <0001> direction). . However, the direction (angle) of this ion implantation may be arbitrary. Of course, when the implantation direction is changed, the impurity concentration profile of the n-type source region 4 changes. However, the relationship with the present invention is weak, and the effect of the present invention is hardly affected.

  When the p-type body layer 3 is formed in this manner, the concentration profile of the p-type impurity in the depth direction of the n-type drift layer 2 in the channel formation region 3b and the p-type termination region 5 rather than the body region 3a. The pull becomes longer. That is, the tail of the concentration profile of the p-type impurity becomes longer at the end of the p-type body layer 3. As a result, the characteristics of the inclined junction appear strongly at the end of the pn junction between the p-type body layer 3 and the n-type drift layer 2, and the breakdown voltage at that portion increases. Avalanche breakdown begins (at low voltage). Therefore, a non-punch through type MOSFET in which avalanche breakdown occurs stably at the pn junction between the p-type body layer 3 and the n-type drift layer 2 is obtained.

  In the above description, the first ion implantation, the second ion implantation, and the ion implantation for forming the n-type source region 4 are performed in this order. However, each ion implantation (the third ion implantation, which is not described) is also performed. The order of (including) is not limited to this, and may be arbitrary. The same applies to the following embodiments.

<Embodiment 2>
8 and 9 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the second embodiment. FIG. 8A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. Similar to the first embodiment, the n-type substrate 1 has an off angle of 8 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 8B, the first ion implantation for forming the body region 3a is inclined by + 8 ° with respect to the direction (<0001> direction) perpendicular to the surface of the n-type drift layer 2 (the surface of the n-type substrate 1). From the direction). Subsequently, as shown in FIG. 9A, the second ion implantation for forming the channel formation region 3b and the p-type termination region 5 is inclined by -12 ° with respect to the normal of the surface of the n-type drift layer 2 (<0001). > Direction inclined by −4 ° with respect to the direction).

  Thereafter, as shown in FIG. 9B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined + 8 ° with respect to the <0001> direction). (This ion implantation may be performed from other directions).

  In the present embodiment, the direction of the second ion implantation is changed with respect to the first embodiment, but the same as in the first embodiment when attention is paid to the magnitude (absolute value) of the inclination from the <0001> direction. (The positive and negative angles have only changed). Therefore, the tailing state of the p-type impurity concentration profile in the p-type body layer 3 of the present embodiment is almost the same as that of the first embodiment. Therefore, as in the first embodiment, the tail of the concentration profile of the p-type impurity becomes longer at the end of the p-type body layer 3, and the avalanche occurs at the pn junction between the p-type body layer 3 and the n-type drift layer 2. A non-punch through type MOSFET in which breakdown occurs stably can be obtained.

  In the first and second ion implantations, even if the angle of the implantation direction with respect to the <0001> direction is changed between positive and negative, the resulting p-type impurity concentration profile of the p-type body layer 3 has a tailing state. Almost unchanged. For this reason, there are a plurality of methods for forming the p-type body layer 3 having substantially the same trailing edge of the p-type impurity concentration profile.

  However, if ion implantation that is excessively inclined from the normal to the surface of the n-type drift layer 2 is used, the object of the shape of the p-type body layer 3 is lost, which may affect the electrical characteristics of the MOSFET. Therefore, when there are a plurality of implantation directions capable of obtaining a desired implantation angle with respect to the <0001> direction, the first and second ion implantation angles should be close to the normal to the surface of the n-type drift layer 2. It is desirable to select (for the same reason, the direction of ion implantation for forming the n-type source region 4 and the contact region 3c (not shown) is also preferably close to the normal to the surface of the n-type drift layer 2).

<Embodiment 3>
10 and 11 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the third embodiment. FIG. 10A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. As shown in the figure, the off-angle of the n-type substrate 1 used in the present embodiment is 4 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 10B, the first ion implantation for forming the body region 3a is performed with respect to the direction (<0001> direction) inclined by + 4 ° with respect to the surface of the n-type drift layer 2 (surface of the n-type substrate 1). + 8 ° tilted direction). Subsequently, as shown in FIG. 11A, the second ion implantation for forming the channel formation region 3b and the p-type termination region 5 is performed in a direction perpendicular to the surface of the n-type drift layer 2 (+ 4 ° with respect to the <0001> direction). From the tilted direction.

  Thereafter, as shown in FIG. 11B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined by + 4 ° with respect to the <0001> direction). . However, the direction (angle) of this ion implantation may be arbitrary.

  When the p-type body layer 3 is formed in this manner, the concentration profile of the p-type impurity in the depth direction of the n-type drift layer 2 in the channel formation region 3b and the p-type termination region 5 rather than the body region 3a. The pull becomes longer. In other words, the tail of the concentration profile of the p-type impurity becomes longer at the end of the p-type body layer 3, and the avalanche breakdown occurs stably at the pn junction between the p-type body layer 3 and the n-type drift layer 2. A punch-through type MOSFET is obtained.

<Embodiment 4>
12 and 13 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the fourth embodiment. FIG. 12A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. Similar to the third embodiment, the off-angle of the n-type substrate 1 is 4 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 12B, the first ion implantation for forming the body region 3a is performed in a direction (<0001> direction) inclined by −12 ° with respect to the surface of the n-type drift layer 2 (the surface of the n-type substrate 1). (In a direction tilted by −8 °). Subsequently, as shown in FIG. 13A, the second ion implantation for forming the channel formation region 3b and the p-type termination region 5 is performed in a direction perpendicular to the surface of the n-type drift layer 2 (+ 4 ° with respect to the <0001> direction). From the tilted direction.

  Thereafter, as shown in FIG. 13B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined + 4 ° with respect to the <0001> direction). (This ion implantation may be performed from other directions).

  In the present embodiment, the second ion implantation direction is changed with respect to the third embodiment. However, when attention is paid to the magnitude (absolute value) of the inclination from the <0001> direction, the same as in the third embodiment. (The positive and negative angles have only changed). Therefore, the tailing state of the p-type impurity concentration profile in the p-type body layer 3 of the present embodiment is almost the same as that of the third embodiment.

  However, when there are a plurality of implantation directions capable of obtaining a desired implantation angle with respect to the <0001> direction, the first and second ion implantation angles should be close to the perpendicular to the surface of the n-type drift layer 2. It is desirable to select.

<Embodiment 5>
Embodiment 5 shows an example in which the present invention is applied to a diode element. FIG. 14 is a configuration diagram of a diode element which is a semiconductor device according to the fifth embodiment.

  The configuration of this diode element is such that the channel formation region 3b, contact region 3c and n-type source region 4 of the p-type body layer 3 are omitted from the configuration of the MOSFET according to the present invention. That is, the p-type body layer 3 serving as the anode of the diode element is composed only of the body region 3a. The central portion of the pn junction between the n-type drift layer 2 and the p-type body layer 3 is an active region of the diode element, and the end of the pn junction is a termination region that is an outer peripheral portion of the active region. . A p-type termination region 5 is provided at the end of the pn junction, that is, the outer periphery of the p-type body layer 3.

  Except for not forming the channel formation region 3b and the contact region 3c, the manufacturing method of the p-type body layer 3 of this diode element is the same as that of the MOSFET of the first to fourth embodiments.

  In the diode element of the present embodiment, the tail of the p-type impurity concentration profile is longer at the end (p-type termination region 5) of the p-type body layer 3 serving as the anode than at the center (body region 3a). Become. Therefore, a non-punch through type diode element in which avalanche breakdown occurs stably at the pn junction between the p-type body layer 3 and the n-type drift layer 2 is obtained.

<Embodiment 6>
15 and 16 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the sixth embodiment. The MOSFET is a part of the body region 3a without dividing the region where the channel of the p-type body layer 3 is formed (corresponding to the channel formation region 3b) with respect to the MOSFET of the first embodiment, without dividing it into other regions. It is different in that it is.

  FIG. 15A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. As shown in the figure, the p-type body layer 3 of the present embodiment is composed only of the body region 3a (the contact region 3c may be provided inside the body region 3a), and the region where the channel is formed (n The upper part of p-type body layer 3 sandwiched between n-type source region 4 and n-type drift layer 2 is a part of body region 3a. On the other hand, in the outer peripheral portion (termination portion) of the MOSFET, the p-type termination region 5 is provided outside the body region 3a as in the first embodiment. Note that the off-angle of the n-type substrate 1 used in the present embodiment is 8 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 15B, the first ion implantation for forming the body region 3a is inclined by + 8 ° with respect to the direction (<0001> direction) perpendicular to the surface of the n-type drift layer 2 (the surface of the n-type substrate 1). From the direction). In the present embodiment, the p-type dopant is also implanted into the region of the p-type body layer 3 where the channel is formed by the first ion implantation. Subsequently, as shown in FIG. 16A, the second ion implantation for forming the p-type termination region 5 is performed with respect to the direction inclined by −4 ° with respect to the normal of the surface of the n-type drift layer 2 (<0001> direction). + 4 ° tilt direction).

  Thereafter, as shown in FIG. 16B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined + 8 ° with respect to the <0001> direction). . However, the direction (angle) of this ion implantation may be arbitrary.

  When the p-type body layer 3 is formed in this manner, the tailing of the p-type impurity concentration profile in the depth direction of the n-type drift layer 2 becomes longer in the p-type termination region 5 than in the body region 3a. That is, the tail of the concentration profile of the p-type impurity becomes longer at the outer end portion of the p-type body layer 3 located in the outer peripheral portion of the MOSFET formation region, and the breakdown voltage at that portion becomes larger. As a result, the avalanche breakdown is started first (at a low voltage) in the central portion of the MOSFET formation region. Therefore, a non-punch through type MOSFET in which avalanche breakdown occurs stably at the pn junction between the p-type body layer 3 and the n-type drift layer 2 is obtained.

<Embodiment 7>
17 and 18 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the seventh embodiment. FIG. 17A shows a state where the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 is completed. Also in the present embodiment, the region where the channel of p-type body layer 3 is formed is a part of body region 3a. The n-type substrate 1 has an off angle of 8 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 17B, the first ion implantation for forming the body region 3a is inclined by + 8 ° with respect to the direction (<0001> direction) perpendicular to the surface of the n-type drift layer 2 (the surface of the n-type substrate 1). From the direction). Subsequently, as shown in FIG. 18A, the second ion implantation for forming the p-type termination region 5 is performed with respect to a direction inclined by −12 ° with respect to the normal of the surface of the n-type drift layer 2 (<0001> direction). -4 ° tilted direction).

  Thereafter, as shown in FIG. 18B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined + 8 ° with respect to the <0001> direction). (This ion implantation may be performed from other directions).

  In the present embodiment, the second ion implantation direction is changed with respect to the sixth embodiment, but the same as in the sixth embodiment when attention is paid to the magnitude (absolute value) of the inclination from the <0001> direction. (The positive and negative angles have only changed). Therefore, the tailing state of the p-type impurity concentration profile in the p-type body layer 3 of the present embodiment is almost the same as that of the sixth embodiment.

  However, when there are a plurality of implantation directions capable of obtaining a desired implantation angle with respect to the <0001> direction, the first and second ion implantation angles should be close to the perpendicular to the surface of the n-type drift layer 2. It is desirable to select.

<Eighth embodiment>
19 and 20 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the eighth embodiment. FIG. 19A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. Also in the present embodiment, the region where the channel of p-type body layer 3 is formed is a part of body region 3a. The n-type substrate 1 has an off angle of 4 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 19B, the first ion implantation for forming the body region 3a is tilted by + 4 ° with respect to the normal of the surface of the n-type drift layer 2 (the surface of the n-type substrate 1) (<0001> direction). From the direction tilted + 8 ° with respect to. Subsequently, as shown in FIG. 20A, the second ion implantation for forming the p-type termination region 5 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined by + 4 ° with respect to the <0001> direction). Do.

  Thereafter, as shown in FIG. 20B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined by + 4 ° with respect to the <0001> direction). . However, the direction (angle) of this ion implantation may be arbitrary.

  When the p-type body layer 3 is formed in this manner, the tailing of the p-type impurity concentration profile in the depth direction of the n-type drift layer 2 becomes longer in the p-type termination region 5 than in the body region 3a. That is, the tailing of the concentration profile of the p-type impurity becomes longer at the outer end of the p-type body layer 3 located in the outer peripheral portion of the MOSFET formation region, and the gap between the p-type body layer 3 and the n-type drift layer 2 is increased. A non-punch through type MOSFET in which avalanche breakdown occurs stably at the pn junction is obtained.

<Embodiment 9>
21 and 22 are diagrams showing an ion implantation step in the MOSFET manufacturing method according to the ninth embodiment. FIG. 21A shows a state in which the ion implantation process for the p-type body layer 3, the p-type termination region 5 and the n-type source region 4 has been completed. Also in the present embodiment, the region where the channel of p-type body layer 3 is formed is a part of body region 3a. The n-type substrate 1 has an off angle of 4 °.

  In the present embodiment, p-type body layer 3, p-type termination region 5 and n-type source region 4 are formed by the following procedure.

  First, as shown in FIG. 21 (b), the first ion implantation for forming the body region 3a is tilted by -12 ° with respect to the normal of the surface of the n-type drift layer 2 (the surface of the n-type substrate 1) (<0001>). From the direction inclined by −8 ° with respect to the direction). Subsequently, as shown in FIG. 22A, the second ion implantation for forming the p-type termination region 5 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined by + 4 ° with respect to the <0001> direction). Do.

  Thereafter, as shown in FIG. 22B, ion implantation for forming the n-type source region 4 is performed from a direction perpendicular to the surface of the n-type drift layer 2 (a direction inclined + 4 ° with respect to the <0001> direction). (This ion implantation may be performed from other directions).

  In the present embodiment, the second ion implantation direction is changed with respect to the eighth embodiment, but the same as in the eighth embodiment when attention is paid to the magnitude (absolute value) of the inclination from the <0001> direction. (The positive and negative angles have only changed). Therefore, the tailing state of the p-type impurity concentration profile in the p-type body layer 3 of the present embodiment is almost the same as that of the eighth embodiment.

  However, when there are a plurality of implantation directions capable of obtaining a desired implantation angle with respect to the <0001> direction, the first and second ion implantation angles should be close to the perpendicular to the surface of the n-type drift layer 2. It is desirable to select.

<Embodiment 10>
FIG. 23 and FIG. 24 are diagrams showing the configuration of the semiconductor device according to the tenth embodiment. FIG. 23 shows the structure of the MOSFET, and FIG. 24 shows the structure of the diode element.

  As shown in FIGS. 23 and 24, in the present embodiment, a second p-type termination region 15 deeper than the p-type termination region 5 is provided in a portion outside the p-type termination region 5. That is, in the present embodiment, the termination structure is a stepwise structure including the p-type termination region 5 and the second termination region 15 deeper than the p-type termination region 5. Thereby, when an avalanche breakdown occurs in the pn junction between the p-type body layer 3 and the n-type drift layer 2, the electric field concentration at the terminal portion can be reduced. The second termination region 15 is formed by ion implantation of a p-type dopant deeper than the p-type termination region 5 in a step different from the ion implantation for forming the p-type body layer 3.

  The second termination region 15 can be provided in any of the MOSFETs or diode elements of the first to ninth embodiments described above. Of course, the avalanche breakdown can be stably produced as in the embodiments.

  In each of the embodiments described above, the n-type substrate 1 having the (0001) plane as a reference plane and the surface inclined by a predetermined off angle in the <11-20> direction from the reference plane is used. Is not limited to this. Even in the case of using a substrate having another crystal plane as a reference plane, in the step of forming an impurity layer that forms a pn junction with the drift layer, ion implantation from a direction in which the angle of the reference plane with respect to the perpendicular is large is used. By forming the central portion and forming the end portion of the impurity layer by ion implantation from a direction with a small angle with respect to the normal to the reference plane, the tail of the impurity concentration profile is longer at the end portion of the impurity layer than at the central portion. A portion can be provided. As a result, a non-punch-through type semiconductor element in which avalanche breakdown occurs stably at the pn junction can be obtained.

  Also, the off-angle of the substrate and the implantation direction (angle) of each ion implantation are just examples, and the application of the present invention is not limited thereto.

  In the above description, a MOSFET having a structure in which the drift layer 2 and the substrate 1 have the same conductivity type has been described. However, the present invention describes an IGBT (Insulated) having a structure in which the drift layer 2 and the substrate 1 have different conductivity types. Gate Bipolar Transistor) is also applicable. For example, if the n-type substrate 1 is replaced with a p-type substrate in the configuration shown in FIG. 1, an IGBT configuration is obtained. In that case, the n-type source region 4 and source electrode 10 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively, and the drain electrode 11 of the MOSFET corresponds to the collector electrode.

  Even in the case of application to IGBT, as in the case of MOSFET, in the step of forming an impurity layer that forms a pn junction with the drift layer, the center of the impurity layer is formed by ion implantation from a direction in which the angle with respect to the normal to the reference plane is large. A portion where the tail of the impurity concentration profile is longer at the end of the impurity layer than at the center by forming the end of the impurity layer by ion implantation from a direction in which the angle with respect to the normal to the reference plane is small Can be provided. Thereby, a non-punch through type IGBT in which avalanche breakdown is stably generated at the pn junction can be obtained.

  1 n-type substrate, 2 n-type drift layer, 3 p-type body layer, 3a body region, 3b channel formation region, 3c contact region, 4 n-type source region, 5 p-type termination region, 7 gate insulating film, 8 gate electrode , 9 Interlayer insulating film, 10 source electrode, 11 drain electrode, 12 wiring, 15 second termination region.

Claims (13)

A drift layer of a first conductivity type formed on a silicon carbide substrate;
A second conductivity type region selectively formed on the drift layer;
A semiconductor device comprising a non-punch-through type semiconductor element in which a depletion layer extending from a pn junction does not penetrate the drift layer when a breakdown voltage is applied to the pn junction at the boundary between the second conductivity type region and the drift layer There,
The second conductivity type region is
A semiconductor device characterized in that the end portion has a portion with a longer tail at 10 ¹⁵ cm ^{−3 in} the depth direction of the drift layer of the second conductivity type impurity concentration profile than the center portion. . The semiconductor element is an IGBT,
The second conductivity type region is a body layer of the IGBT;
An end of the second conductivity type region is a channel formation region of the IGBT.
The semiconductor device according to claim 1. The semiconductor element is an IGBT,
The second conductivity type region is a body layer of the IGBT;
An end portion of the second conductivity type region is a termination region that is an outer peripheral portion of the IGBT formation region.
The semiconductor device according to claim 1. The termination region has a stepped structure with a deep outside.
The semiconductor device according to claim 3. The semiconductor element is a diode element;
The central part of the pn junction is an active region of the diode element,
The end of the pn junction is a termination region that is the outer periphery of the active region
The semiconductor device according to claim 1. The termination region has a stepped structure with a deep outside.
The semiconductor device according to claim 5. Preparing a silicon carbide substrate having a surface inclined by a predetermined off angle from a crystal plane that is a reference plane;
Forming a first conductivity type drift layer on the substrate;
An ion implantation step of selectively forming a second conductivity type region on the drift layer,
The ion implantation step includes
A first ion implantation for forming a region including a central portion of the second conductivity type region;
A second ion implantation for forming an end of the second conductivity type region,
The angle of the first injection direction of the ion implantation forms a perpendicular of the reference plane, by the size Kusuru than the angle which the second injection direction of the ion implantation forms a perpendicular of the reference plane, the second conductive The tailing of the second conductivity type impurity concentration profile at the end of the mold region at the 10 ¹⁵ cm ⁻³ level in the depth direction of the drift layer is more than the tailing at the center of the second conductivity type region. A method of manufacturing a semiconductor device, characterized by being lengthened . The second conductivity type region is an IGBT body layer,
An end of the second conductivity type region is a channel formation region of the IGBT.
A method for manufacturing a semiconductor device according to claim 7. The second conductivity type region is an IGBT body layer,
An end portion of the second conductivity type region is a termination region that is an outer peripheral portion of the IGBT formation region.
A method for manufacturing a semiconductor device according to claim 7. The method further includes forming a second conductivity type region deeper than the termination region by ion implantation in a portion outside the termination region.
A method for manufacturing a semiconductor device according to claim 9. The drift layer and the second conductivity type region constitute a diode element,
The central part of the pn junction between the drift layer and the second conductivity type region is an active region of the diode element,
The end of the pn junction is a termination region that is the outer periphery of the active region
A method for manufacturing a semiconductor device according to claim 7. The method further includes forming a second conductivity type region deeper than the termination region by ion implantation in a portion outside the termination region.
A method for manufacturing a semiconductor device according to claim 11. The ion implantation step includes
Including a step of setting an implantation direction of each ion implantation performed in the ion implantation step,
In the step of setting the injection direction,
When there are a plurality of implantation directions capable of obtaining a desired implantation angle with respect to the normal of the reference surface, the one close to the perpendicular of the upper surface of the drift layer is selected.
The method for manufacturing a semiconductor device according to claim 7.

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