JP5471406B2 - Semiconductor verification apparatus and method - Google Patents

Description

  The present invention relates to a semiconductor verification apparatus and method for verifying a semiconductor device.

  With the progress of semiconductor technology, the degree of integration of semiconductor devices (logical LSI (Large Scale Integrated circuit)) has been improved year by year, and it has become possible to mount a large-scale system on one chip. For this reason, the manufacturing cost of the semiconductor device becomes extremely expensive, and it takes a lot of time to manufacture the semiconductor device. Therefore, it is important to perform sufficient verification before manufacturing.

  Verification of semiconductor devices is performed at various stages of design. The design process includes many stages from an abstract level in the initial design to a detailed manufacturing level in the final stage, and handles logical information corresponding to each level. For example, abstract level logical information that determines the degree of input / output relation is handled in the initial design stage, functional level logical information that determines the function of each logic unit is handled in the functional design stage, and logical structure is handled in the final detailed design stage. Handles structure-level logical information that establishes In general, the above-described logic information at various design stages can be expressed using various hardware description languages (SystemC, SystemVerilog, Verilog-HDL, VHDL, etc.).

  As a logic verification method for a semiconductor device or a system using a plurality of semiconductor devices, there are a method using a software simulator, a method using a hardware emulator, and a method using an actual semiconductor device.

  Since the software simulator processes logical information described in a hardware description language according to a program, it can be used in various design stages. Further, since the circuit operation can be simulated according to the program, it has an advantage that the values of all variables in the hardware description language can be easily observed.

  On the other hand, a logic verification method using an actual semiconductor device or hardware emulator can execute logic operations faster than a software simulator by using hardware. As the hardware emulator, for example, an FPGA (Field Programmable Gate Array) or an FPID (Field Programmable Interconnect Device) that can configure a circuit to be verified by program control is used.

  However, in general semiconductor devices and hardware emulators, it is difficult to observe all signals due to cost and hardware restrictions, and it is difficult to analyze when a malfunction occurs in circuit operation. is there.

  As a technique for solving such a problem, for example, in Patent Document 1 and Patent Document 2, a function called read back included in an FPGA is controlled by using JTAG (IEEE1149.1). A method of reading a value of an arbitrary storage element mounted on an FPGA without requiring hardware support is disclosed. By using such an FPGA as a hardware emulator, restrictions on observable signals can be reduced.

JP 2005-174349 A Japanese Patent Application No. 2006-553063

  As described above, Patent Document 1 and Patent Document 2 control an FPGA used as a hardware emulator by using a circuit corresponding to JTAG (IEEE1149.1) included in the FPGA, thereby controlling the internal of the FPGA. A method for reading a value of a storage element is disclosed.

  However, JTAG employs a serial communication system so that a semiconductor device can be verified with a small number of test terminals, and further controls the semiconductor device using the small number of test terminals. There is a problem that the number of control procedures until the wear emulator is set to a predetermined state increases, and it takes a long time to acquire a value of a required storage element.

  For example, when using a Virtex-4 FPGA manufactured by Xilinx, Inc. as a hardware emulator, to read the value of a storage element in the FPGA, first shut down the FPGA (by inputting the JSHUTDOWN command to the FPGA), and then It is necessary to input a command for reading the value of the storage element, then supply a clock to the FPGA to read the value of the storage element, and finally start the FPGA (input a JSTART command to the FPGA). Therefore, when reading the values of a plurality of memory elements from the FPGA, it is necessary to repeat the above control procedure a plurality of times, and the time required to read the values of the memory elements from the FPGA becomes long.

  In particular, a general hardware emulator receives an instruction input from a user and starts a read operation from a storage element designated by the user. Therefore, a value of a required storage element is output after the user inputs an instruction. If it takes a long time, it will be difficult to analyze the verification target circuit built in the hardware emulator. For example, when you want to display the signal waveform by acquiring the value of the required storage element for each clock cycle supplied to the semiconductor device, or when reading multiple data from a predetermined range of memory area, more time is required. Therefore, this problem becomes remarkable.

  The present invention has been made to solve the above-described problems of the background art, and can read out the value of a memory element included in a semiconductor device or hardware emulator to be verified at a higher speed than the background art. An object is to provide a semiconductor verification apparatus and method.

In order to achieve the above object, a semiconductor verification apparatus of the present invention is a semiconductor verification apparatus using the semiconductor device capable of identifying a plurality of memory elements included in the semiconductor device by a first number and a second number,
Based on the number of frames indicating the number of the first number and said storage element that consists of a frame specified by the first number, the external value of the memory element corresponding to the number of said consecutive frames from the first number and read out unit you output to,
A method of reading a value of the storage element to be observed based on a number database indicating the first number and the second number for each storage element and an observation signal list designating the storage element to be observed A control information calculation unit for creating control information to be determined;
Based on the control information, a central control unit that acquires the value of each storage element specified in the observation signal list from the reading unit;
Have
The control information calculation unit
When the storage elements included in the observation signal list are classified as entries having the same first number and all entries are arranged in ascending or descending order, the time required to process one entry alone and the setting target The total of N-1 entries following the frame and the time for continuously processing N entries are set as P, and a total of N entries consisting of the setting target frame and the N-1 entries following this are continuously processed. Where Q is Q, the largest N satisfying P <Q is determined, N-1 is set as the number of frames to be set,
The central control unit
A value of the storage element included in the observation signal list is read from the reading unit in units of the number of frames.

On the other hand, the semiconductor verification method of the present invention is a semiconductor verification method using the semiconductor device capable of identifying a plurality of memory elements included in the semiconductor device by a first number and a second number,
Based on the number of frames indicating the number of the first number and said storage element that consists of a frame specified by the first number, the external value of the memory element corresponding to the number of said consecutive frames from the first number and read out unit you output to,
A method of reading a value of the storage element to be observed based on a number database indicating the first number and the second number for each storage element and an observation signal list designating the storage element to be observed A control information calculation unit for creating control information to be determined;
Based on the control information, a central control unit that acquires the value of each storage element specified in the observation signal list from the reading unit;
With
The control information calculation unit is
When the storage elements included in the observation signal list are classified as entries having the same first number and all entries are arranged in ascending or descending order, the time required to process one entry alone and the setting target The total of N-1 entries following the frame and the time for continuously processing N entries are set as P, and a total of N entries consisting of the setting target frame and the N-1 entries following this are continuously processed. Where Q is Q, the largest N satisfying P <Q is determined, N-1 is set as the number of frames to be set,
The central control unit is
In this method, the value of the storage element included in the observation signal list is read from the reading unit in units of the number of frames.

  According to the present invention, the value of a memory element included in a semiconductor device or hardware emulator to be verified can be read faster than the background art.

FIG. 1 is a block diagram illustrating a configuration example of the semiconductor verification apparatus according to the present embodiment. FIG. 2 is a table diagram showing an example of information for identifying a memory element included in the semiconductor device shown in FIG. FIG. 3 is a schematic diagram showing a specific example of information for identifying a memory element included in the semiconductor device shown in FIG. FIG. 4 is a table showing an example of read unit control information included in the overall control unit shown in FIG. FIG. 5 is a block diagram showing a configuration example of the semiconductor device shown in FIG. FIG. 6 is a block diagram illustrating a configuration example of the device control unit illustrated in FIG. FIG. 7 is a timing chart illustrating an operation example of the device control unit illustrated in FIG. 6. FIG. FIG. 8 is a table showing an example of an observation signal list provided in the overall control unit shown in FIG. FIG. 9 is a flowchart illustrating an example of a processing procedure of a control information calculation unit included in the overall control unit illustrated in FIG. FIG. 10 is a table showing an example of control information provided in the overall control unit shown in FIG. FIG. 11 is a flowchart illustrating an example of a processing procedure of the central control unit included in the overall control unit illustrated in FIG. 1.

  Next, the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the semiconductor verification apparatus according to the present embodiment supplies a clock to or supplies a device control unit 110 that reads a value of a storage element from a semiconductor device 100 to be verified. The clock control unit 140 to be stopped and the overall control unit 120 for controlling the operation of the device control unit 110 and the clock control unit 140 are provided.

  The overall control unit 120 can be realized by, for example, a computer including a CPU or DSP that executes required processing according to a program, a storage device that stores information, and a user I / F. Further, the device control unit 110 can be realized by, for example, an FPGA or FPID, or an LSI having a logic circuit or a memory. The clock control unit 140 can be realized by the computer, LSI, or the like. The function of the clock control unit 140 may be included in the overall control unit 120 or the device control unit 110.

  The clock control unit 140 supplies a clock to the semiconductor device 100 according to an instruction from the overall control unit 120, or stops supplying the clock.

  The semiconductor device 100 is a semiconductor device or hardware emulator to be verified that operates in synchronization with a clock supplied from the clock control unit 140, and a plurality of storage elements that can be uniquely identified by a first number and a second number It has. The memory element included in the semiconductor device 100 refers to a flip-flop circuit, a latch circuit, a memory, a register, or the like. The semiconductor device 100 also includes a reading unit 101 for enabling reading of the value of the storage element via the device control unit 110. In the present embodiment, since data is transmitted and received between the reading unit 101 and the device control unit using a serial signal, the reading unit 101 and the device control unit 110 have P / S conversion for converting parallel data into a serial signal. A circuit (not shown) and an S / P conversion circuit (not shown) for converting a serial signal into parallel data are provided.

  Hereinafter, the value of one or a plurality of storage elements designated by the first number is defined as one frame. For example, when the first number and the second number are assigned to each storage element as shown in FIG. 2, one frame is constituted by the values of the storage elements A and D specified by the first number 0x1024. One frame is composed of the value of the storage element B specified by the first number 0x0384, and one frame is composed of the value of the storage element C specified by the first number 0x2578. Information for identifying all the memory elements included in the semiconductor device 100 as shown in FIG. 2 is stored in a number database 124 described later, which is included in the overall control unit 120.

  For example, when the semiconductor device 100 is a hardware emulator and the Xilinx Corp. Virtex-4 FPGA is used as the hardware emulator, information for identifying each storage element as shown in FIG. 2 is stored in the Logic Location File. Therefore, the number database 124 may be constructed using the file. The Logic Location File of the Virtex-4 FPGA is described in the chapter 8 of “Virtex-4 Configuration Guide” (hereinafter referred to as Non-Patent Document 1) issued by Xilinx, USA, and FIG. 8-8.

  FIG. 3 is a diagram showing a part of the Logic Location File described in the Virtex-4 Configuration Guide. The third column in FIG. 3 corresponds to the first number (Frame Address), and the fourth column corresponds to the second number (Frame Offset). The seventh column in FIG. 3 is a name assigned to the storage element.

  When reading the value of the storage element from the semiconductor device 100 via the reading unit 101, the overall control unit 120 specifies the reading unit control information 125 together with the first number and the number of frames. The read unit control information 125 is information indicating a control command or the like for reading the value of the storage element from the semiconductor device 100 corresponding to the type of the semiconductor device 100. FIG. 4 is a table showing an example of the reading unit control information.

  A “device stop instruction” shown in FIG. 4 is a command for stopping the operation of the semiconductor device 100. The “first number instruction” is a command for inputting a first number to the reading unit 101. The “frame number designation command” shown in FIG. 4 is a command for designating the number of frames to be read continuously. The “read command” is a command for causing the read unit 101 to output the value of the storage element corresponding to the first number designated by the “first number command”. The “device start command” is a command for returning the semiconductor device 100 to the operating state.

  For example, when the semiconductor device 100 is a hardware emulator, and the above Xilinx Virtex-4 FPGA is used as the hardware emulator, the device stop instruction corresponds to a JSHUTDOWN command, and the device start instruction corresponds to a JSTART command. . In the case of Virtex-4 FPGA, the size of one frame is 1312 bits. Information indicating a control procedure for reading the value of the storage element, which can be used as the reading unit control information 125 of this embodiment, is described in Chapter 8 and Table 8-5 of Non-Patent Document 1.

  Note that the reading unit 101 included in the semiconductor device 100 continuously reads a function for reading one or a plurality of storage elements corresponding to the first number and a value of each storage element corresponding to the plurality of first numbers. The readout method is not limited as long as it has a function for the purpose.

  As shown in FIG. 5, the semiconductor device 100 includes a plurality of storage elements 1000.1.1.1-1000. M.M. M first selectors 1001.1-1001. For selecting a value read from N. M and the first selector 1001.1-1001. A second selector 1001 for selecting the value of the storage element designated by the first number from the value selected by M, and the first selector 1001.1-1001. The memory element 1000.1.1-1000. M.M. A first incrementer 1002 that outputs a selection signal for sequentially selecting the values read from N, and the value of the storage element designated by the first number in the second selector 1001 according to the instruction of the reading unit 101 And a second incrementer 1003 that outputs a selection signal for selecting. The value of the storage element output from the second selector 1001 is output to the device control unit 110 via the reading unit 101. Here, M is a number (frame number) given to each frame read from the semiconductor device 100 in ascending order, for example, and N is the number of bits of the storage elements included in one frame.

  When the reading unit 101 receives the first number command and the frame number designation command from the device control unit 110, the value of the storage element corresponding to the number of frames included in the frame number designation command from the first number included in the first number command To get.

  For example, the memory element 1000. Corresponding to the first number (X). X (1 ≦ X ≦ M). 1-1000. X. N, the storage element 1000. Corresponding to the first number (X + 1). X + 1.1-1000. X + 1. When reading the value of N for two frames, the reading unit 101 first sets the value of the first incrementer 1002 to “1” and the first selectors 1001.1 to 1001. The memory element 1000.1.1-1000. M.M. A value of 1 is output.

  Next, the reading unit 101 sets the first number (X) in the second incrementer 1003 and the storage element 1000. X. A value of 1 is output. In addition, the reading unit 101 increases the value of the first incrementer 1002 to “2”, and stores the storage element 1000. X. The value of 2 is output.

  The reading unit 101 repeats the same processing until the value of the first incrementer 1002 becomes “N”, whereby the storage elements 1000. X. 1-1000. X. The value of N is output to the second selector 1001, and the result is held and output to the device control unit 110.

  Further, the reading unit 101 increases the value of the second incrementer 1003 to “X + 1” and increases the value of the first incrementer 1002 from “1” to “N” in the same manner as described above. Storage element 1000 .. corresponding to the number (X + 1). (X + 1). 1-1000. (X + 1). The value of N is output to the second selector 1001, and the result is held and output to the device control unit 110.

  As shown in FIG. 1, the device control unit 110 transmits and receives information between the acquisition unit 111 for reading the value of the storage element from the semiconductor device 100 via the reading unit 101, and the overall control unit 120 and the acquisition unit 111. Control I / F 113.

  The acquisition unit 111 reads the value from the input memory 115 that holds the value of the storage element output from the reading unit 101 every clock cycle, and the required storage element that is supplied to the reading unit 101 every clock cycle. The output memory 116 that holds information such as various commands, the first number, the number of frames, and the like, and the value of the storage element output from the reading unit 101 are held in the input memory 115, and the output memory 116 sends the value to the reading unit 101. And a memory control unit 117 that supplies information such as various instructions, a first number, and the number of frames. The input memory 115 and the output memory 116 are directly connected to the reading unit 101.

  The control I / F 113 is an interface circuit for enabling transmission and reception of information and commands between the overall control unit 120 and the acquisition unit 111. When the overall control unit 120 is realized by a computer having a CPU, for example, the control I / F 113 is used to send and receive information and commands to and from the computer, for example, PCI, PCI express bus, USB, IEEE 1394, Ethernet (registered trademark). It is an interface corresponding to etc.

  FIG. 6 is a connection diagram showing the connection relationship of the input memory, output memory and memory control unit provided in the device control unit, and FIG. 7 is a timing chart showing an operation example of the device control unit shown in FIG.

  As shown in FIG. 6, the memory control unit 117 includes an enable signal generation unit, an address signal generation unit, and a clock signal generation unit.

  A clock 501 shown in FIG. 7 is a signal supplied to the reading unit 101, the input memory 115, and the output memory 116, and is a signal necessary for these units to operate in synchronization. The clock 501 is generated by the clock signal generating means shown in FIG.

  An address signal 502 shown in FIG. 7 is a signal indicating the address of the input memory 115 that stores the value of the storage element output from the reading unit 101 and the address of the output memory 116 that stores information to be supplied to the reading unit 101. . The address signal 502 is generated by the address signal generating means shown in FIG. 6 and 7 show an example in which the same address signal is supplied to the input memory 115 and the output memory 116. However, if the processing speed of the device control unit 110 and the reading unit 101 does not decrease, individual address signals are shown. May be supplied.

  The enable signal 503 is a signal for enabling the operation of storing information in the input memory 115 and the operation of reading information from the output memory 116 in accordance with instructions from the overall control unit. The enable signal 503 is generated by the enable signal generating means shown in FIG. 6 and 7 show an example in which the same enable signal is supplied to the input memory 115 and the output memory 116. However, if the processing speed of the device control unit 110 and the reading unit 101 does not decrease, individual enable signals are shown. May be supplied.

  Reference numeral 504 shown in FIG. 7 shows an example of information supplied from the output memory 116 to the reading unit 101. The reading unit 101 outputs the value of the storage element specified by the first number and the number of frames included in the information 504 to the input memory 115.

  6 shows an example in which the clock 501 supplied to the input memory 115, the output memory 116, and the reading unit 101 is generated in the memory control unit 117. However, the clock 501 is generated outside the memory control unit 117. May be supplied to the input memory 115, the output memory 116, and the reading unit 101.

  FIG. 7 shows an operation example in which one piece of information 504 is input to or output from the reading unit 101 for each cycle of the clock 501. However, the reading unit 101 includes one information 504 for each cycle of the clock 501. Information 504 may be input or output.

  FIG. 7 shows an example in which the address signal is incremented every cycle of the clock 501, but the address signal may be decremented every cycle of the clock 501.

  7 shows an example in which the input memory 115, the output memory 116, and the reading unit 101 operate with positive logic. However, the input memory 115, the output memory 116, and the reading unit 101 may operate with negative logic. .

  As described above, the output memory 116 and the input memory 115 directly connected to the reading unit 101 are provided. Information is input from the output memory 116 to the reading unit 101 every cycle of the clock 501, and the reading unit 101 supplies the clock to the input memory 115. Since the value of the storage element is stored for each cycle of 501, the value of the storage element can be read from the reading unit 101 at a relatively high speed even if the device control unit 110 is realized by, for example, a relatively slow FPGA. it can.

  As described above, in the present embodiment, it is assumed that data is transmitted / received between the reading unit 101 and the device control unit by a serial signal. However, the reading unit 101 can input / output data in units of a plurality of bits. In this case, a memory having the same number of input / output bits as the reading unit 101 may be used as the input memory 115 and the output memory 116. In that case, since there is no memory area that is not used in the input memory 115 and the output memory 116, the waste of the memory area can be eliminated. In addition, an S / P conversion circuit that converts serial signals into parallel data and a P / S conversion circuit that converts parallel data into serial signals are not required, so that the reading time of the value of the storage element in the semiconductor device 100 can be shortened. . When the reading unit 101 is configured to input / output data in units of a plurality of bits, a memory having a larger number of input / output bits than the reading unit 101 may be used as the input memory 115 and the output memory 116. Even in this case, the S / P conversion circuit and the P / S conversion circuit are not necessary.

  FIG. 1 shows a configuration example in which one semiconductor device 100 is verified by the semiconductor verification apparatus of the present embodiment, but a plurality of acquisition units 111 are provided corresponding to each reading unit 101 provided in the plurality of semiconductor units 100. If provided, a plurality of semiconductor devices 100 can be verified by one semiconductor verification apparatus.

  As shown in FIG. 1, the overall control unit 120 includes a user I / F unit 131, a number database 124, a control information calculation unit 135, an initial value calculation unit 126, a first number rewriting unit 129, a frame number rewriting unit 133, an extraction Unit 122 and central control unit 121.

  The central control unit 121 performs operations of the user I / F unit 131, the control information calculation unit 135, the initial value calculation unit 126, the extraction unit 122, the first number rewriting unit 129, and the frame number rewriting unit 133 included in the overall control unit 120. It controls the operation of the device control unit 110 and the clock control unit 140.

  The central control unit 121 controls the clock control unit 140 to stop the clock supplied to the semiconductor device 100 based on, for example, the value of the memory element output from the semiconductor device 100 (break setting function). ), And a function of causing the semiconductor device 100 to supply a clock having the number of cycles specified by the user. In that case, the value of the memory element can be observed in units of one clock cycle, and the operation of the semiconductor device 100 can be stopped when a required event occurs.

  In addition, when the semiconductor device 100 includes a CPU or DSP that executes processing according to a program, the central control unit 121 supplies / stops the clock by the clock control unit 140 using the program counter of the CPU or DSP. The clock control unit 140 may control the supply / stop of the clock when a write or read to a specific address in the memory is detected, and the number of times that the breakpoint has been reached has reached a predetermined number. The clock supply / stop by the clock control unit 140 may be controlled at the time.

In summary, the clock stop conditions for the semiconductor device 100 are as follows:
(1) When the signal to be observed reaches a predetermined value,
(2) When the value of the signal to be observed falls within or outside the specified range,
(3) When the number of times specified in (1) or (2) is reached,
(4) When the semiconductor device 100 includes a CPU, a DSP, or the like that operates according to a program, when a predetermined break condition occurs in the processing by the CPU or the DSP,
(5) When any one of the above conditions (1) to (4) occurs for a plurality of signals, etc. can be considered.

  Further, when the semiconductor device 100 is a hardware emulator, the circuit to be verified can be changed, and a break condition (condition for stopping clock supply) can be set using an arbitrary signal of the semiconductor device 100. Detailed verification work becomes possible.

  As described above, the number database 124 stores information (first number and second number) for uniquely identifying each storage element in the semiconductor device 100, including the first number, the second number, and the storage element name. Is done.

  The user I / F unit 131 has a function of receiving a designation input of a storage element by a user and a function of presenting a value read from the storage element to the user. The observation target storage element designated by the user using the user I / F unit 131 is stored as an observation signal list 134 under the control of the central control unit 121. When the overall control unit 120 is realized by a computer, the user I / F unit 131 corresponds to an interface of an input device such as a keyboard or a mouse and an interface of an output device such as a display or a printer.

  The overall control unit 120 may receive the observation target storage element name input by the user using, for example, a keyboard, and the observation target storage element selected by the user using the mouse from the list of storage elements displayed on the display A name may be accepted. The overall control unit 120 may allow the user to specify the entire bus signal or the entire memory as an observation target. Further, the overall control unit 120 may display the read storage element value for each bit, may display the entire bus signal, hexadecimal display, decimal display, and waveform display of the storage element value. The function to perform may be provided.

  Based on the number database 124 and the observation signal list 134, the control information calculation unit 135 generates control information 136 indicating the reading order of the values of the respective storage elements to be observed designated by the user. The operation of the control information calculation unit 135 will be specifically described with reference to FIGS.

  For example, it is assumed that the storage elements P, Q, R, S, T, U, V, and W are designated as observation targets by the user, and an observation signal list 134 as shown in FIG. 8 is generated. In this case, the control information calculation unit 135 generates control information 136 as shown in FIG. 10 according to the flowchart shown in FIG.

  As shown in FIG. 9, the control information calculation unit 135 first classifies each storage element designated in the observation signal list 134 for each same first number (step S900), and sorts them in ascending order of the first numbers ( Step S901), an entry for each first number is created. Each entry includes one first number, the number of frames, one or more second numbers, the name of the storage element identified by the first number and the second number. In the processing up to step S901, the number of frames of each entry is set to “0”. The number of frames for each entry is determined in the next step S902.

  In step S902, the control information calculation unit 135 determines whether to read only one frame or to continuously read a plurality of frames, and inserts the number of frames into the control information 136 based on the determination result (step S902). S902).

  The number of frames is determined as follows.

  For example, when C is a time for reading one frame independently and D is a time for continuously reading a frame to be set and a subsequent frame, if 2 × C <D, the number of frames to be set is Set to “1”.

  On the other hand, when 2 × C> D, the time when the frame to be set and the subsequent two frames are continuously read is E, and when C + D <E, the frame of the frame to be set The number is (“first number of second frame” − “first number of frame to be set” +1) +1, and the frame to be set and one subsequent frame are read out successively.

  On the other hand, when C + D> E, the time for continuously reading the frame to be set and the subsequent three frames is F, and when C + E <F, the number of frames to be set is set to “(third As “first number of frame” − “first number of frame to be set” +1), the setting target frame and the subsequent two frames are set to be read continuously. By repeating the above processing, the number of frames of each entry corresponding to the first frame to be read is set.

  That is, when the storage elements included in the observation signal list are classified as entries having the same first number and all entries are arranged in ascending or descending order, the time required to process one entry alone and the setting target When the sum of the time for continuously processing N−1 entries following the frame is P and the time for continuously processing N entries following the setting target frame is Q, P <Q What is necessary is just to obtain | require the largest N satisfy | filled and to set N-1 to the number of frames of a setting object frame.

  The initial value calculation unit 126 is a memory element corresponding to the semiconductor device 100 that is initially held in the output memory 116 based on the test standard (JTAG or the like) supported by the semiconductor device 100 and the read unit control information 125. Initial value information 127 including a control command for reading a value, first position information 132 indicating a storage position (bit position) of a first number in information supplied from the output memory 116 to the reading unit 101, and output memory 116 Frame number position information 130 indicating the storage position (bit position) of the number of frames in the information supplied to the reading unit 101, and the storage position for each storage element corresponding to the second number in the information output from the reading unit 101 to the input memory 115 Second position information 128 indicating (bit position) is obtained.

  For example, the first number and the number of frames are represented by 32 bits, each instruction shown in FIG. 4 is 12 bits (the first number instruction and the frame number designation instruction are 12 + 32 = 44 bits), and each instruction is shown in FIG. When represented by the indicated value, the initial value information 127 is 0x300_005_XXXXXXXXX_002_YYYYYYYY_001_301. Here, each instruction is expressed in hexadecimal (4 bits). XXXXXXXXX indicates a first number that is rewritten each time a value of a storage element is read from the semiconductor device 100 according to the control information 136 in units of frames, and YYYYYYYY indicates a value of the storage element from the semiconductor device 100 according to the control information 136. Is the number of frames that are rewritten each time frame is read out in units of frames. Information is input to the output memory 116 by MSB First.

  In this example, the first position information 132 is inserted into 24 bits to 56 bits of information output as a serial signal from the output memory 116 to the reading unit 101, and the frame number position information is set to 68 to 100 bits. Inserted.

  The second position information 128 is a table for obtaining the bit position of the input memory 115 that holds the value of each storage element by using the second number and the number of frames at the time of reading as inputs. For example, in the case of a single read operation, even if the number of frames is read continuously, the device is written sequentially from address 0 of the input memory 115. If the size of one frame is 1312 bits (fixed), the input memory The value of the storage element of “second number 0” in “first frame” is written in address 0 of 115, and the value of the storage element of “second number 1” in “first frame” is written in address 1 Is written, and the address 1311 is written with the value of the storage element “second number 1311” of “first frame”, and the address 1312 is the storage element of “second number 0” of “second frame”. The value of the storage element of “second number 1311” of “second frame” is written to address 2623. Such a correspondence table is recorded as the second position information 128. In an actual device, depending on the configuration of the reading unit control information 125 and the device control unit 111, it may not be arranged in this order, so in order to shorten the reading time, such a correspondence table is provided. It is necessary to prepare the 2-position information 128.

  By the way, when the semiconductor device 100 to be verified is compatible with JTAG, test data corresponding to the state of the semiconductor device 100 is read using a TDI (Test Data In) and TMS (Test Mode Select) signal. Since it is necessary to supply the unit 101 and also to consider the configuration of the semiconductor device 100, complicated calculation is required to obtain the first position information 132 and the frame number position information 133.

  Therefore, in this embodiment, the initial value information 127 and the second position information excluding the first position information 132 and the frame number position information 133 are calculated in advance and stored in the output memory 116, and only the first number and the number of frames are stored. rewrite. In this way, the value of the output memory 116 that is rewritten every time the value of the storage element is read from the reading unit 101 in units of the number of frames included in the control information 136 can be suppressed to a minimum. Therefore, the time required to read the values of a plurality of storage elements can be shortened.

  The first number rewriting unit 129 uses the first position information 132 to rewrite the value of the first number held in the output memory 116 to the value instructed by the central control unit 121. The central control unit 121 designates a value of the first number to be rewritten based on the control information 136 to the first number rewriting unit 129.

  When rewriting of the first number is instructed from the central control unit 121, the first number rewriting unit 129 is the bit of the output memory 116 indicated by the first position information 131 (“XXXXXXX” in the above example, and the initial value information 127. The 24th to 56th bits) are rewritten to the designated first number value.

  When the output memory 116 is realized by a 32-bit 1-port memory, data is written to the output memory 116 in units of 32 bits, so the first number located at the 24th to 56th bits of the initial value information 127 Cannot be rewritten at once. In this case, two rewrite processes are required: a process of rewriting the value from the 24th bit to the 32nd bit of the initial value information 127 and a process of rewriting the value of the 33rd bit to the 56th bit. However, if the storage location of the initial value information in the output memory 116 is devised, the first number stored in the output memory 116 can be rewritten at a time. For example, if the initial value information is stored from the address “8” and the overall control unit 120 is controlled to access the output memory 116 from the address “8”, the first number is stored from 33 bits to 64 bits. All of the first numbers can be rewritten by a single rewriting process.

  On the other hand, when the output memory 116 is realized by a dual port memory, the writing process from the output memory 116 to the reading unit 101 and the rewriting process of the first number in the output memory 116 can be performed in parallel. Therefore, it is possible to apparently eliminate the rewrite time of the first number for the output memory 116, and the value of the storage element can be read from the semiconductor device 100 at higher speed.

  The frame number rewriting unit 133 rewrites the value of the frame number held in the output memory 116 to the value instructed by the central control unit 121 using the frame number position information 130. The central control unit 121 designates the value of the number of frames to be rewritten to the frame number rewriting unit 133 based on the control information 136. Since the frame number rewriting process by the frame number rewriting unit 133 may be executed in the same manner as the first number rewriting process by the first number rewriting unit 129 described above, the description thereof is omitted here.

  The extraction unit 122 acquires the value of the storage element for each frame from the input memory 115 according to the instruction from the central control unit 121 using the number of frames specified in the previous read operation and the second position information.

  When the processing to be read from the central control unit 121 is specified based on the control information 136, the extraction unit 122 inputs from the second position information 128 using the number of frames described in the processing and each second number described in the processing. The bit position of the memory 115 is obtained, and the value of the bit position is read via the control I / F 113. For example, when reading the value of the storage element Q shown in FIG. 8, since the values of three frames corresponding to the first numbers 0xD, 0XE, and 0xF are continuously stored in the input memory 115, the extracting unit 122 The value of the address 2625 (= 2 × 1312 + 1) of the input memory 115 may be read.

  When the input memory 115 is realized by a dual port memory, it is preferable that the bit width of input / output data of the input memory 115 and the bit width of data that can be transferred by the control I / F 113 are matched. In that case, data can be most efficiently transmitted and received between the overall control unit 120 and the device control unit 110. For example, if the control I / F 113 is a 32-bit PCI bus, the most efficient data transfer between the overall control unit 120 and the device control unit 110 is achieved by using a memory with a bit width of input / output data of 32 bits for the input memory 115. Can be sent and received.

  Next, the operation of the semiconductor verification apparatus of this embodiment will be described with reference to FIG.

  The central control unit 121 generates initial value information 127, first position information 132, second position information 128, and frame number position information 130 by using the read unit control information 125 by the initial value calculation unit 126 (step). S1101).

  Next, the central control unit 121 writes the initial value information 127 to the output memory 116 via the control I / F 113 (step S1102).

  When the user uses the user I / F unit 131 to specify a storage element to be observed of the semiconductor device 100, the central control unit 121 creates and stores an observation signal list 134 including the specified storage element (step S1103). ).

  Next, the central control unit 121 causes the control information calculation unit 135 to create control information 136 based on the observation signal list 134 and the number database 124. At this time, the control information 136 may include the number of clock cycles supplied from the clock control unit 140 to the semiconductor device 100 specified by the user using the user I / F function 131. When the semiconductor device 100 or the clock control unit 140 has a break function, the control information 136 may include a break condition specified by the user using the user I / F function 131.

  Next, the central control unit 121 controls the clock control unit 140 to supply a clock to the semiconductor device 100 and operate the semiconductor device 100 (step S1104).

  When a user instructs the semiconductor device 100 to stop supplying a clock using the user I / F 131, when a clock having a predetermined number of cycles is supplied from the clock control unit 140, or when a predetermined break condition occurs The central control unit 121 controls the clock control unit 140 to stop the clock supplied to the semiconductor device 100 (step S1105).

  When the clock control unit 140 stops the supply of the clock to the semiconductor device 100, the central control unit 121 reads a value of a required storage element of the semiconductor device 100 according to the control information 136 (step S1106). Subsequently, it is determined whether or not the reading of the values of the storage elements specified in all the entries of the control information 136 has been completed (step S1107), and the values of the storage elements described in all the entries of the control information 136 are determined. If the reading has not been completed, the process returns to step S1106 and steps S1106 and S1107 are repeated.

  Here, the reading process of the value of the storage element executed in step S1106 will be specifically described using an example including the control information 136 shown in FIG.

  In step S1106, the central control unit 121 first acquires the first number (0x1) and the number of frames (1) specified in the first process of FIG.

  Next, the central control unit 121 rewrites the first number held in the output memory 116 using the first number rewriting unit 129 to the value acquired in step S1106, and uses the frame number rewriting unit 133 to output the output memory 116. The number of frames held in step S1106 is rewritten to the value acquired in step S1106.

  Next, the central control unit 121 supplies the information held in the output memory 116 to the reading unit 101 using the memory control unit 117 and stores the value of the storage element output from the reading unit 101 in the input memory 115. To do.

  When the value of the storage element specified in the first process of FIG. 10 is stored in the input memory 115, the central control unit 121 extracts the number of frames and the second number included in the first process of the control information 136. To supply. The acquisition unit 122 uses the second position information 128 to determine the bit position of the input memory 115 in which the value of the storage element to be read in the first process is stored based on the number of frames and the second number specified by the central control unit 121. The value of the storage element corresponding to the second number is obtained from the bit position via the control I / F 113.

  The above processing is repeated for the remaining processing included in the control information 136 (second processing 2 and third processing in the example shown in FIG. 8), and the values of the storage elements specified in all the entries of the control information 136 are read. Is completed, the read value is output from the output device using the user I / F unit 131 and presented to the user.

  The central control unit 121 uses the user I / F unit 131 to output whether or not to continue the operation of the semiconductor device 100 when reading of the values of the storage elements specified in all the entries of the control information 136 is completed. Are output to the user (step S1108).

  The central control unit 121 stops the operation of the semiconductor device 100 when the user instructs the operation stop using the user I / F unit 131, and returns to the process of step S1103 when the user instructs the continuation of the operation. The processing from step S1103 to step S1108 is repeated.

  According to the present embodiment, information necessary for reading the value of the storage element to be observed designated by the user is stored in the output memory 116, and the reading unit 101 included in the semiconductor device 100 is provided from the output memory 116. Is output to the output memory 116 as information necessary for designating the storage element to be read next while storing the value of the storage element read by the reading unit 101 in accordance with the information in the input memory 115. Only the values of the first number and the number of frames held in step 1 are rewritten. For this reason, it is possible to shorten the processing time required to read the value of the required storage element.

  Further, when reading the value of each frame, the control information calculation unit 135 calculates whether to read the values of a plurality of frames individually or sequentially so that the total reading time is the shortest, and the calculation result Since the control information 136 including the number of frames based on is generated and the value of the memory element of the semiconductor device 100 is read according to the control information, the total read time required for reading the values of the plurality of memory elements can be minimized.

  For example, when the semiconductor device 100 is a hardware emulator and the above Xilinx Corp. Virtex-4 FPGA is used as the hardware emulator, when reading three frame values individually, the FPGA is shut down, and the memory element from the FPGA. Need to be read three times, and the FPGA start process must be executed three times. On the other hand, if the values of the three frames are read continuously, the time required for one read process becomes longer, but the FPGA shutdown and start process only needs to be performed once, so the values of the three frames are read. The total readout time required for the process can be shortened. Further, in the above-described Virtex-4 FPGA, the first frame to be read is always a dummy frame (a frame without information). For example, if the values of a plurality of storage elements are individually read for each frame, the dummy frame needs to be read three times. . On the other hand, if the values of the three frames are read continuously, it is only necessary to read the dummy frame once, so that the total reading time required for reading the values of the three frames can be shortened.

  In the semiconductor verification apparatus according to the present embodiment, the output memory 116 and the input memory 115 provided in the device control unit 110 can be directly connected to the reading unit 101 of the semiconductor device 100 to be verified. On the other hand, it is possible to supply a command for reading a value of a storage element every clock cycle and information designating a storage element to be read, and the semiconductor device is read from the reading unit 101 to the input memory 115 every clock cycle. A value read from 100 can be stored. Therefore, the reading process of the value of the memory element from the semiconductor device 100 can be easily controlled.

  Therefore, according to the semiconductor verification apparatus of this embodiment, the value of the memory element included in the semiconductor device or hardware emulator to be verified can be read faster than the background art. Therefore, the verification work of the semiconductor device and the hardware emulator can be performed more efficiently.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Reading unit 110 Device control unit 111 Acquisition unit 113 Control I / F part 115 Input memory 116 Output memory 117 Memory control unit 120 Overall control unit 121 Central control part 122 Extraction part 124 Number database 126 Initial value calculation part 129 1st 1-number rewriting unit 131 User I / F unit 133 Frame number rewriting unit 135 Control information calculating unit 136 Control information 140 Clock control unit

Claims (6)

A semiconductor verification apparatus using the semiconductor device capable of identifying a plurality of storage elements included in the semiconductor device by a first number and a second number,
Based on the number of frames indicating the number of the first number and said storage element that consists of a frame specified by the first number, the external value of the memory element corresponding to the number of said consecutive frames from the first number and read out unit you output to,
A method of reading a value of the storage element to be observed based on a number database indicating the first number and the second number for each storage element and an observation signal list designating the storage element to be observed A control information calculation unit for creating control information to be determined;
Based on the control information, a central control unit that acquires the value of each storage element specified in the observation signal list from the reading unit;
Have
The control information calculation unit
When the storage elements included in the observation signal list are classified as entries having the same first number and all entries are arranged in ascending or descending order, the time required to process one entry alone and the setting target The total of N-1 entries following the frame and the time for continuously processing N entries are set as P, and a total of N entries consisting of the setting target frame and the N-1 entries following this are continuously processed. Where Q is Q, the largest N satisfying P <Q is determined, N-1 is set as the number of frames to be set,
The central control unit
A semiconductor verification apparatus, wherein the value of the storage element included in the observation signal list is read from the reading unit in units of the number of frames . An output memory holding information for reading the value of the storage element, including the first number and the number of frames supplied to the reading unit;
An input memory for holding the value of the storage element output from the reading unit;
Initial value information including a control command for reading the value of the storage element from the semiconductor device, first position information indicating a storage position of the first number in information supplied from the output memory to the reading unit, and the output memory The frame number position information indicating the storage position of the number of frames in the information supplied from the read unit to the read unit, and the storage position for each storage element corresponding to the second number in the information output from the read unit to the input memory. 2 an initial value calculation unit for obtaining position information;
Have
The central control unit
Change only the first number and the number of frames held in the output memory in units of the number of frames,
The value of the storage element is extracted from the input memory in units of the number of frames based on the initial value information including the first position information and the frame number position information, and the second number. Item 2. The semiconductor verification device according to Item 1. A clock control unit for supplying a clock to the semiconductor device or stopping the supply of the clock;
The central control unit
(1) When the value of the memory element to be observed becomes a predetermined value,
(2) When the value of the memory element to be observed falls within or outside the predetermined range,
(3) When the condition shown in (1) or (2) reaches a predetermined number of times,
(4) When a predetermined break condition occurs in the processing by the semiconductor device,
(5) When the conditions shown in the above (1) to (4) occur in the values of a plurality of storage elements,
3. The semiconductor verification apparatus according to claim 2 , wherein the value of the storage element is read after the clock control unit stops supplying the clock to the semiconductor device. A semiconductor verification method using the semiconductor device, wherein a plurality of memory elements included in the semiconductor device can be identified by a first number and a second number,
Based on the number of frames indicating the number of the first number and said storage element that consists of a frame specified by the first number, the external value of the memory element corresponding to the number of said consecutive frames from the first number and read out unit you output to,
A method of reading a value of the storage element to be observed based on a number database indicating the first number and the second number for each storage element and an observation signal list designating the storage element to be observed A control information calculation unit for creating control information to be determined;
Based on the control information, a central control unit that acquires the value of each storage element specified in the observation signal list from the reading unit;
With
The control information calculation unit is
When the storage elements included in the observation signal list are classified as entries having the same first number and all entries are arranged in ascending or descending order, the time required to process one entry alone and the setting target The total of N-1 entries following the frame and the time for continuously processing N entries are set as P, and a total of N entries consisting of the setting target frame and the N-1 entries following this are continuously processed. Where Q is Q, the largest N satisfying P <Q is determined, N-1 is set as the number of frames to be set,
The central control unit is
A semiconductor verification method, wherein a value of the storage element included in the observation signal list is read from the reading unit in units of the number of frames . An output memory holding information for reading the value of the storage element, including the first number and the number of frames supplied to the reading unit;
An input memory for holding the value of the storage element output from the reading unit;
Initial value information including a control command for reading the value of the storage element from the semiconductor device, first position information indicating a storage position of the first number in information supplied from the output memory to the reading unit, and the output memory The frame number position information indicating the storage position of the number of frames in the information supplied from the read unit to the read unit, and the storage position for each storage element corresponding to the second number in the information output from the read unit to the input memory. 2 an initial value calculation unit for obtaining position information;
With
The central control unit is
Change only the first number and the number of frames held in the output memory in units of the number of frames,
The value of the storage element is extracted from the input memory in units of the number of frames based on the initial value information including the first position information and the frame number position information, and the second number. Item 5. The semiconductor verification method according to Item 4. A clock control unit for supplying a clock to the semiconductor device or stopping the supply of the clock;
The central control unit is
(1) When the value of the memory element to be observed becomes a predetermined value,
(2) When the value of the memory element to be observed falls within or outside the predetermined range,
(3) When the condition shown in (1) or (2) reaches a predetermined number of times,
(4) When a predetermined break condition occurs in the processing by the semiconductor device,
(5) When the conditions shown in the above (1) to (4) occur in the values of a plurality of storage elements,
The semiconductor verification method according to claim 5 , wherein the value of the storage element is read after the clock control unit stops supplying a clock to the semiconductor device.

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