JP5468959B2 - LCD panel source driver - Google Patents

Description

  The present invention relates to a source driver for an active matrix type liquid crystal panel.

  It is known that AC driving is necessary to prevent deterioration of the characteristics of the liquid crystal material of the liquid crystal panel and to ensure long-term reliability of the liquid crystal panel. For this reason, in a conventional active matrix type liquid crystal display device, a driving voltage corresponding to the gradation level of image data is applied between the electrodes of the liquid crystal elements of each cell (pixel) of the liquid crystal panel by a source driver, and the driving is performed. For example, the polarity of the voltage is inverted with respect to the reference potential for each frame of the video signal (see Patent Document 1). For example, the drive voltage on the L (low potential) side with respect to the reference potential is applied in the frame following the frame in which the drive voltage on the H (high potential) side with respect to the reference potential is applied.

  Also, instead of setting all the cells of the liquid crystal panel to the same driving voltage at the same time with respect to the reference potential, adjacent cells in each column and row have driving voltages opposite to each other with respect to the reference potential. A dot inversion driving method, or a two-line dot inversion method in which adjacent cells in a column have opposite driving voltages and are inverted every two lines in a row is employed.

  FIG. 1 shows an example of a signal waveform supplied from a source driver to one column terminal among a plurality of column terminals of a liquid crystal panel. The VCOM signal that is a reference potential is one terminal potential of a liquid crystal element that is a two-terminal element, and is a constant DC voltage (for example, 6 V). The VCOM signal usually has a potential of about ½ of the output voltage of the drive power supply. As shown by the characteristic indicated by the solid line AL in FIG. 1, the drive voltage indicates that the polarity is inverted with respect to the VCOM signal in the line scan cycle (scan period per line). A characteristic indicated by a broken line BL in FIG. 1 indicates a driving voltage applied to the liquid crystal element via an adjacent column terminal in the case of the dot inversion driving method. The drive voltage is a voltage according to the gradation level of the image data as described above, but in FIG. 1, the drive voltage after inversion is shown to be constant (same gradation value).

Japanese Patent Laid-Open No. 2005-201974 Japanese Patent Laid-Open No. 2003-060453

  In recent years, liquid crystal display devices have been required to operate at high speed in order to improve image quality. To that end, it is necessary to increase the writing speed for charging the liquid crystal elements of the liquid crystal panel with a driving voltage corresponding to the gradation indicated by the image data. It is. On the other hand, reduction in power consumption of the device and reduction in the amount of heat generated by the driver are in a trade-off relationship with an increase in the writing speed.

  Therefore, an object of the present invention is to provide a source driver for a liquid crystal panel that can realize low heat generation while enabling high-speed driving.

The source driver according to the present invention includes an inverting unit that outputs a voltage corresponding to image data by inverting a polarity at a predetermined cycle with respect to a reference potential for each column of the active matrix type liquid crystal panel, and the inverting unit at the predetermined cycle. A plurality of amplifiers composed of voltage followers that output a driving voltage from an output terminal to a column terminal of the liquid crystal panel according to an output voltage, each of the plurality of amplifiers including an output voltage of the inverting means Differential amplifying means for inputting the voltage at the non-inverting input terminal, first and second output amplifying means to which the output voltage of the differential amplifying means is supplied as an input voltage, and the output terminal of the first output amplifying means, Means for connecting the output terminal; a first switch element for turning on / off a connection between an output terminal of the second output amplifying means and the output terminal; the output terminal; A second switch element for turning on / off the connection between the amplifier and the common line; and a third switch element for turning on / off the connection between the output terminal of the second output amplifier and the inverting input terminal of the differential amplifier. And a fourth switch element that turns on and off the connection between the output terminal and the inverting input terminal of the differential amplifying unit, and immediately after the voltage corresponding to the image data is inverted in polarity by the inverting unit with the first predetermined time period is controlled to the high impedance state in response to the control signal to the first output amplifying means, said first and said fourth switching element is controlled to the oFF state, the second and the first 3 is for controlling the switching element in the oN state, the in the period from after the end of the first predetermined period of time to a voltage corresponding to the image data is then polarity inverted by said inverting means And controls the amplifier operating state in response to the control signal 1 output amplifying means, and controlling said first and said fourth switching element in an ON state, controlling said second and said third switching element in the off state that It is characterized by.
The source driver according to the present invention includes an inverting unit that outputs a voltage corresponding to image data by inverting a polarity at a predetermined cycle with respect to a reference potential for each column of the active matrix type liquid crystal panel, and the inverting unit at the predetermined cycle. A plurality of amplifiers composed of voltage followers that output a driving voltage from an output terminal to a column terminal of the liquid crystal panel according to an output voltage, each of the plurality of amplifiers including an output voltage of the inverting means Differential amplifying means for inputting at the non-inverting input terminal, and first and second output amplifying means to which the output voltage of the differential amplifying means is supplied as an input voltage, respectively. with voltage corresponding the the first predetermined time period immediately after the polarity inversion is controlled in the high impedance state in response to the control signal to the first output amplifier means to the data, The outputs of the second output amplifying means are controlled in a disconnected state between the output terminal of the second output amplifying means and the output terminal and between the output terminal and the inverting input terminal of the differential amplifying means. controls between the end and the inverting input terminal of said differential amplifier means to the connection state, and the a line Umono charge sharing for converging the potential to the reference potential of the output terminal, said first termination predetermined period and controls the amplifier operating state in response to a control signal of the first output amplification means within until a voltage corresponding to the image data is then polarity inverted by said inverting means later, the second output amplification means And controlling the connection between the output terminal and the output terminal and between the output terminal and the inverting input terminal of the differential amplification means, and the output terminal of the second output amplification means and the differential amplification means No connection between inverting input of It is characterized in controlling and stopping the charge sharing thing.

  According to the source driver of the present invention, the voltage supplied from the output terminal to the column terminal of the liquid crystal panel can be quickly changed to a desired drive voltage. Further, the amount of heat generation can be reduced, and the level of the drive voltage can be output to the liquid crystal panel with high accuracy.

It is a figure which shows an example of the signal waveform applied to one column terminal of a liquid crystal panel from the conventional source driver. It is a block diagram which shows the structure of a source driver as 1st Example of this invention. It is a figure which shows the data structure of the image data in FIG. FIG. 3 is a diagram illustrating a configuration of a second switch circuit in the source driver of FIG. 2. FIG. 3 is a circuit diagram illustrating a configuration of an amplifier in the source driver of FIG. 2. FIG. 3 is a diagram illustrating an example of a signal waveform applied from the source driver of FIG. 2 to one column terminal of the liquid crystal panel. FIG. 6 is a circuit diagram showing an on / off state of each switch element in the amplifier of FIG. 5 and a high impedance state of the first output amplifier in the CS period. It is a circuit diagram which shows the other structural example of an amplifier. It is a block diagram which shows the structure of a source driver as 2nd Example of this invention. FIG. 10 is a circuit diagram illustrating a configuration of an amplifier in the source driver of FIG. 9. It is a figure which shows an example of the signal waveform applied to one column terminal of a liquid crystal panel from the source driver of FIG. FIG. 11 is a circuit diagram showing an on / off state of each switch element in the amplifier of FIG. 10 and a high impedance state of the first output amplifier in the CS period. FIG. 11 is a circuit diagram showing an on / off state of each switch element in the amplifier of FIG. 10 and a high impedance state of the second output amplifier in a normal period.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 2 shows the configuration of the source driver as the first embodiment of the present invention. The source driver includes a plurality of amplifiers 601, a plurality of first switch circuits 102, a plurality of second switch circuits 101, a plurality of first latches 606, a plurality of second latches 608, a shift register 607, and a plurality of P-channel reference voltages. A selector 602, a plurality of N-channel reference voltage selectors 603, an input pad and control circuit 701, a VH generation circuit 501, a VL generation circuit 502, and a plurality of delay circuits 521 are provided.

  This source driver forms one drive unit for six adjacent columns of an active matrix type liquid crystal panel (not shown). In FIG. 2, two drive units (first drive unit A1 and second drive unit A2) are formed. ) Only. Further, in six columns of each drive unit, a drive group is formed by two adjacent columns, and the first and second switch circuits 102 are described later with two signal supply systems corresponding to the two columns in each drive group. , 101 can switch data and reference voltage.

  The shift register 607 includes a plurality of flip-flops FF, and latch signals L1, L2,... Indicating data latch timing to the first latch 606 according to a start signal. . . Is output.

  The input pad and control circuit 701 inputs image data, rearranges the first latch 606 so that the image data can be sequentially taken in at the output timing of the shift register 607, and outputs six output image data 702 (R1, G1, B1, R2, G2, B2) are supplied to the first latch 606.

  As shown in FIG. 3, the image data 702 includes six columns of data R1, G1, B1, R2, G2, and B2 at the same time. That is, the data R1, G1, B1, R2, G2, and B2 are first R_1, G_1, B_1, R_2, G_2, and B_2 for the first six columns, and then R_3, G_3, B_3 for the six columns that follow. R_4, G_4, and B_4, and then R_5, G_5, B_5, R_6, G_6, and B_6 for six columns. The same continues thereafter.

  The number of gradations of the image data 702 is, for example, 64 gradations when the data is 6 bits, 256 gradations when the data is 8 bits, and 1024 gradations when the data is 10 bits.

  The first latch 606 includes latches having the number of column terminals of the liquid crystal panel (103 to 108 in the first driving unit A1). Each first latch 606 outputs the output timing signals L1, L2,. . . In response to this, any one of the image data 702 is captured.

  The second latch 608 includes latches for the number of column terminals of the liquid crystal panel (109 to 114 in the first drive unit A1), and latches and outputs the image data captured in the first latch 606 according to the load signal LOAD. .

  The first switch circuit 102 serving as the first switching means is composed of switch circuits (201 to 203 in the first drive unit A1) that is half the number of column terminals. Each switch circuit 102 supplies the signal latched by the two second latches 608 constituting one drive group to the P channel reference voltage selector 602 and the N channel reference voltage selector 603 according to the polarity inversion signal POL. Switch between inputs. Although each switch circuit 102 is shown in FIG. 2 as two inputs and two outputs, there are input and output lines corresponding to the number of bits of the data signal for each input and output. The configuration of the switch circuit for one bit is the same as that of each switch circuit of the switch circuit 101 of FIG.

  The VH generation circuit 501 has a plurality of voltage dividing circuits in which the reference voltage VREF_H1 (12 V) is applied to one end and VREF_H2 (6 V) is applied to the other end, and the applied voltage is divided by each of the plurality of voltage dividing circuits to generate an image. A plurality of different reference voltages VH corresponding to the number of data gradations are generated.

  The VL generation circuit 502 includes a plurality of voltage dividing circuits in which the reference voltage VREF_L1 (6 V) is applied to one end and VREF_L2 (0 V) is applied to the other end, and the applied voltage is divided by each of the plurality of voltage dividing circuits to generate an image. A plurality of different reference voltages VL corresponding to the number of data gradations are generated.

  P-channel reference voltage selectors 602 are provided as many as half the number of column terminals of the liquid crystal panel, and each is composed of a P-channel transistor. Each P-channel reference voltage selector 602 selects any one of a plurality of reference voltages VH according to the data from the switch circuit 102 and outputs it to the switch circuit 101. In the first driver A1, the P channel reference voltage selectors are 115, 117, and 119.

  N-channel reference voltage selectors 603 are provided as many as half the number of column terminals of the liquid crystal panel, and each is composed of an N-channel transistor. Each N-channel reference voltage selector 603 selects any one of a plurality of reference voltages VL according to data from the switch circuit 102 and outputs the selected voltage to the switch circuit 101. In the first drive unit A1, the N-channel reference voltage selectors are 116, 118, 120.

  The second switch circuit 101 as the second switching means is composed of switch circuits (204, 205, 206 in the first drive unit A1) that is half the number of column terminals of the liquid crystal panel. Each switch circuit 101 interchanges the connection between the inputs of the two amplifiers 601 forming one drive group and the outputs of the P-channel reference voltage selector 602 and the N-channel reference voltage selector 603. As shown in FIG. 4, the switch circuit 101 includes two switches that are switched to each other by the polarity inversion signal POL. Each switch circuit 101 has two inputs and two outputs.

  The amplifier 601 includes a plurality of amplifiers (voltage followers) that drive the liquid crystal panel using the reference voltage output from the switch circuit 101 as a driving voltage, and is provided for the number of column terminals of the liquid crystal panel. In the first drive unit A1, the amplifier 601 is also indicated by reference numerals 121-126. Each amplifier 601 is supplied with a control signal CTRL1 and a common line COM is connected to each amplifier 601. The internal configuration of the amplifier 601 will be described later. The common line COM is used for short-circuiting the output terminals of all the amplifiers 601, that is, all the column terminals of the liquid crystal panel during a CS period to be described later.

  The delay circuit 521 is provided between the above-described driving units, delays the load signal LOAD, supplies it to the second latch 608 of the adjacent driving unit, and thereby sets the timing for transferring the image data to the second latch 608.

  The image data, the start signal, the polarity inversion signal POL, the load signal LOAD, and the control signal CTRL1 are generated by a controller (not shown) according to the input video signal.

  As shown in FIG. 5, each of the amplifiers 601 constitutes a voltage follower. As shown in FIG. 5, a differential amplifier 611 (differential amplification means), a first output amplifier 612 (first output amplification means), and a second output amplifier 613 (first output). 2 output amplifying means) and switch elements SW1 to SW4 (first to fourth switch elements). Each of the differential amplifier 611 and the first and second output amplifiers 612 and 613 is composed of an operational amplifier. The first and second output amplifiers 612 and 613 are current amplification amplifiers, and the current output capability of the first output amplifier 612 is greater than the current output capability of the second output amplifier 613. That is, the first output amplifier 612 is a main amplifier with a large output current amount, and the second output amplifier 613 is a sub-amplifier with a small output current amount.

  A reference voltage output from the switch circuit 101 is supplied to the non-inverting input terminal of the differential amplifier 611 via the input terminal IN, and a voltage follower feedback signal FB is supplied to the inverting input terminal. The output terminal of the differential amplifier 611 is connected to the input terminals of the first and second output amplifiers 612 and 613. The first and second output amplifiers 612 and 613 are configured to be connected in parallel as output amplifiers. Such a parallel connection configuration is a conventional technique, and is disclosed in Patent Document 2, for example. The output terminal of the first output amplifier 612 is connected to the output terminal OUT of the amplifier 601. A switch element SW1 is provided between the output terminal of the second output amplifier 613 and the output terminal OUT. The switch element SW2 is provided between the output terminal OUT and the common line COM. The switch element SW3 is provided between the output terminal of the second output amplifier 613 and the inverting input terminal of the differential amplifier 611, and the switch element SW4 is provided between the output terminal OUT and the inverting input terminal of the differential amplifier 611. ing.

  The control signal CTRL1 is supplied to the first output amplifier 612, and the first output amplifier 612 becomes one of an amplifier operation state and a high impedance state according to the control signal CTRL1. Although not shown, the control signal CTRL1 is also supplied to the switch elements SW1 to SW4. The switch elements SW1 to SW4 are turned on or off according to the control signal CTRL1. FIG. 5 shows on / off (open / close) of the switch elements SW1 to SW4 in a normal state, the switch elements SW1 and SW4 are turned on, and the switch elements SW2 and SW3 are turned off.

The liquid crystal panel has, for example, the configuration shown in FIG. 1 of Patent Document 1, and the output terminals OUT of each amplifier 601 are connected to the source lines S _{1 to} S _m shown in FIG. Is connected.

  In the source driver having such a configuration, the drive voltage applied from the output terminal of the amplifier 601 to one column terminal of the liquid crystal panel changes as indicated by a solid line CL in FIG. 6, for example. The drive voltage is made equal to the potential of the VCOM signal (reference potential) in the first CS (charge sharing) period (first predetermined period) of each line scanning cycle. The CS period is a period for redistributing the charges charged in the capacitive components of the liquid crystal elements located on one line. During the CS period, the output terminal OUT of each amplifier 601 is short-circuited to the common line COM in accordance with the control signal CTRL1. In the remaining period after the CS period in the line scanning cycle, the driving voltage becomes a voltage corresponding to a desired gradation, and the voltage is inverted in the line scanning cycle. The characteristic indicated by the broken line DL in FIG. 6 indicates the drive voltage applied to the column terminal adjacent to the one column terminal. The drive voltage is a voltage according to the gradation level of the image data as described above, but in FIG. 6, it is shown that the drive voltage after inversion is constant (same gradation value). Further, the CS period may be long enough so that the potential of the column terminal can reach at least the potential of the VCOM signal.

  Further, the drive voltage applied to each column terminal of the liquid crystal panel is inverted in accordance with the polarity inversion signal POL for each frame. That is, if the drive voltage is on the H (high level) side of the reference potential VCOM in one frame of the video signal, the drive voltage is on the L (low level) side of the reference potential VCOM in the next frame.

  In the source driver configured as described above, first, the polarity inversion signal POL is at L (low level), and the data R1, G1, B1, R2, G2, and B2 are R_1, G_1, B_1, R_2, G_2, and B_2, respectively. The operation when the drive voltage based on the data of the first drive unit A1 is set to the H side, L side, H side, L side, H side, and L side of the reference potential in that order will be described.

  The latch signal L1 generated from the shift register 607 causes the data R_1 to be held in the latch 103 of the first latch 606, G_1 is latch 104, B_1 is latch 105, R_2 is latch 106, G_2 is latch 107, B_2 is latch 108 Is done. Similarly for R_1, G_1, B_1, R_2, G_2, and B_2 and thereafter, the input image data 702 is sequentially latched in the first latch 606 by the latch signal Ln (n is 2 to the number of outputs / 6) generated from the shift register 607. Is done.

  After all the input image data corresponding to the number of outputs is latched by the first latch 606, the data of the first latch 103 is the second latch 109 and the data of the first latch 104 is the second latch according to the load signal LOAD. 110, the first latch 105 data is in the second latch 111, the first latch 106 data is in the second latch 112, the first latch 107 data is in the second latch 113, and the first latch 108 data is in the second latch 114. It is transferred in a batch. Similarly, the data of the first latch 606 after the first latch 108 is also sequentially stored for 6 columns by a signal Tn (n is 2 to the number of outputs / 6) obtained by delaying the load signal LOAD every 6 columns (drive unit). The data is transferred to the second latch 608 every time.

  The data of the second latch 109 is input to the P channel reference voltage selector 115 of the P channel reference voltage selector 602 by the first switch circuit 201, and the data of the second latch 110 is the N channel of the N channel reference voltage selector 603. Input to the reference voltage selector 116. The data of the second latch 111 is input to the P-channel reference voltage selector 117 by the switch circuit 202, and the data of the second latch 112 is input to the N-channel reference voltage selector 118. The data of the second latch 113 is input to the P channel reference voltage selector 119 by the switch circuit 203, and the data of the second latch 114 is input to the N channel reference voltage selector 120. A plurality of reference voltages VH are supplied from the VH generation circuit 501 to the P channel reference voltage selector 602 (115, 117, 119), and a VL generation circuit 502 is supplied to the N channel reference voltage selector 603 (116, 118, 120). Are supplied with a plurality of reference voltages VL.

  Each of the P-channel reference voltage selectors 115, 117, and ll9 selects one reference voltage VH from among a plurality of reference voltages VH having a higher potential than the VCOM signal (reference potential) in accordance with the input image data.

  Each of the N-channel reference voltage selectors 116, 118, and 120 selects one reference voltage VL from among a plurality of reference voltages VL having a lower potential than the VCOM signal (reference potential) according to the input image data.

  The reference voltage VH selected and output from the P-channel reference voltage selector 115 is input to the amplifier 121 of the plurality of amplifiers 601 by the second switch circuit 204. The reference voltage VL output from the N-channel reference voltage selector 116 is input to the amplifier 122 of the amplifier 601 by the second switch circuit 204. The reference voltage VH output from the P-channel reference voltage selector 117 is input to the amplifier 123 of the plurality of amplifiers 601 by the second switch circuit 205. The reference voltage VL output from the N-channel reference voltage selector 118 is input to the amplifier 124 of the plurality of amplifiers 601 by the switch circuit 205. The reference voltage VH output from the P channel reference voltage selector 119 is input to the amplifier 125 of the plurality of amplifiers 601 by the second switch circuit 206. The reference voltage VL output from the N-channel reference voltage selector 120 is input to the amplifier 126 of the plurality of amplifiers 601 by the second switch circuit 206.

  When the polarity inversion signal POL becomes L, it is the CS period shown in FIG. In this CS period, in each of the plurality of amplifiers 601, as shown in FIG. 7, the switch elements SW1 and SW4 are turned off and the switch elements SW2 and SW3 are turned on. Since the first output amplifier 612 is in a high impedance state, it does not affect the output terminal OUT. Since each column terminal of the liquid crystal panel is connected to the common line COM by turning on the switch element SW2, the voltage of the output terminal OUT, that is, the column terminal voltage of the liquid crystal panel gradually converges to the potential of the VCOM signal. On the other hand, in this CS period, the second output amplifier 613 operates as an amplifier, generates a voltage according to the output voltage of the differential amplifier 611 at that time, and the voltage is inverted by the differential amplifier 611 via the switch element SW3. A feedback signal FB is supplied to the input terminal. Therefore, the second output amplifier 613 outputs a voltage corresponding to the reference voltage VH or VL input to each amplifier 601.

  When the CS period ends, each of the plurality of amplifiers 601 operates in a normal period, the switch elements SW1 and SW4 are turned on, and the switch elements SW2 and SW3 are turned off. Both the first and second output amplifiers 612 and 613 operate as amplifiers, and output the same drive voltage to the output terminal OUT according to the output voltage of the differential amplifier 611. The output drive voltage of the first output amplifier 612 is supplied as a feedback signal FB to the inverting input terminal of the differential amplifier 611 via the switch element SW4, and the output drive voltage of the second output amplifier 613 is supplied via the switch elements SW1 and SW4. The Therefore, the voltage of the output terminal OUT transits from the potential of the VCOM signal in the CS period to a desired drive voltage. Since feedback of the output voltage of the second output amplifier 613 to the differential amplifier 611 is performed via the connection line of the output terminal OUT, the output voltage of the second output amplifier 613 in the CS period is output from the output terminal OUT. Since it is immediately reflected in the drive voltage, the voltage of the output terminal OUT can reach the desired drive voltage quickly from the potential of the VCOM signal.

  As a result, an H-side drive voltage corresponding to R_l is generated from the amplifier 121 in accordance with the reference voltage VH input to the amplifier 121 among the plurality of amplifiers 601. A drive voltage on the L side corresponding to G_1 is generated from the amplifier 122 in accordance with the reference voltage VL input to the amplifier 122 of the amplifier 601. An H-side drive voltage corresponding to B_l is generated from the amplifier 123 in accordance with the reference voltage VH input to the amplifier 123 of the amplifier 601. A drive voltage on the L side corresponding to R_2 is generated from the amplifier 124 in accordance with the reference voltage VL input to the amplifier 124 of the amplifier 601. An H-side drive voltage corresponding to G_2 is generated from the amplifier 125 in accordance with the reference voltage VH input to the amplifier 125 of the amplifier 601. An L-side drive voltage corresponding to B_2 is generated from the amplifier 126 according to the reference voltage VL input to the amplifier 126 of the amplifier 601.

  Next, the polarity inversion signal POL is switched to H (high level), and the drive voltage based on the data R_1, G_1, B_1, R_2, G_2, and B_2 of the first drive unit A1 is sequentially changed to the L side and the H side of the reference potential. , L side, H side, L side, H side operation will be described.

  In this case, since the operation from the input image data 702 to the second latch 608 is the same as that described above, the description of the operation is omitted. Each of the switch circuits 101 and 102 is switched by POL = H.

  The data of the second latch 109 is input to the N channel reference voltage selector 116 of the N channel reference voltage selector 603 by the switch circuit 201 of the plurality of first switch circuits 102, and the data of the second latch 110 is the P channel reference. The voltage is input to the P-channel reference voltage selector 115 of the voltage selector 602. The data of the second latch 111 is input to the N-channel reference voltage selector 118 by the switch circuit 202, and the data of the second latch 112 is input to the P-channel reference voltage selector 117. The data of the second latch 113 is input to the N-channel reference voltage selector 120 by the switch circuit 203, and the data of the second latch 114 is input to the P-channel reference voltage selector 119.

  Each of the P-channel reference voltage selectors 115, 117, and ll9 selects one reference voltage VH from among a plurality of reference voltages VH having a higher potential than the VCOM signal (reference potential) in accordance with the input image data.

  Each of the N-channel reference voltage selectors 116, 118, and 120 selects one reference voltage VL from among a plurality of reference voltages VL having a lower potential than the VCOM signal (reference potential) according to the input image data.

  The reference voltage VH output from the P-channel reference voltage selector 115 is input to the amplifier 122 of the amplifier 601 by the switch circuit 204. The reference voltage VL output from the N-channel reference voltage selector 116 is input to the amplifier 121 of the amplifier 601 by the switch circuit 204. The reference voltage VH output from the P channel reference voltage selector 117 is input to the amplifier 124 of the amplifier 601 by the switch circuit 205. The reference voltage VL output from the N-channel reference voltage selector 118 is input to the amplifier 123 of the amplifier 601 by the switch circuit 205. The reference voltage VH output from the P-channel reference voltage selector 119 is input to the amplifier 126 of the amplifier 601 by the switch circuit 206. The reference voltage VL output from the N-channel reference voltage selector 120 is input to the amplifier 125 of the amplifier 601 by the switch circuit 206.

  When the polarity inversion signal POL becomes H, it is the CS period shown in FIG. In this CS period, in each of the plurality of amplifiers 601, as shown in FIG. 7, the switch elements SW1 and SW4 are turned off, the switch elements SW2 and SW3 are turned on, and the first output amplifier 612 is in a high impedance state. As a result, the operation is performed in the same manner as in the CS period when POL = L. Since each column terminal of the liquid crystal panel is connected to the common line COM by turning on the switch element SW2, the voltage of the output terminal OUT, that is, the terminal voltage of each liquid crystal element on the same line of the liquid crystal panel gradually converges to the potential of the VCOM signal. To do. On the other hand, in this CS period, the second output amplifier 613 operates as an amplifier, generates a voltage according to the output voltage of the differential amplifier 611 at that time, and the voltage is inverted by the differential amplifier 611 via the switch element SW3. A feedback signal FB is supplied to the input terminal. Therefore, the second output amplifier 613 outputs a voltage corresponding to the reference voltage VH or VL input to each amplifier 601.

  When the CS period ends, as in the case of POL = L, each of the plurality of amplifiers 601 operates in the normal period, and the switch elements SW1 and SW4 are turned on and the switch elements SW2 and SW3 are turned off. Both the first and second output amplifiers 612 and 613 operate as amplifiers, and output a drive voltage to the output terminal OUT according to the output voltage of the differential amplifier 611. The output voltage of the first output amplifier 612 is supplied as a feedback signal FB to the inverting input terminal of the differential amplifier 611 via the switch element SW4, and the output voltage of the second output amplifier 613 is supplied via the switch elements SW1 and SW4. Therefore, the voltage at the output terminal OUT rapidly changes from the potential of the VCOM signal during the CS period to a desired drive voltage.

  As a result, an H-side drive voltage corresponding to G_1 is generated from the amplifier 122 according to the reference voltage VH input to the amplifier 122 of the plurality of amplifiers 601. A driving voltage on the L side corresponding to R_1 is generated from the amplifier 121 in accordance with the reference voltage VL input to the amplifier 121 of the amplifier 601. A driving voltage on the H side corresponding to R_2 is generated from the amplifier 124 in accordance with the reference voltage VH input to the amplifier 124 of the amplifier 601. A driving voltage on the L side corresponding to B_1 is generated from the amplifier 123 in accordance with the reference voltage VL input to the amplifier 123 of the amplifier 601. An H-side drive voltage corresponding to B_2 is generated according to the reference voltage VH input to the amplifier 126 of the amplifier 601. A driving voltage on the L side corresponding to G_2 is generated from the amplifier 125 in accordance with the reference voltage VL input to the amplifier 125 of the amplifier 601.

  For example, when the amplifier 601 is configured using only two switch elements SW1A and SW2A as a switch element as shown in FIG. 8, the first output amplifier 612 is in a high impedance state during the CS period, and the switch element SW1A Is turned off and the switch element SW2A is turned on. On the other hand, the switch element SW1A is turned on and the switch element SW2A is turned off during the operation in the normal period. In the configuration of FIG. 8, since the output signal of the second output amplifier 613 is fed back to the differential amplifier 611 without passing through the switch element SW1A during normal operation, the output voltage of the second output amplifier 613 obtained during the CS period. Until the output terminal OUT is reflected by the delay of the switch element SW1A. On the other hand, according to the first embodiment described above, the switch element SW3 is provided between the second output amplifier 613 side of the switch element SW1 and the feedback signal FB line in each amplifier 601, and the output terminal OUT and the feedback signal FB are provided. Since the switch element SW4 is provided between the output line OUT and the output voltage of the second output amplifier 613 obtained in the CS period immediately occurs at the output terminal OUT during the normal period operation, the signal delay of the switch element SW1 is reduced. It can be made unaffected.

  In the configuration shown in FIG. 8, since the output signal of the first output amplifier 612 having a large output current flows as a feedback signal to the switch element SW1A during the operation in the normal period, it is necessary to increase the size of the switch element SW1A. is there. On the other hand, according to the first embodiment, only the output current of the second output amplifier 613 flows through the switch element SW1 corresponding to the switch element SW1A in FIG. 8, so that the heat generation is low and the size of the switch element SW1 is reduced. There is an effect that the chip size of the source driver can be reduced.

  FIG. 9 shows the configuration of a source driver as a second embodiment of the present invention, and FIG. 10 shows the configuration of each amplifier 601 in the source driver.

  In the source driver of FIG. 9, a control signal CTRL2 is supplied to each amplifier 601 (including 121 to 126) in addition to the control signal CTRL1. Other configurations are the same as those of the source driver shown in FIG.

  As shown in FIG. 10, each amplifier 601 includes a differential amplifier 611, a first output amplifier 612, a second output amplifier 613, and switch elements SW1 to SW4 to form a voltage follower.

  The control signal CTRL1 is supplied to the first output amplifier 612, and the first output amplifier 612 becomes one of an amplifier operation state and a high impedance state according to the control signal CTRL1. The control signal CTRL2 is supplied to the second output amplifier 613, and the second output amplifier 613 becomes one of an amplifier operation state and a high impedance state according to the control signal CTRL2. The switch elements SW1 to SW4 are turned on or off according to the control signal CTRL1 as in the first embodiment shown in FIG.

  In the source driver having the configuration shown in FIGS. 9 and 10, the operation of the amplifier 601 is performed in the line scanning cycle in a CS (charge sharing) period (first predetermined period), a swing period (second predetermined period), And a stable period. For example, the drive voltage applied from the output terminal of the amplifier 601 to one column terminal of the liquid crystal panel changes as indicated by a solid line EL in FIG. During the CS period, the drive voltage is made equal to the potential of the VCOM signal (reference potential). During the CS period, the output terminal OUT of each amplifier 601 is short-circuited to the common line COM in accordance with the control signal CTRL1. The characteristic indicated by the broken line FL in FIG. 11 indicates the driving voltage applied to the liquid crystal element via the adjacent column terminal in the case of the dot inversion driving method.

  In the CS period, in the amplifier 601, the switch elements SW1 and SW4 are turned off and the switch elements SW2 and SW3 are turned on in response to the control signal CTRL1 as shown in FIG. Also, the first output amplifier 612 is in a high impedance state. Since each column terminal of the liquid crystal panel is connected to the common line COM by turning on the switch element SW2, the voltage of the output terminal OUT, that is, the terminal voltage of each liquid crystal element on the same line of the liquid crystal panel gradually converges to the potential of the VCOM signal. To do. On the other hand, in this CS period, the second output amplifier 613 operates as an amplifier, generates a voltage according to the output voltage of the differential amplifier 611 at that time, and the voltage is inverted by the differential amplifier 611 via the switch element SW3. A feedback signal FB is supplied to the input terminal. Therefore, the second output amplifier 613 outputs a voltage corresponding to the reference voltage VH or VL input to each amplifier 601.

  When the CS period ends and the swing period starts, as shown in FIG. 10, in the amplifier 601, the switch elements SW1 and SW4 are turned on and the switch elements SW2 and SW3 are turned off according to the control signal CTRL1. Both the first and second output amplifiers 612 and 613 are in an amplifier operating state. A voltage is generated from each of the first and second output amplifiers 612 and 613 according to the output voltage of the differential amplifier 611. The output voltage of the first output amplifier 612 is supplied as a feedback signal FB to the inverting input terminal of the differential amplifier 611 via the switch element SW4, and the output voltage of the second output amplifier 613 is supplied via the switch elements SW1 and SW4. Further, the output voltages of the first and second output amplifiers 612 and 613 are combined to be a drive voltage and output from the output terminal OUT to the column terminal of the liquid crystal panel. The drive voltage changes rapidly according to the output voltage of the second output amplifier 613 in the CS period, and reaches a desired voltage (voltage corresponding to the input reference voltage) from the potential of the VCOM signal.

  After the drive voltage reaches a desired voltage corresponding to the image data in the amplifier 601, it becomes a stable period, and as shown in FIG. 13, the second output amplifier 613 enters a high impedance state according to the control signal CTRL2. The states of the switch elements SW1 to SW4 and the first output amplifier 612 are the same as in the swing period. Since the drive voltage is stable at a desired voltage during the stable period, only the first output amplifier 612 of the main amplifier enters the amplifier operation state and outputs the drive voltage.

  According to the second embodiment described above, in each amplifier 601, the switch element SW3 is provided between the switch element SW1 on the second output amplifier 613 side and the feedback signal FB line, and between the output terminal OUT and the feedback signal FB line. By providing the switch element SW4, the output voltage of the second output amplifier 613 obtained in the CS period is immediately reflected as the drive voltage on the output terminal OUT in the swing period, so that the influence of the signal delay by the switch element SW1 is reduced. It can be made not to receive. Further, since only the output current of the second output amplifier 613 flows through the switch element SW1, there is an effect that the heat generation is reduced, the size of the switch element SW1 can be reduced, and the chip size of the source driver can be reduced.

  Furthermore, according to the second embodiment described above, the second output amplifier 613 is brought into a high impedance state when the change of the driving voltage is stabilized according to the control signal CTRL2, so that the steady current flowing through the amplifier 601 is reduced, Power consumption can be reduced.

  In each of the above-described embodiments, a case has been described in which 9V of the plurality of reference voltages VH is selected by the P-channel reference voltage selector and 3V of the plurality of reference voltages VL is selected by the N-channel reference voltage selector. However, even if a VH other than 9V among the plurality of reference voltages VH is selected and a VL other than 3V among the plurality of reference voltages VL is selected, the same effect can be obtained. Further, the present invention can be similarly applied when the reference voltages VH and VL supplied to the amplifier 601 before and after switching of the polarity inversion signal POL are the same but change. Further, the reference voltages VREF_H1 and VREF_H2 used for generating the plurality of reference voltages VH in the VH generation circuit 501 are not limited to 12V and 6V shown as examples, and other voltage values may be used. Similarly, the reference voltages VREF_L1 and VREF_L2 used for generating a plurality of reference voltages VL in the VL generation circuit 502 are not limited to 6V and 0V shown as examples, and other voltage values may be used.

  The source driver of the present invention can be formed as a semiconductor integrated circuit, that is, a semiconductor chip. The switch elements SW1 to SW4 can be configured by connecting at least two FETs (field effect transistors) in parallel. Further, the first and second output amplifiers 612 and 613 can be constituted by a plurality of FETs in which gates are arranged in a comb shape. The current output capability is determined by the number of comb teeth, that is, the number of transistors, with the gate length and the gate width of the FET being constant, and the number of transistors in the first output amplifier 612 having a high current output is larger than that in the second output amplifier 613. ing. In each of the above embodiments, the first output amplifier 612 has a higher current output capability than the second output amplifier 613, but the first output amplifier 612 and the second output amplifier 613 have the same current output. You may have the ability.

DESCRIPTION OF SYMBOLS 101,102 Switch circuit 401 Switch 501 VH generation circuit 502 VL generation circuit 601 Amplifier 602 P channel reference voltage selector 603 N channel reference voltage selector 611 Differential amplifier 612, 613 Output amplifier SW1-SW4, SW1A, SW2A Switch element

Claims (7)

Inversion means for outputting the voltage corresponding to the image data for each column of the active matrix type liquid crystal panel by inverting the polarity at a predetermined cycle with respect to the reference potential;
A source driver comprising: a plurality of amplifiers composed of voltage followers that output a drive voltage from an output terminal to a column terminal of the liquid crystal panel according to an output voltage of the inverting means at the predetermined period;
Each of the plurality of amplifiers includes differential amplification means for inputting the output voltage of the inverting means at a non-inverting input terminal,
First and second output amplifying means to which output voltages of the differential amplifying means are respectively supplied as input voltages;
Means for connecting the output terminal of the first output amplification means and the output terminal;
A first switch element for turning on and off the connection between the output terminal of the second output amplifying means and the output terminal;
A second switch element for turning on and off the connection between the output terminal and a common line for the plurality of amplifiers;
A third switch element for turning on and off the connection between the output terminal of the second output amplifier and the inverting input terminal of the differential amplifier;
A fourth switch element for turning on and off the connection between the output terminal and the inverting input terminal of the differential amplification means,
And controls the high-impedance state in response to a first control signal to the first output amplifier means during a predetermined period immediately after the voltage corresponding to the image data is polarity inverted by said inverting means, said first and said The fourth switch element is controlled to be in an OFF state, and the second and third switch elements are controlled to be in an ON state. After the first predetermined period, a voltage corresponding to image data is applied by the inversion means. then controls the amplifier operation state according to the first output amplifier means to the control signal in the until the polarity inversion, and controls the first and the fourth switching element in an oN state, the second And a source driver that controls the third switch element to be in an OFF state. The first output amplifying means is controlled to be in a high impedance state during the first predetermined period immediately after the polarity of the voltage corresponding to the image data is inverted by the inverting means, and the second output amplifying means is in an amplifier operating state. Controlling the first and fourth switch elements to an off state, controlling the second and third switch elements to an on state,
In a second predetermined period after the end of the first predetermined period, the first and second output amplifying means are controlled to be in an amplifier operating state, and the first and fourth switch elements are controlled to be in an on state. , Controlling the second and third switch elements to an off state,
After the second predetermined period, the first output amplifying unit is controlled to be in an amplifier operating state until the voltage corresponding to the image data is next inverted in polarity by the inverting unit, and the second output amplifying unit is set to a high impedance state. 2. The source driver according to claim 1, wherein the source driver is controlled to be in a state, the first and fourth switch elements are controlled to be in an on state, and the second and third switch elements are controlled to be in an off state.   The first predetermined period is a period in which the potential of the column terminal of the liquid crystal panel is made equal to the reference potential, and the second predetermined period is the driving voltage applied from the output terminal to the column terminal of the liquid crystal panel. 3. The source driver according to claim 2, wherein is a period until the voltage stabilizes to a voltage corresponding to a gradation indicated by the image data.   2. The source driver according to claim 1, wherein the current output capability of the first output amplifying means is greater than the current output capability of the second output amplifying means.   The source driver according to claim 1, wherein the predetermined period is a line scanning period of the liquid crystal panel.   Each of the plurality of amplifiers is formed of a semiconductor integrated circuit, and each of the first and second output amplifying units is configured by a plurality of field effect transistors in which gates are arranged in a comb shape, depending on the number of the field effect transistors. 5. The source driver according to claim 4, wherein a current output capability of each of the first and second output amplifying means is determined. Inversion means for outputting the voltage corresponding to the image data for each column of the active matrix type liquid crystal panel by inverting the polarity at a predetermined cycle with respect to the reference potential;
A source driver comprising: a plurality of amplifiers composed of voltage followers that output a drive voltage from an output terminal to a column terminal of the liquid crystal panel according to an output voltage of the inverting means at the predetermined period;
Each of the plurality of amplifiers includes differential amplification means for inputting the output voltage of the inverting means at a non-inverting input terminal,
First and second output amplifying means to which the output voltage of the differential amplifying means is supplied as an input voltage, respectively,
And controls the high-impedance state in response to a first control signal to the first output amplifier means during a predetermined period immediately after the voltage corresponding to the image data is polarity inverted by said inverting means, said second output amplifier And controlling the output terminal of the second output amplifying means and the differential between the output terminal of the second amplifying means and the inverting input terminal of the differential amplifying means. controls between the inverting input terminal of the amplifying means in the connected state, and the is the potential of the output terminal charge sharing that converges to the reference potential row Umono, the reversing means after completion of the first predetermined time period and it controls the amplifier operating state in response to a control signal of the first output amplification means within until a voltage corresponding to the image data is then polarity inverted by the output end of the second output amplification means A power terminal and between the output terminal and the inverting input terminal of the differential amplifying means are respectively controlled to be connected, and an output terminal of the second output amplifying means and an inverting input terminal of the differential amplifying means A source driver, wherein the charge sharing is stopped and the charge sharing is stopped.

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