JP5468196B2 - Semiconductor device, display device, and liquid crystal display device - Google Patents

Description

  The present invention relates to a display device having a circuit formed using a transistor. In particular, the present invention relates to a display device using an electro-optical element such as a liquid crystal element or a light-emitting element as a display medium, and a driving method thereof.

  In recent years, the development of display devices has been actively promoted due to an increase in large display devices such as liquid crystal televisions. In particular, a technique for integrally forming a drive circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate In order to greatly contribute to the reduction of power consumption and cost, development is being actively promoted. An internal circuit formed on the insulating substrate is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC (Flexible Printed Circuit) or the like, and its operation is controlled.

  Among the internal circuits shown above, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised. A structure of a flip-flop included in a conventional shift register is illustrated in FIG. The flip-flop in FIG. 100A includes a transistor 11 (bootstrap transistor), a transistor 12, a transistor 13, a transistor 14, a transistor 15, a transistor 16, and a transistor 17, and includes a signal line 21, a signal line 22, and a wiring 23. , Signal line 24, power supply line 25, and power supply line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. The operation period of the flip-flop in FIG. 100A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in the timing chart of FIG.

  In the set period, an H signal is input from the signal line 21 and the potential of the node 41 is increased to VDD−Vth15 (Vth15: threshold voltage of the transistor 15), so that the node 41 is in a floating state while the transistor 11 is on. It is said. Since the transistor 16 is turned on when an H signal is input from the signal line 21, the transistor 14 whose gate electrode is connected to the node 41 is turned on, and the potential of the node 42 is set to the L level. 16 is off. That is, charges leaked from the gate electrode of the transistor 11 during a period from when the H signal was input to the signal line 21 to when the transistor 16 was turned off.

  Here, a signal whose potential is VDD is called an H signal, and a signal whose potential is VSS is called an L signal. The L level means that the potential of the L signal is VSS.

The display devices of Non-Patent Document 1 and Non-Patent Document 2 use a shift register formed of an amorphous silicon transistor as a scanning line driving circuit, and further receive a video signal from one signal line to R, G, and B sub-pixels. By inputting, the number of signal lines is reduced to 1/3. Thus, the display devices of Non-Patent Document 1 and Non-Patent Document 2 reduce the number of connections between the display panel and the driver IC.
JP 2004-157508 A Jin Young Choi, et al. , “A Compact and Cost-Efficient TFT-LCD through the Triple-Gate Pixel Structure II, SOCIETY FOR INFORMATION DISPLAY PICTURE VISION TECHNO TECHN 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNIONAL SYMPOSIUM DIGITAL OF TECHNICAL PAPERS, X. 1083-1086

  According to the conventional technique, the gate electrode of the bootstrap transistor is in a floating state while the bootstrap transistor is on. However, the conventional technique has a problem that it cannot be operated at high speed because it takes time until the gate electrode of the bootstrap transistor is brought into a floating state while the bootstrap transistor is turned on. Further, when amorphous silicon is used as the semiconductor layer of the transistor, there is a problem that a threshold voltage shift of the transistor occurs. Furthermore, it has been proposed to reduce the number of signal lines to 1/3 to reduce the number of contact points between the display panel and the driver IC (Non-Patent Document 1 and Non-Patent Document 2). There is a need to further reduce the number of IC contacts.

  That is, as a problem that cannot be solved by the conventional technique, a circuit technique that allows the shift register to operate at high speed and a circuit technique that suppresses fluctuations in the threshold voltage of the transistor remain as problems. In addition, a technique for reducing the number of contacts of a driver IC mounted on a display panel, a reduction in power consumption of the display device, and an increase in size or definition of the display device remain as problems.

  In the display device of this specification, a switch controlled by a start signal is provided in a gate electrode of a transistor connected to a gate electrode of a bootstrap transistor. When a start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. When the transistor is turned off, charge leakage from the gate electrode of the bootstrap transistor can be prevented. Therefore, since the time for charging the gate electrode of the bootstrap transistor can be shortened, the operation can be performed at high speed.

  The switch shown in this document (the specification, the claims, the drawings, or the like) can have various forms. Examples include electrical switches and mechanical switches. That is, it is only necessary to be able to control the current flow, and is not limited to a specific one. For example, as a switch, a transistor (for example, bipolar transistor, MOS transistor, etc.), a diode (for example, PN diode, PIN diode, Schottky diode, MIM (Metal Insulator Metal) diode, MIS (Metal Insulator Semiconductor) diode, diode-connected Transistor), a thyristor, or the like can be used. In addition, a logic circuit combining these can be used as a switch.

  In the case where a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress off-state current, it is desirable to use a transistor having a polarity with smaller off-state current. Examples of a transistor with low off-state current include a transistor having an LDD region and a transistor having a multi-gate structure. In the case where the transistor operates as a switch when the potential of the source terminal of the transistor is close to a low potential power source (Vss, GND, 0 V, or the like), an N-channel transistor is preferably used. On the other hand, in the case where the source terminal operates in a state close to a high potential side power supply (Vdd or the like), it is desirable to use a P-channel transistor. This is because when the source terminal of the N-channel transistor operates in a state close to the low-potential side power supply or when the source terminal of the P-channel transistor operates in a state close to the high-potential side power supply, This is because the absolute value can be increased and the switch can be easily turned on or off. In addition, since the transistor rarely performs a source follower operation, the output voltage is less likely to decrease.

  A CMOS switch may be used as a switch by using both an N-channel transistor and a P-channel transistor. When a CMOS switch is used, a current flows when either the P-channel transistor or the N-channel transistor is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

  When a transistor is used as a switch, the switch includes an input terminal (one of a source terminal and a drain terminal), an output terminal (the other of the source terminal and the drain terminal), and a terminal that controls conduction (a gate terminal). ing. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, the use of a diode as a switch rather than a transistor can reduce the wiring for controlling the terminal.

  In this specification, when it is explicitly described that A and B are connected, A and B are electrically connected, and A and B are functionally connected , A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the configuration disclosed in this specification is not limited to a predetermined connection relationship, for example, the connection relationship illustrated in the drawing or text, and includes other than the connection relationship illustrated in the drawing or text.

  For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistance element, or a diode) that enables electrical connection between A and B is A 1 or more may be arranged between B and B. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (DA Conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level), voltage source, current source, switching circuit, amplification One circuit between A and B (circuit that can increase signal amplitude or current, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) It may be arranged above. Alternatively, when A and B are directly connected, A and B may be directly connected without interposing another element or other circuit between A and B.

  When it is explicitly stated that A and B are directly connected, when A and B are directly connected (that is, no other element or other circuit is interposed between A and B) And A and B are electrically connected (that is, connected with another element or circuit between A and B). Shall be.

  When it is explicitly described that A and B are electrically connected, when A and B are electrically connected (that is, another element or another circuit is connected between A and B). A) and B are functionally connected (that is, functionally connected with another circuit between A and B), and A and B The case where B is directly connected (that is, the case where A and B are connected without sandwiching another element or another circuit) is included. That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  A display element, a display device that is a device having a display element, a light-emitting element, and a light-emitting device that is a device having a light-emitting element can be used in various forms and can have various elements. For example, as a display element, a display device, a light-emitting element, or a light-emitting device, an EL element (an organic EL element, an inorganic EL element or an EL element containing an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, an electrophoretic element, Display media whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action, such as grating light valve (GLV), plasma display (PDP), digital micromirror device (DMD), piezoelectric ceramic display, and carbon nanotube Can be used. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). Liquid crystal displays (transmission type liquid crystal display, transflective type liquid crystal display, reflection type liquid crystal display, direct view type liquid crystal display, projection type liquid crystal display), display devices using electronic ink and electrophoretic elements There is electronic paper.

  As the transistor described in this document (the specification, the claims, the drawings, or the like), various types of transistors can be used. Thus, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like can be used. When using TFT, there are various advantages. For example, since manufacturing can be performed at a lower temperature than that of single crystal silicon, manufacturing cost can be reduced or a manufacturing apparatus can be increased in size. Transistors can be manufactured on a large substrate by increasing the size of the manufacturing apparatus. As a result, a large number of display devices can be manufactured at low cost at the same time. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. As a result, transmission of light through the display element can be controlled using a transistor on a transparent substrate. Alternatively, since the thickness of the transistor is small, part of the film included in the transistor can transmit light. As a result, the aperture ratio can be improved.

  By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with good electrical characteristics. As a result, a gate driver circuit (scanning line driving circuit), a source driver circuit (signal line driving circuit), and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate. .

  By using a catalyst (such as nickel) when manufacturing microcrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with good electrical characteristics. At this time, crystallinity can be improved only by performing heat treatment without using a laser. As a result, part of the gate driver circuit (scanning line driving circuit) and the source driver circuit (such as an analog switch) can be formed over the substrate. Further, when a laser is not used for crystallization, unevenness in crystallinity of silicon can be suppressed. As a result, an image with improved image quality can be displayed.

  However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

  A transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. Accordingly, a transistor with small variations in characteristics, size, shape, and the like, high current supply capability, and small size can be manufactured. When these transistors are used, low power consumption of the circuit or high integration of the circuit can be achieved.

  Usable transistors include zinc oxide (ZnO), amorphous oxide (a-InGaZnO), silicon germanium (SiGe), gallium arsenide (GaAs), indium zinc oxide (IZO), indium tin oxide (ITO), tin oxide There are a transistor having a compound semiconductor such as (SnO) or an oxide semiconductor, and a thin film transistor in which these compound semiconductor or oxide semiconductor is thinned. Accordingly, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, the transistor can be formed directly on a substrate having low heat resistance, for example, a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors can be used not only for a channel portion of a transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Furthermore, since they can be formed or formed simultaneously with the transistor, cost can be reduced.

  As a transistor that can be used, a transistor formed using an inkjet method or a printing method is given. Accordingly, the transistor can be manufactured at room temperature, manufactured at a low degree of vacuum, or manufactured over a large substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost is reduced and the number of processes can be reduced. Further, since a film is formed only on a necessary portion, the material is not wasted and cost can be reduced as compared with a manufacturing method in which etching is performed after film formation on the entire surface.

  As a transistor that can be used, there are an organic semiconductor, a transistor having a carbon nanotube, and the like. Thus, a transistor can be formed over a substrate that can be bent. Therefore, an apparatus using a transistor having an organic semiconductor or a carbon nanotube can be strong against impact.

  In addition, various transistors can be used.

  Various types of substrates on which transistors are formed can be used, and are not limited to specific types. As a substrate on which a transistor is formed, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp) ), Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. Can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a transistor may be formed using a certain substrate and then transferred to another substrate. As a substrate to which the transistor is transferred, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), Use synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foils, etc. Can do. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as a substrate on which the transistor is transferred. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, or reduce weight.

  The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is employed, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, the off-state current can be reduced and the reliability can be improved by improving the withstand voltage of the transistor. Alternatively, when operating in a saturation region, the multi-gate structure can obtain a voltage / current characteristic in which the drain-source current does not change much even if the drain-source voltage changes, and the slope is flat. . By using voltage / current characteristics with a flat slope, it is possible to realize an ideal current source circuit and an active load having a very high resistance value. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By employing a structure in which the gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased or the S value can be reduced due to the ease of forming a depletion layer. When gate electrodes are provided above and below a channel, a plurality of transistors are connected in parallel.

  In addition, a structure in which a gate electrode is disposed over a channel region may be employed, or a structure in which a gate electrode is disposed under a channel region may be employed. Alternatively, a normal stagger structure or an inverted stagger structure may be used, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. Good. In addition, a source electrode or a drain electrode may overlap with the channel region (or a part thereof). With the structure in which the source electrode or the drain electrode overlaps with the channel region (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel region and unstable operation. Further, an LDD region may be provided. By providing the LDD region, the off-state current can be reduced or the reliability can be improved by improving the withstand voltage of the transistor. Alternatively, by providing an LDD region, when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change so much, and the slope of the voltage-current characteristic is flat. can do.

  Various types of transistors can be used in this specification and can be formed over various substrates. Therefore, all the circuits necessary for realizing the predetermined function may be formed on the same substrate. For example, all the circuits necessary for realizing a predetermined function may be formed on a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, or other various substrates. It may be. Since all the circuits necessary to realize a given function are formed on the same board, the number of parts is reduced, the cost is reduced, and the number of connection points with circuit parts is reduced, thereby improving the reliability. be able to. Alternatively, a part of the circuit necessary for realizing the predetermined function is formed on a certain substrate, and another part of the circuit necessary for realizing the predetermined function is formed on another substrate. It may be formed. That is, all the circuits necessary for realizing the predetermined function may not be formed on the same substrate. For example, a part of a circuit necessary for realizing a predetermined function is formed using a transistor over a glass substrate, and another part of a circuit required for realizing a predetermined function is a single crystal substrate. The IC chip formed on the single crystal substrate and formed of a transistor may be connected to the glass substrate by COG (Chip On Glass), and the IC chip may be arranged on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board. As described above, since a part of the circuit is formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with the circuit parts can be reduced to improve the reliability. In addition, since the power consumption of a circuit having a high driving voltage or a high driving frequency is large, such a circuit is not formed on the same substrate. Instead, the circuit is formed on a single crystal substrate. If a circuit for that portion is formed and an IC chip constituted by the circuit is used, an increase in power consumption can be prevented.

  In this specification, one pixel represents one element whose brightness can be controlled. As an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is composed of three pixels, an R pixel, a G pixel, and a B pixel. Shall be. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, W (white) may be added to obtain RGBW. Further, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such a color element, it is possible to display an image closer to the real object and to reduce power consumption. As another example, when brightness is controlled using a plurality of areas for one color element, one area may be used as one pixel. As an example, when area gradation is performed or when sub-pixels (sub-pixels) are provided, there are a plurality of areas for controlling brightness for each color element, and the gradation is expressed as a whole. One area for controlling the brightness may be one pixel. In that case, one color element is composed of a plurality of pixels. Alternatively, even if there are a plurality of areas for controlling the brightness in one color element, they may be combined into one pixel. In that case, one color element is composed of one pixel. When brightness is controlled using a plurality of areas for one color element, the size of the area contributing to display may be different depending on the pixel. In that case, the viewing angle may be widened by slightly varying the signals supplied to each of the areas for controlling the brightness, which are plural for each color element. That is, for one color element, the potentials of the pixel electrodes in each of a plurality of regions may be different from each other. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

  Note that when explicitly described as one pixel (for three colors), three pixels of R, G, and B are considered as one pixel. When one pixel (for one color) is explicitly described, when there are a plurality of regions for one color element, they are collectively considered as one pixel.

  In this document, the pixels may be arranged (arranged) in a matrix. Here, the pixel being arranged (arranged) in the matrix includes a case where the pixels are arranged in a straight line or a jagged line in the vertical direction or the horizontal direction. For example, when full-color display is performed with three color elements (for example, RGB), this includes a case where stripes are arranged and a case where dots of three color elements are arranged in a delta arrangement. Furthermore, the case where a Bayer is arranged is included. The color elements are not limited to three colors and may be more than that. For example, there are RGBW (W is white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. Further, the size of the display area may be different for each dot of the color element. This can reduce power consumption or extend the life of the display element.

  In this document, an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

  In the active matrix system, not only transistors but also various active elements (active elements, nonlinear elements) can be used as active elements (active elements, nonlinear elements). For example, MIM (Metal Insulator Metal) or TFD (Thin Film Diode) can be used. Since these elements have few manufacturing steps, manufacturing cost can be reduced or yield can be improved. Further, since the element size is small, the aperture ratio can be improved, and power consumption and luminance can be increased.

  As a method other than the active matrix method, a passive matrix type that does not use an active element (an active element or a non-linear element) can be used. Since no active element (active element or nonlinear element) is used, the number of manufacturing steps is small, and manufacturing costs can be reduced or yield can be improved. In addition, since an active element (an active element or a non-linear element) is not used, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

  A transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region. The drain region, the channel region, and the source Current can flow through the region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this specification, a region functioning as a source and a drain may not be referred to as a source or a drain. In that case, they may be referred to as a first terminal and a second terminal, respectively. Alternatively, they may be referred to as a first electrode and a second electrode, respectively. Alternatively, they may be referred to as a source region and a drain region.

  The transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, the emitter and the collector may be referred to as a first terminal and a second terminal.

  A gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, a scanning line, a scanning signal line, or the like). A gate electrode refers to a portion of a conductive film which overlaps with a semiconductor forming a channel region with a gate insulating film interposed therebetween. Note that a part of the gate electrode may overlap an LDD (Lightly Doped Drain) region, a source region, or a drain region with a gate insulating film interposed therebetween. The gate wiring is a wiring for connecting between the gate electrodes of each transistor, a wiring for connecting between the gate electrodes of each pixel, or a wiring for connecting the gate electrode to another wiring. I mean.

  However, there are portions (regions, conductive films, wirings, and the like) that also function as gate electrodes and function as gate wirings. Such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring extended and the channel region overlaps, the portion (region, conductive film, wiring, etc.) functions as a gate wiring, but also as a gate electrode It is functioning. Therefore, such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring.

  A portion (a region, a conductive film, a wiring, or the like) that is formed using the same material as the gate electrode and is connected to form the same island (island) as the gate electrode may be called a gate electrode. Similarly, a portion (a region, a conductive film, a wiring, or the like) that is formed using the same material as the gate wiring and is connected to form the same island (island) as the gate wiring may be called a gate wiring. In a strict sense, such a portion (region, conductive film, wiring, or the like) may not overlap with the channel region or may not have a function of being connected to another gate electrode. However, there are portions (regions, conductive films, wirings, and the like) that are formed using the same material as the gate electrode or the gate wiring and are connected by forming the same island as the gate electrode or the gate wiring. Therefore, such a portion (region, conductive film, wiring, or the like) may also be called a gate electrode or a gate wiring.

  For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film formed using the same material as the gate electrode. Such a portion (region, conductive film, wiring, or the like) is a portion (region, conductive film, wiring, or the like) for connecting the gate electrode and the gate electrode, and may be called a gate wiring. A multi-gate transistor can be regarded as a single transistor, and thus may be referred to as a gate electrode. That is, a portion (region, conductive film, wiring, or the like) that is formed using the same material as the gate electrode or gate wiring and is connected to form the same island (island) as the gate electrode or gate wiring is connected to the gate electrode or gate wiring. You may call it. Further, a conductive film in a portion where the gate electrode and the gate wiring are connected and formed using a material different from that of the gate electrode or the gate wiring may be referred to as a gate electrode. You may call it.

  The gate terminal refers to a part of a portion of the gate electrode (region, conductive film, wiring, or the like) or a portion (region, conductive film, wiring, or the like) electrically connected to the gate electrode.

  In the case where a wiring is called a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are formed using the same layer as the gate of the transistor, the wiring formed of the same material as the gate of the transistor, or the gate of the transistor. It may mean a wiring formed at the same time. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

  A source refers to the whole or a part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, or the like). A source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a small amount of P-type impurities and N-type impurities, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode may be referred to as a source electrode including the source region. The source wiring is a wiring for connecting the source electrodes of the transistors, a wiring for connecting the source electrodes of each pixel, or a wiring for connecting the source electrode to another wiring. I mean.

  However, there are portions (regions, conductive films, wirings, and the like) that function as source electrodes and also function as source wirings. Such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when a part of the source wiring that is extended and the source region overlap, the portion (region, conductive film, wiring, etc.) functions as the source wiring, but also as the source electrode It is functioning. Thus, such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring.

  A portion (region, conductive film, wiring, or the like) that is formed of the same material as the source electrode and forms the same island (island) as the source electrode, or a portion that connects the source electrode and the source electrode (region, conductive film) , Wiring, etc.) may also be referred to as source electrodes. Further, a portion overlapping with the source region may be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected by forming the same island (island) as the source wiring may be called a source wiring. Such a portion (region, conductive film, wiring, or the like) may not have a function of connecting to another source electrode in a strict sense. However, there is a portion (a region, a conductive film, a wiring, or the like) formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring. Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a source electrode or a source wiring.

  For example, a conductive film that is a portion of a conductive film that connects a source electrode and a source wiring and is formed using a material different from that of the source electrode or the source wiring may be called a source electrode or a source wiring. But you can.

  A source terminal refers to a part of a source region, a source electrode, or a portion (region, conductive film, wiring, or the like) electrically connected to the source electrode.

  In the case where a wiring is referred to as a source wiring, a source line, a source signal line, a data line, a data signal line, or the like, the source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are the wiring formed in the same layer as the source (drain) of the transistor and the wiring formed of the same material as the source (drain) of the transistor. Or a wiring formed at the same time as the source (drain) of the transistor. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

  The drain is the same as the source.

  A semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, a thyristor, or the like). Furthermore, a device that can function by utilizing semiconductor characteristics may be called a semiconductor device.

  Display elements include optical modulation elements, liquid crystal elements, light emitting elements, EL elements (organic EL elements, inorganic EL elements or EL elements containing organic and inorganic substances), electron emitting elements, electrophoretic elements, discharge elements, light reflecting elements, An optical diffraction element, DMD, etc. However, it is not limited to these.

  A display device refers to a device having a display element. Note that a display device refers to a display panel body in which a plurality of pixels including a display element or a peripheral driver circuit for driving the pixels is formed over the same substrate. Note that the display device may include a peripheral driver circuit disposed on the substrate by wire bonding, bumps, or the like, an IC chip connected by COG, or an IC chip connected by TAB or the like. Further, the display device may include an FPC to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, and the like are attached. Further, the display device may include a printed wiring board (PWB) connected via an FPC or the like, to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, and the like are attached. Furthermore, the display device may include an optical sheet such as a polarizing plate or a retardation plate. Furthermore, the display device may include a lighting device, a housing, a voice input / output device, a light sensor, and the like. Here, the illumination device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type) and the like. Good.

  The illumination device refers to a device having a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, and the like.

  A light-emitting device refers to a device having a light-emitting element or the like.

  The reflection device refers to a device having a light reflection element, a light diffraction element, a light reflection electrode, and the like.

  A liquid crystal display device refers to a display device having a liquid crystal element. Liquid crystal display devices include direct view type, projection type, transmission type, reflection type, and transflective type.

  A driving device refers to a device having a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor or a switching transistor), a transistor that supplies voltage or current to a pixel electrode, or a voltage or current to a light-emitting element A transistor that supplies the voltage is an example of a driving device. Further, a circuit for supplying a signal to the gate signal line (sometimes referred to as a gate driver or a gate line driver circuit) and a circuit for supplying a signal to the source signal line (sometimes referred to as a source driver or source line driver circuit). ) Is an example of a driving device.

  In some cases, a display device, a semiconductor device, a lighting device, a cooling device, a light emitting device, a reflecting device, a driving device, and the like overlap each other. For example, the display device may include a semiconductor device and a light-emitting device. Alternatively, the semiconductor device may include a display device and a driving device.

  In this document, when it is explicitly stated that B is formed on A or B is formed on A, B must be formed on A directly in contact with A It is not limited to. The case where the object is not in direct contact, that is, the case where another object is interposed between A and B is also included. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  For example, when it is explicitly stated that the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A. And the case where another layer (for example, layer C or layer D) is formed in direct contact with the layer A and the layer B is formed thereon. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

  Furthermore, the same applies to the case where B is explicitly described as being formed above A, and is not limited to the direct contact of B on A. This includes the case where another object is interposed in. For example, when the layer B is formed above the layer A, when the layer B is formed in direct contact with the layer A, another layer (directly in contact with the layer A ( For example, the layer C and the layer D) are formed, and the layer B is formed thereon. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

  When it is explicitly stated that B is formed directly on A, it includes only the case where B is formed directly on A and includes another object between A and B. It shall not be included when objects are present.

  The same applies to the case where B is below A or B is below A.

  With the structure described in this specification, the shift register can operate at high speed. In particular, even when amorphous silicon is used for the semiconductor layer of the transistor, the shift register can be operated at high speed. Therefore, a semiconductor device to which the shift register such as a liquid crystal display device is applied can be operated at high speed, and can be easily increased in size or definition.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the structure of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit are described.

  A basic structure of the flip-flop of this embodiment is described with reference to FIG. The flip-flop illustrated in FIG. 1A includes a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, and a seventh transistor. A transistor 107 and an eighth transistor 108 are included. In this embodiment, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, the seventh transistor 107, and the eighth transistor The transistor 108 is an N-channel transistor and becomes conductive when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

  The flip-flop of this embodiment is characterized in that the first transistor 101 to the eighth transistor 108 are all N-channel transistors. In the flip-flop of this embodiment, amorphous silicon can be used as a semiconductor layer of a transistor. Therefore, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. However, the manufacturing process can be simplified even when polysilicon or single crystal silicon is used for the semiconductor layer of the transistor.

  A connection relation of the flip-flop in FIG. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is the first electrode. 3 wiring 123. A first electrode of the second transistor 102 is connected to the fourth wiring 124, and a second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the gate of the third transistor 103 The electrode is connected to the sixth wiring 126. The first electrode of the fourth transistor 104 is connected to the eighth wiring 128, the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate of the fourth transistor 104 The electrode is connected to the gate electrode of the first transistor 101. The first electrode of the fifth transistor 105 is connected to the seventh wiring 127, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate of the fifth transistor 105 The electrode is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the tenth wiring 130, the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and the gate of the sixth transistor 106 The electrode is connected to the gate electrode of the second transistor 102. The first electrode of the seventh transistor 107 is connected to the eleventh wiring 131, the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 101, and the gate of the seventh transistor 107 The electrode is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the ninth wiring 129, the second electrode of the eighth transistor 108 is connected to the gate electrode of the second transistor 102, and the gate of the eighth transistor 108 The electrode is connected to the first wiring 121.

  The gate electrode of the first transistor 101, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107 This connection location is referred to as a node 141. The gate electrode of the second transistor 102, the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, the gate electrode of the sixth transistor 106, and the second electrode of the eighth transistor 108 Is a node 142.

  The first wiring 121, the second wiring 122, the third wiring 123, and the fifth wiring 125 are respectively connected to the first signal line, the second signal line, the third signal line, and the fourth signal line. You may call it. In addition, the fourth wiring 124, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are respectively connected to the first power supply. May be referred to as a line, a second power line, a third power line, a fourth power line, a fifth power line, a sixth power line, and a seventh power line.

  Next, operation of the flip-flop illustrated in FIG. 1A is described with reference to a timing chart of FIG. 2 and FIG. Further, the timing chart of FIG. 2 will be described by being divided into a set period, a selection period, a reset period, and a non-selection period. However, the set period, the reset period, and the non-selection period may be collectively referred to as a non-selection period.

  The sixth wiring 126 and the seventh wiring 127 are supplied with the potential V1. The potential of V2 is supplied to the fourth wiring 124, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131. Here, V1> V2. A signal having a potential V1 is referred to as an H signal, and a signal having a potential V2 is referred to as an L signal.

  Signals 221, 225, and 222 shown in FIG. 2 are input to the first wiring 121, the fifth wiring 125, and the second wiring 122, respectively. A signal 223 shown in FIG. 2 is output from the third wiring 123. Here, the signal 221, the signal 225, the signal 222, and the signal 223 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). . Further, the signal 221, the signal 225, the signal 222, and the signal 223 may be referred to as a start signal, a clock signal, a reset signal, and an output signal, respectively.

  Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the fourth wiring 124 to the eleventh wiring 131, respectively.

  In the set period shown in FIGS. 2A and 3A, the signal 221 becomes H level and the fifth transistor 105 and the eighth transistor 108 are turned on. Further, since the signal 222 is at the L level, the seventh transistor 107 is turned off. At this time, the potential of the node 141 (the potential 241) is obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the seventh wiring 127 with the second electrode of the fifth transistor 105 serving as a source electrode. Therefore, V1−Vth105 (Vth105: threshold voltage of the fifth transistor 105). Accordingly, the first transistor 101 and the fourth transistor 104 are turned on, and the fifth transistor 105 is turned off. At this time, a potential difference (V1−V2) between the potential (V2) of the eighth wiring 128 and the potential (V1) of the sixth wiring 126 is the potential of the node 142 (potential 242). The voltage is divided by the fourth transistor 104 and the eighth transistor 108 to be V2 + β (β: any positive number). Note that β <Vth102 (Vth102: threshold voltage of the second transistor 102) and β <Vth106 (threshold voltage of the sixth transistor 106). Accordingly, the second transistor 102 and the sixth transistor 106 are turned off. In this manner, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input, and thus the potential of the third wiring 123 is V2. Therefore, the L signal is output from the third wiring 123. Further, the node 141 is in a floating state with the potential maintained at V1−Vth105.

  The third transistor 103 and the fourth transistor 104 constitute an inverter having a node 141 as an input terminal and a node 142 as an output terminal. Therefore, the flip-flop in this embodiment only needs to be provided with a circuit functioning as an inverter between the node 141 and the node 142.

  In the flip-flop of this embodiment, V2 is supplied to the node 142 through the eighth transistor 108, and the timing at which the sixth transistor 106 is turned off is advanced. Therefore, the time during which the potential of the node 142 is V1−Vth105 can be shortened. Therefore, the flip-flop of this embodiment can operate at high speed and can be applied to a larger display device or a higher definition display device.

  As shown in FIG. 4B, the flip-flop of this embodiment operates in the same manner as the above-described set period even when the first electrode of the fifth transistor 105 is connected to the first wiring 121. Can do. As a result, the flip-flop in FIG. 4B does not require the seventh wiring 127, so that the yield can be improved. Further, the flip-flop in FIG. 4B can reduce the layout area.

  In order to set the potential of the node 142 to V2 + β, the value of the ratio W / L of the channel width W to the channel length L of the fourth transistor 104 is at least 10 times higher than the value of W / L of the third transistor 103. It is preferable to make it twice or more. Therefore, the transistor size (W × L) of the fourth transistor 104 is increased. Therefore, the value of the channel length L of the third transistor 103 is preferably larger than the value of the channel length L of the fourth transistor 104, more preferably 2 to 3 times. As a result, the transistor size of the fourth transistor 104 can be reduced, so that the layout area can be reduced.

  In the selection period illustrated in FIGS. 2B and 3B, the signal 221 is at the L level, and the fifth transistor 105 and the eighth transistor 108 are turned off. Further, since the signal 222 remains at the L level, the seventh transistor 107 remains off. At this time, the node 141 maintains the potential at V1−Vth105. Accordingly, the first transistor 101 and the fourth transistor 104 remain on. At this time, the node 142 maintains the potential at V2 + β. Accordingly, the second transistor 102 and the sixth transistor 106 remain off. Here, since the H signal is input to the fifth wiring 125, the potential of the third wiring 123 starts to increase. Then, the potential of the node 141 rises from V1−Vth105 by the bootstrap operation, and becomes V1 + Vth101 + α (Vth101: threshold voltage of the first transistor 101, α: any positive number). Therefore, the potential of the third wiring 123 is equal to the potential V1 of the fifth wiring 125. In this manner, in the selection period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 is V1. Therefore, the H signal is output from the third wiring 123.

  This bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. As illustrated in FIG. 1B, by providing the capacitor 151 between the gate electrode and the second electrode of the first transistor 101, a bootstrap operation can be performed stably, and the first transistor 101 Parasitic capacitance can be reduced. In the capacitor 151, a gate insulating film may be used as an insulating layer, and a gate electrode layer and a wiring layer may be used as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and a gate electrode layer and a semiconductor layer to which an impurity is added may be used as the conductive layer. Alternatively, an interlayer film (insulating film) may be used as the insulating layer, and a wiring layer and a transparent electrode layer may be used as the conductive layer. In the case where the capacitor 151 uses a gate electrode layer and a wiring layer as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101 and the wiring layer is connected to the second electrode of the first transistor 101. Good. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. Good. This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitor 151 is reduced.

  A transistor 152 may be used as the capacitor 151 as illustrated in FIG. The transistor 152 can function as a capacitor having a large capacitance component because the gate electrode is connected to the node 141 and the first electrode and the second electrode are connected to the third wiring 123. Note that the transistor 152 can function as a capacitor even when one of the first electrode and the second electrode is in a floating state.

  The first transistor 101 must supply an H signal to the third wiring 123. Therefore, in order to shorten the fall time and the rise time of the signal 223, the W / L value of the first transistor 101 is set to the W / L value of each of the first transistor 101 to the eighth transistor 108. It is desirable to maximize it.

  In the fifth transistor 105, the potential of the node 141 (the gate electrode of the first transistor 101) must be V1−Vth105 in the set period. Therefore, the value of W / L of the fifth transistor 105 is 1/2 times to 1/5 times, more preferably 1/3 times to 1/4 times the value of W / L of the first transistor 101. Good.

  In the reset period illustrated in FIGS. 2C and 3C, since the signal 221 remains at the L level, the fifth transistor 105 and the eighth transistor 108 remain off. Further, since the signal 222 is at the H level, the seventh transistor 107 is turned on. The potential of the node 141 at this time is V 2 because the potential (V 2) of the eleventh wiring 131 is supplied through the seventh transistor 107. Accordingly, the first transistor 101 and the fourth transistor 104 are turned off. The potential of the node 142 at this time is obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of the sixth wiring 126 with the second electrode of the third transistor 103 serving as a source electrode. Therefore, V1−Vth103 (Vth103: threshold voltage of the third transistor 103). Accordingly, the second transistor 102 and the sixth transistor 106 are turned on. In this manner, in the reset period, the third wiring 123 and the fourth wiring 124 to which V2 is supplied are electrically connected, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

  By delaying the turn-on timing of the seventh transistor 107, the fall time of the signal 223 can be shortened. This is because the L signal input to the fifth wiring 125 is supplied to the third wiring 123 through the first transistor 101 having a large W / L value.

  Even if the value of W / L of the seventh transistor 107 is reduced and the fall time until the potential of the node 141 becomes V2 is increased, the fall time of the signal 223 can be shortened. In this case, the W / L value of the seventh transistor 107 is 1/10 to 1/40 times the W / L value of the first transistor 101, more preferably 1/20 to 1/30 times. It is good to do.

  As illustrated in FIG. 4A, the potential of the node 142 can be set to V1 by using the resistor 401 instead of the third transistor 103. Therefore, the second transistor 102 and the sixth transistor 106 can be easily turned on, and the operation efficiency can be improved. In addition, as illustrated in FIG. 4C, the transistor 402 may be connected in parallel to the third transistor 103.

  In the non-selection period illustrated in FIGS. 2D and 3D, since the signal 221 remains at the L level, the fifth transistor 105 and the eighth transistor 108 remain off. Further, since the signal 222 becomes L level, the seventh transistor 107 is turned off. At this time, the node 142 maintains the potential at V1−Vth103. Therefore, the second transistor 102 and the sixth transistor 106 remain on. At this time, the potential of the node 141 remains V2 because V2 is supplied through the sixth transistor 106. Accordingly, the first transistor 101 and the fourth transistor 104 remain off. Thus, in the non-selection period, the third wiring 123 and the fourth wiring 124 to which V2 is supplied are brought into conduction, and thus the potential of the third wiring 123 remains V2. Therefore, the L signal is output from the third wiring 123.

  By making the potential supplied to the sixth wiring 126 smaller than V1, the potential of the node 142 can be reduced. Therefore, threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. Therefore, the flip-flop of this embodiment can suppress transistor characteristic deterioration even when amorphous silicon in which characteristic deterioration (threshold voltage shift) is noticeable is used as the semiconductor layer of the transistor.

  From the above, the flip-flop of this embodiment can shorten the rise time of the potential of the node 141 in the set period, and thus can operate at high speed and can be applied to a larger display device or a higher definition display device. .

  Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting timing for supplying the potential of the fifth wiring 125 to the third wiring 123. Further, it has a function of increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. The second transistor 102 has a function of selecting timing for supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 has a function of dividing the potential of the sixth wiring 126 and the potential of the eighth wiring 128 and functions as an element having a resistance component or a resistance element. The fourth transistor 104 has a function of selecting timing for supplying the potential of the eighth wiring 128 to the node 142 and functions as a switching transistor. The fifth transistor 105 has a function of selecting timing for supplying the potential of the seventh wiring 127 to the node 141 and functions as an input transistor. The sixth transistor 106 has a function of selecting timing for supplying the potential of the tenth wiring 130 to the node 141 and functions as a switching transistor. The seventh transistor 107 has a function of selecting timing for supplying the potential of the eleventh wiring 131 to the node 141 and functions as a switching transistor. The eighth transistor 108 has a function of selecting timing for supplying the potential of the ninth wiring 129 to the node 142 and functions as a switching transistor.

  Note that the first transistor 101 to the eighth transistor 108 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102, the fourth transistor 104, the sixth transistor 106, the seventh transistor 107, and the eighth transistor 108 that function as switching transistors can be diodes, CMOSs, and the like as long as they are elements having a switching function. An analog switch or various logic circuits may be applied. Further, as long as the fifth transistor 105 functioning as an input transistor has a function of increasing the potential of the node 141 and selecting a timing for turning it off, a PN junction diode or a diode-connected transistor is applied. Also good.

  As long as the transistor operates in the same manner as in FIG. 1, the arrangement and number of transistors are not limited to those in FIG. 1. As can be seen from FIG. 3 illustrating the operation of the flip-flop in FIG. 1A, in this embodiment, the set period, the selection period, the reset period, and the non-selection period are respectively shown in FIGS. It suffices that conduction is obtained as shown by the solid line in D). Therefore, transistors and other elements can be arranged and operated so as to satisfy this requirement. Transistors, other elements (such as resistance elements and capacitor elements), diodes, switches, and various logic circuits are newly arranged. Also good.

  Furthermore, the driving timing of the flip-flop of this embodiment mode is not limited to the timing chart of FIG. 2 as long as it operates similarly to FIG.

  For example, as illustrated in the timing chart of FIG. 6, the period during which an H signal is input to the first wiring 121, the second wiring 122, and the fifth wiring 125 may be shortened. In FIG. 6, the timing at which the signal switches from the L level to the H level is delayed by the period Ta1, and the timing at which the signal switches from the H level to the L level is advanced by the period Ta2, as compared with the timing chart of FIG. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring is small, so that power saving, malfunction prevention, and improvement in operation efficiency can be achieved. Further, the flip-flop to which the timing chart of FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 in the reset period. This is because the timing at which the potential of the node 141 becomes the L level is delayed by the period Ta1 + the period Ta2, so that the L signal input to the fifth wiring 125 has a large current capability (a large channel width). This is because the voltage is supplied to the third wiring 123 through the transistor 101. Note that portions common to the timing chart of FIG. 2 are denoted by common reference numerals and description thereof is omitted.

  The relationship between the period Ta1, the period Ta2, and the period Tb is preferably ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <10 [%]. More desirably, ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%] is desirable. Further, it is desirable that the period Ta1≈the period Ta2.

  The first wiring 121 to the eleventh wiring 131 can be freely connected as long as they operate in the same manner as in FIG. For example, as illustrated in FIG. 5A, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the seventh transistor 107 The first electrode of the eighth transistor 108 and the first electrode of the eighth transistor 108 may be connected to the sixth wiring 506. Further, the first electrode of the fifth transistor 105, the first electrode of the third transistor 103, and the gate electrode of the third transistor 103 may be connected to the fifth wiring 505. In addition, as illustrated in FIG. 5B, the first electrode of the third transistor 103 and the gate electrode of the third transistor 103 may be connected to the seventh wiring 507. Here, the first wiring 501, the second wiring 502, the third wiring 503, and the fourth wiring 504 are the first wiring 121, the second wiring 122, and the third wiring in FIG. 123 and the fifth wiring 125.

  The flip-flops in FIGS. 5A and 5B can reduce the number of wirings, so that yield can be improved and layout area can be reduced. Further, the flip-flops in FIGS. 5A and 5B can improve reliability and operating efficiency. Further, since the flip-flop in FIG. 5B can reduce the potential supplied to the sixth wiring 506, a shift in threshold voltage of the second transistor 102 and the sixth transistor 106 can be suppressed.

  FIG. 29 illustrates an example of a top view of the flip-flop illustrated in FIG. The conductive layer 2901 includes a portion functioning as the first electrode of the first transistor 101 and is connected to the fourth wiring 504 through the wiring 2951. The conductive layer 2902 includes a portion functioning as the second electrode of the first transistor 101 and is connected to the third wiring 503 through the wiring 2952. The conductive layer 2903 includes a portion functioning as the gate electrode of the first transistor 101 and the gate electrode of the fourth transistor 104. The conductive layer 2904 serves as the first electrode of the second transistor 102, the first electrode of the sixth transistor 106, the first electrode of the fourth transistor 104, and the first electrode of the eighth transistor 108. It includes a functioning portion and is connected to the sixth wiring 506. The conductive layer 2905 includes a portion functioning as the second electrode of the second transistor 102 and is connected to the third wiring 503 through the wiring 2954. The conductive layer 2906 includes a portion functioning as the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 106. The conductive layer 2907 includes a portion functioning as the first electrode of the third transistor 103 and is connected to the fifth wiring 505 through the wiring 2955. The conductive layer 2908 includes a portion functioning as the second electrode of the third transistor 103 and the second electrode of the fourth transistor 104, and is connected to the conductive layer 2906 through the wiring 2956. The conductive layer 2909 includes a portion functioning as the gate electrode of the third transistor 103 and is connected to the fifth wiring 505 through the wiring 2955. The conductive layer 2910 includes a portion functioning as the first electrode of the fifth transistor 105 and is connected to the fifth wiring 505 through the wiring 2959. The conductive layer 2911 includes a portion functioning as the second electrode of the fifth transistor 105 and the second electrode of the seventh transistor 107, and is connected to the conductive layer 2903 through the wiring 2958. The conductive layer 2912 includes a portion functioning as the gate electrode of the fifth transistor 105 and is connected to the first wiring 501 through the wiring 2960. The conductive layer 2913 includes a portion functioning as the second electrode of the sixth transistor 106 and is connected to the conductive layer 2903 through the wiring 2957. The conductive layer 2914 includes a portion functioning as the gate electrode of the seventh transistor 107 and is connected to the second wiring 502 through the wiring 2962. The conductive layer 2915 includes a portion functioning as the gate electrode of the eighth transistor 108 and is connected to the conductive layer 2912 through a wiring 2961. The conductive layer 2916 includes a portion functioning as the second electrode of the eighth transistor 108 and is connected to the conductive layer 2906 through the wiring 2953.

Here, the wiring 2962 is smaller in width than the wiring 2951, the wiring 2952, the wiring 2953, the wiring 2954, the wiring 2955, the wiring 2955, the wiring 2957, the wiring 2958, the wiring 2959, the wiring 2960, or the wiring 2961. And Alternatively, the length of the wiring is large. That is, the resistance value of the wiring 2962 is increased. Thus, the timing at which the potential of the conductive layer 2914 becomes H level can be delayed in the reset period. Accordingly, the timing at which the seventh transistor 107 is turned on can be delayed in the reset period, so that the signal of the third wiring 503 can be quickly set to the L level. This is because the timing at which the node 141 becomes L level is delayed, and the L signal is supplied to the third wiring 503 through the first transistor 101 during the delay period.

Note that the wiring 2951, the wiring 2952, the wiring 2953, the wiring 2054, the wiring 2955, the wiring 2957, the wiring 2957, the wiring 2958, the wiring 2959, the wiring 2960, the wiring 2961, and the wiring 2962 are also referred to as pixel electrodes (or transparent electrodes or reflective electrodes). ) And is formed by similar processes and materials.

  The portions functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2981. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2982. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2983. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2984. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2985. The portions functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2986. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2987. The portions functioning as the gate electrode, the first electrode, and the second electrode of the eighth transistor 108 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2988.

  Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

  A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 7 includes n flip-flops (flip-flops 701_1 to 701_n).

  Connection relations of the shift register in FIG. 7 are described. In the shift register in FIG. 7, the i-th flip-flop 701 </ b> _i (any one of the flip-flops 701 </ b> _ <b> 1 to 701 </ b> _n) has the first wiring 121 illustrated in FIG. -1. The second wiring 122 illustrated in FIG. 1A is connected to the seventh wiring 717 — i + 1. The third wiring 123 illustrated in FIG. 1A is connected to the seventh wiring 717 — i. The fourth wiring 124, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. 1A are connected to the fifth wiring 715. The fifth wiring 125 illustrated in FIG. 1A is connected to the second wiring 712 in the odd-numbered flip-flops and connected to the third wiring 713 in the even-numbered flip-flops. The sixth wiring 126 and the seventh wiring 127 illustrated in FIG. 1A are connected to the fourth wiring 714. The first wiring 121 illustrated in FIG. 1A of the first flip-flop 701_1 is connected to the first wiring 711. Further, the second wiring 122 illustrated in FIG. 1A of the n-th flip-flop 701 — n is connected to the sixth wiring 716.

  The first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716 are respectively connected to the first signal line, the second signal line, the third signal line, and the fourth signal line. You may call it. Further, the fourth wiring 714 and the fifth wiring 715 may be referred to as a first power supply line and a second power supply line, respectively.

  Next, operation of the shift register illustrated in FIG. 10 is described with reference to a timing chart in FIG. 8 and a timing chart in FIG. The timing chart of FIG. 8 is divided into a scanning period and a blanking period. The scan period is a period from when the selection signal is output from the seventh wiring 717_1 to when the selection signal is output from the seventh wiring 717_n. The blanking period is a period from when the output of the selection signal from the seventh wiring 717 — n is finished until the output of the selection signal from the seventh wiring 717 — 1 is started.

  The fourth wiring 714 is supplied with the potential V1, and the fifth wiring 715 is supplied with the potential V2.

  The signal 811, the signal 812, the signal 813, and the signal 816 illustrated in FIG. 8 are input to the first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716, respectively. Here, the signal 811, the signal 812, the signal 813, and the signal 816 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2. Further, the signal 811, the signal 812, the signal 813, and the signal 816 may be referred to as a start signal, a first clock signal, a second clock signal (inverted clock signal), and a reset signal, respectively.

  Note that various signals, potentials, and currents may be input to the first wiring 711 to the sixth wiring 716, respectively.

  From the seventh wiring 717_1 to the seventh wiring 717_n, digital signals 817_1 to 817_n in which the potential of the H signal is V1 and the potential of the L signal is V2 are output, respectively. Note that as illustrated in FIG. 10, signals may be output from the seventh wiring 717_1 to the seventh wiring 717_n through the buffers 1001_1 to 1001_n, respectively. The shift register in FIG. 10 can be easily operated because the output signal of the shift register and the transfer signal of each flip-flop can be divided.

  Examples of the buffers 1001_1 to 1001_n included in the shift register illustrated in FIG. 10 are described with reference to FIGS. 99A and 99B. In the buffer 8000 illustrated in FIG. 99A, the inverter 8001a, the inverter 8001b, and the inverter 8001c are connected between the wiring 8011 and the wiring 8012, so that an inverted signal of the signal input to the wiring 8011 is output from the wiring 8012. Is done. However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited. For example, when an even number of inverters are connected between the wiring 8011 and the wiring 8012, the same signal as the signal input to the wiring 8011 is used. A polarity signal is output from the wiring 8012. Further, as shown in a buffer 8100 in FIG. 99B, an inverter 8002a, an inverter 8002b, and an inverter 8002c connected in series, and an inverter 8003a, an inverter 8003b, and an inverter 8003c arranged in series are connected in parallel. Also good. The buffer 8100 in FIG. 99B can average variation in transistor characteristics, so that delay and rounding of a signal output from the wiring 8012 can be reduced. Further, the outputs of inverter 8002a and inverter 8003a and the outputs of inverter 8002b and inverter 8003b may be connected.

  99A, it is preferable that W of the transistor included in the inverter 8001a <W of the transistor included in the inverter 8001b <W of the transistor included in the inverter 8001c. This is because when the transistor W included in the inverter 8001a is small, the driving capability of the flip-flop (specifically, the W / L value of the transistor 101 in FIG. 1A) can be reduced. This is because the layout area can be reduced. Similarly, in FIG. 99B, it is preferable that W of the transistor included in the inverter 8002a <W of the transistor included in the inverter 8002b <W of the transistor included in the inverter 8002c. Similarly, in FIG. 99B, it is preferable that W of the transistor included in the inverter 8003a <W of the transistor included in the inverter 8003b <W of the transistor included in the inverter 8003c. Further, W of the transistor included in the inverter 8002a = W of the transistor included in the inverter 8003a, W of the transistor included in the inverter 8002b = W of the transistor included in the inverter 8003b, W of the transistor included in the inverter 8002c = W of the transistor included in the inverter 8003c, It is preferable that

  There is no particular limitation on the inverter illustrated in FIGS. 99A and 99B as long as it can output an inverted signal. For example, as illustrated in FIG. 99C, an inverter may be formed using the first transistor 8201 and the second transistor 8202. Further, a signal is input to the first wiring 8211, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. . In the inverter in FIG. 99C, when an H signal is input to the first wiring 8211, a potential obtained by dividing V1-V2 by the first transistor 8201 and the second transistor 8202 (W / L of the first transistor 8201 <W / L of the second transistor 8202) is output from the second wiring 8212. Further, when the L signal is input to the first wiring 8211, the inverter in FIG. 99C outputs V1−Vth8201 (Vth8201: threshold voltage of the first transistor 8201) from the second wiring 8212. Further, the first transistor 8201 may be a PN junction diode or simply a resistance element as long as it is an element having a resistance component.

  As shown in FIG. 99D, an inverter may be formed using the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. A signal is input to the first wiring 8311, a signal is output from the second wiring 8312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and the fourth wiring 8314 and the sixth wiring 8315 The wiring 8316 is supplied with V2. The inverter in FIG. 99D outputs V2 from the second wiring 8312 when an H signal is input to the first wiring 8311. At this time, since the potential of the node 8341 is set to the L level, the first transistor 8301 is turned off. Further, when the L signal is input to the first wiring 8311, the inverter in FIG. 99D outputs V1 from the second wiring 8312. At this time, when the potential of the node 8341 becomes V1−Vth8303 (Vth8303: threshold voltage of the third transistor 8303), the node 8341 is in a floating state. As a result, the potential of the node 8341 becomes higher than V1 + Vth8301 (Vth8301: threshold voltage of the first transistor 8301) by the bootstrap operation, so that the first transistor 8301 is turned on. Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

  As shown in FIG. 30A, an inverter may be formed using the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 30A is a two-input inverter and can perform a bootstrap operation. A signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413. V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. The inverter in FIG. 30A outputs V2 from the third wiring 8413 when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412. At this time, since the potential of the node 8441 is V2, the first transistor 8401 is turned off. Further, when the H signal is input to the first wiring 8411 and the L signal is input to the second wiring 8412, the inverter in FIG. 30A outputs V1 from the third wiring 8413. At this time, when the potential of the node 8441 becomes V1−Vth8403 (Vth8403: threshold voltage of the third transistor 8403), the node 8441 is in a floating state. As a result, the potential of the node 8441 becomes higher than V1 + Vth8401 (Vth8401: threshold voltage of the first transistor 8401) by the bootstrap operation, so that the first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8411 and the second wiring 8412 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

  As shown in FIG. 30B, an inverter may be formed using the first transistor 8501, the second transistor 8502, and the third transistor 8503. The inverter in FIG. 30B is a two-input inverter and can perform a bootstrap operation. A signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, and a signal is output from the third wiring 8513. V1 is supplied to the fourth wiring 8514 and the sixth wiring 8516, and V2 is supplied to the fifth wiring 8515. The inverter in FIG. 30B outputs V2 from the third wiring 8513 when an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512. At this time, since the potential of the node 8541 is V2, the first transistor 8501 is turned off. Further, when the H signal is input to the first wiring 8511 and the L signal is input to the second wiring 8512, the inverter in FIG. 30B outputs V1 from the third wiring 8513. At this time, when the potential of the node 8541 becomes V1−Vth8503 (Vth8503: the threshold voltage of the third transistor 8503), the node 8541 is in a floating state. As a result, the potential of the node 8541 becomes higher than V1 + Vth8501 (Vth8501: the threshold voltage of the first transistor 8501) by the bootstrap operation, so that the first transistor 8501 is turned on. Further, since the first transistor 8501 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8511 and the second wiring 8512 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

  As shown in FIG. 30C, an inverter may be formed using the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 30C is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613. V1 is supplied to the fourth wiring 8614 and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. The inverter in FIG. 30C outputs V2 from the third wiring 8613 when an L signal is input to the first wiring 8611 and an H signal is input to the second wiring 8612. At this time, since the potential of the node 8641 becomes V2, the first transistor 8601 is turned off. Further, when an H signal is input to the first wiring 8611 and an L signal is input to the second wiring 8612, the inverter in FIG. 30C outputs V1 from the third wiring 8613. At this time, when the potential of the node 8641 becomes V1−Vth8603 (Vth8603: the threshold voltage of the third transistor 8603), the node 8641 is in a floating state. As a result, the potential of the node 8641 becomes higher than V1 + Vth8601 (Vth8601: threshold voltage of the first transistor 8601) by the bootstrap operation, so that the first transistor 8601 is turned on. Since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8611 and the second wiring 8612 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

  In FIG. 7, a signal output from the seventh wiring 717 — i−1 is used as a start signal of the flip-flop 701 — i and a signal output from the seventh wiring 717 — i + 1 is used as a reset signal. A start signal of the flip-flop 701_1 is input from the first wiring 711. The reset signal of the flip-flop 701 — n is input from the sixth wiring 716. Note that as the reset signal of the flip-flop 701_n, a signal output from the seventh wiring 717_1 may be used, or a signal output from the seventh wiring 717_2 may be used. Alternatively, a dummy flip-flop may be newly disposed and the output signal of the dummy flip-flop may be used. By doing so, the number of wirings and the number of signals can be reduced.

  As illustrated in FIG. 9, for example, when the flip-flop 701 — i enters the selection period, an H signal (selection signal) is output from the seventh wiring 717 — i. At this time, the flip-flop 701_i + 1 is in the set period. After that, the flip-flop 701 — i enters the reset period, and the L signal is output from the seventh wiring 717 — i. At this time, the flip-flop 701_i + 1 is in a selection period. After that, the flip-flop 701_i enters a non-selection period, and the L signal remains output from the seventh wiring 717_i. At this time, the flip-flop 701_i + 1 is in the reset period.

  In this manner, the shift register in FIG. 7 can output a selection signal from the seventh wiring 717_1 to the seventh wiring 717_n in order. That is, the shift register in FIG. 7 can scan the seventh wiring 717_1 to the seventh wiring 717_n.

  A shift register to which the flip-flop of this embodiment is applied can operate at high speed, and thus can be applied to a higher-definition display device or a larger display device. Further, in the shift register to which the flip-flop of this embodiment is applied, the process can be simplified, the manufacturing cost can be reduced, and the yield can be improved.

  Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

  A structure of the display device of this embodiment is described with reference to FIG. The display device in FIG. 11 includes a signal line driver circuit 1101, a scan line driver circuit 1102, and a pixel portion 1104. The pixel portion 1104 includes a plurality of signal lines S1 to Sm arranged extending from the signal line driver circuit 1101 in the column direction, and a plurality of scanning lines G1 to Gn arranged extending from the scanning line driver circuit 1102 in the row direction. And a plurality of pixels 1103 arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. Each pixel 1103 is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

  As the scan line driver circuit 1102, the shift register of this embodiment can be used. Needless to say, the shift register of this embodiment may also be used for the signal line driver circuit 1101.

  The scan lines G1 to Gn are connected to the seventh wiring 717_1 to the seventh wiring 717_n illustrated in FIGS.

  The signal line and the scanning line may be simply called wiring. Further, each of the signal line driver circuit 1101 and the scan line driver circuit 1102 may be referred to as a driver circuit.

  The pixel 1103 includes at least one switching element, one capacitor element, and a pixel electrode. Note that the pixel 1103 may include a plurality of switching elements or a plurality of capacitor elements. Furthermore, the capacitive element is not always necessary. The pixel 1103 may include a transistor that operates in a saturation region. The pixel 1103 may include a display element such as a liquid crystal element or an EL element. A transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is preferable that the transistor operates in a linear region. Further, in the case where the scan line driver circuit 1102 includes only N-channel transistors, it is preferable to use N-channel transistors as switching elements. Further, in the case where the scan line driver circuit 1102 includes only P-channel transistors, it is preferable to use P-channel transistors as switching elements.

  The scan line driver circuit 1102 and the pixel portion 1104 are formed over the insulating substrate 1105, and the signal line driver circuit 1101 is not formed over the insulating substrate 1105. The signal line driver circuit 1101 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1105. The signal line driver circuit 1101 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. Note that the signal line driver circuit 1101 may be formed over the insulating substrate 1105, or a circuit that forms part of the signal line driver circuit 1101 may be formed over the insulating substrate 1105.

  The signal line driver circuit 1101 inputs voltage or current as video signals to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the positive and negative electrodes of the video signal may be inverted every frame (frame inversion driving), and the positive and negative electrodes may be inverted every one row (gate line inversion driving). Alternatively, in the video signal, the positive electrode and the negative electrode may be inverted for each column (source line inversion driving), and the positive electrode and the negative electrode may be inverted for each row and column (dot inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or may be input by line sequential driving. Further, the signal line driver circuit 1101 may input not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm. It is desirable to input a constant voltage such as a precharge voltage every frame selection period and every frame.

  The scanning line driving circuit 1102 inputs signals to the scanning lines G1 to Gn, and selects the scanning lines G1 to Gn in order from the first row (hereinafter also referred to as scanning). Then, the scan line driver circuit 1102 selects a plurality of pixels 1103 connected to the selected scan line. Here, a period in which one scanning line is selected is referred to as one gate selection period, and a period in which the scanning line is not selected is referred to as a non-selection period. Further, a signal output from the scanning line driver circuit 1102 to the scanning line is referred to as a scanning signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line. .

  When the pixel 1103 is selected, a video signal is input from the signal line driver circuit 1101 to the pixel 1103 via the signal line. Further, when the pixel 1103 is not selected, the pixel 1103 holds a video signal (a potential corresponding to the video signal) input during the selection period.

  Although not illustrated, a plurality of potentials and a plurality of signals are supplied to the signal line driver circuit 1101 and the scan line driver circuit 1102.

  Next, the operation of the display device illustrated in FIG. 11 will be described with reference to the timing chart of FIG. FIG. 12 shows one frame period corresponding to a period for displaying an image for one screen. The period of one frame is not particularly limited, but is preferably 1/60 second or less so that a person viewing the image does not feel flicker.

  The timing chart of FIG. 12 shows the timing at which the first scanning line G1, the i-th scanning line Gi, the i + 1-th scanning line Gi + 1, and the n-th scanning line Gn are selected.

  In FIG. 12, for example, the i-th scanning line Gi is selected, and a plurality of pixels 1103 connected to the scanning line Gi are selected. Each of the plurality of pixels 1103 connected to the scanning line Gi receives a video signal and holds a potential corresponding to the video signal. Thereafter, the i-th scanning line Gi is deselected, the i + 1-th scanning line Gi + 1 is selected, and the plurality of pixels 1103 connected to the scanning line Gi + 1 are selected. Each of the plurality of pixels 1103 connected to the scanning line Gi + 1 receives a video signal and holds a potential corresponding to the video signal. In this manner, in one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1103 connected to the respective scanning lines are also selected in order. A plurality of pixels 1103 connected to each scanning line are each input with a video signal and hold a potential corresponding to the video signal.

  Since a display device using the shift register of this embodiment as the scan line driver circuit 1102 can operate at high speed, higher definition or a larger size can be achieved. Further, the display device in this embodiment can simplify processes, reduce manufacturing costs, and improve yield.

  In the display device in FIG. 11, the signal line driver circuit 1101, which requires high-speed operation, the scan line driver circuit 1102, and the pixel portion 1104 are formed over different substrates. Therefore, amorphous silicon can be used for a semiconductor layer of a transistor included in the scan line driver circuit 1102 and a semiconductor layer of a transistor included in the pixel 1103. As a result, the manufacturing process can be simplified, and the manufacturing cost can be reduced and the yield can be improved. Further, the display device of this embodiment can be increased in size. Alternatively, even when polysilicon or single crystal silicon is used for the semiconductor layer of the transistor, the manufacturing process can be simplified.

  In the case where the signal line driver circuit 1101, the scan line driver circuit 1102, and the pixel portion 1104 are formed over the same substrate, a semiconductor layer of a transistor included in the scan line driver circuit 1102 and a semiconductor layer of a transistor included in the pixel 1103 Polysilicon or single crystal silicon may be used.

  As shown in FIG. 11, the number and arrangement of the driver circuits are not limited to those in FIG. 11 as long as a pixel can be selected and a video signal can be written to the pixel independently.

  For example, as shown in FIG. 13, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 1302a and the second scanning line driving circuit 1302b. The first scan line driver circuit 1302a and the second drive circuit 1302b have the same configuration as the scan line driver circuit 1102 shown in FIG. 11, and scan the scan lines G1 to Gn at the same timing. Further, the first scan line driver circuit 1302a and the second driver circuit 1302b may be referred to as a first driver circuit and a second driver circuit, respectively.

  In the display device in FIG. 13, even if one of the first scan line driver circuit 1302 a and the second scan line driver circuit 1302 b is defective, the scan line driver circuit 1302 a and the second scan line driver circuit 1302 b Since the other can scan the scanning lines G1 to Gn, it can have redundancy. Further, in the display device of FIG. 13, the load of the first scan line driver circuit 1302a (the wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 1302b are about half that of FIG. Can be. Therefore, delay and rounding of signals input to the scanning lines G1 to Gn (output signals of the first scanning line driver circuit 1302a and the second driving circuit 1302b) can be reduced. Further, since the load on the first scan line driver circuit 1302a and the load on the second scan line driver circuit 1302b are reduced, the display device in FIG. 13 can scan the scan lines G1 to Gn at high speed. it can. Further, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. Note that portions common to the configuration in FIG. 11 are denoted by common reference numerals, and description thereof is omitted.

  As another example, FIG. 14 illustrates a display device capable of writing video signals to pixels at high speed. In the display device in FIG. 14, video signals are input to odd-numbered pixels 1103 from odd-numbered signal lines, and video signals are input to even-numbered pixels 1103 from even-numbered signal lines. Further, in the display device of FIG. 14, the odd-numbered scanning lines among the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 1402a, and the even-numbered scanning lines among the scanning lines G1 to Gn. Are scanned by the second scanning line driving circuit 1402b. Further, the start signal input to the first scan line driver circuit 1402a is input with a delay of ¼ period of the clock signal from the start signal input to the second scan line driver circuit 1402b.

  The display device in FIG. 14 can perform dot inversion driving only by inputting a positive video signal and a negative video signal for each column in one frame period. Further, the display device in FIG. 14 can perform frame inversion driving by inverting the polarity of a video signal input to each signal line for each frame period.

  The operation of the display device in FIG. 14 will be described with reference to the timing chart in FIG. In the timing chart of FIG. 15, the first scanning line G1, the i-1th scanning line Gi-1, the ith scanning line Gi, the i + 1th scanning line Gi + 1, and the nth scanning line Gn. Indicates the timing of selection. Further, in the timing chart of FIG. 15, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG. 15, the case where the display device of FIG. 14 performs dot inversion driving and frame inversion driving will be described.

  In FIG. 15, for example, the selection period “a” of the i-th scanning line Gi overlaps the selection period “b” of the i−1th scanning line Gi−1. The selection period b of the i-th scanning line Gi overlaps the selection period a of the i + 1-th scanning line Gi + 1. Therefore, in the selection period a, the same video signal input to the pixel 1103 in the (i−1) th row j + 1 column is input to the pixel 1103 in the i row j column. Further, in the selection period b, the same video signal as input to the pixel 1103 in the i-th row and j-th column is input to the pixel 1103 in the i + 1-th row and j + 1-th column. Note that a video signal input to the pixel 1103 in the selection period b is an original video signal, and a video signal input to the pixel 1103 in the selection period a is a video signal for precharging the pixel 1103. Accordingly, each pixel 1103 is precharged with the video signal input to the pixel 1103 in the (i−1) th row and j + 1th column in the selection period a, and then the original video signal (ith row and jth column) is selected in the selection period b. input.

  From the above, the display device in FIG. 14 can write video signals to the pixels 1103 at high speed, so that an increase in size and definition can be easily realized. Furthermore, since the video signal having the same polarity is input to each of the signal lines in one frame period, the display device in FIG. 14 can reduce the power consumption of each signal line and reduce power consumption. Further, in the display device of FIG. 14, since the load on the IC for inputting the video signal is significantly reduced, the heat generation of the IC and the power consumption of the IC can be reduced. Further, the display device in FIG. 14 can reduce power consumption of the first scan line driver circuit 1402a and the second scan line driver circuit 1402b by approximately half, so that power saving can be achieved.

  The display device of this embodiment can perform various driving methods depending on the structure and driving method of the pixel 1103. For example, in one frame period, the scan line driver circuit may scan the scan line a plurality of times.

  11, 13, and 14, another wiring or the like may be added depending on the configuration of the pixel 1103. For example, a power supply line, a capacitor line, a new scanning line, or the like maintained at a constant potential may be added. When a new scan line is added, a scan line driver circuit to which the shift register of this embodiment is applied may be newly added. As another example, dummy scanning lines, signal lines, power supply lines, or capacitor lines may be arranged in the pixel portion.

  In this embodiment mode, various drawings have been used. However, the contents described in each figure or a part of the contents may be applied to or combined with the contents described in another figure or a part of the contents. Can do. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents or a part of the contents described in each drawing in this embodiment mode can be applied to or combined with the contents or a part of the contents described in a drawing in another embodiment mode. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Alternatively, they can be combined.

(Embodiment 2)
In this embodiment, a structure and a driving method of a flip-flop different from that in Embodiment 1, a driver circuit including the flip-flop, and a display device including the driver circuit will be described. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  As the structure of the flip-flop in this embodiment, the same flip-flop structure as in Embodiment 1 can be used. Therefore, in this embodiment mode, description of the structure of the flip-flop is omitted. However, the timing for driving the flip-flop is different from that of the first embodiment.

  Although the case where the drive timing of this embodiment is applied to FIG. 1A will be described, the drive timing of this embodiment is shown in FIG. 1B, FIG. 1C, FIG. 4 (B), FIG. 4 (C), FIG. 5 (A), and the flip-flop of FIG. Furthermore, the drive timing in this embodiment can be implemented in combination with the drive timing described in Embodiment 1 freely.

  The operation of the flip-flop of this embodiment is described with reference to the flip-flop in FIG. 1A and the timing chart in FIG. Further, the timing chart of FIG. 16 will be described by being divided into a set period, a selection period, a reset period, and a non-selection period. However, the set period is divided into a first set period and a second set period, and the selection period is divided into a first selection period and a second selection period.

  A signal 1621, a signal 1625, and a signal 1622 illustrated in FIG. 16 are input to the first wiring 121, the fifth wiring 125, and the second wiring 122, respectively. A signal 1623 shown in FIG. 16 is output from the third wiring 123. Here, the signal 1621, the signal 1625, the signal 1622, and the signal 1623 correspond to the signal 221, the signal 225, the signal 222, and the signal 223 shown in FIG. 2, respectively. Further, the signal 1621, the signal 1625, the signal 1622, and the signal 1623 may be referred to as a start signal, a clock signal, a reset signal, and an output signal, respectively.

  The flip-flop of this embodiment basically operates in the same manner as the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the timing at which the H signal is input to the first wiring 121 is delayed by ¼ period of the clock signal.

  The flip-flop of this embodiment mode is shown in FIG. 2 in the first set period (A1), the second set period (A2), the reset period (C), and the non-selection period (D) shown in FIG. Since the operations are the same as those in the non-selection period (D), the set period (A), the reset period (C), and the non-selection period (D), description thereof is omitted.

  As shown in FIG. 17, the flip-flop of this embodiment delays the fall time of the output signal by delaying the timing at which the H signal is input to the second wiring 122 by ¼ period of the clock signal. Can be significantly shortened. That is, in the flip-flop of this embodiment to which FIG. 17 is applied, the L signal is input to the fifth wiring 125 in the first reset period illustrated in FIG. 17, and the potential of the node 141 is decreased to approximately V1 + Vth101. Accordingly, the first transistor 101 remains on and the L signal is output from the third wiring 123. An L signal is input to the third wiring 123 through the first transistor 101 having a large W / L value. Therefore, the time until the potential of the third wiring 123 changes from the H level to the L level can be significantly shortened. After that, in the flip-flop of this embodiment to which FIG. 17 is applied, the seventh transistor 107 is turned on and the potential of the node 141 becomes V2 in the second reset period illustrated in FIG. At this time, the potential of the node 142 (the potential 1642) is V1−Vth103, and the third transistor 103 is turned on, so that the L signal is output from the third wiring 123.

  The flip-flop of this embodiment can obtain the same effect as that of the flip-flop described in Embodiment 1.

  Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

  A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 18 includes n flip-flops (flip-flops 1801_1 to 1801_n).

  Connection relations of the shift register in FIG. 18 are described. In the i-th flip-flop 1801_i (any one of the flip-flops 1801_1 to 1801_n) in the shift register in FIG. 18, the first wiring 121 illustrated in FIG. 1A is the tenth wiring 1820_i. -1. The second wiring 122 illustrated in FIG. 1A is connected to the tenth wiring 1820_i + 2. The third wiring 123 illustrated in FIG. 1A is connected to the tenth wiring 1820_i. The fourth wiring 124, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 illustrated in FIG. 1A are connected to the seventh wiring 1817. The fifth wiring 125 shown in FIG. 1A is connected to the second wiring 1812 in the 4N-3 (N is a natural number of 1 or more) stage flip-flop, and in the 4N-2 stage flip-flop. The fourth wiring 1813 is connected to the third wiring 1813, the fourth wiring 1814 is connected to the 4N−1 stage flip-flop, and the fifth wiring 1815 is connected to the 4Nth flip-flop. The sixth wiring 126 and the seventh wiring 127 illustrated in FIG. 1A are connected to the sixth wiring 1816. Note that in the first-stage flip-flop 1801_1, the first wiring 121 illustrated in FIG. 1A is connected to the first wiring 1811. In the n−1-th flip-flop 1801 — n−1, the second wiring 122 illustrated in FIG. 1A is connected to the ninth wiring 1819. In the n-th flip-flop 1801 </ b> _n, the second wiring 122 illustrated in FIG. 1A is connected to the eighth wiring 1818.

  When the timing chart of FIG. 17 is applied to the flip-flop of this embodiment, the second wiring 122 illustrated in FIG. 1 is connected to the tenth wiring 1820_i + 3 in the i-th flip-flop 1801_i. Therefore, in the n-3th flip-flop 1801_n-3, a newly added wiring is connected to the second wiring 122 illustrated in FIG.

  The first wiring 1811, the second wiring 1812, the third wiring 1813, the fourth wiring 1814, the fifth wiring 1815, the eighth wiring 1818, and the ninth wiring 1819 are respectively connected to the first signal line, You may call the 2nd signal line, the 3rd signal line, the 4th signal line, the 5th signal line, the 6th signal line, and the 7th wiring. Further, the sixth wiring 1816 and the seventh wiring 1817 may be referred to as a first power supply line and a second power supply line, respectively.

  Next, operation of the shift register illustrated in FIG. 18 is described with reference to a timing chart of FIG. 19 and a timing chart of FIG. Here, the timing chart of FIG. 19 is divided into a scanning period and a blanking period.

  The sixth wiring 1816 is supplied with the potential of V1. The seventh wiring 1817 is supplied with the potential of V2.

  The first wiring 1811, the second wiring 1812, the third wiring 1813, the fourth wiring 1814, the fifth wiring 1815, the eighth wiring 1818, and the ninth wiring 1819 have signals shown in FIG. 1911, signal 1912, signal 1913, signal 1914, signal 1915, signal 1918 and signal 1919 are input. Here, the signal 1911, the signal 1912, the signal 1913, the signal 1914, the signal 1915, the signal 1918, and the signal 1919 are digital signals in which the potential of the H signal is V1 and the potential of the L signal is V2. Further, the signal 1911, the signal 1912, the signal 1913, the signal 1914, the signal 1915, the signal 1918, and the signal 1919 are respectively converted into a start signal, a first clock signal, a second clock signal, a third clock signal, and a fourth clock. You may call a signal, a 1st reset signal, and a 2nd reset signal.

  Note that various signals, potentials, and currents may be input to the first wiring 1811 to the ninth wiring 1819, respectively.

  From the tenth wirings 1820_1 to 1820_n, digital signals 1920_1 to 1920_n having an H signal potential V1 and an L signal potential V2 are output, respectively. Further, similarly to Embodiment 1, it can be easily operated by buffer connection to the tenth wirings 1820_1 to 1820_n.

  A signal output from the tenth wiring 1820_i-1 is used as a start signal of the flip-flop 1801_i, and a signal output from the tenth wiring 1820_i + 2 is used as a reset signal. Here, a start signal of the flip-flop 1801_1 is input from the first wiring 1811. The second reset signal of the flip-flop 1801_n−1 is input from the ninth wiring 1819. The first reset signal of the flip-flop 1801 — n is input from the eighth wiring 1818. However, a signal output from the tenth wiring 1820_1 is used as the second reset signal of the flip-flop 1801_n-1, and a signal output from the tenth wiring 1820_2 is used as the first reset signal of the flip-flop 1801_n. It may be used. Alternatively, a signal output from the tenth wiring 1820_2 is used as the second reset signal of the flip-flop 1801_n-1, and a signal output from the tenth wiring 1820_3 is used as the first reset signal of the flip-flop 1801_n. It may be used. Alternatively, a first dummy flip-flop and a second dummy flip-flop are newly arranged, and the output signal of the first dummy flip-flop and the output signal of the second dummy flip-flop are respectively changed to the first dummy flip-flop and the second dummy flip-flop. The reset signal and the second reset signal may be used. By doing so, the number of wirings and the number of signals can be reduced.

  As illustrated in FIG. 20, for example, when the flip-flop 1801_i enters the first selection period, an H signal (selection signal) is output from the tenth wiring 1820_i. At this time, the flip-flop 1801_i + 1 is in the second set period. After that, even when the flip-flop 1801_i enters the second selection period, the H signal is still output from the tenth wiring 1820_i. At this time, the flip-flop 1801_i + 1 is in the first selection period. After that, when the flip-flop 1801_i enters a reset period, an L signal is output from the tenth wiring 1820_i. At this time, the flip-flop 1801_i + 1 is in the second selection period. After that, even when the flip-flop 1801_i enters the non-selection period, the L signal is still output from the tenth wiring 1820_i. At this time, the flip-flop 1801_i + 1 is in the reset period.

  In this manner, the shift register in FIG. 18 can output a selection signal from the tenth wiring 1820_1 to the tenth wiring 1820_n in order. Further, in the shift register in FIG. 18, since the second selection period of the flip-flop 1801_i and the first selection period of the flip-flop 1801_i + 1 are the same period, the tenth wiring 1820_i and the tenth period are the same in the same period. A selection signal can be output from the wiring 1820 — i + 1.

  The shift register to which the flip-flop of this embodiment is applied can be applied to a high-definition display device or a large display device. Further, the shift register of this embodiment can obtain the same effects as those of the shift register described in Embodiment 1.

  Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

  The structure of the display device of this embodiment will be described with reference to FIG. In the display device in FIG. 21, the scanning lines G <b> 1 to Gn are scanned by the scanning line driving circuit 2102. Further, in the display device in FIG. 21, video signals are input from odd-numbered signal lines to odd-numbered pixels 1103, and video signals are input to even-numbered pixels 1103 from even-numbered signal lines. input. Note that portions common to the configuration in FIG. 11 are denoted by common reference numerals and description thereof is omitted.

  The display device in FIG. 21 can operate similarly to the display device in FIG. 14 with one scan line driver circuit by applying the shift register of this embodiment to the scan line driver circuit 2102. As a result, the same effect as that of the display device of FIG. 14 can be obtained.

  Similarly to FIG. 13, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b. As a result, the same effect as that of the display device of FIG. 13 can be obtained. The configuration in that case is shown in FIG.

  In this embodiment mode, various drawings have been used. However, the contents described in each figure or a part of the contents may be applied to or combined with the contents described in another figure or a part of the contents. Can do. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents or a part of the contents described in each drawing in this embodiment mode can be applied to or combined with the contents or a part of the contents described in a drawing in another embodiment mode. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 3)
In this embodiment, a structure and a driving method of a flip-flop different from those in Embodiments 1 and 2, a driving circuit including the flip-flop, and a display device including the driving circuit will be described. The flip-flop of this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. Note that components similar to those in Embodiments 1 and 2 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  A basic structure of the flip-flop of this embodiment is described with reference to FIG. The flip-flop illustrated in FIG. 23 is similar to the flip-flop illustrated in FIG. 1A in which a ninth transistor 109 and a tenth transistor 110 are added.

  A connection relation of the flip-flop of FIG. 23 will be described. The first electrode of the ninth transistor 109 is connected to the thirteenth wiring 133, the second electrode of the ninth transistor 109 is connected to the twelfth wiring 132, and the gate electrode of the ninth transistor 109 Are connected to the node 141. The first electrode of the tenth transistor 110 is connected to the fourteenth wiring 134, the second electrode of the tenth transistor 110 is connected to the twelfth wiring 132, and the gate electrode of the tenth transistor 110 Is connected to the node 142. Other connection relationships are the same as those in FIG.

  The thirteenth wiring 133 and the fourteenth wiring 134 may be referred to as a fifth signal line and an eighth power supply line, respectively.

  Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. Here, the timing chart of FIG. 24 will be described by being divided into a set period, a selection period, a reset period, and a non-selection period. However, the set period, the reset period, and the non-selection period may be collectively referred to as a non-selection period.

  A signal 223 and a signal 232 are output from the third wiring 123 and the twelfth wiring 132, respectively. Signal 232 is an output signal of the flip-flop, and signal 223 is a transfer signal of the flip-flop. However, the signal 223 may be the output signal of the flip-flop, and the signal 232 may be the transfer signal of the flip-flop.

  In the case where the signal 232 is used as an output signal of the flip-flop and the signal 223 is used as a transfer signal of the flip-flop, the value of W / L of the ninth transistor 109 is set as W / L of the first transistor 101 to the tenth transistor 110. It is best to make it the largest of all. In the case where the signal 223 is used as an output signal of the flip-flop and the signal 232 is used as a transfer signal of the flip-flop, the value of W / L of the first transistor 101 is set as W of the first transistor 101 to the tenth transistor 110. / L should be the maximum.

  In this embodiment mode, as described above, the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop in FIG. 23 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102. In addition, a signal is output from the twelfth wiring 132 by the ninth transistor 109 and the tenth transistor 110. Further, since the ninth transistor 109 and the tenth transistor 110 are connected in the same manner as the first transistor 101 and the second transistor 102, they are output from the twelfth wiring 132 as shown in FIG. The signal (signal 232) has substantially the same waveform as the signal (signal 223) output from the third wiring 123.

  The first transistor 101 only needs to be able to supply electric charge to the gate electrode of the fifth transistor 105 and the gate electrode of the eighth transistor 108 in the next stage, so the value of W / L of the first transistor 101 is It is preferable that the W / L value of the fifth transistor 105 be twice or less. More preferably, the W / L value of the fifth transistor 105 or less is set.

  The ninth transistor 109 and the tenth transistor 110 have functions similar to those of the first transistor 101 and the second transistor 102, respectively. Further, the ninth transistor 109 and the tenth transistor 110 may be referred to as a buffer portion.

  From the above, the flip-flop in FIG. 23 can prevent malfunction even when a large load is connected to the twelfth wiring 132 and a delay or a rounding occurs in the signal 232. This is because the flip-flop in FIG. 23 is not affected by delay or rounding of the output signal by outputting the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors. It is.

  The flip-flop of FIG. 23 can obtain the same effect as the flip-flop described in Embodiments 1 and 2.

  The flip-flop of this embodiment includes the flip-flops illustrated in FIGS. 1B, 1C, 4A, 4B, 4C, 5A, and 5B. And can be combined freely. Furthermore, the flip-flop of this embodiment can be implemented by freely combining the driving timing described in Embodiment 1 and the driving timing described in Embodiment 2.

  Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

  A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 25 includes n flip-flops (flip-flops 2501_1 to 2501_n).

  The flip-flops 2501_1 to 2501_n, the first wiring 2511, the second wiring 2512, the third wiring 2513, the fourth wiring 2514, the fifth wiring 2515, and the sixth wiring 2516 are the flip-flops in FIG. 701_1 to flip-flop 701_n, corresponding to the first wiring 711, the second wiring 712, the third wiring 713, the fourth wiring 714, the fifth wiring 715, and the sixth wiring 716, similar signals or similar The power supply voltage is input. The seventh wiring 2517_1 to the seventh wiring 2517_n and the eighth wiring 2518_1 to the eighth wiring 2518_n correspond to the seventh wiring 717_1 to the seventh wiring 717_n in FIG.

  Next, operation of the shift register illustrated in FIG. 25 is described with reference to a timing chart in FIG.

  The operation of the shift register illustrated in FIG. 25 is different from the operation of the shift register illustrated in FIG. 7 in that the output signal and the transfer signal are output to different wirings. Specifically, the output signal is output to each of the eighth wiring 2518_1 to the eighth wiring 2518_n, and the transfer signal is output to each of the seventh wiring 2517_1 to the seventh wiring 2517_n.

  The shift register in FIG. 25 can operate without being affected by the load even when a large load (such as a resistor and a capacitor) is connected to the eighth wiring 2518_1 to the eighth wiring 2518_n. In addition, the shift register in FIG. 25 can continue normal operation even when any of the eighth wirings 2518_1 to 2518_n is short-circuited to a power supply line or a signal line. Therefore, the shift register in FIG. 25 can improve operation efficiency, reliability, and yield. This is because the shift register of FIG. 25 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

  The shift register to which the flip-flop of this embodiment is applied can achieve the same effect as the shift register described in Embodiments 1 and 2.

  The shift register of this embodiment can be implemented by being freely combined with the shift registers of FIGS. Further, the shift register of this embodiment can be implemented by being freely combined with the description in Embodiment 1 and Embodiment 2.

  As the display device of this embodiment, the display devices of FIGS. 11, 13, 14, 21, and 22 can be used. Therefore, the display device of this embodiment can obtain the same effects as those of the display devices described in Embodiments 1 and 2.

  In this embodiment mode, description is made using various drawings. However, the contents or part of the contents described in each figure can be applied to or combined with the contents or part of the contents described in another figure. be able to. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents or a part of the contents described in each drawing in this embodiment mode can be applied to or combined with the contents or a part of the contents described in a drawing in another embodiment mode. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 4)
In this embodiment, the case where a p-channel transistor is used as a transistor included in the flip-flop of this specification will be described. Further, a structure and a driving method of a driving circuit including the flip-flop and a display device including the driving circuit are described.

  In the flip-flop of this embodiment, the case where the polarity of the transistor included in the flip-flop in FIG. Therefore, the flip-flop of FIG. 27 can obtain the same effect as the flip-flop of FIG. 1B, FIG. 1C, FIG. 4A, FIG. 4B, FIG. 4C, FIG. 5A, FIG. 5B, and FIG. The polarity of the transistor included in the transistor can be a P-channel type. Note that the flip-flop of this embodiment can be freely combined with the description in Embodiments 1 to 3.

  A basic structure of the flip-flop of this embodiment is described with reference to FIG. The flip-flop illustrated in FIG. 27 includes a first transistor 2701 to an eighth transistor 2708. The first transistor 2701 to the eighth transistor 2708 correspond to the first transistor 101 to the eighth transistor 108 in FIG. Note that the first transistor 2701 to the eighth transistor 2708 are P-channel transistors, and the absolute value of the gate-source voltage (| Vgs |) exceeds the absolute value of the threshold voltage (| Vth |). (When Vgs is less than Vth), the conductive state is assumed.

  The flip-flop of this embodiment is characterized in that the first transistor 2701 to the eighth transistor 2708 are all P-channel transistors. Therefore, the flip-flop of this embodiment can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

  The connection relation of the flip-flop in FIG. 27 is the same as that in FIG.

  The first wiring 2721 to the eleventh wiring 2731 in FIG. 27 correspond to the first wiring 121 to the eleventh wiring 131 in FIG. 1, respectively.

  Next, the operation of the flip-flop shown in FIG. 27 will be described with reference to the timing chart of FIG. Here, the timing chart of FIG. 28 is divided into a set period, a selection period, a reset period, and a non-selection period. However, the set period, the reset period, and the non-selection period may be collectively referred to as a non-selection period.

  The timing chart of FIG. 28 is the same as that obtained by inverting the H level and the L level of the timing chart of FIG. That is, in the flip-flop in FIG. 27, the H level and the L level of the input signal and the output signal are only inverted as compared with the flip-flop in FIG. Note that the signal 2821, the signal 2825, the signal 2841, the signal 2842, the signal 2822, and the signal 2823 correspond to the signal 221, the signal 225, the signal 241, the signal 242, the signal 222, and the signal 223 in FIG. 2, respectively.

  Note that the power supply voltage supplied to the flip-flop in FIG. 27 is inverted between V1 and V2 as compared with the flip-flop in FIG.

  First, the operation of the flip-flop in the set period shown in FIG. The potential 2841 of the node 2741 becomes V2 + | Vth2705 |. The node 2741 is in a floating state with the potential maintained at V2 + | Vth2705 |. At this time, at the node 2742, the potential 2842 becomes V1−θ (θ is an arbitrary positive number). Note that since the first transistor 2701 and the second transistor 2702 are on, an H signal is output from the third wiring 2723.

  The operation of the flip-flop in the selection period shown in FIG. The potential 2841 of the node 2741 becomes V2− | Vth2701 | −γ (Vth2701: threshold voltage of the first transistor 2701, γ: any positive number) by the bootstrap operation. Accordingly, the first transistor 2701 is turned on, so that the L signal is output from the third wiring 2723.

  The operation of the flip-flop in the reset period shown in FIG. Since the seventh transistor 2707 is turned on, the potential 2841 of the node 2741 is V1. Accordingly, the first transistor 2701 is turned off. At this time, the potential 2842 of the node 2742 becomes V2 + | Vth2703 |, and the second transistor 2702 is turned on. Accordingly, the H signal is output from the third wiring 2723.

  The operation of the flip-flop in the non-selection period shown in FIG. The potential 2841 of the node 2741 remains at V1. Since the potential 2842 of the node 2742 is also V2 + | Vth2703 |, the second transistor 2702 remains on. Accordingly, the H signal is output from the third wiring 2723.

  The shift register of this embodiment can be implemented by freely combining the flip-flop of this embodiment with the shift register described in any of Embodiments 1 to 3. For example, the shift register of this embodiment mode can be implemented by freely combining the flip-flops of this embodiment mode with the shift registers of FIGS. However, in the shift register of this embodiment, the H level and the L level are inverted as compared with the shift register described in any of Embodiments 1 to 3.

  The display device of this embodiment can be implemented by freely combining the shift register of this embodiment with the display device described in any of Embodiments 1 to 3. For example, the display device of this embodiment mode can be implemented by being freely combined with the display devices of FIGS. 11, 13, 14, 21, and 22. However, in the display device of this embodiment, the H level and the L level are inverted as compared with the display devices described in Embodiments 1 to 3.

  In this embodiment mode, description is made using various drawings. However, the contents or part of the contents described in each figure can be applied to or combined with the contents or part of the contents described in another figure. be able to. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents described in each drawing of this embodiment mode or a part of the contents can be applied to or combined with the contents described in the drawings of another embodiment mode or a part of the contents. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 5)
In this embodiment, a signal line driver circuit included in the display device described in any of Embodiments 1 to 4 is described.

  The signal line driver circuit of FIG. 31 will be described. The signal line driver circuit illustrated in FIG. 31 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a third switch 5603c.

  The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to any of the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to the switch groups 5602_1 to 5602_M. Each of the wirings 5621_1 to 5621_M is connected to three signal lines through the first switch 5603a, the second switch 5603b, and the third switch 5603c. For example, the wiring 5621_J (any one of the wirings 5621_1 to 5621_M) in the J-th column is connected to the signal line through the first switch 5603a, the second switch 5603b, and the third switch 5603c included in the switch group 5602_J. Sj−1, signal line Sj and signal line Sj + 1 are connected.

  Signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

  The driver IC 5601 is preferably formed over a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Further, the switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion described in Embodiments 1 and 2. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are preferably connected through an FPC or the like.

  Next, operation of the signal line driver circuit illustrated in FIG. 31 is described with reference to a timing chart of FIG. Note that the timing chart of FIG. 32 shows the timing chart when the i-th scanning line Gi is selected. Further, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driver circuit in FIG. 31 operates in the same manner as in FIG. 32 even when a scan line in another row is selected.

  In the timing chart of FIG. 32, the wiring 5621_J in the J-th column is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1 through the first switch 5603a, the second switch 5603b, and the third switch 5603c. It shows the case of connection.

  The timing chart of FIG. 32 shows the timing at which the i-th scanning line Gi is selected, the on / off timing 5703a of the first switch 5603a, the on / off timing 5703b of the second switch 5603b, and the third switch. An ON / OFF timing 5703c of 5603c and a signal 5721_J input to the wiring 5621_J in the J-th column are shown.

  Different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, in the first sub-selection period T1, the video signal input to the wiring 5621_J is input to the signal line Sj-1. In the second sub-selection period T2, the video signal input to the wiring 5621_J is input to the signal line Sj. In the third sub-selection period T3, the video signal input to the wiring 5621_J is input to the signal line Sj + 1. Further, video signals input to the wiring 5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are Dataj-1, Dataj, and Dataj + 1, respectively.

  As shown in FIG. 32, in the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, and the first switch 5603a and the second switch 5603b are turned off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

  From the above, the signal line driver circuit in FIG. 31 divides one gate selection period into three to input video signals from one wiring 5621 to three signal lines during one gate selection period. be able to. Therefore, in the signal line driver circuit in FIG. 31, the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed can be reduced to about 1/3 of the number of signal lines. . When the number of connections is about ３, the signal line driver circuit in FIG. 31 can improve reliability, yield, and the like.

  By applying the signal line driver circuit of this embodiment mode to the display device described in Embodiment Modes 1 to 4, the number of connections between the substrate over which the pixel portion is formed and the external substrate is further reduced. be able to. Therefore, the display device of the present invention can improve reliability and yield.

  Next, the case where N-channel transistors are used for the first switch 5603a, the second switch 5603b, and the third switch 5603c will be described with reference to FIGS. Note that components similar to those in FIG. 31 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  The first transistor 5903a in FIG. 33 corresponds to the first switch 5603a in FIG. The second transistor 5903b in FIG. 33 corresponds to the second switch 5603b in FIG. The third transistor 5903c in FIG. 33 corresponds to the third switch 5603c in FIG.

  For example, in the case of the switch group 5602_M, the first transistor 5903a includes a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the first wiring 5611. Is done. In the second transistor 5903b, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring 5612. In the third transistor 5903c, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the third wiring 5613.

  The first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor. Further, each of the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c is turned on when a signal input to the gate electrode is at an H level, and when the signal input to the gate electrode is at an L level. Turned off.

  By using N-channel transistors as the first switch 5603a, the second switch 5603b, and the third switch 5603c, amorphous silicon can be used as the semiconductor layer of the transistor, which simplifies the manufacturing process. Manufacturing cost can be reduced and yield can be improved. Further, a semiconductor device such as a large display panel can be manufactured. Further, even when polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor, the manufacturing process can be simplified.

  In the signal line driver circuit in FIG. 33, the case where N-channel transistors are used as the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c has been described; however, the first transistor 5903a, P-channel transistors may be used as the transistor 5903b and the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is at L level, and is turned off when the signal input to the gate electrode is at H level.

  As shown in FIG. 31, if one gate selection period is divided into a plurality of sub-selection periods and a video signal can be input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, The arrangement, number, driving method, etc. are not limited.

  For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, if one gate selection period is divided into four or more sub selection periods, one sub selection period becomes too short. Therefore, it is desirable that one gate selection period is divided into two or three sub selection periods.

  As another example, as shown in the timing chart of FIG. 34, one selection period is divided into a precharge period Tp, a first sub selection period T1, a second sub selection period T2, and a third selection period T3. May be. Further, in the timing chart of FIG. 34, the timing at which the i-th scanning line Gi is selected, the on / off timing 5803a of the first switch 5603a, the on / off timing 5803b of the second switch 5603b, The ON / OFF timing 5803c of the switch 5603c and the signal 5821_J input to the wiring 5621_J in the J-th column are shown. As shown in FIG. 34, in the precharge period Tp, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is supplied to the signal line Sj−1, the signal line Sj, and the signal line Sj + 1 through the first switch 5603a, the second switch 5603b, and the third switch 5603c, respectively. Is input. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, and the first switch 5603a and the second switch 5603b are turned off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

  From the above, the signal line driver circuit in FIG. 31 to which the timing chart in FIG. 34 is applied can precharge the signal line by providing the precharge selection period before the sub selection period. Therefore, a video signal can be written to the pixel at high speed. Note that components similar to those in FIG. 32 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  Also in FIG. 35, as shown in FIG. 31, one gate selection period is divided into a plurality of sub-selection periods, and a video signal is input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods. Can do. Note that FIG. 35 illustrates only the switch group 6022_J in the J column in the signal line driver circuit. The switch group 6022_J includes a first transistor 6001, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006. The first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are N-channel transistors. The switch group 6022_J includes a first wiring 6011, a second wiring 6012, a third wiring 6013, a fourth wiring 6014, a fifth wiring 6015, a sixth wiring 6016, a wiring 5621_J, a signal line Sj-1, Connected to signal line Sj and signal line Sj + 1.

  A first electrode of the first transistor 6001 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj-1, and a gate electrode is connected to the first wiring 6011. A first electrode of the second transistor 6002 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj-1, and a gate electrode is connected to the second wiring 6012. A first electrode of the third transistor 6003 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj, and a gate electrode is connected to the third wiring 6013. A first electrode of the fourth transistor 6004 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj, and a gate electrode is connected to the fourth wiring 6014. A first electrode of the fifth transistor 6005 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj + 1, and a gate electrode is connected to the fifth wiring 6015. A first electrode of the sixth transistor 6006 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj + 1, and a gate electrode is connected to the sixth wiring 6016.

  The first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor. Further, in each of the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006, a signal input to the gate electrode is at an H level. Is turned on when the signal is input, and is turned off when the signal input to the gate electrode is at the L level.

  The first wiring 6011 and the second wiring 6012 in FIG. 35 correspond to the first wiring 5611 in FIG. The third wiring 6013 and the fourth wiring 6014 in FIG. 35 correspond to the second wiring 5612 in FIG. The fifth wiring 6015 and the sixth wiring 6016 in FIG. 35 correspond to the third wiring 5613 in FIG. Note that the first transistor 6001 and the second transistor 6002 in FIG. 35 correspond to the first transistor 5903a in FIG. The third transistor 6003 and the fourth transistor 6004 in FIG. 35 correspond to the second transistor 5903b in FIG. The fifth transistor 6005 and the sixth transistor 6006 in FIG. 35 correspond to the third transistor 5903c in FIG.

  35, in the first sub-selection period T1 shown in FIG. 32, either the first transistor 6001 or the second transistor 6002 is turned on. In the second sub-selection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third sub-selection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on. Further, in the precharge period Tp illustrated in FIG. 34, the first transistor 6001, the third transistor 6003, and the fifth transistor 6005, or the second transistor 6002, the fourth transistor 6004, and the sixth transistor 6006 Either one turns on.

  Therefore, in FIG. 35, since the on-time of each transistor can be shortened, deterioration of characteristics of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 shown in FIG. 32, if either the first transistor 6001 or the second transistor 6002 is on, a video signal is input to the signal line Sj-1. Because it can be done. Here, in the first sub-selection period T1 shown in FIG. 32, by simultaneously turning on the first transistor 6001 and the second transistor 6002, a video signal can be input to the signal line Sj-1 at high speed. it can.

  FIG. 35 illustrates the case where two transistors are connected in parallel between the wiring 5621 and the signal line. However, the invention is not limited to this, and three or more transistors may be connected in parallel between the wiring 5621 and the signal line. By doing so, it is possible to further suppress the characteristic deterioration of each transistor.

  In this embodiment mode, description is made using various drawings. However, the contents or part of the contents described in each figure can be applied to or combined with the contents or part of the contents described in another figure. be able to. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents or a part of the contents described in each drawing in this embodiment mode can be applied to or combined with the contents or a part of the contents described in a drawing in another embodiment mode. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 6)
In this embodiment, a structure for preventing a defect due to electrostatic breakdown of the display device described in any of Embodiments 1 to 4 will be described.

  In electrostatic breakdown, positive or negative charges accumulated in the human body or object are instantaneously discharged through the input / output terminals of the device when it touches the semiconductor device, causing a large current to flow inside the device. It is destruction that occurs.

  FIG. 36A shows a structure for preventing electrostatic breakdown generated in the scanning line by the protective diode. FIG. 36A illustrates a structure in which the protective diode is provided between the wiring 6111 and the scan line. Although not shown, a plurality of pixels are connected to the i-th scanning line Gi. A transistor 6101 is used as the protective diode. Note that the transistor 6101 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6101 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel.

  Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

  In the transistor 6101, the first electrode is connected to the i-th scanning line Gi, the second electrode is connected to the wiring 6111, and the gate electrode is connected to the i-th scanning line Gi.

  The operation of FIG. 36A will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scanning line Gi. When positive or negative charges are not discharged to the i-th scanning line Gi, the transistor 6101 is off because the potential of the i-th scanning line Gi is at the H level or the L level. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, when the potential of the i-th scanning line Gi is lower than the value obtained by subtracting the threshold voltage of the transistor 6101 from the potential of the wiring 6111, the transistor 6101 is turned on. As a result, current flows to the wiring 6111 through the transistor 6101. Therefore, the structure illustrated in FIG. 36A can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented.

  FIG. 36B shows a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. A transistor 6102 functioning as a protective diode is provided between the scan line and the wiring 6112. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6102 is an N-channel transistor. However, a P-channel transistor may be used. The polarity of the transistor 6102 may be similar to that of the transistor included in the scan line driver circuit or the pixel. The transistor 6102 has a first electrode connected to the i-th scanning line Gi, a second electrode connected to the wiring 6112, and a gate electrode connected to the wiring 6112. Note that a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6112. Therefore, the transistor 6102 is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, when the potential of the i-th scanning line Gi becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on. As a result, current flows to the wiring 6112 through the transistor 6102. Therefore, the structure illustrated in FIG. 36B can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented.

  As shown in FIG. 36C, by combining FIG. 36A and FIG. 36B, even when positive charges are discharged to the i-th scanning line Gi. Even when negative charges are discharged to the i-th scanning line Gi, electrostatic breakdown of the pixels can be prevented. Note that components similar to those in FIGS. 36A and 36B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  FIG. 37A illustrates a structure in the case where a transistor 6201 functioning as a protective diode is connected between a scan line and a storage capacitor line. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6201 is an N-channel transistor. However, a P-channel transistor may be used. The polarity of the transistor 6201 may be similar to that of the transistor included in the scan line driver circuit or the pixel. Note that the wiring 6211 functions as a storage capacitor line. A first electrode of the transistor 6201 is connected to the i-th scanning line Gi, a second electrode is connected to the wiring 6211, and a gate electrode is connected to the i-th scanning line Gi. Note that a potential lower than an L level of a signal input to the i-th scanning line Gi is input to the wiring 6211. Accordingly, the transistor 6201 is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, when the potential of the i-th scanning line Gi becomes lower than a value obtained by subtracting the threshold voltage of the transistor 6201 from the potential of the wiring 6211, the transistor 6201 is turned on. As a result, current flows to the wiring 6211 through the transistor 6201. Therefore, the structure illustrated in FIG. 37A can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 37A, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring.

  FIG. 37B shows a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. Here, a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6211. Therefore, the transistor 6202 is off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, when the potential of the i-th scanning line Gi becomes higher than the sum of the potential of the wiring 6211 and the threshold voltage of the transistor 6202, the transistor 6202 is turned on. As a result, current flows to the wiring 6211 through the transistor 6202. Accordingly, the structure illustrated in FIG. 37B can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 37B, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring. Note that components similar to those in FIG. 37A are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  Next, FIG. 38A illustrates a structure for preventing electrostatic breakdown generated in the signal line by the protective diode. FIG. 38A illustrates a structure in the case where a protective diode is provided between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the signal line Sj in the j-th column. A transistor 6401 is used as the protective diode. The transistor 6401 is an N-channel transistor. However, a P-channel transistor may be used. The polarity of the transistor 6401 may be similar to that of the signal line driver circuit or the transistor included in the pixel.

  Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

  The transistor 6401 has a first electrode connected to the signal line Sj in the j-th column, a second electrode connected to the wiring 6411, and a gate electrode connected to the wiring 6411.

  The operation of FIG. 38A will be described. A certain potential is input to the wiring 6411, and the potential is lower than the minimum value of the video signal input to the signal line Sj in the j-th column. When positive or negative charges are not discharged to the signal line Sj in the j-th column, the potential of the signal line Sj in the j-th column is the same as that of the video signal, so that the transistor 6401 is off. On the other hand, when negative charges are discharged to the signal line Sj in the j-th row, the potential of the signal line Sj in the j-th column drops instantaneously. At this time, when the potential of the signal line Sj in the j-th column is lower than the value obtained by subtracting the threshold voltage of the transistor 6401 from the potential of the wiring 6411, the transistor 6401 is turned on. As a result, current flows to the wiring 6411 through the transistor 6401. Therefore, the structure illustrated in FIG. 38A can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented.

  FIG. 38B shows a structure for preventing electrostatic breakdown when positive charges are discharged to the signal line Sj in the j-th column. A transistor 6402 functioning as a protective diode is provided between the signal line and the wiring 6412. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. The transistor 6402 is an N-channel transistor. However, a P-channel transistor may be used. The polarity of the transistor 6402 may be similar to that of the signal line driver circuit or the transistor included in the pixel. The transistor 6402 has a first electrode connected to the signal line Sj in the jth column, a second electrode connected to the wiring 6412, and a gate electrode connected to the signal line Sj in the jth column. Note that a potential higher than the maximum value of the video signal input to the j-th signal line Sj is input to the wiring 6412. Therefore, the transistor 6402 is off when the electric charge is not discharged to the signal line Sj in the j-th column. On the other hand, when positive charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj rises instantaneously. At this time, when the potential of the signal line Sj in the j-th column becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on. As a result, current flows to the wiring 6412 through the transistor 6402. Accordingly, the structure illustrated in FIG. 38B can prevent a large current from flowing into the pixel. Therefore, electrostatic breakdown of the pixel can be prevented.

  As shown in FIG. 38C, when a configuration in which FIG. 38A and FIG. 38B are combined, positive charges are discharged to the signal line Sj in the j-th column. However, even when negative charges are discharged to the signal line Sj in the j-th column, the electrostatic breakdown of the pixel can be prevented. Note that components similar to those in FIGS. 38A and 38B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  In this embodiment mode, a configuration for preventing electrostatic breakdown of a pixel connected to a scan line and a signal line has been described. However, the configuration of this embodiment is not applied only to prevention of electrostatic breakdown of pixels connected to the scanning lines and signal lines. For example, in the case where this embodiment is applied to the scan line driver circuit described in Embodiments 1 to 4 and a wiring to which a signal or a potential connected to the signal line driver circuit is input, the scan line driver is used. The electrostatic breakdown of the circuit and the signal line driving circuit can be prevented.

  In this embodiment mode, description is made using various drawings. However, the contents or part of the contents described in each figure can be applied to or combined with the contents or part of the contents described in another figure. be able to. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents described in each drawing in this embodiment mode or a part of the contents can be applied to or combined with the contents described in the drawings in another embodiment mode or a part of the contents. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 7)
In this embodiment, a new structure of a display device which can be applied to the display devices described in Embodiments 1 to 4 will be described.

  FIG. 39A illustrates a structure in which a diode-connected transistor is provided between one scan line and another scan line. In FIG. 39A, a diode-connected transistor 6301a is arranged between the (i-1) th scanning line Gi-1 and the ith scanning line Gi, and the ith scanning line Gi and i + 1 are arranged. A configuration in which a diode-connected transistor 6301b is arranged between the scanning line Gi + 1 in the row is shown. Note that the transistors 6301a and 6301b are N-channel transistors. However, a P-channel transistor may be used. The polarity of the transistor 6301a and the transistor 6301b may be similar to that of the transistor included in the scan line driver circuit or the pixel.

  In FIG. 39A, the i-1th scanning line Gi-1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1 are shown as representatives, but the other scanning lines are similarly shown. A diode-connected transistor is arranged.

  The first electrode of the transistor 6301a is connected to the i-th scanning line Gi, the second electrode is connected to the i-1th scanning line Gi-1, and the gate electrode is connected to the Gi-1th row. Connected to the scanning line Gi-1. The first electrode of the transistor 6301b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the ith scanning line Gi. Is done.

  The operation of FIG. 39A will be described. In the scanning line driver circuit described in any of Embodiments 1 to 4, in the non-selection period, the i−1th scanning line Gi−1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1. Maintains the L level. Accordingly, the transistor 6301a and the transistor 6301b are off. However, when the potential of the i-th scanning line Gi increases due to noise or the like, for example, the i-th scanning line Gi selects a pixel, and an invalid video signal is written to the pixel. Therefore, as shown in FIG. 39A, an illegal video signal can be prevented from being written to a pixel by arranging a diode-connected transistor between scan lines. This is because when the potential of the i-th scanning line Gi rises above the sum of the potential of the (i-1) th scanning line Gi-1 and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on and i The potential of the scanning line Gi in the row is lowered. Therefore, no pixel is selected by the i-th scanning line Gi.

  The structure in FIG. 39A is particularly advantageous when the scan line driver circuit and the pixel portion are formed over the same substrate. This is because in a scan line driver circuit including only an N-channel transistor or a P-channel transistor, the scan line may be in a floating state, and noise is easily generated in the scan line.

  FIG. 39B illustrates a structure in which the direction of the diode-connected transistor provided between the scan lines is reversed. Note that the transistors 6302a and 6302b are N-channel transistors. However, a P-channel transistor may be used. The polarity of the transistor 6302a and the transistor 6302b may be similar to that of the transistor included in the scan line driver circuit or the pixel. In FIG. 39B, the first electrode of the transistor 6302a is connected to the i-th scanning line Gi, the second electrode is connected to the i-1th scanning line Gi-1, and the gate electrode Are connected to the i-th scanning line Gi. The first electrode of the transistor 6302b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the (i + 1) th scanning line Gi + 1. Is done. In FIG. 39B, similarly to FIG. 38A, the potential of the i-th scanning line Gi is the sum of the potential of the i−1th scanning line Gi + 1 and the threshold voltage of the transistor 6302b. When increased above, the transistor 6302b is turned on, and the potential of the i-th scanning line Gi is decreased. Therefore, the pixel is not selected by the i-th scanning line Gi, and an illegal video signal can be prevented from being written to the pixel.

  As shown in FIG. 39C, the structure of FIG. 39A and FIG. 39B is combined so that the transistor 6301a can be used even when the potential of the i-th scanning line Gi rises. Since the transistor 6302b is turned on, the potential of the i-th scanning line Gi is lowered. Note that in FIG. 39C, current flows through two transistors, so that larger noise can be removed. Note that components similar to those in FIGS. 39A and 39B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  As shown in FIGS. 37A and 37B, even if a diode-connected transistor is arranged between the scanning line and the storage capacitor line, the same effect as in FIGS. 39A, 39B, and 39C. Can be obtained.

  In this embodiment mode, description is made using various drawings. However, the contents or part of the contents described in each figure can be applied to or combined with the contents or part of the contents described in another figure. be able to. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents described in each drawing in this embodiment mode or a part of the contents can be applied to or combined with the contents described in the drawings in another embodiment mode or a part of the contents. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  In this embodiment mode, the contents described in the other embodiment modes are described in detail as an example, an example of a slight modification, an example of a partial change, an example of an improvement, and the like. An example of a case, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to or combined with this embodiment.

(Embodiment 8)
In this embodiment, a structure and a manufacturing method of a transistor will be described.

  FIG. 40A illustrates an example of a transistor structure. 40B to 40G illustrate an example of a method for manufacturing a transistor.

  Note that the structure and manufacturing method of the transistor are not limited to those illustrated in FIGS. 40A to 40G, and various structures and manufacturing methods can be used.

  First, an example of a transistor structure is described with reference to FIG. FIG. 40A is a cross-sectional view of a plurality of transistors having different structures. Here, in FIG. 40A, a plurality of transistors having different structures are shown side by side, but this is an expression for describing the structure of the transistors. Therefore, the transistors do not actually have to be juxtaposed as shown in FIG. 40A, and can be formed as needed.

  Next, characteristics of each layer constituting the transistor will be described.

  As the substrate 110111, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, it is also possible to use a plastic substrate represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or a substrate made of flexible synthetic resin such as acrylic. is there. By using a flexible substrate, a semiconductor device that can be bent can be manufactured. If the substrate has flexibility, the area of the substrate and the shape of the substrate are not greatly limited. For example, if the substrate 110111 is a rectangular substrate having a side of 1 meter or more, the productivity is improved. Can be significantly improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate.

  The insulating film 110112 functions as a base film. An alkali metal such as Na or an alkaline earth metal is provided from the substrate 110111 in order to prevent adverse effects on the characteristics of the semiconductor element. The insulating film 110112 is an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). A single-layer structure or a stacked structure thereof can be used. For example, in the case where the insulating film 110112 is provided with a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film and a silicon oxynitride film may be provided as a second insulating film. As another example, in the case where the insulating film 110112 is provided in a three-layer structure, a silicon oxynitride film is provided as a first insulating film, a silicon nitride oxide film is provided as a second insulating film, and a third insulating film A silicon oxynitride film is preferably provided.

The semiconductor layer 110113, the semiconductor layer 110114, and the semiconductor layer 110115 can be formed using an amorphous semiconductor, a microcrystalline semiconductor, or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor layer may be used. SAS is a semiconductor having an intermediate structure between an amorphous structure and a crystalline structure (including a single crystal and a polycrystal) and having a third state that is stable in terms of free energy, and has a short-range order. It includes a crystalline region having lattice distortion. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. As a compensation for dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a material gas. As the material gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Alternatively, GeF ₄ may be mixed. This material gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As impurity elements in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are preferably 1 × 10 ²⁰ cm ⁻¹ or less. In particular, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁹ / cm ³ or less. Here, a material containing silicon (Si) as a main component (e.g., Si (x) Ge (1-x) (0 <x <1) or the like) using a sputtering method, an LPCVD method, a plasma CVD method, or the like is amorphous. The amorphous semiconductor layer is formed by a crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Crystallize.

  The insulating film 110116 is an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). A single-layer structure or a stacked structure thereof can be used.

  The gate electrode 110117 can have a single-layer conductive film or a stacked structure of two-layer or three-layer conductive films. As a material of the gate electrode 110117, for example, a simple film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or the like Nitride film (typically tantalum nitride film, tungsten nitride film, titanium nitride film), alloy film combining the above elements (typically Mo—W alloy, Mo—Ta alloy), or silicide film of the above elements (Typically, a tungsten silicide film, a titanium silicide film) or the like can be used. Note that the single film, nitride film, alloy film, silicide film, and the like described above may be used as a single layer or may be stacked.

  The insulating film 110118 is formed using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like by sputtering or plasma CVD. A single-layer structure of an insulating film containing oxygen or nitrogen or a film containing carbon such as DLC (diamond-like carbon), or a stacked structure thereof.

  The insulating film 110119 is formed using siloxane resin or oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). An insulating film having carbon, a film containing carbon such as DLC (diamond-like carbon), or a single layer made of an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a laminated structure. it can. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that the insulating film 110119 can be provided directly so as to cover the gate electrode 110117 without providing the insulating film 110118.

  The conductive film 110123 includes a single element film of an element such as Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn, a nitride film of the element, an alloy film in which the elements are combined, or the element A silicide film or the like can be used. For example, as an alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, and the like can be used. For example, when a conductive film is provided with a stacked structure, a structure in which Al is sandwiched between Mo, Ti, or the like can be employed. By carrying out like this, the tolerance with respect to the heat | fever and chemical reaction of Al can be improved.

  Next, characteristics of each structure will be described with reference to cross-sectional views of a plurality of transistors having different structures shown in FIG.

  The transistor 110101 is a single drain transistor and can be manufactured by a simple method, and thus has an advantage of low manufacturing cost and high yield. Here, the semiconductor layer 110113 and the semiconductor layer 110115 have different impurity concentrations, the semiconductor layer 110113 is used as a channel region, and the semiconductor layer 110115 is used as a source region and a drain region. Thus, the resistivity of the semiconductor layer can be controlled by controlling the impurity concentration. Therefore, the electrical connection state between the semiconductor layer and the conductive film 110123 can be brought close to ohmic connection. Note that as a method of separately forming semiconductor layers having different impurity concentrations, a method of doping impurities into the semiconductor layer using the gate electrode 110117 as a mask can be used.

  The transistor 110102 has a taper angle at the gate electrode 110117. Here, the taper angle is 45 ° or more and less than 95 °, more preferably 60 ° or more and less than 95 °. However, the taper angle may be less than 45 °. Here, the semiconductor layer 110113, the semiconductor layer 110114, and the semiconductor layer 110115 have different impurity concentrations. The semiconductor layer 110113 is used as a channel region, the semiconductor layer 110114 is used as a lightly doped impurity region (LDD), and the semiconductor layer 110115 is used as a source region and a drain region. Thus, the resistivity of the semiconductor layer can be controlled by controlling the impurity concentration. Therefore, the electrical connection state between the semiconductor layer and the conductive film 110123 can be brought close to ohmic connection. Since the LDD region is included, a high electric field is hardly applied to the inside of the transistor, and deterioration of the element due to hot carriers can be suppressed. Note that as a method of separately forming semiconductor layers having different impurity concentrations, a method of doping impurities into the semiconductor layer using the gate electrode 110117 as a mask can be used. In the transistor 110102, since the gate electrode 110117 has a taper angle, the concentration of impurities doped in the semiconductor layer through the gate electrode 110117 can be given a gradient, so that an LDD region can be easily formed. be able to. As a result, there are advantages that the manufacturing cost is low and the yield can be increased.

  In the transistor 110103, the gate electrode 110117 includes at least two layers, and the lower gate electrode has a longer shape than the upper gate electrode. In the present specification, such shapes of the upper gate electrode and the lower gate electrode are referred to as a hat shape. When the gate electrode 110117 has a hat shape, an LDD region can be formed without adding a photomask. Note that a structure in which the LDD region overlaps with the gate electrode 110117 like the transistor 110103 is particularly referred to as a GOLD structure (Gate Overlapped LDD). Note that the following method may be used as a method of making the shape of the gate electrode 110117 into a hat shape.

  First, when the gate electrode 110117 is patterned, the lower gate electrode and the upper gate electrode are etched by dry etching so that the side surfaces are inclined (tapered). Subsequently, the upper-layer gate electrode is processed to be nearly vertical by anisotropic etching. Thereby, a gate electrode having a hat-shaped cross section is formed. After that, by doping the impurity element twice, a semiconductor layer 110113 used as a channel region, a semiconductor layer 110114 used as an LDD region, and a semiconductor layer 110115 used as a source electrode and a drain electrode are formed.

  Note that an LDD region overlapping with the gate electrode 110117 is referred to as a Lov region, and an LDD region not overlapping with the gate electrode 110117 is referred to as a Loff region. The Loff region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain and preventing the deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field near the drain and is effective in preventing deterioration of the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is preferable to manufacture a transistor having a structure corresponding to a required characteristic for each of various circuits. For example, in the case where a semiconductor device is used as a display device, it is preferable to use a transistor having a Loff region as the pixel transistor in order to suppress an off-state current value. On the other hand, as the transistor in the peripheral circuit, it is preferable to use a transistor having a Lov region in order to relax the electric field in the vicinity of the drain and prevent deterioration of the on-current value.

  The transistor 110104 includes a sidewall 110121 in contact with a side surface of the gate electrode 110117. By including the sidewall 110121, a region overlapping with the sidewall 110121 can be an LDD region.

  In the transistor 110105, an LDD (Loff) region is formed by doping a semiconductor layer using a mask. Thus, the LDD region can be formed reliably and the off-state current value of the transistor can be reduced.

  In the transistor 110106, an LDD (Lov) region is formed by doping a semiconductor layer using a mask. Thus, the LDD region can be formed reliably, the electric field in the vicinity of the drain of the transistor can be relaxed, and the deterioration of the on-current value can be reduced.

  Next, an example of a method for manufacturing the transistor is illustrated in FIGS.

  In this embodiment, the surface of the substrate 110111, the surface of the insulating film 110112, the surface of the semiconductor layer 110113, the surface of 110110, the surface of 110110, the surface of the insulating film 110116, the surface of the insulating film 110118, or the surface of the insulating film 110119 By performing oxidation or nitridation using plasma treatment, the semiconductor layer or the insulating film can be oxidized or nitrided. In this manner, the surface of the semiconductor layer or the insulating film is modified by oxidizing or nitriding the semiconductor layer or the insulating film by using plasma treatment, and compared with the insulating film formed by a CVD method or a sputtering method. Thus, a denser insulating film can be formed. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

  For the sidewall 110121, silicon oxide (SiOx) or silicon nitride (SiNx) can be used. As a method of forming the sidewall 110121 on the side surface of the gate electrode 110117, for example, after forming the gate electrode 110117, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is formed, and then oxidized by anisotropic etching. A method of etching a silicon (SiOx) film or a silicon nitride (SiNx) film can be used. By doing so, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film can be left only on the side surface of the gate electrode 110117, so that the sidewall 110121 can be formed on the side surface of the gate electrode 110117.

  FIG. 44 illustrates a cross-sectional structure of a bottom-gate transistor and a cross-sectional structure of a capacitor.

  A first insulating film (insulating film 110502) is formed over the entire surface of the substrate 110501. However, the present invention is not limited to this, and the first insulating film (the insulating film 110502) can be omitted. The first insulating film has a function of preventing impurities from the substrate side from affecting the semiconductor layer and changing the characteristics of the transistor. That is, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. Note that as the first insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  A first conductive layer (a conductive layer 110503 and a conductive layer 110504) is formed over the first insulating film. The conductive layer 110503 includes a portion functioning as the gate electrode of the transistor 110520. The conductive layer 110504 includes a portion functioning as the first electrode of the capacitor 110521. As the first conductive layer, elements such as Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, or these elements can be used. Alloys can be used. Alternatively, a stack of these elements (including alloys) can be used.

  A second insulating film (insulating film 110514) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Note that as the second insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  As the second insulating film in contact with the semiconductor layer, it is desirable to use a silicon oxide film. This is because the trap level at the interface between the semiconductor layer and the second insulating film is reduced.

  When the second insulating film is in contact with Mo, it is desirable to use a silicon oxide film as the second insulating film in the portion in contact with Mo. This is because the silicon oxide film does not oxidize Mo.

  A semiconductor layer is formed by a photolithography method, an inkjet method, a printing method, or the like on part of a portion of the second insulating film that overlaps with the first conductive layer. A part of the semiconductor layer extends to a portion on the second insulating film that is not formed so as to overlap the first conductive layer. The semiconductor layer includes a channel formation region (channel formation region 110510), an LDD region (LDD region 110508, LDD region 110509), and impurity regions (impurity region 110505, impurity region 110506, and impurity region 110507). The channel formation region 110510 functions as a channel formation region of the transistor 110520. The LDD region 110508 and the LDD region 110509 function as an LDD region of the transistor 110520. Note that the LDD region 110508 and the LDD region 110509 are not necessarily required. The impurity region 110505 includes a portion functioning as one of the source electrode and the drain electrode of the transistor 110520. The impurity region 100506 includes a portion functioning as the other of the source electrode and the drain electrode of the transistor 110520. The impurity region 110507 includes a portion functioning as the second electrode of the capacitor 110521.

  A third insulating film (insulating film 110511) is formed over the entire surface over the impurity region 110505, the LDD region 110508, the channel formation region 110510, the LDD region 110509, the impurity region 110506, the second insulating film 110514, and the impurity region 110507. Yes. A contact hole is selectively formed in a part of the third insulating film. The insulating film 110511 has a function as an interlayer film. As the third insulating film, an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, or the like), a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material), or the like can be used. Alternatively, a material containing siloxane can be used. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  A second conductive layer (a conductive layer 110512 and a conductive layer 110513) is formed over the third insulating film. The conductive layer 110512 is connected to the other of the source electrode and the drain electrode of the transistor 110520 through a contact hole formed in the third insulating film. Therefore, the conductive layer 110512 includes a portion functioning as the other of the source electrode and the drain electrode of the transistor 110520. In the case where the conductive layer 110513 is electrically connected to the conductive layer 110504, the conductive layer 110513 includes a portion functioning as the first electrode of the capacitor 110521. Alternatively, in the case where the conductive layer 110513 is electrically connected to the conductive layer 110507, the conductive layer 110513 includes a portion functioning as the second electrode of the capacitor 110521. Alternatively, in the case where the conductive layer 110513 is not connected to the conductive layer 110504 and the conductive layer 110507, a capacitor other than the capacitor 110521 is formed. In this capacitor, the conductive layer 110513, the conductive layer 110507, and the insulating film 110511 are used as the first electrode, the second electrode, and the insulating film of the capacitor, respectively. As the second conductive layer, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, or an alloy thereof is used. Can be used. Alternatively, a stack of these elements (including alloys) can be used.

  As a process after the second conductive layer is formed, various insulating films or various conductive films may be formed.

  Next, the structure of the transistor and the capacitor in the case where an amorphous silicon (a-Si: H) film, a microcrystal silicon film, or the like is used for the semiconductor layer of the transistor will be described.

  FIG. 41 illustrates a cross-sectional structure of a top-gate transistor and a cross-sectional structure of a capacitor.

  A first insulating film (insulating film 110202) is formed over the entire surface of the substrate 110201. The first insulating film has a function of preventing impurities from the substrate side from affecting the semiconductor layer and changing the characteristics of the transistor. That is, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. Note that as the first insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  Note that the first insulating film is not necessarily formed. In this case, the number of processes and the manufacturing cost can be reduced. Further, since the structure can be simplified, the yield can be improved.

  A first conductive layer (a conductive layer 110203, a conductive layer 110204, and a conductive layer 110205) is formed over the first insulating film. The conductive layer 110203 includes a portion functioning as one of a source electrode and a drain electrode of the transistor 110220. The conductive layer 110204 includes a portion functioning as the other of the source electrode and the drain electrode of the transistor 110220. The conductive layer 110205 includes a portion functioning as the first electrode of the capacitor 110221. As the first conductive layer, elements such as Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, or these elements can be used. Alloys can be used. Alternatively, a stack of these elements (including alloys) can be used.

  A first semiconductor layer (semiconductor layer 110206 and semiconductor layer 110207) is formed over the conductive layer 110203 and the conductive layer 110204. The semiconductor layer 110206 includes a portion functioning as one of a source electrode and a drain electrode. The semiconductor layer 110207 includes a portion functioning as the other of the source electrode and the drain electrode. Note that as the first semiconductor layer, silicon containing phosphorus or the like can be used.

  A second semiconductor layer (semiconductor layer 110208) is formed between the conductive layer 110203 and the conductive layer 110204 and over the first insulating film. A part of the semiconductor layer 110208 extends to the conductive layer 110203 and the conductive layer 110204. The semiconductor layer 110208 includes a portion functioning as a channel region of the transistor 110220. Note that as the second semiconductor layer, an amorphous semiconductor layer such as amorphous silicon (a-Si: H) or a semiconductor layer such as a microcrystalline semiconductor (μ-Si: H) can be used. .

  A second insulating film (the insulating film 110209 and the insulating film 110210) is formed so as to cover at least the semiconductor layer 110208 and the conductive layer 110205. The second insulating film functions as a gate insulating film. Note that as the second insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  As the second insulating film in contact with the second semiconductor layer, it is desirable to use a silicon oxide film. This is because trap levels at the interface between the second semiconductor layer and the second insulating film are reduced.

  Note that when the second insulating film is in contact with Mo, it is desirable to use a silicon oxide film as the second insulating film in a portion in contact with Mo. This is because the silicon oxide film does not oxidize Mo.

  A second conductive layer (a conductive layer 110211 and a conductive layer 110212) is formed over the second insulating film. The conductive layer 110211 includes a portion functioning as a gate electrode of the transistor 110220. The conductive layer 110212 functions as the second electrode or the wiring of the capacitor 110221. As the second conductive layer, elements such as Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, or these elements can be used. Alloys can be used. Alternatively, a stack of these elements (including alloys) can be used.

  As a process after the second conductive layer is formed, various insulating films or various conductive films may be formed.

  FIG. 42 illustrates a cross-sectional structure of an inverted staggered (bottom gate) transistor and a cross-sectional structure of a capacitor. In particular, the transistor illustrated in FIG. 42 has a structure called a channel etch type.

  A first insulating film (insulating film 110302) is formed over the entire surface of the substrate 110301. The first insulating film has a function of preventing impurities from the substrate side from affecting the semiconductor layer and changing the characteristics of the transistor. That is, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. Note that as the first insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  Note that the first insulating film is not necessarily formed. In this case, the number of processes and the manufacturing cost can be reduced. Further, since the structure can be simplified, the yield can be improved.

  A first conductive layer (a conductive layer 110303 and a conductive layer 110304) is formed over the first insulating film. The conductive layer 110303 includes a portion functioning as the gate electrode of the transistor 110320. The conductive layer 110304 includes a portion functioning as the first electrode of the capacitor 110321. As the first conductive layer, elements such as Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, or these elements can be used. Alloys can be used. Alternatively, a stack of these elements (including alloys) can be used.

  A second insulating film (insulating film 110305) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Note that as the second insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  As the second insulating film in contact with the semiconductor layer, it is desirable to use a silicon oxide film. This is because trap levels at the interface between the semiconductor layer and the second insulating film are reduced.

  When the second insulating film is in contact with Mo, it is desirable to use a silicon oxide film as the second insulating film in the portion in contact with Mo. This is because the silicon oxide film does not oxidize Mo.

  The first semiconductor layer (semiconductor layer 110306) is formed on a part of the second insulating film which overlaps with the first conductive layer by a photolithography method, an inkjet method, a printing method, or the like. Is formed. A part of the semiconductor layer 110306 is extended to a portion of the second insulating film which is not formed so as to overlap with the first conductive layer. The semiconductor layer 110306 includes a portion functioning as a channel region of the transistor 110320. Note that as the semiconductor layer 110306, an amorphous semiconductor layer such as amorphous silicon (a-Si: H) or a semiconductor layer such as a microcrystalline semiconductor (μ-Si: H) can be used.

  A second semiconductor layer (semiconductor layer 110307 and semiconductor layer 110308) is formed over part of the first semiconductor layer. The semiconductor layer 110307 includes a portion that functions as one of a source electrode and a drain electrode. The semiconductor layer 110308 includes a portion functioning as the other of the source electrode and the drain electrode. Note that as the second conductor layer, silicon containing phosphorus or the like can be used.

  A second conductive layer (a conductive layer 110309, a conductive layer 110310, and a conductive layer 1103111) is formed over the second semiconductor layer and the second insulating film. The conductive layer 110309 includes a portion functioning as one of a source electrode and a drain electrode of the transistor 110320. The conductive layer 110310 includes a portion functioning as the other of the source electrode and the drain electrode of the transistor 110320. The conductive layer 1103111 includes a portion functioning as the second electrode of the capacitor 110321. As the second conductive layer, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, or an alloy thereof is used. Can be used. Alternatively, a stack of these elements (including alloys) can be used.

  Note that as a process after the second conductive layer is formed, various insulating films or various conductive films may be formed.

  Here, an example of a process that is characterized by a channel-etched transistor will be described. The first semiconductor layer and the second semiconductor layer can be formed using the same mask. Specifically, the first semiconductor layer and the second semiconductor layer are continuously formed. At that time, the first semiconductor layer and the second semiconductor layer are formed using the same mask.

  Another example of a process characterized by a channel-etched transistor will be described. The channel region of the transistor can be formed without using a new mask. Specifically, after the second conductive layer is formed, part of the second semiconductor layer is removed using the second conductive layer as a mask. Alternatively, part of the second semiconductor layer is removed using the same mask as the second conductive layer. Then, the first semiconductor layer formed under the removed second semiconductor layer becomes a channel region of the transistor.

  FIG. 43 illustrates a cross-sectional structure of an inverted staggered (bottom gate) transistor and a cross-sectional structure of a capacitor. In particular, the transistor illustrated in FIG. 43 has a structure called a channel protection type (channel stop type).

  A first insulating film (insulating film 110402) is formed over the entire surface of the substrate 110401. The first insulating film has a function of preventing impurities from the substrate side from affecting the semiconductor layer and changing the characteristics of the transistor. That is, the first insulating film functions as a base film. Therefore, a highly reliable transistor can be manufactured. Note that as the first insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  Note that the first insulating film is not necessarily formed. In this case, the number of processes and the manufacturing cost can be reduced. Further, since the structure can be simplified, the yield can be improved.

  A first conductive layer (a conductive layer 110403 and a conductive layer 110404) is formed over the first insulating film. The conductive layer 110403 includes a portion functioning as the gate electrode of the transistor 110420. The conductive layer 110404 includes a portion functioning as the first electrode of the capacitor 110421. As the first conductive layer, elements such as Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, and Ge, or these elements can be used. Alloys can be used. Alternatively, a stack of these elements (including alloys) can be used.

  A second insulating film (insulating film 110405) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. Note that as the second insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  As the second insulating film in contact with the semiconductor layer, it is desirable to use a silicon oxide film. This is because trap levels at the interface between the semiconductor layer and the second insulating film are reduced.

  When the second insulating film is in contact with Mo, it is desirable to use a silicon oxide film as the second insulating film in the portion in contact with Mo. This is because the silicon oxide film does not oxidize Mo.

  The first semiconductor layer (semiconductor layer 110406) is formed on part of the second insulating film which overlaps with the first conductive layer by a photolithography method, an inkjet method, a printing method, or the like. Is formed. A part of the semiconductor layer 110406 is extended to a portion of the second insulating film that is not formed so as to overlap with the first conductive layer. The semiconductor layer 110406 includes a portion functioning as a channel region of the transistor 110420. Note that as the semiconductor layer 110406, an amorphous semiconductor layer such as amorphous silicon (C—Si: H) or a semiconductor layer such as a microcrystalline semiconductor (μ-Si: H) can be used.

  A third insulating film (insulating film 110412) is formed over part of the first semiconductor layer. The insulating film 110412 has a function of preventing the channel region of the transistor 110420 from being removed by etching. That is, the insulating film 110412 functions as a channel protective film (channel stop film). Note that as the third insulating film, a single layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked layer thereof can be used.

  A second semiconductor layer (semiconductor layer 110407 and semiconductor layer 110408) is formed over part of the first semiconductor layer and part of the third insulating film. The semiconductor layer 110407 includes a portion functioning as one of a source electrode and a drain electrode. The semiconductor layer 110408 includes a portion functioning as the other of the source electrode and the drain electrode. Note that as the second conductor layer, silicon containing phosphorus or the like can be used.

  A second conductive layer (a conductive layer 110409, a conductive layer 110410, and a conductive layer 110411) is formed over the second semiconductor layer. The conductive layer 110409 includes a portion functioning as one of a source electrode and a drain electrode of the transistor 110420. The conductive layer 110410 includes a portion functioning as the other of the source electrode and the drain electrode of the transistor 110420. The conductive layer 110411 includes a portion functioning as the second electrode of the capacitor 110421. As the second conductive layer, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, or an alloy thereof is used. Can be used. Alternatively, a stack of these elements (including alloys) can be used.

  As a process after the second conductive layer is formed, various insulating films or various conductive films may be formed.

Up to this point, the structure of the transistor and the method for manufacturing the transistor have been described. Here, wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, and the like are made of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd). , Chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn) , Niobium (Nb), Silicon (Si), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O) Or one or more elements selected from the above, or a compound or alloy material (for example, indium tin oxide (ITO), indium zinc oxide (IZO) containing one or more elements selected from the above group as a component) ) Indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), tin cadmium oxide (CTO), aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium ( Mo—Nb) and the like. Alternatively, the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like are preferably formed using a substance in which these compounds are combined. Or one or more elements selected from the above group and a silicon compound (silicide) (eg, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the above group and nitrogen It is desirable to form the above compound (for example, titanium nitride, tantalum nitride, molybdenum nitride, or the like).

  Silicon (Si) may contain an n-type impurity (such as phosphorus) or a p-type impurity (such as boron). When silicon contains impurities, the conductivity is improved and the same behavior as a normal conductor can be achieved. Therefore, it becomes easy to use as wiring, electrodes, and the like.

  As the silicon, silicon having various crystallinity such as single crystal, polycrystal (polysilicon), and microcrystal (microcrystal silicon) can be used. Alternatively, silicon having no crystallinity such as amorphous (amorphous silicon) can be used. By using single crystal silicon or polycrystalline silicon, resistance of a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like can be reduced. By using amorphous silicon or microcrystalline silicon, a wiring or the like can be formed by a simple process.

  Since aluminum or silver has high conductivity, signal delay can be reduced. Further, since etching is easy, patterning is easy and fine processing can be performed.

  Since copper has high conductivity, signal delay can be reduced. When copper is used, it is desirable to have a laminated structure in order to improve adhesion.

  Molybdenum or titanium is desirable because it does not cause defects even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon, and is easily etched and has high heat resistance.

  Tungsten is desirable because it has advantages such as high heat resistance.

  Neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, heat resistance is improved, and aluminum is less likely to cause hillocks.

  Silicon can be formed at the same time as a semiconductor layer included in the transistor. This is desirable because it has advantages such as high heat resistance.

  ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (SnO), and tin cadmium oxide (CTO) have translucency, so they are used for light transmitting parts. it can. For example, it can be used as a pixel electrode or a common electrode.

  IZO is desirable because it is easy to etch and process. In addition, it is difficult for IZO to leave a residue when it is etched. Therefore, when IZO is used as the pixel electrode, it is possible to reduce the occurrence of defects (short circuit, alignment disorder, etc.) in the liquid crystal element and the light emitting element.

  The wiring, electrode, conductive layer, conductive film, terminal, via, plug, and the like may have a single-layer structure or a multilayer structure. With a single-layer structure, the manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, and the like can be simplified, the number of steps can be reduced, and costs can be reduced. Alternatively, by using a multilayer structure, it is possible to reduce the demerits while making use of the merits of each material, and to form wirings and electrodes having good performance. For example, by including a low resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. As another example, a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials can increase the heat resistance of wiring and electrodes while taking advantage of the low heat-resistant material. it can. For example, a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like is preferable.

  When wires, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, or the like may enter the material of the other wiring, electrode, or the like and change its properties, so that the original purpose cannot be achieved. As another example, when forming or manufacturing a high-resistance portion, a problem may occur that prevents normal manufacture. In such a case, it is preferable to sandwich or cover a material that easily reacts with a material that does not easily react by a laminated structure. For example, when ITO and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between ITO and aluminum. As another example, when silicon and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between silicon and aluminum.

  Wiring means that a conductor is arranged. It may extend linearly or may be arranged short without extending. Therefore, the electrode is included in the wiring.

Carbon nanotubes may be used as wirings, electrodes, conductive layers, conductive films, terminals, vias, plugs, and the like. Furthermore, since the carbon nanotube has translucency, it can be used in a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 9)
In this embodiment, a structure of a display device is described.

  A structure of the display device is described with reference to FIG. FIG. 47A is a top view of a display device.

  A pixel portion 170101, a scanning line side input terminal 170103, and a signal line side input terminal 170104 are formed over the substrate 170100. In addition, a scan line extends from the scan line side input terminal 170103 in the row direction and is formed over the substrate 170100, and a signal line extends from the signal line side input terminal 170104 in the column direction and formed over the substrate 170100. Has been. Pixels 170102 are arranged in a matrix in the pixel portion 170101 in regions where scanning lines and signal lines intersect.

  Up to this point, the case where a signal is input by an external drive circuit has been described. However, the present invention is not limited to this, and an IC chip can be mounted on a display device.

  For example, as illustrated in FIG. 48A, the IC chip 170201 can be mounted on the substrate 170100 by a COG (Chip On Glass) method. In this case, since the IC chip 170201 can be inspected before being mounted on the substrate 170100, the yield of the display device can be improved and the reliability can be increased. Note that portions common to the structure in FIG. 47A are denoted by common reference numerals, and description thereof is omitted.

  As another example, as shown in FIG. 48B, the IC chip 170201 can be mounted on an FPC (Flexible Printed Circuit) 170200 by a TAB (Tape Automated Bonding) method. In this case, since the IC chip 170201 can be inspected before being mounted on the FPC 170200, the yield of the display device can be improved and the reliability can be increased. Note that portions common to the structure in FIG. 47A are denoted by common reference numerals, and description thereof is omitted.

  In addition to mounting an IC chip on the substrate 170100, a driver circuit can be formed over the substrate 170100.

  For example, the scan line driver circuit 170105 can be formed over the substrate 170100 as shown in FIG. In this case, the cost can be reduced by reducing the number of parts. In addition, reliability can be improved by reducing the number of connection points with circuit components. In addition, the scanning line driver circuit 170105 has a low driving frequency. Therefore, the scan line driver circuit 170105 can be easily formed using amorphous silicon or microcrystalline silicon as the semiconductor layer of the transistor. Note that an IC chip for outputting a signal to the signal line may be mounted on the substrate 170100 by a COG method. Alternatively, an FPC on which an IC chip for outputting a signal to a signal line is mounted by a TAB method may be provided on the substrate 170100. An IC chip for controlling the scan line driver circuit 170105 may be mounted on the substrate 170100 by a COG method. Alternatively, an FPC on which an IC chip for controlling the scan line driver circuit 170105 is mounted by a TAB method may be provided over the substrate 170100. Note that portions common to the structure in FIG. 47A are denoted by common reference numerals, and description thereof is omitted.

  As another example, the scan line driver circuit 170105 and the signal line driver circuit 170106 can be formed over a substrate 170100 as shown in FIG. As a result, the cost can be reduced by reducing the number of parts. In addition, reliability can be improved by reducing the number of connection points with circuit components. Note that an IC chip for controlling the scan line driver circuit 170105 may be mounted on the substrate 170100 by a COG method. Alternatively, an FPC on which an IC chip for controlling the scan line driver circuit 170105 is mounted by a TAB method may be provided over the substrate 170100. Further, an IC chip for controlling the signal line driver circuit 170106 may be mounted on the substrate 170100 by a COG method. Alternatively, an FPC on which an IC chip for controlling the signal line driver circuit 170106 is mounted by a TAB method may be provided over the substrate 170100. Note that portions common to the structure in FIG. 47A are denoted by common reference numerals, and description thereof is omitted.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 10)
In this embodiment, a method for driving a display device is described. In particular, a method for driving a liquid crystal display device will be described.

  A liquid crystal panel that can be used for the liquid crystal display device described in this embodiment has a structure in which a liquid crystal material is sandwiched between two substrates. Each of the two substrates includes an electrode for controlling an electric field applied to the liquid crystal material. A liquid crystal material is a material whose optical and electrical properties are changed by an electric field applied from the outside. Therefore, a liquid crystal panel is a device that can obtain desired optical and electrical properties by controlling a voltage applied to a liquid crystal material using an electrode of a substrate. Then, by arranging a large number of electrodes side by side, each pixel is a pixel, and a voltage applied to the pixel is individually controlled, whereby a fine image can be displayed on the liquid crystal panel.

  Here, the response time of the liquid crystal material with respect to the change in the electric field is generally several milliseconds to several tens of milliseconds, although it depends on the distance between the two substrates (cell gap), the type of the liquid crystal material, and the like. Furthermore, when the change amount of the electric field is small, the response time of the liquid crystal material is further increased. This property causes obstacles in image display such as afterimages, tailing and lowering of contrast when displaying moving images with a liquid crystal panel, especially when changing from halftone to another halftone (change in electric field). Is small), the above-mentioned degree of failure becomes significant.

  On the other hand, a problem peculiar to a liquid crystal panel using an active matrix is a change in write voltage due to constant charge driving. Hereinafter, constant charge driving in the present embodiment will be described.

  A pixel circuit in the active matrix includes a switch for controlling writing and a capacitor for holding charge. The driving method of the pixel circuit in the active matrix is that the switch is turned on and a predetermined voltage is written in the pixel circuit, and then the switch is turned off and the charge in the pixel circuit is held (hold state). In the hold state, no charge is exchanged between the inside and outside of the pixel circuit (constant charge). Usually, the period in which the switch is off is several hundred times (the number of scanning lines) times longer than the period in which the switch is on. Therefore, it can be considered that the switch of the pixel circuit is almost off. From the above, it is assumed that the constant charge driving in this embodiment is a driving method in which the pixel circuit is in a hold state in almost all periods when the liquid crystal panel is driven.

  Next, electrical characteristics of the liquid crystal material will be described. In the liquid crystal material, when the electric field applied from the outside changes, the optical properties change and the dielectric constant also changes. That is, when each pixel of the liquid crystal panel is considered as a capacitive element (liquid crystal element) sandwiched between two electrodes, the capacitive element is a capacitive element whose capacitance changes according to an applied voltage. This phenomenon is called dynamic capacitance.

  As described above, when the capacitive element whose capacitance is changed by the applied voltage is driven by the above-described constant charge driving, the following problem occurs. When the capacitance of the liquid crystal element changes in the hold state where no charge is transferred, the applied voltage also changes. This can be understood from the fact that the charge amount is constant in the relational expression (charge amount) = (capacitance) × (applied voltage).

For the above reasons, in the liquid crystal panel using the active matrix, the voltage in the hold state changes from the voltage in the writing state due to the constant charge driving. As a result, the change in the transmittance of the liquid crystal element is different from the change in the driving method that does not take the hold state. This state is shown in FIG. FIG. 45A shows a control example of the voltage written in the pixel circuit, with time on the horizontal axis and absolute value of voltage on the vertical axis. FIG. 45B shows a control example of the voltage written to the pixel circuit when the horizontal axis represents time and the vertical axis represents voltage. FIG. 45C illustrates the time when the horizontal axis represents time, the vertical axis represents the transmittance of the liquid crystal element, and the voltage shown in FIG. 45A or 45B is written in the pixel circuit. It shows the change in transmittance over time. In FIGS. 45A to 45C, a period F represents a voltage rewriting period, and the time for rewriting the voltage is described as t ₁ , t ₂ , t ₃ , and t ₄ .

Here, the writing voltage corresponding to the image data input to the liquid crystal display device is | V ₁ | for rewriting at time 0, and | V ₂ | for rewriting at times t ₁ , t ₂ , t ₃ , and t ₄ . (See FIG. 45A).

  The polarity of the writing voltage corresponding to the image data input to the liquid crystal display device may be periodically switched (inversion driving: see FIG. 45B). By this method, it is possible to prevent a direct current voltage from being applied to the liquid crystal as much as possible, so that it is possible to prevent image sticking due to deterioration of the liquid crystal element. Note that the polarity switching period (inversion period) may be the same as the voltage rewriting period. In this case, since the inversion cycle is short, occurrence of flicker due to inversion driving can be reduced. Further, the inversion cycle may be a cycle that is an integral multiple of the voltage rewrite cycle. In this case, since the inversion period is long and the frequency of writing the voltage by changing the polarity can be reduced, the power consumption can be reduced.

FIG. 45C shows a change over time in the transmittance of the liquid crystal element when a voltage as shown in FIG. 45A or 45B is applied to the liquid crystal element. Here, the voltage | V ₁ | is applied to the liquid crystal element, and the transmittance of the liquid crystal element after a sufficient time has elapsed is defined as TR ₁ . Similarly, the transmissivity of the liquid crystal element after the voltage | V ₂ | is applied to the liquid crystal element and a sufficient time has elapsed is defined as TR ₂ . When the voltage applied to the liquid crystal element changes from | V ₁ | to | V ₂ | at time t ₁ , the transmittance of the liquid crystal element does not immediately become TR ₂ as indicated by a broken line 30401, It changes slowly. For example, the rewriting period of the voltage, when the same as the frame period of the image signal of 60 Hz (16.7 msec), until the transmittance is changed to TR _2, it is necessary to time of several frames.

However, the smooth transmittance change with time as indicated by a broken line 30401 is obtained when the voltage | V ₂ | is accurately applied to the liquid crystal element. In an actual liquid crystal panel, for example, a liquid crystal panel using an active matrix, the voltage in the hold state changes from the voltage in the writing state due to constant charge driving. Instead of the time change as shown in FIG. 2, instead of the time change as shown by the solid line 30402. This is because the voltage changes due to the constant charge driving, and the target voltage cannot be reached by one writing. As a result, the response time of the transmissivity of the liquid crystal element is apparently longer than the original response time (broken line 30401), and noticeable image display problems such as afterimage, tailing, and contrast decrease are remarkable. It will cause.

By using the overdrive drive, it is possible to simultaneously solve the problem of the longer response time due to the inherent response time of the liquid crystal element and insufficient writing due to dynamic capacitance and constant charge drive. . This is shown in FIG. FIG. 46A shows a control example of the voltage written in the pixel circuit, with the horizontal axis representing time and the vertical axis representing absolute voltage. FIG. 46B shows a control example of the voltage written to the pixel circuit when the horizontal axis represents time and the vertical axis represents voltage. In FIG. 46C, time is plotted on the horizontal axis and the transmittance of the liquid crystal element is plotted on the vertical axis, and the voltage shown in FIG. 46A or 46B is written in the pixel circuit. It shows the change in transmittance over time. In FIG. 46A to FIG. 46C, a period F represents a voltage rewriting cycle, and the time for rewriting the voltage is described as t ₁ , t ₂ , t ₃ , and t ₄ .

Here, the writing voltage corresponding to the image data input to the liquid crystal display device is | V ₁ | for rewriting at time 0, | V ₃ | for rewriting at time t ₁ , and at times t ₂ , t ₃ , t ₄ In rewriting, it is assumed that | V ₂ | (see FIG. 46A).

  The polarity of the writing voltage corresponding to the image data input to the liquid crystal display device may be periodically switched (inversion driving: see FIG. 46B). By this method, it is possible to prevent a direct current voltage from being applied to the liquid crystal as much as possible, so that it is possible to prevent image sticking due to deterioration of the liquid crystal element. Note that the polarity switching period (inversion period) may be the same as the voltage rewriting period. In this case, since the inversion cycle is short, occurrence of flicker due to inversion driving can be reduced. Further, the inversion cycle may be a cycle that is an integral multiple of the voltage rewrite cycle. In this case, since the inversion period is long and the frequency of writing the voltage by changing the polarity can be reduced, the power consumption can be reduced.

FIG. 46C shows a change over time in the transmittance of the liquid crystal element when a voltage as illustrated in FIG. 46A or FIG. 46B is applied to the liquid crystal element. Here, the voltage | V ₁ | is applied to the liquid crystal element, and the transmittance of the liquid crystal element after a sufficient time has elapsed is defined as TR ₁ . Similarly, the transmissivity of the liquid crystal element after the voltage | V ₂ | is applied to the liquid crystal element and a sufficient time has elapsed is defined as TR ₂ . Similarly, the voltage | V ₃ | is applied to the liquid crystal element, and the transmittance of the liquid crystal element after a sufficient time has elapsed is defined as TR ₃ . When the voltage applied to the liquid crystal element changes from | V ₁ | to | V ₃ | at time t ₁ , the transmittance of the liquid crystal element takes several frames as shown by the broken line 30501, and the transmittance is changed to TR. Try to change up to ₃ . However, the voltage | _{V 3} | applied at the end at time _{t 2,} later than time _{t 2,} the voltage | _{V 2} | is applied. Therefore, the transmittance of the liquid crystal element is not as indicated by the broken line 30501 but as indicated by the solid line 30502. Here, it is preferable to set the value of the voltage | V ₃ | so that the transmittance is approximately TR ₂ at the time t ₂ . Here, the voltage | V ₃ | is also referred to as an overdrive voltage.

If the overdrive voltage | V ₃ | is changed, the response time of the liquid crystal element can be controlled to some extent. This is because the response time of the liquid crystal element changes depending on the strength of the electric field. Specifically, the stronger the electric field, the shorter the response time of the liquid crystal element, and the weaker the electric field, the longer the response time of the liquid crystal element.

The overdrive voltage | V ₃ | is preferably changed according to the amount of voltage change, that is, the voltages | V ₁ | and | V ₂ | that give the desired transmittances TR ₁ and TR ₂ . This is because even if the response time of the liquid crystal element changes depending on the amount of change in voltage, the optimum response time can always be obtained by changing the overdrive voltage | V ₃ | accordingly. is there.

The overdrive voltage | V ₃ | is preferably changed according to the mode of the liquid crystal element such as TN, VA, IPS, OCB. This is because even if the response speed of the liquid crystal element varies depending on the mode of the liquid crystal, an optimal response time can always be obtained by changing the overdrive voltage | V ₃ | accordingly. .

  The voltage rewriting period F may be the same as the frame period of the input signal. In this case, since the peripheral drive circuit of the liquid crystal display device can be simplified, a liquid crystal display device with low manufacturing cost can be obtained.

  The voltage rewriting period F may be shorter than the frame period of the input signal. For example, the voltage rewriting period F may be 1/2 times, 1/3 times, or less than the frame period of the input signal. This method is effective when used in combination with measures for reducing the quality of moving images caused by hold driving of liquid crystal display devices, such as black insertion driving, backlight blinking, backlight scanning, and intermediate image insertion driving by motion compensation. is there. That is, since the response time of the required liquid crystal element is short as a countermeasure against the degradation of the moving image quality caused by the hold driving of the liquid crystal display device, the overdrive driving method described in this embodiment can be used relatively. The response time of the liquid crystal element can be easily shortened. The response time of the liquid crystal element can be essentially shortened by the cell gap, the liquid crystal material, the mode of the liquid crystal element, etc., but is technically difficult. Therefore, it is very important to use a method of shortening the response time of the liquid crystal element by a driving method such as overdrive.

  The voltage rewriting period F may be longer than the frame period of the input signal. For example, the voltage rewrite period F may be twice, three times, or more than the frame period of the input signal. This method is effective when used in combination with means (circuit) for determining whether or not voltage rewriting is not performed for a long period of time. That is, when the voltage is not rewritten for a long time, the operation of the circuit can be stopped during the period by not performing the voltage rewriting operation itself, so that a liquid crystal display device with low power consumption is obtained. Can do.

Next, a specific method for changing the overdrive voltage | V ₃ | according to the voltages | V ₁ | and | V ₂ | that give the desired transmittances TR ₁ and TR ₂ will be described.

The overdrive circuit is a circuit for appropriately controlling the overdrive voltage | V ₃ | according to the voltages | V ₁ | and | V ₂ | that give the desired transmittances TR ₁ and TR _2. Signals input to the drive circuit are a signal related to the voltage | V ₁ | giving the transmittance TR ₁ and a signal related to the voltage | V ₂ | giving the transmittance TR ₂ , and are outputted from the overdrive circuit. Is a signal related to the overdrive voltage | V ₃ |. Here, these signals may be analog voltage values such as voltages (| V ₁ |, | V ₂ |, | V ₃ |) applied to the liquid crystal element, or may be applied to the liquid crystal element. It may be a digital signal for applying a voltage. Here, it is assumed that the signal related to the overdrive circuit is a digital signal.

  First, the overall structure of the overdrive circuit will be described with reference to FIG. Here, input image signals 30101a and 30101b are used as signals for controlling the overdrive voltage. As a result of processing these signals, an output image signal 30104 is output as a signal for giving an overdrive voltage.

Since the voltages | V ₁ | and | V ₂ | that give the desired transmittances TR ₁ and TR ₂ are image signals in frames adjacent to each other, the input image signals 30101a and 30101b are also adjacent to each other. An image signal in a frame is preferable. In order to obtain such a signal, the input image signal 30101a can be input to the delay circuit 30102 in FIG. 82A, and the output signal can be used as the input image signal 30101b. An example of the delay circuit 30102 is a memory. That is, in order to delay the input image signal 30101a by one frame, the input image signal 30101a is stored in the memory, and at the same time, the signal stored in the previous frame is stored in the memory as the input image signal 30101b. The input image signal 30101a and the input image signal 30101b are input to the correction circuit 30103 at the same time, so that image signals in adjacent frames can be handled. Then, by inputting image signals in adjacent frames to the correction circuit 30103, an output image signal 30104 can be obtained. Note that when a memory is used as the delay circuit 30102, a memory having a capacity capable of storing an image signal for one frame (that is, a frame memory) can be used in order to delay by one frame. By doing so, it is possible to have a function as a delay circuit without excessive or insufficient memory capacity.

  Next, a delay circuit 30102 configured mainly for the purpose of reducing the memory capacity will be described. By using such a circuit as the delay circuit 30102, the memory capacity can be reduced, so that the manufacturing cost can be reduced.

  As the delay circuit 30102 having such characteristics, specifically, a circuit as illustrated in FIG. 82B can be used. A delay circuit 30102 illustrated in FIG. 82B includes an encoder 30105, a memory 30106, and a decoder 30107.

  The operation of the delay circuit 30102 shown in FIG. 82 (B) is as follows. First, before the input image signal 30101a is stored in the memory 30106, the encoder 30105 performs compression processing. As a result, the size of data to be stored in the memory 30106 can be reduced. As a result, since the memory capacity can be reduced, the manufacturing cost can be reduced. Then, the compressed image signal is sent to the decoder 30107 where the decompression process is performed. As a result, the previous signal compressed by the encoder 30105 can be restored. Here, the compression / decompression process performed by the encoder 30105 and the decoder 30107 may be a reversible process. In this way, since the image signal is not deteriorated even after the compression / decompression process, the memory capacity can be reduced without degrading the quality of the image finally displayed on the apparatus. Further, the compression / decompression process performed by the encoder 30105 and the decoder 30107 may be an irreversible process. By doing so, the data size of the image signal after compression can be made very small, so that the memory capacity can be greatly reduced.

  As a method for reducing the memory capacity, various methods can be used in addition to the above-described methods. Rather than compressing the image by the encoder, the color information of the image signal is reduced (for example, the color is reduced from 260,000 colors to 65,000 colors), or the data amount is reduced (the resolution is reduced). The method can be used.

  Next, specific examples of the correction circuit 30103 will be described with reference to FIGS. The correction circuit 30103 is a circuit for outputting an output image signal having a certain value from two input image signals. Here, when the relationship between the two input image signals and the output image signal is nonlinear and it is difficult to obtain by a simple calculation, a lookup table (LUT) may be used as the correction circuit 30103. In the LUT, the relationship between the two input image signals and the output image signal is obtained in advance by measurement. Therefore, the output image signals corresponding to the two input image signals can be obtained simply by referring to the LUT. (See FIG. 82C). By using the LUT 30108 as the correction circuit 30103, the correction circuit 30103 can be realized without performing complicated circuit design or the like.

  Since the LUT 30108 is one of the memories, it is preferable to reduce the memory capacity as much as possible in order to reduce the manufacturing cost. As an example of the correction circuit 30103 for realizing this, a circuit shown in FIG. 82D can be considered. A correction circuit 30103 illustrated in FIG. 82D includes an LUT 30109 and an adder 30110. The LUT 30109 stores difference data between the input image signal 30101a and the output image signal 30104 to be output. That is, corresponding difference data is extracted from the LUT 30109 from the input image signal 30101a and the input image signal 30101b, and the output image signal 30104 is obtained by adding the extracted difference data and the input image signal 30101a by the adder 30110. it can. Note that the memory capacity of the LUT 30109 can be reduced by using the difference data as the data stored in the LUT 30109. This is because the data size of the difference data is smaller than that of the output image signal 30104 as it is, so that the memory capacity required for the LUT 30109 can be reduced.

  Furthermore, if the output image signal is obtained by a simple operation such as four arithmetic operations of two input image signals, it can be realized by a combination of simple circuits such as an adder, a subtracter, and a multiplier. As a result, it is not necessary to use an LUT, and the manufacturing cost can be greatly reduced. As such a circuit, a circuit shown in FIG. 82E can be given. A correction circuit 30103 illustrated in FIG. 82E includes a subtractor 30111, a multiplier 30112, and an adder 30113. First, a subtracter 30111 obtains a difference between the input image signal 30101a and the input image signal 30101b. Thereafter, the multiplier 30112 multiplies the difference value by an appropriate coefficient. Then, an output image signal 30104 can be obtained by adding a difference value obtained by multiplying the input image signal 30101a by an appropriate coefficient by the adder 30113. By using such a circuit, it is not necessary to use an LUT, and the manufacturing cost can be greatly reduced.

  By using the correction circuit 30103 illustrated in FIG. 82E under certain conditions, output of an inappropriate output image signal 30104 can be prevented. The condition is that the difference value between the output image signal 30104 giving the overdrive voltage and the input image signal 30101a and the input image signal 30101b has linearity. Then, the linearity gradient is used as a coefficient multiplied by the multiplier 30112. That is, it is preferable to use a correction circuit 30103 illustrated in FIG. 82E for a liquid crystal element having such properties. As a liquid crystal element having such properties, an IPS mode liquid crystal element in which the response speed is small in gradation dependency can be given. As described above, for example, by using the correction circuit 30103 shown in FIG. 82E for the liquid crystal element in the IPS mode, the manufacturing cost can be significantly reduced, and an inappropriate output image signal 30104 can be output. An overdrive circuit that can be prevented can be obtained.

  Functions equivalent to the circuits shown in FIGS. 82A to 82E may be realized by software processing. As for the memory used for the delay circuit, other memory included in the liquid crystal display device, memory included in a device that sends an image to be displayed on the liquid crystal display device (for example, a video card included in a personal computer or a similar device, etc.) Can be diverted. By doing so, not only can the manufacturing cost be reduced, but also the user can select the strength of overdrive, the situation of use, etc. according to his / her preference.

  Next, driving for manipulating the potential of the common line will be described with reference to FIG. FIG. 83A illustrates a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. FIG. A pixel circuit illustrated in FIG. 83A includes a transistor 30201, an auxiliary capacitor 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

  The gate electrode of the transistor 30201 is electrically connected to the scan line 30205, one of the source electrode and the drain electrode of the transistor 30201 is electrically connected to the video signal line 30204, and the other of the source electrode and the drain electrode of the transistor 30201 Are electrically connected to one electrode of the auxiliary capacitor 30202 and one electrode of the display element 30203. The other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206.

  First, since the transistor 30201 is turned on in the pixel selected by the scanning line 30205, a voltage corresponding to the video signal is applied to the display element 30203 and the auxiliary capacitor 30202 through the video signal line 30204, respectively. At this time, when the video signal is to display the lowest gradation for all the pixels connected to the common line 30206, or the highest gradation for all the pixels connected to the common line 30206. Is displayed, it is not necessary to write a video signal to each pixel via the video signal line 30204. Instead of writing a video signal through the video signal line 30204, the voltage applied to the display element 30203 can be changed by moving the potential of the common line 30206.

  Next, FIG. 83B illustrates a plurality of cases where two common lines are arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. It is a figure showing this pixel circuit. A pixel circuit illustrated in FIG. 83B includes a transistor 30211, an auxiliary capacitor 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217.

  The gate electrode of the transistor 30211 is electrically connected to the scan line 30215, one of the source electrode and the drain electrode of the transistor 30211 is electrically connected to the video signal line 30214, and the other of the source electrode and the drain electrode of the transistor 30211 Is electrically connected to one electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213. In addition, the other electrode of the auxiliary capacitor 30212 is electrically connected to the first common line 30216. In the pixel adjacent to the pixel, the other electrode of the auxiliary capacitor 30212 is electrically connected to the second common line 30217.

  Since the pixel circuit illustrated in FIG. 83B has few pixels that are electrically connected to one common line, instead of writing a video signal through the video signal line 30214, the first common line 30216 or The frequency at which the voltage applied to the display element 30213 can be changed by moving the potential of the second common line 30217 is significantly increased. Further, source inversion driving or dot inversion driving is possible. By source inversion driving or dot inversion driving, flicker can be suppressed while improving the reliability of the element.

  Next, a scanning backlight will be described with reference to FIG. FIG. 84A is a diagram showing a scanning backlight in which cold cathode tubes are juxtaposed. The scanning backlight shown in FIG. 84A includes a diffusion plate 30301 and N cold cathode fluorescent lamps 30302-1 to 30302-N. N cold cathode tubes 30302-1 to 30302 -N are juxtaposed behind the diffuser plate 30301, so that the N cold cathode tubes 30302-1 to 30302 -N scan with varying luminance. Can do.

  A change in luminance of each cold cathode tube during scanning will be described with reference to FIG. First, the luminance of the cold cathode fluorescent lamp 30302-1 is changed for a certain time. Thereafter, the luminance of the cold cathode tube 30302-2 arranged next to the cold cathode tube 30302-1 is changed for the same time. In this way, the luminance is changed in order from the cold cathode fluorescent lamps 30302-1 to 30302-N. Note that in FIG. 84C, the luminance to be changed for a certain period of time is smaller than the original luminance, but may be larger than the original luminance. Further, although the cold cathode fluorescent lamps 30302-1 to 30302-N are scanned, the cold cathode fluorescent lamps 30302-N to 30302-1 may be scanned in the reverse direction.

  By driving as shown in FIG. 84C, the average luminance of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for most of the power consumption of the liquid crystal display device, can be reduced.

  An LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. A scanning backlight shown in FIG. 84B includes a diffusion plate 30311 and light sources 30312-1 to 30312 -N in which LEDs are juxtaposed. When an LED is used as the light source of the scanning backlight, there is an advantage that the backlight can be made thin and light. Further, there is an advantage that the color reproduction range can be expanded. Furthermore, since the LEDs juxtaposed in each of the light sources 30312-1 to 30312 -N in which the LEDs are juxtaposed can also be scanned in the same manner, a point scanning backlight can also be obtained. If the point scanning type is adopted, the image quality of the moving image can be further improved.

  Even when an LED is used as the light source of the backlight, it can be driven by changing the luminance as shown in FIG.

  Next, high frequency driving will be described with reference to FIG. FIG. 85A is a diagram when one image and one intermediate image are displayed in one frame period 30400. 30401 is an image of the frame, 30402 is an intermediate image of the frame, 30403 is an image of the next frame, and 30404 is an intermediate image of the next frame.

  The intermediate image 30402 of the frame may be an image created based on the video signal of the frame and the next frame. Further, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Further, the intermediate image 30402 of the frame may be a black image. By doing so, the image quality of the moving image of the hold type display device can be improved. In the case where one image and one intermediate image are displayed in one frame period 30400, there is an advantage that consistency with the frame rate of the video signal can be easily obtained and the image processing circuit is not complicated.

  FIG. 85B is a diagram when one image and two intermediate images are displayed in a period in which two one-frame periods 30400 are continuous (two-frame periods). Reference numeral 30411 denotes an image of the frame, 30412 denotes an intermediate image of the frame, 30413 denotes an intermediate image of the next frame, and 30414 denotes an image of the next frame.

  The intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the frame, the next frame, and the next frame. Further, the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be black images. When one image and two intermediate images are displayed in two frame periods, there is an advantage that the image quality of the moving image can be effectively improved without significantly increasing the operating frequency of the peripheral drive circuit.

  In this embodiment mode, various drawings have been used. However, the contents (may be a part) described in each figure are applied to the contents (may be a part) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (or part of the contents) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (or part of the contents) described in the figure of another embodiment. I can do it. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 11)
In the present embodiment, the peripheral portion of the liquid crystal panel will be described.

  FIG. 49 is a diagram illustrating an example of a liquid crystal display device including a backlight unit 20101 called an edge light type and a liquid crystal panel 20107. The edge light type is a method in which a light source is arranged at the end of the backlight unit and the fluorescence of the light source is emitted from the entire light emitting surface. The edge light type backlight unit 20101 is thin and can save power.

  The backlight unit 20101 includes a diffusing plate 20102, a light guide plate 20103, a reflecting plate 20104, a lamp reflector 20105, and a light source 20106.

  The light source 20106 has a function of emitting light as necessary. For example, as the light source 20106, a cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL element, an organic EL element, or the like is used.

  50A, 50B, 50C, and 50D are diagrams showing a detailed configuration of an edge light type backlight unit. Note that description of the diffusion plate, the light guide plate, the reflection plate, and the like is omitted.

  A backlight unit 20201 illustrated in FIG. 50A has a structure in which a cold cathode tube 20203 is used as a light source. A lamp reflector 20202 is provided in order to reflect light from the cold cathode tube 20203 efficiently. Such a structure has high luminance from the cold cathode fluorescent lamp 20203 and is therefore often used for a large display device.

  A backlight unit 20211 illustrated in FIG. 50B includes a light-emitting diode (LED) 20213 as a light source. For example, light emitting diodes (LEDs) 20213 that emit white light are arranged at predetermined intervals. In order to efficiently reflect light from the light emitting diode (LED) 20213, a lamp reflector 20212 is provided.

  A backlight unit 20221 illustrated in FIG. 50C includes a light-emitting diode (LED) 20223, a light-emitting diode (LED) 20224, and a light-emitting diode (LED) 20225 for each color RGB as a light source. The light emitting diodes (LEDs) 20223, the light emitting diodes (LEDs) 20224, and the light emitting diodes (LEDs) 20225 of each color RGB are arranged at predetermined intervals. By using the light emitting diode (LED) 20223, the light emitting diode (LED) 20224, and the light emitting diode (LED) 20225 for each color RGB, color reproducibility can be improved. A lamp reflector 20222 is provided to efficiently reflect light from the light emitting diode.

  A backlight unit 20231 illustrated in FIG. 50D includes a light-emitting diode (LED) 20233, a light-emitting diode (LED) 20234, and a light-emitting diode (LED) 20235 for each color RGB as a light source. For example, among the light emitting diodes (LEDs) 20233, the light emitting diodes (LEDs) 20234, and the light emitting diodes (LEDs) 20235 of the respective colors RGB, a color having a lower light emission intensity (for example, green) is arranged more than the other light emitting diodes. By using the light emitting diode (LED) 20233, the light emitting diode (LED) 20234, and the light emitting diode (LED) 20235 for each color RGB, color reproducibility can be improved. A lamp reflector 20232 is provided to efficiently reflect light from the light emitting diode.

  FIG. 53 is a diagram illustrating an example of a liquid crystal display device including a backlight unit called a direct type and a liquid crystal panel. The direct type is a method in which a light source is arranged directly under a light emitting surface to emit fluorescence of the light source from the entire light emitting surface. The direct type backlight unit can efficiently use the amount of emitted light.

  The backlight unit 20500 includes a diffusion plate 20501, a light shielding plate 20502, a lamp reflector 20503, a light source 20504, and a liquid crystal panel 20505.

  The light source 20504 has a function of emitting light as necessary. For example, as the light source 20504, a cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL element, an organic EL element, or the like is used.

  FIG. 51 is a diagram illustrating an example of a configuration of a polarizing plate (also referred to as a polarizing film).

  The polarizing film 20300 includes a protective film 20301, a substrate film 20302, a PVA polarizing film 20303, a substrate film 20304, an adhesive layer 20305, and a release film 20306.

  The reliability of the PVA polarizing film 20303 can be increased by sandwiching both sides with films (substrate film 20302 and substrate film 20304) serving as base materials. The PVA polarizing film 20303 may be sandwiched between highly transparent and highly durable triacetyl cellulose (TAC) films. In addition, a board | substrate film and a TAC film function as a protective layer of the polarizer which the PVA polarizing film 20303 has.

  One substrate film (substrate film 20304) has an adhesive layer 20305 attached to a glass substrate of a liquid crystal panel. Note that the adhesive layer 20305 is formed by applying an adhesive to a substrate film (substrate film 20304) on one side. The pressure-sensitive adhesive layer 20305 is provided with a release film 20306 (separate film).

  The other substrate film (substrate film 20302) is provided with a protective film 20301.

  A hard coat scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 20300. The hard coat scattering layer has fine irregularities formed on the surface by AG treatment, and has an antiglare function for scattering external light, so that reflection of external light on the liquid crystal panel can be prevented. Moreover, surface reflection can be prevented.

  A plurality of optical thin film layers having different refractive indexes may be formed on the surface of the polarizing film 20300 (also referred to as anti-reflection treatment or AR treatment). A plurality of multilayered optical thin film layers having different refractive indexes can reduce the reflectance of the surface due to the interference effect of light.

  FIG. 52 is a diagram illustrating an example of a system block of the liquid crystal display device.

  In the pixel portion 20405, a signal line 20412 is extended from the signal line driver circuit 20403. In the pixel portion 20405, a scan line 20410 is arranged extending from the scan line driver circuit 20404. A plurality of pixels are arranged in a matrix in the intersection region between the signal line 20412 and the scanning line 20410. Note that each of the plurality of pixels has a switching element. Therefore, a voltage for controlling the tilt of the liquid crystal molecules can be independently input to each of the plurality of pixels. Such a structure in which switching elements are provided in each crossing region is called an active matrix type. However, it is not limited to such an active matrix type, and may be a passive matrix type configuration. The passive matrix type has a simple process because each pixel has no switching element.

  The driver circuit portion 20408 includes a control circuit 20402, a signal line driver circuit 20403, and a scan line driver circuit 20404. A video signal 20401 is input to the control circuit 20402. The control circuit 20402 controls the signal line driver circuit 20403 and the scanning line driver circuit 20404 in accordance with the video signal 20401. The control circuit 20402 inputs control signals to the signal line driver circuit 20403 and the scan line driver circuit 20404, respectively. In response to this control signal, the signal line driver circuit 20403 inputs a video signal to the signal line 20412, and the scan line driver circuit 20404 inputs a scan signal to the scan line 20410. Then, a switching element included in the pixel is selected according to the scanning signal, and a video signal is input to the pixel electrode of the pixel.

  The control circuit 20402 also controls the power supply 20407 in accordance with the video signal 20401. The power supply 20407 has means for supplying power to the lighting means 20406. As the lighting unit 20406, an edge light type backlight unit or a direct type backlight unit can be used. However, a front light may be used as the illumination unit 20406. The front light is a plate-like light unit that is mounted on the front side of the pixel portion and is composed of a light emitter and a light guide that illuminate the whole. Such illumination means can illuminate the pixel portion evenly with low power consumption.

  As illustrated in FIG. 52B, the scan line driver circuit 20404 includes circuits that function as a shift register 20441, a level shifter 20442, and a buffer 20443. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 20441.

  As shown in FIG. 52C, the signal line driver circuit 20403 includes circuits functioning as a shift register 20431, a first latch 20432, a second latch 20433, a level shifter 20434, and a buffer 20435. A circuit functioning as the buffer 20435 is a circuit having a function of amplifying a weak signal and includes an operational amplifier or the like. A signal such as a start pulse (SSP) is input to the level shifter 20434, and data (DATA) such as a video signal is input to the first latch 20432. A latch (LAT) signal can be temporarily stored in the second latch 20433 and is input to the pixel portion 20405 all at once. This is called line sequential driving. Therefore, the second latch can be omitted if the pixel performs dot sequential driving instead of line sequential driving.

  In this embodiment mode, various liquid crystal panels can be used. For example, a configuration in which a liquid crystal layer is sealed between two substrates can be used as the liquid crystal panel. On one substrate, a transistor, a capacitor, a pixel electrode, an alignment film, or the like is formed. A polarizing plate, a phase difference plate, or a prism sheet may be disposed on the side opposite to the upper surface of one substrate. On the other substrate, a color filter, a black matrix, a counter electrode, an alignment film, or the like is formed. A polarizing plate or a retardation plate may be disposed on the side opposite to the upper surface of the other substrate. Note that the color filter and the black matrix may be formed on the upper surface of one of the substrates. Further, three-dimensional display can be performed by arranging slits (lattices) on the upper surface side of one substrate or the opposite side thereof.

  Each of the polarizing plate, the retardation film and the prism sheet can be disposed between the two substrates. Alternatively, it can be integrated with either of the two substrates.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 12)
In this embodiment, a pixel structure and a pixel operation which can be applied to the liquid crystal display device will be described.

  In this embodiment mode, the operation mode of the liquid crystal element includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, and a PV. Patterned Vertical Alignment (ASM) mode, Asymmetrically Aligned Micro-cell (ASM) mode, Optical Compensated Bireflective Liquid (Cr) mode, and FLC (Ferroelectric Liquid AF) mode Crystal) mode or the like can be used.

  FIG. 54A illustrates an example of a pixel structure which can be applied to the liquid crystal display device.

  The pixel 40100 includes a transistor 40101, a liquid crystal element 40102, and a capacitor 40103. A gate of the transistor 40101 is connected to the wiring 40105. A first terminal of the transistor 40101 is connected to the wiring 40104. A second terminal of the transistor 40101 is connected to the first electrode of the liquid crystal element 40102 and the first electrode of the capacitor 40103. The second electrode of the liquid crystal element 40102 corresponds to the counter electrode 40107. A second electrode of the capacitor 40103 is connected to the wiring 40106.

  The wiring 40104 functions as a signal line. The wiring 40105 functions as a scanning line. The wiring 40106 functions as a capacitor line. The transistor 40101 functions as a switch. The capacitor 40103 functions as a storage capacitor.

  The transistor 40101 may function as a switch. The polarity of the transistor 40101 may be a P-channel type or an N-channel type.

  FIG. 54B illustrates an example of a pixel structure which can be applied to the liquid crystal display device. In particular, FIG. 54B illustrates an example of a pixel structure which can be applied to a liquid crystal display device suitable for a horizontal electric field mode (including an IPS mode and an FFS mode).

  The pixel 40110 includes a transistor 40111, a liquid crystal element 40112, and a capacitor 40113. A gate of the transistor 40111 is connected to the wiring 40115. A first terminal of the transistor 40111 is connected to the wiring 40114. A second terminal of the transistor 40111 is connected to the first electrode of the liquid crystal element 40112 and the first electrode of the capacitor 40113. A second electrode of the liquid crystal element 40112 is connected to the wiring 40116. A second electrode of the capacitor 40113 is connected to the wiring 40116.

  The wiring 40114 functions as a signal line. The wiring 40115 functions as a scanning line. The wiring 40116 functions as a capacitor line. The transistor 40111 functions as a switch. The capacitor 40113 functions as a storage capacitor.

  The transistor 40111 may function as a switch. The polarity of the transistor 40111 may be a P-channel type or an N-channel type.

  FIG. 55 is a diagram illustrating an example of a pixel configuration applicable to the liquid crystal display device. In particular, FIG. 55 illustrates an example of a pixel configuration in which the number of wirings can be reduced and the pixel aperture ratio can be increased.

  FIG. 55 shows two pixels (pixel 40200 and pixel 40210) arranged in the same column direction. For example, when the pixel 40200 is arranged in the Nth row, the pixel 40210 is arranged in the N + 1th row.

  The pixel 40200 includes a transistor 40201, a liquid crystal element 40202, and a capacitor 40203. A gate of the transistor 40201 is connected to the wiring 40205. A first terminal of the transistor 40201 is connected to the wiring 40204. A second terminal of the transistor 40201 is connected to the first electrode of the liquid crystal element 40202 and the first electrode of the capacitor 40203. The second electrode of the liquid crystal element 40202 corresponds to the counter electrode 40207. A second electrode of the capacitor 40203 is connected to the same wiring as the gate of the transistor in the previous row.

  A pixel 40210 includes a transistor 40211, a liquid crystal element 40212, and a capacitor 40213. A gate of the transistor 40211 is connected to the wiring 40215. A first terminal of the transistor 40211 is connected to the wiring 40204. A second terminal of the transistor 40211 is connected to the first electrode of the liquid crystal element 40212 and the first electrode of the capacitor 40213. The second electrode of the liquid crystal element 40212 corresponds to the counter electrode 40217. The second electrode of the capacitor 40213 is connected to the same wiring (wiring 40205) as the gate of the preceding transistor.

  The wiring 40204 functions as a signal line. The wiring 40205 functions as an Nth row scanning line. The wiring 40205 also functions as an N + 1 stage capacitor line. The transistor 40201 functions as a switch. The capacitor 40203 functions as a storage capacitor.

  The wiring 40215 functions as a scan line in the (N + 1) th row. The wiring 40215 also functions as an N + 2 stage capacitor line. The transistor 40211 functions as a switch. The capacitor 40213 functions as a storage capacitor.

  The transistor 40201 and the transistor 40211 may function as switches. Further, the polarity of the transistor 40201 and the polarity of the transistor 40211 may be a P-channel type or an N-channel type.

  FIG. 56 is a diagram illustrating an example of a pixel configuration applicable to the liquid crystal display device. In particular, FIG. 56 shows an example of a pixel configuration in which the viewing angle can be improved by using sub-pixels.

  The pixel 40320 includes a sub-pixel 40300 and a sub-pixel 40310. Hereinafter, a case where the pixel 40320 includes two sub-pixels will be described; however, the pixel 40320 may include three or more sub-pixels.

  The subpixel 40300 includes a transistor 40301, a liquid crystal element 40302, and a capacitor 40303. A gate of the transistor 40301 is connected to the wiring 40305. A first terminal of the transistor 40301 is connected to the wiring 40304. A second terminal of the transistor 40301 is connected to the first electrode of the liquid crystal element 40302 and the first electrode of the capacitor 40303. The second electrode of the liquid crystal element 40302 corresponds to the counter electrode 40307. A second electrode of the capacitor 40303 is connected to the wiring 40306.

  The subpixel 40310 includes a transistor 40311, a liquid crystal element 40312, and a capacitor 40313. A gate of the transistor 40311 is connected to the wiring 40315. A first terminal of the transistor 40311 is connected to the wiring 40304. A second terminal of the transistor 40311 is connected to the first electrode of the liquid crystal element 40312 and the first electrode of the capacitor 40313. A second electrode of the liquid crystal element 40312 corresponds to the counter electrode 40317. A second electrode of the capacitor 40313 is connected to the wiring 40306.

  The wiring 40304 functions as a signal line. The wiring 40305 functions as a scanning line. The wiring 40315 functions as a signal line. The wiring 40306 functions as a capacitor line. The transistor 40301 functions as a switch. The transistor 40311 functions as a switch. The capacitor 40303 functions as a storage capacitor. The capacitor 40313 functions as a storage capacitor.

  The transistor 40301 may function as a switch. The polarity of the transistor 40301 may be a P-channel type or an N-channel type. The transistor 40311 may function as a switch. The polarity of the transistor 40311 may be a P-channel type or an N-channel type.

  The video signal input to the sub-pixel 40300 may have a value different from the video signal input to the sub-pixel 40310. In this case, the alignment angle of the liquid crystal molecules of the liquid crystal element 40302 is different from the alignment of the liquid crystal molecules of the liquid crystal element 40312, so that the viewing angle can be widened.

  Note that in this embodiment mode, description has been made with reference to various drawings. However, the contents described in each drawing (may be a part) are different from the contents described in another figure (may be a part). , Application, combination or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 13)
In this embodiment, various liquid crystal modes will be described.

  First, various liquid crystal modes will be described with reference to cross-sectional views.

  FIGS. 57A and 57B are schematic views of cross sections of a TN mode.

  A liquid crystal layer 50100 is sandwiched between a first substrate 50101 and a second substrate 50102 which are arranged to face each other. A first electrode 50105 is formed on the top surface of the first substrate 50101. A second electrode 50106 is formed on the top surface of the second substrate 50102. A first polarizing plate 50103 is provided on the opposite side of the first substrate 50101 from the liquid crystal layer 50100. On the opposite side of the second substrate 50102 from the liquid crystal layer 50100, a second polarizing plate 50104 is provided. Note that the first polarizing plate 50103 and the second polarizing plate 50104 are arranged to be crossed Nicols.

  The first polarizing plate 50103 may be disposed on the top surface of the first substrate 50101, that is, between the first substrate 50101 and the liquid crystal layer 50100. The second polarizing plate 50104 may be disposed on the upper surface of the second substrate 50102, that is, between the second substrate 50102 and the liquid crystal layer 50100.

  It is sufficient that at least one of the first electrode 50105 and the second electrode 50106 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 57A is a schematic view of a cross section when voltage is applied to the first electrode 50105 and the second electrode 50106 (referred to as a vertical electric field mode).

  FIG. 57B is a schematic view of a cross section when voltage is not applied to the first electrode 50105 and the second electrode 50106.

  58A and 58B are schematic views of cross sections of the VA mode. The VA mode is a mode in which liquid crystal molecules are aligned so as to be perpendicular to the substrate when there is no electric field.

  A liquid crystal layer 50200 is sandwiched between a first substrate 50201 and a second substrate 50202 which are arranged to face each other. A first electrode 50205 is formed on the top surface of the first substrate 50201. A second electrode 50206 is formed on the top surface of the second substrate 50202. A first polarizing plate 50203 is provided on the opposite side of the first substrate 50201 from the liquid crystal layer 50200. A second polarizing plate 50204 is provided on the opposite side of the second substrate 50202 from the liquid crystal layer 50200. Note that the first polarizing plate 50203 and the second polarizing plate 50204 are arranged so as to be crossed Nicols.

  The first polarizing plate 50203 may be disposed on the top surface of the first substrate 50201, that is, between the first substrate 50201 and the liquid crystal layer 50200. The second polarizing plate 50204 may be disposed on the upper surface of the second substrate 50202, that is, between the second substrate 50202 and the liquid crystal layer 50200.

  It is sufficient that at least one of the first electrode 50205 and the second electrode 50206 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 58A is a schematic view of a cross section when voltage is applied to the first electrode 50205 and the second electrode 50206 (referred to as a vertical electric field mode).

  FIG. 58B is a schematic view of a cross section when voltage is not applied to the first electrode 50205 and the second electrode 50206.

  58C and 58D are schematic views of cross sections of the MVA mode. The MVA mode is a method for mutually compensating the viewing angle dependency of each part.

  A liquid crystal layer 50210 is sandwiched between a first substrate 50211 and a second substrate 50212 which are arranged to face each other. A first electrode 50215 is formed on the top surface of the first substrate 50211. A second electrode 50216 is formed on the top surface of the second substrate 50212. A first protrusion 50217 is formed over the first electrode 50215 for alignment control. A second protrusion 50218 is formed over the second electrode 50216 for alignment control. A first polarizing plate 50213 is provided on the opposite side of the first substrate 50211 from the liquid crystal layer 50210. A second polarizing plate 50214 is provided on the side of the second substrate 50212 opposite to the liquid crystal layer 50210. Note that the first polarizing plate 50213 and the second polarizing plate 50214 are arranged so as to be crossed Nicols.

  The first polarizing plate 50213 may be disposed on the top surface of the first substrate 50211, that is, between the first substrate 50211 and the liquid crystal layer 50210. The second polarizing plate 50214 may be disposed on the upper surface of the second substrate 50212, that is, between the second substrate 50212 and the liquid crystal layer 50210.

  It is sufficient that at least one of the first electrode 50215 and the second electrode 50216 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 58C is a schematic view of a cross section in the case where voltage is applied to the first electrode 50215 and the second electrode 50216 (referred to as a vertical electric field mode).

  FIG. 58D is a schematic view of a cross section when voltage is not applied to the first electrode 50215 and the second electrode 50216.

  FIGS. 59A and 59B are schematic views of cross sections of the OCB mode. In the OCB mode, the alignment of the liquid crystal molecules forms an optically compensated state in the liquid crystal layer, and thus the viewing angle dependency is small. This state of the liquid crystal molecules is called bend alignment.

  A liquid crystal layer 50300 is sandwiched between a first substrate 50301 and a second substrate 50302 which are arranged to face each other. A first electrode 50305 is formed on the top surface of the first substrate 50301. A second electrode 50306 is formed on the top surface of the second substrate 50302. A first polarizing plate 50303 is provided on the opposite side of the first substrate 50301 from the liquid crystal layer 50300. A second polarizing plate 50304 is disposed on the opposite side of the second substrate 50302 from the liquid crystal layer 50300. Note that the first polarizing plate 50303 and the second polarizing plate 50304 are arranged so as to be crossed Nicols.

  The first polarizing plate 50303 may be disposed on the top surface of the first substrate 50301, that is, between the first substrate 50301 and the liquid crystal layer 50300. The second polarizing plate 50304 may be disposed on the upper surface of the second substrate 50302, that is, between the second substrate 50302 and the liquid crystal layer 50300.

  It is sufficient that at least one of the first electrode 50305 and the second electrode 50306 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 59A is a schematic view of a cross section when voltage is applied to the first electrode 50305 and the second electrode 50306 (referred to as a vertical electric field mode).

  FIG. 59B is a schematic view of a cross section when voltage is not applied to the first electrode 50305 and the second electrode 50306.

  FIGS. 59C and 59D are schematic views of cross sections of the FLC mode or the AFLC mode.

  A liquid crystal layer 50310 is sandwiched between a first substrate 50311 and a second substrate 50312 which are arranged to face each other. A first electrode 50315 is formed on the top surface of the first substrate 50311. A second electrode 50316 is formed on the top surface of the second substrate 5031. A first polarizing plate 50313 is provided on the opposite side of the first substrate 50311 from the liquid crystal layer 50310. A second polarizing plate 50314 is provided on the opposite side of the second substrate 5031 from the liquid crystal layer 50310. Note that the first polarizing plate 50313 and the second polarizing plate 50314 are arranged so as to be crossed Nicols.

  The first polarizing plate 50313 may be disposed on the top surface of the first substrate 50311, that is, between the first substrate 50311 and the liquid crystal layer 50310. The second polarizing plate 50314 may be disposed on the top surface of the second substrate 5031, that is, between the second substrate 5031 and the liquid crystal layer 50310.

  It is sufficient that at least one of the first electrode 50315 and the second electrode 50316 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 59C is a schematic view of a cross section when voltage is applied to the first electrode 50315 and the second electrode 50316 (referred to as a vertical electric field mode).

  FIG. 59D is a schematic view of a cross section when voltage is not applied to the first electrode 50315 and the second electrode 50316.

  60A and 60B are schematic views of cross sections of the IPS mode. The IPS mode is a mode in which the alignment of liquid crystal molecules can be optically compensated in the liquid crystal layer, and the liquid crystal molecules are always rotated in a plane with respect to the substrate. A lateral electric field method in which electrodes are provided only on one substrate side is used. Take.

  A liquid crystal layer 50400 is sandwiched between a first substrate 50401 and a second substrate 50402 which are arranged to face each other. A first electrode 50405 and a second electrode 50406 are formed on the top surface of the second substrate 50402. A first polarizing plate 50403 is provided on the opposite side of the first substrate 50401 from the liquid crystal layer 50400. A second polarizing plate 50404 is provided on the opposite side of the second substrate 50402 from the liquid crystal layer 50400. Note that the first polarizing plate 50403 and the second polarizing plate 50404 are arranged so as to be crossed Nicols.

  The first polarizing plate 50403 may be disposed on the top surface of the first substrate 50401, that is, between the first substrate 50401 and the liquid crystal layer. The second polarizing plate 50404 may be disposed on the upper surface of the second substrate 50402, that is, between the second substrate 50402 and the liquid crystal layer.

  It is sufficient that at least one of the first electrode 50405 and the second electrode 50406 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 60A is a schematic view of a cross section when voltage is applied to the first electrode 50405 and the second electrode 50406 (referred to as a vertical electric field mode).

  FIG. 60B is a schematic view of a cross section when voltage is not applied to the first electrode 50405 and the second electrode 50406.

  60C and 60D are schematic views of cross sections of the FFS mode. The FFS mode is a mode in which the alignment of liquid crystal molecules can be optically compensated in the liquid crystal layer, and the liquid crystal molecules are always rotated in a plane with respect to the substrate. Take.

  A liquid crystal layer 50410 is sandwiched between a first substrate 50411 and a second substrate 50412 which are arranged to face each other. A second electrode 50416 is formed on the top surface of the second substrate 50412. An insulating film 50417 is formed on the top surface of the second electrode 50416. A first electrode 50415 is formed over the insulating film 50417. A first polarizing plate 50413 is provided on the opposite side of the first substrate 50411 from the liquid crystal layer 50410. A second polarizing plate 50414 is provided on the opposite side of the second substrate 50412 from the liquid crystal layer 50410. Note that the first polarizing plate 50413 and the second polarizing plate 50414 are arranged so as to be crossed Nicols.

  The first polarizing plate 50413 may be disposed on the top surface of the first substrate 50411, that is, between the first substrate 50411 and the liquid crystal layer 50410. The second polarizing plate 50414 may be disposed on the upper surface of the second substrate 50412, that is, between the second substrate 50412 and the liquid crystal layer 50410.

  It is sufficient that at least one of the first electrode 50415 and the second electrode 50416 has a light-transmitting property (a transmission type or a reflection type). Or both electrodes may have translucency and a part of one electrode may have reflectivity (semi-transmissive type).

  FIG. 60C is a schematic view of a cross section when voltage is applied to the first electrode 50415 and the second electrode 50416 (referred to as a vertical electric field mode).

  FIG. 60D is a schematic view of a cross section when voltage is not applied to the first electrode 50415 and the second electrode 50416.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 14)
In this embodiment mode, a pixel structure of a display device is described. In particular, a pixel structure of a liquid crystal display device will be described.

  A pixel structure in which each liquid crystal mode and a transistor are combined will be described with reference to a cross-sectional view of the pixel.

  As the transistor, a thin film transistor (TFT) including a non-single-crystal semiconductor layer typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystalline or semi-amorphous) silicon, or the like can be used.

  As a structure of the transistor, a top gate type, a bottom gate type, or the like can be used. As the bottom-gate transistor, a channel etch type, a channel protection type, or the like can be used.

  FIG. 61 is an example of a cross-sectional view of a pixel in the case where a TN mode and a transistor are combined. The first substrate 10101 and the second substrate 10116 sandwich the liquid crystal 10111 including the liquid crystal molecules 10118. A transistor, a pixel electrode, an alignment film, and the like are arranged on the first substrate 10101, and a light-shielding film 10114, a color filter 10115, a counter electrode, an alignment film, and the like are arranged on the second substrate 10116. A spacer 10117 is provided between the first substrate 10101 and the second substrate 10116. By applying the pixel structure shown in FIG. 61 to a liquid crystal display device, the liquid crystal display device can be manufactured at low cost.

  FIG. 62A illustrates an example of a cross-sectional view of a pixel in the case where a multi-domain vertical alignment (MVA) method and a transistor are combined. The first substrate 10201 and the second substrate 10216 sandwich the liquid crystal 10211 including the liquid crystal molecules 10218. A transistor, a pixel electrode, an alignment film, and the like are provided on the first substrate 10201, and a light-shielding film 10214, a color filter 10215, a counter electrode, an alignment control protrusion 10219, an alignment film, and the like are provided on the second substrate 10216. Has been. A spacer 10217 is provided between the first substrate 10201 and the second substrate 10216. By applying the pixel structure shown in FIG. 62A to a liquid crystal display device, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

  FIG. 62B is an example of a cross-sectional view of a pixel in the case where a PVA (Patterned Vertical Alignment) method and a transistor are combined. The first substrate 10231 and the second substrate 10246 sandwich the liquid crystal 10241 including the liquid crystal molecules 10248. A transistor, a pixel electrode, an alignment film, and the like are provided on the first substrate 10231, and a light-shielding film 10244, a color filter 10245, a counter electrode, an alignment film, and the like are provided on the second substrate 10231. Note that the pixel electrode has an electrode cutout portion 10249. A spacer 10247 is provided between the first substrate 10231 and the second substrate 10246. By applying the pixel structure shown in FIG. 62B to a liquid crystal display device, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

  FIG. 63A is an example of a cross-sectional view of a pixel in the case where an IPS (In-Plane-Switching) method and a transistor are combined. The first substrate 10301 and the second substrate 10316 sandwich the liquid crystal 10311 including the liquid crystal molecules 10318. A transistor, a pixel electrode, a common electrode, an alignment film, and the like are formed over the first substrate 10301, and a light shielding film 10314, a color filter 10315, an alignment film, and the like are formed over the second substrate 10316. A spacer 10317 is formed between the first substrate 10301 and the second substrate 10316. By applying the pixel structure shown in FIG. 63A to a liquid crystal display device, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

FIG. 63B is an example of a cross-sectional view of a pixel in the case where an FFS (Fringe Field Switching) method and a transistor are combined. The first substrate 10331 and the second substrate 10346 sandwich the liquid crystal 10341 including the liquid crystal molecules 10348. A transistor, a pixel electrode, a common electrode, an alignment film, and the like are provided on the first substrate 10331, and a light-shielding film 10344, a color filter 10345, an alignment film, and the like are provided on the second substrate 10346. A spacer 10347 is provided between the first substrate 10331 and the second substrate 10346. By applying the pixel structure shown in FIG. 63B to a liquid crystal display device, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

  Here, materials that can be used for each conductive layer or each insulating film will be described.

  The first insulating film 10102 in FIG. 61, the first insulating film 10202 in FIG. 62A, the first insulating film 10232 in FIG. 62B, the first insulating film 10302 in FIG. As the first insulating film 10332 of 63 (B), an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride (SiOxNy) film can be used. Alternatively, an insulating film having a stacked structure in which two or more films of a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiOxNy) film, and the like are combined can be used.

  The first conductive layer 10103 in FIG. 61, the first conductive layer 10203 in FIG. 62A, the first conductive layer 10233 in FIG. 62B, the first conductive layer 10303 in FIG. As the first conductive layer 10333 of 63 (B), Mo, Ti, Al, Nd, Cr, or the like can be used. Alternatively, a stacked structure in which two or more of Mo, Ti, Al, Nd, Cr, and the like are combined can be used.

  The second insulating film 10104 in FIG. 61, the second insulating film 10204 in FIG. 62A, the second insulating film 10234 in FIG. 62B, the second insulating film 10304 in FIG. As the second insulating film 10334 in FIG. 63B, a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used. Alternatively, a stacked structure in which two or more of thermal oxide films, silicon oxide films, silicon nitride films, silicon oxynitride films, or the like are combined can be used. Note that the portion in contact with the semiconductor layer is preferably a silicon oxide film. This is because the trap level at the interface with the semiconductor layer is reduced when a silicon oxide film is used. Note that the portion in contact with Mo is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

  The first semiconductor layer 10105 in FIG. 61, the first semiconductor layer 10205 in FIG. 62A, the first semiconductor layer 10235 in FIG. 62B, the first semiconductor layer 10305 in FIG. As the first semiconductor layer 10335 of 63 (B), silicon, silicon germanium (SiGe), or the like can be used.

  The second semiconductor layer 10106 in FIG. 61, the second semiconductor layer 10206 in FIG. 62A, the second semiconductor layer 10236 in FIG. 62B, the second semiconductor layer 10306 in FIG. As the second semiconductor layer 10336 of 63 (B), silicon containing phosphorus or the like can be used.

  The second conductive layer 10107, the third conductive layer 10109, and the fourth conductive layer 10113 in FIG. 61, the second conductive layer 10207, the third conductive layer 10209, and the fourth conductive layer 10213 in FIG. 62B, the second conductive layer 10237, the third conductive layer 10239, and the fourth conductive layer 10243, the second conductive layer 10307 and the third conductive layer 10309 in FIG. 63A, or FIG. As the transparent material of the second conductive layer 10337, the third conductive layer 10339, and the fourth conductive layer 10343 of 63 (B), an indium tin oxide (ITO) film in which tin oxide is mixed with indium oxide is used. Indium tin oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (ISO) in which zinc oxide is mixed with indium oxide (I O) film, such as a zinc oxide film or tin oxide film may be used. Note that IZO is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt% of zinc oxide (ZnO) is mixed with ITO.

  The second conductive layer 10107 and the third conductive layer 10109 in FIG. 61, the second conductive layer 10207 and the third conductive layer 10209 in FIG. 62A, the second conductive layer 10237 in FIG. The third conductive layer 10239, the second conductive layer 10307 and the third conductive layer 10309 in FIG. 63A, or the second conductive layer 10337, the third conductive layer 10339, and the fourth in FIG. As the reflective material of the conductive layer 10343, Ti, Mo, Ta, Cr, W, Al, or the like can be used. Alternatively, a two-layer structure in which Ti, Mo, Ta, Cr, and W and Al are stacked, or a three-layer stack structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may be used.

  The third insulating film 10108 in FIG. 61, the third insulating film 10208 in FIG. 62A, the third insulating film 10238 in FIG. 62B, the third conductive layer 10239 in FIG. As the third insulating film 10308 in FIG. 63A, the third insulating film 10338, and the fourth insulating film 10349 in FIG. 63B, an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) or A low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material) or the like can be used. Alternatively, a material containing siloxane can be used. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The first alignment film 10110 and the second alignment film 10112 in FIG. 61, the first alignment film 10210 and the second alignment film 10212 in FIG. 62A, the first alignment film 10240 in FIG. As the second alignment film 10242, the first alignment film 10310 and the second alignment film 10312 in FIG. 63A, and the first alignment film 10340 and the second alignment film 10342 in FIG. A polymer film such as can be used.

  Next, a pixel structure in which each liquid crystal mode and a transistor are combined will be described with reference to a top view (layout diagram) of the pixel.

  As the liquid crystal mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, and a PVA (Pertified Pattern) mode are used. ASM (Axial Symmetrical Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antirefractive Liquid mode) It can be used.

  FIG. 64 is an example of a top view of a pixel in the case where a TN mode and a transistor are combined. By applying the pixel structure shown in FIG. 64 to a liquid crystal display device, the liquid crystal display device can be manufactured at low cost.

  The pixel shown in FIG. 64 includes a scan line 10401, a video signal line 10402, a capacitor line 10403, a transistor 10404, a pixel electrode 10405, and a pixel capacitor 10406.

  FIG. 65A is an example of a top view of a pixel in the case where an MVA method and a transistor are combined. By applying the pixel structure illustrated in FIG. 65A to a liquid crystal display device, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

  A pixel illustrated in FIG. 65A includes a scan line 10501, a video signal line 10502, a capacitor line 10503, a transistor 10504, a pixel electrode 10505, a pixel capacitor 10506, and an alignment control protrusion 10507.

  FIG. 65B is an example of a top view of a pixel in the case where a PVA method and a transistor are combined. By applying the pixel structure shown in FIG. 65B to a liquid crystal display device, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

  A pixel illustrated in FIG. 65B includes a scan line 10511, a video signal line 10512, a capacitor line 10513, a transistor 10514, a pixel electrode 10515, a pixel capacitor 10516, and an electrode notch portion 10517.

  FIG. 66A is an example of a top view of a pixel in the case where an IPS mode and a transistor are combined. By applying the pixel structure shown in FIG. 66A to a liquid crystal display device, a liquid crystal display device with a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

  A pixel illustrated in FIG. 66A includes a scan line 10601, a video signal line 10602, a common electrode 10603, a transistor 10604, and a pixel electrode 10605.

  FIG. 66B is a top view of a pixel in the case where the FFS method and a transistor are combined. By applying the pixel structure shown in FIG. 66B to a liquid crystal display device, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

  A pixel illustrated in FIG. 66B includes a scan line 10611, a video signal line 10612, a common electrode 10613, a transistor 10614, and a pixel electrode 10615.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 15)
In this embodiment mode, a structure of a pixel of a display device and an operation of the pixel will be described.

  67A and 67B are timing charts showing an example of digital time grayscale driving. The timing chart in FIG. 67A shows a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are separated.

A period for completely displaying an image for one display area is called one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required for signal writing to pixels for all rows, and the periods Tb1 to Tb4 indicate the time required for signal writing to pixels for one row (or one pixel). The sustain periods Ts1 to Ts4 indicate the time during which the lighting or non-lighting state is maintained according to the video signal written to the pixel, and the ratio of the lengths is Ts1: Ts2: Ts3: Ts4 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1. The gradation is expressed by the sustain period during which light is emitted.

  Here, with reference to FIG. 67B, description will be made focusing on the i-th pixel row. First, in the address period Ta1, a pixel selection signal is input to the scanning line in order from the first row, and in the address period Ta1, a pixel in the i-th row is selected in the period Tb1 (i). Then, when the i-th row pixel is selected, a video signal is input from the signal line to the i-th row pixel. When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. By this written video signal, lighting and non-lighting of the pixel in the i-th row in the sustain period Ts1 are controlled. Similarly, a video signal is input to the i-th row pixel in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of the i-th row pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. In each subframe period, the pixel is not lit during the address period, and after the address period ends, the sustain period starts, and the pixel in which a signal for lighting is written is lit.

  Here, the case where a 4-bit gradation is expressed has been described, but the number of bits and the number of gradations are not limited thereto. Note that the order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of light sources. Note that the lighting times of Ts1, Ts2, Ts3, and Ts4 do not need to be a power of 2, but may be the same length of lighting time or may be slightly shifted from the power of 2.

  Next, a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are not separated will be described. The pixels in the row where the video signal writing operation is completed hold the signal until the signal is written (or erased) to the pixel next time. The period from the writing operation to the next signal writing to this pixel is called the data holding time. During this data holding time, the pixel is turned on or off according to the video signal written to the pixel. The same operation is performed up to the last line, and the address period ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended.

  As described above, when the signal writing operation is completed and the data retention time is reached, in the driving method in which the pixels are immediately turned on or off according to the video signal written to the pixels, signals cannot be input to two rows at the same time. . Therefore, since the address periods must not overlap, the data holding time cannot be made shorter than the address period. As a result, high gradation display becomes difficult.

  Therefore, by providing an erasing period, a data holding time shorter than the address period is set. FIG. 68A shows a driving method in the case where an erasing period is provided and a data holding time shorter than the address period is set.

  Here, the i-th pixel row will be described with reference to FIG. In the address period Ta1, a pixel scanning signal is input to the scanning line in order from the first row, and a pixel is selected. Then, when the i-th row pixel is selected in the period Tb1 (i), a video signal is input to the i-th row pixel. When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. By the written video signal, lighting and non-lighting of the pixel in the i-th row in the sustain period Ts1 (i) are controlled. That is, when the video signal writing operation is completed in the i-th row, the pixel in the i-th row is turned on or off in accordance with the written video signal. Similarly, a video signal is input to the i-th row pixel in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of the i-th row pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. The end of the sustain period Ts4 (i) is set by starting the erase operation. This is because, during the erasing time Te (i) of the i-th row, the light is forcibly turned off regardless of the video signal written to the pixel of the i-th row. That is, when the erasing time Te (i) starts, the data holding time of the pixel in the i-th row ends.

  Therefore, it is possible to provide a display device having a high gradation and a high duty ratio (the ratio of the lighting period in one frame period) having a data retention time shorter than the address period without separating the address period and the sustain period. . Since the instantaneous luminance can be lowered, the reliability of the display element can be improved.

  Here, the case where a 4-bit gradation is expressed has been described, but the number of bits and the number of gradations are not limited thereto. Further, the lighting order need not be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of light emission. Further, the lighting times of Ts1, Ts2, Ts3, and Ts4 do not need to be a power of 2, but may be the same lighting time or may be shifted from a power of 2.

  A structure and operation of a pixel to which digital time gray scale driving can be applied will be described.

  FIG. 69 is a diagram illustrating an example of a pixel configuration to which digital time gray scale driving can be applied.

  The pixel 80300 includes a switching transistor 80301, a driving transistor 80302, a light-emitting element 80304, and a capacitor 80303. The switching transistor 80301 has a gate connected to the scan line 80306, a first electrode (one of the source electrode and the drain electrode) connected to the signal line 80305, and a second electrode (the other of the source electrode and the drain electrode). Are connected to the gate of the driving transistor 80302. The driving transistor 80302 has a gate connected to the power supply line 80307 through the capacitor 80303, a first electrode connected to the power supply line 80307, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 80304. It is connected to the. The second electrode of the light emitting element 80304 corresponds to the common electrode 80308.

  A low power supply potential is set for the second electrode (the common electrode 80308) of the light-emitting element 80304. The low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80307. Even if GND, 0V, or the like is set as the low power supply potential, for example. Good. A potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 80304 so that a current flows through the light emitting element 80304. Here, in order to cause the light-emitting element 80304 to emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the light-emitting element 80304.

  The capacitor 80303 can be omitted by using the gate capacitance of the driving transistor 80302 instead. With respect to the gate capacitance of the driving transistor 80302, the source region, the drain region, the LDD region, or the like may overlap with the gate electrode, and the capacitance may be formed in an overlapping region. Alternatively, a capacitor may be formed between the channel region and the gate electrode.

  In the case of the voltage input voltage driving method, a video signal that is in two states, that is, whether the driving transistor 80302 is sufficiently turned on or off is input to the gate of the driving transistor 80302. That is, the driving transistor 80302 operates in a linear region.

  When the driving transistor 80302 inputs a video signal that operates in a saturation region, a current can flow through the light-emitting element 80304. If the light-emitting element 80304 is an element that determines luminance in accordance with current, reduction in luminance due to deterioration of the light-emitting element 80304 can be suppressed. Further, when the video signal is analog, current corresponding to the video signal can flow through the light-emitting element 80304. In this case, analog gradation driving can be performed.

  A configuration and operation of a pixel called a threshold voltage correction type will be described. The threshold voltage correction type pixel can be applied to digital time gray scale driving and analog gray scale driving.

  FIG. 70 is a diagram illustrating an example of a configuration of a pixel called a threshold voltage correction type.

  70 includes a driving transistor 80600, a first switch 80601, a second switch 80602, a third switch 80603, a first capacitor element 80604, a second capacitor element 80605, and a light-emitting element 80620. ing. The gate of the driving transistor 80600 is connected to the signal line 80611 through the first capacitor 80604 and the first switch 80601 in this order. In addition, the gate of the driving transistor 80600 is connected to the power supply line 80612 through the second capacitor element 80605. A first electrode of the driving transistor 80600 is connected to the power supply line 80612. The second electrode of the driving transistor 80600 is connected to the first electrode of the light-emitting element 80620 through the third switch 80603. The second electrode of the driving transistor 80600 is connected to the gate of the driving transistor 80600 via the second switch 80602. The second electrode of the light-emitting element 80620 corresponds to the common electrode 80621. Note that the first switch 80601, the second switch 80602, and the third switch 80603 are a signal input to the first scan line 80613, a signal input to the second scan line 80615, and a third scan, respectively. On / off is controlled by a signal input to the line 80614.

  The pixel configuration illustrated in FIG. 70 is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG. For example, the second switch 80602 is a P-channel transistor or an N-channel transistor, the third switch 80603 is a transistor having a polarity different from that of the second switch 80602, and the second switch The 80602 and the third switch 80603 may be controlled by the same scanning line.

  A structure and operation of a pixel called a current input type will be described. The current input type pixel can be applied to digital gradation driving and analog gradation driving.

  FIG. 71 is a diagram illustrating an example of a configuration of a pixel called a current input type.

  A pixel shown in FIG. 71 includes a driving transistor 80700, a first switch 80701, a second switch 80702, a third switch 80703, a capacitor 80704, and a light-emitting element 80730. The gate of the driving transistor 80700 is connected to the signal line 80711 through the second switch 80702 and the first switch 80701 in this order. The gate of the driving transistor 80700 is connected to the power supply line 80712 through the capacitor 80704. A first electrode of the driving transistor 80700 is connected to the power supply line 80712. A second electrode of the driving transistor 80700 is connected to the signal line 80711 through the first switch 80701. The second electrode of the driving transistor 80700 is connected to the first electrode of the light-emitting element 80730 through the third switch 80703. The second electrode of the light-emitting element 80730 corresponds to the common electrode 80731. Note that the first switch 80701, the second switch 80702, and the third switch 80703 are a signal input to the first scan line 80713, a signal input to the second scan line 80714, and a third scan, respectively. On / off is controlled by a signal input to a line 80715.

  The pixel configuration illustrated in FIG. 71 is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG. For example, the first switch 80701 is formed using a P-channel transistor or an N-channel transistor, the second switch 80702 is formed using a transistor having the same polarity as the first switch 80701, and the first switch 80701 and the second switch 80701 Two switches 80702 may be controlled by the same scanning line. The second switch 80702 may be disposed between the gate of the driving transistor 80700 and the signal line 80711.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 16)
In this embodiment mode, a pixel structure of a display device is described. In particular, a pixel structure of a display device using an organic EL element will be described.

  FIG. 72A is an example of a top view (layout diagram) of a pixel having two transistors in one pixel. FIG. 72B is an example of a cross-sectional view taken along line X-X ′ illustrated in FIG.

  FIG. 72A illustrates a first transistor 60105, a first wiring 60106, a second wiring 60107, a second transistor 60108, a third wiring 60111, a counter electrode 60112, a capacitor 60113, a pixel electrode 60115, and a partition wall 60116. , An organic conductor film 60117, an organic thin film 60118, and a substrate 60119 are shown. Note that the first transistor 60105 is preferably used as a switching transistor, and the second transistor 60108 is preferably used as a driving transistor. The first wiring 60106 is preferably used as a gate signal line, the second wiring 60107 is used as a source signal line, and the third wiring 60111 is preferably used as a current supply line.

  The gate electrode of the first transistor 60105 is electrically connected to the first wiring 60106. One of the source electrode and the drain electrode of the first transistor 60105 is electrically connected to the second wiring 60107. The other of the source electrode and the drain electrode of one transistor 60105 is electrically connected to the gate electrode of the second transistor 60108 and one electrode of the capacitor 60113. Note that the gate electrode of the first transistor 60105 includes a plurality of gate electrodes. Thus, leakage current in the off state of the first transistor 60105 can be reduced.

  One of a source electrode and a drain electrode of the second transistor 60108 is electrically connected to the third wiring 60111, and the other of the source electrode and the drain electrode of the second transistor 60108 is electrically connected to the pixel electrode 60115. Has been. Accordingly, the current flowing through the pixel electrode 60115 can be controlled by the second transistor 60108.

  An organic conductor film 60117 is provided over the pixel electrode 60115, and an organic thin film 60118 (organic compound layer) is further provided. A counter electrode 60112 is provided over the organic thin film 60118 (organic compound layer). Note that the counter electrode 60112 may be formed so as to be commonly connected to all the pixels, or may be patterned using a shadow mask or the like.

  Light emitted from the organic thin film 60118 (organic compound layer) is emitted through either the pixel electrode 60115 or the counter electrode 60112.

  In FIG. 72B, the case where light is emitted to the pixel electrode side, that is, the side where a transistor or the like is formed is called bottom emission, and the case where light is emitted to the counter electrode side is called top emission.

  In the case of bottom emission, the pixel electrode 60115 is preferably formed using a transparent conductive film. Conversely, in the case of top emission, the counter electrode 60112 is preferably formed using a transparent conductive film.

  In a light emitting device for color display, EL elements having emission colors of R, G, and B may be created separately, or monochromatic EL elements are formed uniformly and light emission of R, G, and B is performed by a color filter. May be obtained.

  The configuration illustrated in FIG. 72 is merely an example, and various configurations other than the configuration illustrated in FIG. 72 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. As the light emitting element, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 17)
In this embodiment, the structure of an EL element will be described. In particular, the structure of the organic EL element will be described.

  The structure of the mixed junction type EL element will be described. For example, a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material It is not a layered structure that clearly distinguishes, but a layer in which a plurality of materials are mixed among materials such as a hole injection material, a hole transport material, a light emitting material, an electron transport material, and an electron injection material ( A structure having a mixed layer (hereinafter referred to as a mixed junction type EL element) will be described.

  73A, 73B, 73C, 73D, and 73E are schematic views illustrating the structure of a mixed junction EL element. Note that a layer sandwiched between the anode 190101 and the cathode 190102 corresponds to an EL layer.

  The structure shown in FIG. 73A includes a hole transport region 190103 in which the EL layer is made of a hole transport material and an electron transport region 190104 made of an electron transport material. The hole transport region 190103 is located on the anode side with respect to the electron transport region 190104. In addition, a mixed region 190105 including both a hole transport material and an electron transport material is provided between the hole transport region 190103 and the electron transport region 190104.

  In the direction from the anode 190101 to the cathode 190102, the concentration of the hole transport material in the mixed region 190105 decreases and the concentration of the electron transport material in the mixed region 190105 increases.

  The method of setting the concentration gradient can be set freely. For example, the hole transport region 190103 made of only the hole transport material does not exist, and the concentration ratio of each functional material changes in the mixed region 190105 including both the hole transport material and the electron transport material (concentration gradient). It may have a configuration. Alternatively, the hole transport region 190103 made only of the hole transport material and the electron transport region 190104 made only of the electron transport material do not exist, and each function is performed inside the mixed region 190105 including both the hole transport material and the electron transport material. A configuration in which the ratio of the concentration of the material changes (has a concentration gradient) may be employed. Alternatively, the concentration ratio may be changed depending on the distance from the anode or the cathode. The change in the concentration ratio may be continuous.

  In the mixed region 190105, a region 190106 to which a light-emitting material is added is provided. The emission color of the EL element can be controlled by the light emitting material. Further, carriers can be trapped by the light emitting material. As the light-emitting material, various fluorescent dyes can be used in addition to a metal complex including a quinoline skeleton, a metal complex including a benzoxador skeleton, a metal complex including a benzothiazol skeleton, and the like. By adding these light emitting materials, the light emission color of the EL element can be controlled.

As the anode 190101, an electrode material having a high work function is preferably used in order to inject holes efficiently. For example, a transparent electrode such as indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, SnO _2, or In ₂ O ₃ can be used. Alternatively, if it is not necessary to have a light-transmitting property, the anode 190101 may be an opaque metal material.

  As the hole transport material, an aromatic amine compound or the like can be used.

As the electron transporting material, a metal complex having a quinoline derivative, 8-quinolinol or a derivative thereof as a ligand (particularly, tris (8-quinolinolato) aluminum (Alq ₃ )) or the like can be used.

  As the cathode 190102, an electrode material having a low work function is preferably used in order to inject electrons efficiently. For example, metals such as aluminum, indium, magnesium, silver, calcium, barium, and lithium can be used alone. Or the alloy of these metals may be sufficient and the alloy of these metals and another metal may be sufficient.

  A schematic view of an EL element having a structure different from that in FIG. 73A is illustrated in FIG. Note that the same portions as those in FIG. 73A are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 73B, there is no region to which the light-emitting material is added. However, as a material added to the electron transporting region 190104, a material having both electron transporting properties and light emitting properties (electron transporting light emitting material), for example, tris (8-quinolinolato) aluminum (Alq ₃ ) is used. , Can emit light.

  Alternatively, as a material added to the hole transporting region 190103, a material having both hole transporting properties and light emitting properties (hole transporting light emitting material) may be used.

  FIG. 73C shows a schematic diagram of an EL element having a structure different from those in FIGS. 73A and 73B. Note that the same portions as those in FIGS. 73A and 73B are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 73C, a hole blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest unoccupied molecular orbital than the hole transporting material has a region 190107 added in the mixed region 190105. . The region 190107 to which the hole blocking material is added is disposed closer to the cathode 190102 than the region 190106 to which the light emitting material is added in the mixed region 190105, thereby increasing the carrier recombination rate and increasing the light emission efficiency. Can do. The above structure in which the region 190107 to which a hole blocking material is added is provided is particularly effective in an EL element using light emission (phosphorescence) by triplet excitons.

  FIG. 73D shows a schematic diagram of an EL element having a structure different from those in FIGS. 73A, 73B, and 73C. Note that the same portions as those in FIGS. 73A, 73B, and 73C are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 73D, an electron blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest unoccupied molecular orbital than the electron transporting material has a region 190108 added in the mixed region 190105. By arranging the region 190108 to which the electron blocking material is added closer to the anode 190101 than the region 190106 to which the light emitting material is added in the mixed region 190105, the carrier recombination rate can be increased and the light emission efficiency can be increased. it can. The above structure in which the region 190108 to which an electron blocking material is added is provided is particularly effective in an EL element using light emission (phosphorescence) by triplet excitons.

  FIG. 73E is a schematic diagram illustrating a structure of a mixed-junction EL element which is different from those in FIGS. 73A, 73B, 73C, and 73D. FIG. 73E illustrates an example of a structure including a region 190109 to which a metal material is added in the portion of the EL layer in contact with the electrode of the EL element. 73E, the same portions as those in FIGS. 73A to 73D are denoted by the same reference numerals, and description thereof is omitted. The structure shown in FIG. 73E uses, for example, MgAg (Mg—Ag alloy) as the cathode 190102 and an Al (aluminum) alloy in a region in contact with the cathode 190102 in the electron transport region 190104 to which the electron transport material is added. A structure including the added region 190109 may be used. With the above structure, the cathode can be prevented from being oxidized and the efficiency of electron injection from the cathode can be increased. Thus, the life of the mixed junction type EL element can be extended. Further, the drive voltage can be lowered.

  As a method for manufacturing the mixed junction type EL element, a co-evaporation method or the like can be used.

  In the mixed junction type EL element as shown in FIGS. 73A to 73E, there is no clear layer interface, and charge accumulation can be reduced. In this way, the lifetime can be extended. Further, the drive voltage can be lowered.

  The structures shown in FIGS. 73A to 73E can be implemented in any combination.

  The structure of the mixed junction type EL element is not limited to this, and various structures can be freely used.

  The organic material constituting the EL layer of the EL element may be a low molecular material or a high molecular material. Alternatively, both of these materials may be used. When a low molecular material is used as the organic compound material, the film can be formed by an evaporation method. On the other hand, in the case where a polymer material is used for the EL layer, the polymer material can be dissolved in a solvent and formed into a film by a spin coating method or an inkjet method.

  The EL layer may be made of a medium molecular material. In the present specification, the medium molecular organic light-emitting material refers to an organic light-emitting material having no sublimation property and having a degree of polymerization of about 20 or less. In the case where a medium molecular material is used for the EL layer, the EL layer can be formed by an inkjet method or the like.

  A low molecular material, a high molecular material, and a medium molecular material may be used in combination.

  The EL element may be either one that uses light emission (fluorescence) from singlet excitons or one that uses light emission (phosphorescence) from triplet excitons.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 18)
In this embodiment, the structure of an EL element will be described. In particular, the structure of the inorganic EL element will be described.

As a base material used for the light-emitting material, sulfide, oxide, or nitride can be used. Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), or the like can also be used. Alternatively, a ternary mixed crystal such as calcium sulfide-gallium (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), or barium sulfide-gallium (BaGa ₂ S ₄ ) may be used.

  As emission centers of localized emission, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr) or the like can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

  On the other hand, a light-emitting material including a first impurity element that forms a donor level and a second impurity element that forms an acceptor level can be used as the emission center of donor-acceptor recombination light emission. For example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used as the first impurity element. For example, copper (Cu), silver (Ag), or the like can be used as the second impurity element.

  74A to 74C illustrate an example of a thin-film inorganic EL element that can be used as a light-emitting element. 74A to 74C, the light-emitting element includes a first electrode layer 120100, an electroluminescent layer 120102, and a second electrode layer 120103.

  74B and 74C each have a structure in which an insulating film is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 74A. A light-emitting element illustrated in FIG. 74B includes an insulating film 120104 between the first electrode layer 120100 and the electroluminescent layer 120102. A light-emitting element illustrated in FIG. 74C includes an insulating film 120105 between the first electrode layer 120100 and the electroluminescent layer 120102, and between the second electrode layer 120103 and the electroluminescent layer 120102. In addition, an insulating film 120106 is provided. Thus, the insulating film may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating film may be a single layer or a stacked layer having a plurality of layers.

  75A to 75C illustrate an example of a dispersion-type inorganic EL element that can be used as a light-emitting element. A light-emitting element in FIG. 75A has a stacked structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light-emitting material 120201 held in the electroluminescent layer 120202 by a binder. including.

The light-emitting element illustrated in FIGS. 75B and 75C has a structure in which an insulating film is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 75A. A light-emitting element illustrated in FIG. 75B includes an insulating film 120204 between the first electrode layer 120200 and the electroluminescent layer 120202. A light-emitting element illustrated in FIG. 75C includes an insulating film 120205 between the first electrode layer 120200 and the electroluminescent layer 120202, and between the second electrode layer 120203 and the electroluminescent layer 120202. In addition, an insulating film 120206 is provided. Thus, the insulating film may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating film may be a single layer or a stacked layer including a plurality of layers.

  75B, the insulating film 120204 is provided so as to be in contact with the first electrode layer 120200; however, the order of the insulating film and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 120203. An insulating film 120204 may be provided.

A material that can be used for the insulating film, such as the insulating film 120104 in FIG. 74B and the insulating film 120204 in FIG. 75B, preferably has high withstand voltage and a dense film quality. Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), or a mixed film thereof or two or more kinds The laminated film can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. The insulating film may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm.

  The light emitting element emits light by applying a voltage between a pair of electrode layers sandwiching the electroluminescent layer, but can operate in either DC driving or AC driving.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, with respect to each part of the drawings in this embodiment mode, a larger number of diagrams can be formed by combining parts of different embodiment modes.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 19)
In this embodiment, an example of a display device, particularly a case where optical handling is performed will be described.

  A rear projection display device 130100 shown in FIGS. 76A and 76B includes a projector unit 130111, a mirror 130112, and a screen panel 130101. In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 is disposed below the casing 130110 of the rear projection display device 130100, and projects projection light that projects an image based on the image signal toward the mirror 130112. The rear projection display device 130100 is configured to display an image projected from the rear surface of the screen panel 130101.

  On the other hand, FIG. 77 shows a front projection display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The projection optical system 130201 is configured to project an image on a screen or the like disposed on the front surface.

  The configuration of the projector unit 130111 applied to the rear projection display device 130100 shown in FIG. 76 and the front projection display device 130200 shown in FIG. 77 will be described below.

  FIG. 78 shows a configuration example of the projector unit 130111. The projector unit 130111 includes a light source unit 130301 and a modulation unit 130304. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302. The light source lamp 130302 is housed in the housing so that stray light does not diffuse. As the light source lamp 130302, for example, a high-pressure mercury lamp or a xenon lamp that can emit a large amount of light is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like. The light source unit 130301 is disposed so that the emitted light is incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, a color filter, a dichroic mirror 130305, a total reflection mirror 130306, a phase difference plate 130307, a prism 130309, and a projection optical system 130310. Light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305.

  Each optical path is provided with a color filter that transmits light of a predetermined wavelength or wavelength band, and a display panel 130308. The transmissive display panel 130308 modulates transmitted light based on the video signal. The light of each color transmitted through the display panel 130308 enters the prism 130309, and displays an image on the screen through the projection optical system 130310. A Fresnel lens may be disposed between the mirror and the screen. The projection light projected by the projector unit 130111 and reflected by the mirror is converted into substantially parallel light by the Fresnel lens and projected onto the screen. The parallel light preferably has a deviation between the principal ray and the optical axis of ± 10 ° or less. More preferably, the deviation between the light beam and the optical axis is preferably ± 5 ° or less.

  A projector unit 130111 shown in FIG. 79 has a configuration including a reflective display panel 130407, a reflective display panel 130408, and a reflective display panel 130409.

  A projector unit 130111 shown in FIG. 79 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as that in FIG. The light from the light source unit 130301 is divided into a plurality of optical paths by the dichroic mirror 130401, the dichroic mirror 130402, and the total reflection mirror 130403, and is incident on the polarization beam splitter 130404, the polarization beam splitter 130405, and the polarization beam splitter 130406. The polarizing beam splitter 130404, the polarizing beam splitter 130405, and the polarizing beam splitter 130406 are provided corresponding to the reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 corresponding to each color. The reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 modulate reflected light based on the video signal. Light of each color reflected by the reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 is combined by being incident on the prism 130410, and is projected through the projection optical system 130411.

  Light emitted from the light source unit 130301 is transmitted through the dichroic mirror 130401 only in the red wavelength region and reflects in the green and blue wavelength regions. Further, the dichroic mirror 130402 reflects only light in the green wavelength region. The light in the red wavelength region that has passed through the dichroic mirror 130401 is reflected by the total reflection mirror 130403 and enters the polarization beam splitter 130404. Further, light in the blue wavelength region enters the polarization beam splitter 130405, and light in the green wavelength region enters the polarization beam splitter 130406. The polarizing beam splitter 130404, the polarizing beam splitter 130405, and the polarizing beam splitter 130406 have a function of separating incident light into P-polarized light and S-polarized light, and have a function of transmitting only P-polarized light. The reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 polarize incident light based on the video signal.

  Only S-polarized light corresponding to each color is incident on the reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 corresponding to each color. Note that the reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 may be liquid crystal panels. At this time, the liquid crystal panel operates in an electric field controlled birefringence mode (ECB). The liquid crystal molecules are vertically aligned with a certain angle with respect to the substrate. Therefore, the reflective display panel 130407, the reflective display panel 130408, and the reflective display panel 130409 are arranged such that when the pixel is in the off state, the display molecules are aligned so that the incident light is reflected without changing the polarization state. Yes. When the pixel is in the on state, the orientation state of the display molecules changes, and the polarization state of incident light changes.

  The projector unit 130111 shown in FIG. 79 can be applied to the rear projection display device 130100 shown in FIG. 76 and the front projection display device 130200 shown in FIG.

  The projector unit shown in FIG. 80 has a single-plate configuration. A projector unit 130111 shown in FIG. 80A includes a light source unit 130301, a display panel 130507, a projection optical system 130511, and a phase difference plate 130504. The projection optical system 130511 includes one or more lenses. The display panel 130507 may be provided with a color filter.

  FIG. 80B shows the configuration of a projector unit 130111 that operates in a field sequential manner. The field sequential method is a method in which light of each color such as red, green, and blue is sequentially shifted and incident on a display panel to perform color display without a color filter. In particular, when combined with a display panel having a high response speed with respect to input signal changes, a high-definition image can be displayed. In FIG. 80B, a rotary color filter plate 130505 provided with a plurality of color filters such as red, green, and blue is provided between the light source unit 130301 and the display panel 130508.

  A projector unit 130111 shown in FIG. 80C has a configuration of a color separation system using a microlens as a color display system. In this method, a microlens array 130506 is provided on the light incident side of the display panel 130509, and color display is realized by illuminating light of each color from each direction. The projector unit 130111 that employs this method has a feature that light from the light source unit 130301 can be effectively used because light loss due to the color filter is small. A projector unit 130111 shown in FIG. 80C includes a dichroic mirror 130501, a dichroic mirror 130502, and a dichroic mirror 130503 so as to illuminate the display panel 130509 with light of each color from each direction.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 20)
In this embodiment, examples of electronic devices are described.

  FIG. 81 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. The display panel 900101 includes a pixel portion 900102, a scan line driver circuit 900103, and a signal line driver circuit 900104. On the circuit board 900111, for example, a control circuit 900112 and a signal dividing circuit 900113 are formed. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. An FPC or the like can be used for the connection wiring.

  FIG. 86 is a block diagram illustrating a main configuration of a television receiver. A tuner 900201 receives a video signal and an audio signal. The video signal includes a video signal amplification circuit 900202, a video signal processing circuit 900203 that converts a signal output from the video signal amplification circuit 900202 into a color signal corresponding to each color of red, green, and blue, and the video signal. , And processed by the control circuit 900212 for conversion to the input specification of the drive circuit. The control circuit 900212 outputs signals to the scan line driver circuit 900214 and the signal line driver circuit 900204, respectively. Then, the scan line driver circuit 900214 and the signal line driver circuit 900204 drive the display panel 900211. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side, and an input digital signal may be divided into m pieces (m is a positive integer) and supplied.

  Of the signals received by the tuner 900201, the audio signal is sent to the audio signal amplifier circuit 900205, and the output is supplied to the speaker 900207 via the audio signal processing circuit 900206. The control circuit 900208 receives the receiving station (reception frequency) and volume control information from the input unit 9000020, and sends a signal to the tuner 900201 or the audio signal processing circuit 900206.

  A television receiver incorporating a display panel module, which is different from that in FIG. 86, is illustrated in FIG. In FIG. 87A, a display screen 900302 housed in a housing 900301 is formed using a display panel module. Note that the speaker 900303, input means (operation keys 900304, connection terminals 900305, sensors 900306 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time) , Including a function of measuring hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared)), a microphone 930307), and the like.

  FIG. 87B illustrates a television receiver that can carry only a display wirelessly. This television receiver includes a display portion 900313, a speaker portion 900317, input means (operation keys 900316, a connection terminal 900318, a sensor 900319 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, Magnetic, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared, etc.), microphone 900320) etc. are provided as appropriate It has been. A housing 900312 houses a battery and a signal receiver, and the display portion 900313, the speaker portion 900317, the sensor 900319, and the microphone 900320 are driven by the battery. The battery can be repeatedly charged by the charger 900310. The charger 900310 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The device illustrated in FIG. 87B is controlled by an operation key 900316. Alternatively, the device illustrated in FIG. 87B can send a signal to the charger 900310 by operating the operation keys 900316. That is, it may be a video / audio bidirectional communication device. Alternatively, the device illustrated in FIG. 87B operates by operating the operation key 900316 to transmit a signal to the charger 900310 and further cause the other electronic device to receive a signal that can be transmitted by the charger 900310. It is also possible to control communication of electronic devices. That is, a general-purpose remote control device may be used. Note that the contents (or part of the contents) described in each drawing of this embodiment mode can be applied to the display portion 900313.

  Next, a configuration example of a mobile phone will be described with reference to FIG.

  The display panel 900501 is incorporated in a housing 900530 so as to be detachable. The shape or dimension of the housing 900530 can be changed as appropriate in accordance with the size of the display panel 900501. A housing 900530 to which the display panel 900501 is fixed is fitted into the printed circuit board 900531 and assembled as a module.

  The display panel 900501 is connected to the printed circuit board 900531 through the FPC 900531. A printed circuit board 900531 includes a speaker 900532, a microphone 900533, a transmission / reception circuit 900534, a signal processing circuit 900555 including a CPU, a controller, and a sensor 900541 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid , Magnetic, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared). Such a module is combined with the operation key 90056, the battery 900577, and the antenna 900540 and housed in the housing 900539. The pixel portion of the display panel 900501 is arranged so as to be visible from an opening window formed in the housing 9000053.

  In the display panel 900501, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using transistors, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driving circuit having a high operating frequency among the circuits) may be formed over the IC chip, and the IC chip may be mounted on the display panel 900501 using COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed circuit board. With such a structure, the power consumption of the display device can be reduced, and the usage time by one charge of the mobile phone can be extended. In addition, the cost of the mobile phone can be reduced.

  The mobile phone shown in FIG. 88 has a function of displaying various information (still images, moving images, text images, and the like). It has a function of displaying a calendar, date or time on the display unit. It has a function of operating or editing information displayed on the display unit. It has a function of controlling processing by various software (programs). Has a wireless communication function. It has a function of making a call with another mobile phone, a fixed phone, or a voice communication device using a wireless communication function. It has a function of connecting to various computer networks using a wireless communication function. It has a function of transmitting or receiving various data using a wireless communication function. The vibrator has a function to operate in response to an incoming call, data reception or an alarm. It has a function to generate sound in response to an incoming call, data reception or alarm. Note that the functions of the cellular phone illustrated in FIG. 88 are not limited to these, and the cellular phone can have various functions.

  FIG. 89A shows a display, which includes a housing 900711, a support base 900712, a display portion 900713, a speaker 900717, an LED lamp 900719, input means (a connection terminal 900714, a sensor 900715 (force, displacement, position, velocity, acceleration, angular velocity). Includes functions to measure speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared 1), a microphone 900716, an operation key 900718) and the like. The display illustrated in FIG. 89A has a function of displaying various information (still images, moving images, text images, and the like) on the display portion. Note that the function of the display illustrated in FIG. 89A is not limited to this, and the display can have a variety of functions.

  FIG. 89B shows a camera, which includes a main body 900731, a display portion 900732, a shutter button 9000073, a speaker 900740, an LED lamp 900741, input means (an image receiving portion 900733, operation keys 900734, an external connection port 900735, a connection terminal 900737, a sensor 900738. (Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , Including a function of measuring vibration, odor, or infrared)), a microphone 900739) and the like. The camera illustrated in FIG. 89B has a function of shooting a still image. Has a function to shoot movies. It has a function of automatically correcting captured images (still images, moving images). It has a function of storing captured images in a recording medium (externally or built in a camera). It has a function of displaying a photographed image on a display unit. Note that the function of the camera illustrated in FIG. 89B is not limited to this, and the camera can have a variety of functions.

  FIG. 89C shows a computer, which is a main body 900751, a housing 900722, a display portion 900733, a speaker 900760, an LED lamp 900761, a reader / writer 900762, input means (a keyboard 900754, an external connection port 900755, a pointing device 9000075, a connection terminal 900777, sensor 900780 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate , Including the function of measuring humidity, gradient, vibration, odor or infrared)), and microphone 9000075). The computer illustrated in FIG. 89C has a function of displaying a variety of information (still images, moving images, text images, and the like) on a display portion. It has a function of controlling processing by various software (programs). It has a communication function such as wireless communication or wired communication. It has a function of connecting to various computer networks using a communication function. It has a function of transmitting or receiving various data using a communication function. Note that the function of the computer illustrated in FIG. 89C is not limited thereto, and the computer can have various functions.

  FIG. 96A illustrates a mobile computer, which includes a main body 901411, a display portion 901411, a switch 901413, a speaker 901419, an LED lamp 901420, input means (operation keys 901414, an infrared port 901415, a connection terminal 901416, a sensor 901417 (force, displacement, Position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or Including a function of measuring infrared rays), a microphone 901418) and the like. A mobile computer illustrated in FIG. 96A has a function of displaying various kinds of information (a still image, a moving image, a text image, and the like) on a display portion. The display unit has a touch panel function. The display unit has a function of displaying a calendar, date or time. It has a function of controlling processing by various software (programs). Has a wireless communication function. It has a function of connecting to various computer networks using a wireless communication function. It has a function of transmitting or receiving various data using a wireless communication function. Note that the function of the mobile computer illustrated in FIG. 96A is not limited to this, and the mobile computer can have various functions.

  FIG. 96B illustrates a portable image playback device (eg, a DVD playback device) provided with a recording medium, which includes a main body 901431, a housing 901432, a display portion A901433, a display portion B901434, a speaker portion 901437, an LED lamp 901441, Input means (recording medium (DVD etc.) reading unit 901435, operation key 901436, connection terminal 901438, sensor 901439 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical Materials, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared, etc.), microphone 901440) and the like. The display unit A901433 mainly displays image information, and the display unit B901434 mainly displays character information.

  FIG. 96C shows a goggle type display, which is a main body 901451, a display portion 901452, an earphone 901453, a support portion 901454, an LED lamp 901455, a speaker 901458, input means (a connection terminal 901455, a sensor 901456 (force, displacement, position, speed). Measure acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 901457) and the like. The goggle type display shown in FIG. 96C has a function of displaying an externally acquired image (a still image, a moving image, a text image, or the like) on a display portion. Note that the function of the goggle display illustrated in FIG. 96C is not limited thereto, and the display can have a variety of functions.

  FIG. 97A illustrates a portable game machine, which includes a housing 901511, a display portion 901512, a speaker portion 901513, a recording medium insertion portion 901515, an LED lamp 901519, input means (operation keys 901514, a connection terminal 901516, a sensor 901517 (force , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including the function of measuring odors or infrared rays), microphones 901518) and the like. A portable game machine shown in FIG. 97A has a function of reading a program or data recorded in a recording medium and displaying the program or data on a display portion. It has a function of wirelessly communicating with other portable game machines and sharing information. Note that the portable game machine illustrated in FIG. 97A is not limited to this, and can have a variety of functions.

  FIG. 97B illustrates a digital camera with a television receiving function, which includes a main body 901531, a display portion 901532, a speaker 901534, a shutter button 901535, an LED lamp 901541, input means (operation keys 901533, an image receiving portion 901536, an antenna 901537, a connection terminal 901538. , Sensor 901539 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, Including a function of measuring humidity, inclination, vibration, odor or infrared rays), a microphone 901540) and the like. The digital camera with a television reception function illustrated in FIG. 97B has a function of shooting a still image. Has a function to shoot movies. It has a function of automatically correcting a photographed image. It has a function to acquire various information from the antenna. It has a function of storing captured images or information acquired from an antenna. It has a function of displaying a photographed image or information acquired from an antenna on a display unit. Note that the function of the digital camera with a television reception function illustrated in FIG. 97B is not limited to this, and the digital camera can have a variety of functions.

  FIG. 98 shows a portable game machine, which includes a chassis 901611, a first display portion 901612, a second display portion 901613, a speaker portion 901614, a recording medium insertion portion 901616, an LED lamp 901620, input means (operation keys 901615, connection terminals 901617). , Sensor 901618 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, Including a function of measuring humidity, gradient, vibration, odor or infrared light), microphone 901619) and the like. The portable game machine shown in FIG. 98 has a function of reading a program or data recorded on a recording medium and displaying the program or data on a display unit. It has a function of wirelessly communicating with other portable game machines and sharing information. Note that the functions of the portable game machine illustrated in FIG. 98 are not limited thereto, and the portable game machine can have various functions.

  89 (A) to 89 (C), 96 (A) to 96 (C), 97 (A) to 97 (B), and 98, as shown in FIG. A display portion for displaying information is provided.

  Next, application examples of the semiconductor device will be described.

  FIG. 90 illustrates an example in which a semiconductor device is provided so as to be integrated with a building. FIG. 90 includes a housing 900810, a display portion 900811, a remote control device 900812 as an operation portion, a speaker portion 9000081, and the like. The semiconductor device is integrated with the building as a wall-hanging type, and can be installed without requiring a large installation space.

  FIG. 91 shows another example in which a semiconductor device is provided integrally with a building in the building. The display panel 900901 is integrally attached to the unit bath 900902, so that the bather can view the display panel 900901. The display panel 900901 has a function of displaying information when operated by a bather. It has a function that can be used as an advertising or entertainment means.

  The semiconductor device can be installed not only on the side wall of the unit bus 900902 shown in FIG. For example, it may be integrated with a part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may be adapted to the shape of the mirror surface or the bathtub.

  FIG. 92 illustrates another example in which the semiconductor device is provided so as to be integrated with a building. The display panel 901002 is attached so as to be curved according to the curved surface of the columnar body 901001. Here, the columnar body 901001 is described as a utility pole.

  A display panel 901002 shown in FIG. 92 is provided at a position higher than the human viewpoint. By installing the display panel 901002 on a building that stands outdoors like a utility pole, an advertisement can be made to an unspecified number of viewers. The display panel 901002 can easily display the same image and instantaneously switch the image by external control, so that highly efficient information display and advertising effect can be expected. By providing a self-luminous display element in the display panel 901002, it can be said that the display panel 901002 is useful as a display medium with high visibility even at night. By installing it on the utility pole, it is easy to secure the power supply means of the display panel 901002. In the event of an emergency such as a disaster, it can also be a means of quickly and accurately communicating information to the victims.

  As the display panel 901002, for example, a display panel which displays an image by providing a switching element such as an organic transistor on a film-like substrate and driving the display element can be used.

  In this embodiment, a wall, a columnar body, and a unit bus are taken as examples of buildings, but this embodiment is not limited to this, and semiconductor devices can be installed in various buildings.

  Next, an example in which the semiconductor device is provided integrally with the moving body is described.

  FIG. 93 is a diagram illustrating an example in which a semiconductor device is provided integrally with an automobile. A display panel 901102 is attached integrally with a vehicle body 901101 of an automobile, and can display on-demand information on the operation of the vehicle body or information input from inside or outside the vehicle body. Note that a navigation function may be provided.

  The semiconductor device can be installed not only in the vehicle body 901101 shown in FIG. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a room mirror, and the like. At this time, the shape of the display panel 901102 may be adapted to the shape of what is to be installed.

  FIG. 94 is a diagram showing an example in which a semiconductor device is provided integrally with a train car.

  FIG. 94A is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, there is an advantage that labor costs required for advertisement switching are not incurred. Since the display panel 901202 can instantaneously switch the image displayed on the display unit by a signal from the outside, for example, the display panel image is switched every time period when the customer class of passengers on the train is switched. More effective advertising effect can be expected.

  FIG. 94B is a diagram showing an example in which a display panel 901202 is provided on a glass window 901203 and a ceiling 901204 in addition to the glass of the door 901201 of the train car. As described above, since the semiconductor device can be easily installed in a place where it has been difficult to install in the past, an effective advertising effect can be obtained. Since the semiconductor device can instantaneously switch the image displayed on the display unit by a signal from the outside, the cost and time at the time of advertisement switching can be reduced, and more flexible advertisement operation and information transmission can be achieved. It becomes possible.

  The semiconductor device can be installed not only in the door 901201, the glass window 901203, and the ceiling 901204 shown in FIG. For example, it may be integrated with a strap, a seat, a rail, a floor, or the like. At this time, the shape of the display panel 901202 may be matched with the shape of the display panel.

  FIG. 95 is a diagram illustrating an example in which a semiconductor device is provided integrally with a passenger airplane.

  FIG. 95A is a diagram showing a shape in use when a display panel 901302 is provided on the ceiling 901301 above the seat of a passenger airplane. The display panel 901302 is integrally attached via a ceiling 901301 and a hinge part 901303, and the passenger can view the display panel 901302 by expansion and contraction of the hinge part 901303. The display panel 901302 has a function of displaying information when operated by a passenger. Also, it has a function that can be used as an advertisement or entertainment means. As shown in FIG. 95 (B), safety at the time of takeoff and landing can be considered by folding the hinge part and storing it in the ceiling 901301. In addition, by turning on the display element of the display panel in an emergency, it can be used as an information transmission means and a guide light.

  The semiconductor device can be installed not only on the ceiling 901301 shown in FIG. For example, it may be integrated with a seat seat, a seat table, an armrest, a window and the like. A large display panel that can be viewed simultaneously by a large number of people may be installed on the wall of the aircraft. At this time, the shape of the display panel 901302 may be adapted to the shape of the object to be installed.

  In this embodiment, examples of the moving body include a train car body, an automobile body, and an airplane body. However, the present invention is not limited to this, and a motorcycle, an automobile (including an automobile, a bus, etc.), a train (monorail, railway) Etc.), and can be installed on various things such as ships. Since the semiconductor device can instantly switch the display of the display panel in the moving body by an external signal, installing the semiconductor device in the moving body targets a large number of unspecified customers. It can be used for applications such as advertisement display boards and information display boards in the event of a disaster.

  In this embodiment mode, various drawings have been used. However, the contents (or part of the contents) described in each figure may be applied to the contents (or part of the contents) described in another figure. , Can be freely combined or replaced. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

  The contents (may be a part) described in each figure of this embodiment can be freely applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. It can be carried out. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

  This embodiment is an example in which the content (may be a part) described in other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement An example, an example when it is described in detail, an example when it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiment modes can be freely applied to, combined with, or replaced with this embodiment mode.

(Embodiment 21)
As described above, the present specification includes at least the following inventions.

  One embodiment of the present invention is a liquid crystal display device including a pixel including a liquid crystal element and a driver circuit. The driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. And have. This drive circuit includes at least a part of the following connection relationship. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the second transistor is electrically connected to the third wiring. The first electrode of the third transistor is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the third electrode A gate electrode of the transistor is electrically connected to the fifth wiring. The first electrode of the fourth transistor is electrically connected to the sixth wiring, the second electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor, and the fourth electrode The gate electrode of the transistor is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the fifth wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and the fifth electrode A gate electrode of the transistor is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the sixth electrode The gate electrode of the transistor is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the seventh electrode A gate electrode of the transistor is electrically connected to the second wiring. The first electrode of the eighth transistor is electrically connected to the sixth wiring, the second electrode of the eighth transistor is electrically connected to the gate electrode of the second transistor, and the eighth electrode A gate electrode of the transistor is electrically connected to the first wiring.

  A liquid crystal display device including a pixel having the above liquid crystal element and a driver circuit has a first ratio of the channel length L to the channel width W of the first to eighth transistors. A configuration including a drive circuit that maximizes the value of W / L of the transistor may be used.

  In the liquid crystal display device including the pixel including the liquid crystal element and the driver circuit, the ratio W / L of the channel length L to the channel width W of the first transistor is equal to the channel length L and the channel of the fifth transistor. A configuration including a drive circuit that is not less than 2 times and not more than 5 times the value of the ratio W / L of the width W may be employed.

  The liquid crystal display device including the pixel including the liquid crystal element and the driver circuit may include a case where the channel length L of the third transistor is larger than the channel length L of the fourth transistor.

  In a liquid crystal display device including a pixel having the above liquid crystal element and a driver circuit, a capacitor element is disposed between the second electrode of the first transistor and the gate electrode of the first transistor. The structure containing these may be sufficient.

  The liquid crystal display device including the pixel including the liquid crystal element and the driver circuit may include a structure in which the first transistor to the eighth transistor are N-channel transistors.

  The liquid crystal display device including the pixel including the liquid crystal element and the driver circuit may have a structure in which the first to eighth transistors include one using amorphous silicon as a semiconductor layer.

  One embodiment of the present invention is a liquid crystal display device including a pixel including a liquid crystal element, a first driver circuit, and a second driver circuit. The first drive circuit and the second drive circuit at least partially include the following connection relationship. The first driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, 8 transistors. The first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the sixth wiring, and the second electrode of the second transistor is electrically connected to the third wiring. The first electrode of the third transistor is electrically connected to the fifth wiring, the second electrode of the third transistor is electrically connected to the gate electrode of the second transistor, and the third electrode A gate electrode of the transistor is electrically connected to the fifth wiring. The first electrode of the fourth transistor is electrically connected to the sixth wiring, the second electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor, and the fourth electrode The gate electrode of the transistor is electrically connected to the gate electrode of the first transistor. The first electrode of the fifth transistor is electrically connected to the fifth wiring, the second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and the fifth electrode A gate electrode of the transistor is electrically connected to the first wiring. The first electrode of the sixth transistor is electrically connected to the sixth wiring, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the sixth electrode The gate electrode of the transistor is electrically connected to the gate electrode of the second transistor. The first electrode of the seventh transistor is electrically connected to the sixth wiring, the second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the seventh electrode A gate electrode of the transistor is electrically connected to the second wiring. The first electrode of the eighth transistor is electrically connected to the sixth wiring, the second electrode of the eighth transistor is electrically connected to the gate electrode of the second transistor, and the eighth electrode A gate electrode of the transistor is electrically connected to the first wiring. The second driver circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. , And a sixteenth transistor. The first electrode of the ninth transistor is electrically connected to the tenth wiring, and the second electrode of the ninth transistor is electrically connected to the ninth wiring. The first electrode of the tenth transistor is electrically connected to the twelfth wiring, and the second electrode of the tenth transistor is electrically connected to the ninth wiring. The first electrode of the eleventh transistor is electrically connected to the eleventh wiring, the second electrode of the eleventh transistor is electrically connected to the gate electrode of the tenth transistor, A gate electrode of the transistor is electrically connected to the eleventh wiring. The first electrode of the twelfth transistor is electrically connected to the twelfth wiring, the second electrode of the twelfth transistor is electrically connected to the gate electrode of the tenth transistor, The gate electrode of the transistor is electrically connected to the gate electrode of the ninth transistor. The first electrode of the thirteenth transistor is electrically connected to the eleventh wiring, the second electrode of the thirteenth transistor is electrically connected to the gate electrode of the ninth transistor, and the thirteenth A gate electrode of the transistor is electrically connected to the seventh wiring. The first electrode of the fourteenth transistor is electrically connected to the twelfth wiring, the second electrode of the fourteenth transistor is electrically connected to the gate electrode of the ninth transistor, and the fourteenth electrode The gate electrode of the transistor is electrically connected to the gate electrode of the tenth transistor. The first electrode of the fifteenth transistor is electrically connected to the twelfth wiring, the second electrode of the fifteenth transistor is electrically connected to the gate electrode of the ninth transistor, and the fifteenth A gate electrode of the transistor is electrically connected to the eighth wiring. The first electrode of the sixteenth transistor is electrically connected to the twelfth wiring, the second electrode of the sixteenth transistor is electrically connected to the gate electrode of the tenth transistor, and the sixteenth transistor A gate electrode of the transistor is electrically connected to the seventh wiring.

  In a liquid crystal display device including a pixel including a liquid crystal element, a first driver circuit, and a second driver circuit, the fourth wiring and the tenth wiring are electrically connected, and the fifth wiring The configuration may include a configuration in which the eleventh wiring is electrically connected and the sixth wiring and the twelfth wiring are electrically connected.

  In a liquid crystal display device including a pixel including a liquid crystal element, a first driver circuit, and a second driver circuit, the fourth wiring and the tenth wiring are the same wiring, and the fifth wiring The eleventh wiring may be the same wiring, and the sixth wiring and the twelfth wiring may include the same wiring.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit includes a device in which a third wiring and a ninth wiring are electrically connected. It may be a configuration.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit includes a configuration in which the third wiring and the ninth wiring are the same wiring. May be.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit has a ratio W / L of the channel length L to the channel width W of the first to eighth transistors. Among the values of the first transistor, the W / L value of the first transistor is the largest, and the value of the ratio W / L of the channel length L to the channel width W of the ninth to sixteenth transistors is the ninth. The transistor including the transistor having the maximum W / L value may be used.

  In a liquid crystal display device having a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit, the ratio W / L of the channel length L to the channel width W of the first transistor is 5 to 2 times the value of the ratio W / L of the channel length L and the channel width W of the transistor No. 5, and the value of the ratio W / L of the channel length L to the channel width W of the ninth transistor is The transistor may include a transistor having a ratio W / L of the channel length L to the channel width W of 2 to 5 times.

  In a liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit, the channel length L of the third transistor is larger than the channel length L of the fourth transistor. The eleventh transistor may have a channel length L that is greater than the channel length L of the twelfth transistor.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit is provided between a second electrode of the first transistor and a gate electrode of the first transistor. A structure including a capacitor element and a capacitor element disposed between the second electrode of the ninth transistor and the gate electrode of the ninth transistor may be employed.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit includes a structure in which the first to sixteenth transistors are N-channel transistors. There may be.

  A liquid crystal display device including a pixel having a liquid crystal element, a first driver circuit, and a second driver circuit includes a structure in which the first to sixteenth transistors use amorphous silicon as a semiconductor layer. It may be.

  The liquid crystal display device described above can be included in various electronic devices.

  The liquid crystal display device described in this embodiment is described in this specification, and thus has the same effect as that of the other embodiments.

3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 2 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3 is a timing chart illustrating operation of the flip-flop described in Embodiment 1; FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; 8 is a timing chart illustrating operation of the shift register illustrated in FIG. 8 is a timing chart illustrating operation of the shift register illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 1; 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; 12 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 11. 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; 3A and 3B each illustrate a structure of a display device shown in Embodiment 1; FIG. 15 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 14. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. FIG. 5 illustrates a structure of a shift register described in Embodiment 2; FIG. 19 is a timing chart illustrating operation of the shift register illustrated in FIG. 18. FIG. 19 is a timing chart illustrating operation of the shift register illustrated in FIG. 18. FIG. 6 illustrates a structure of a display device described in Embodiment 2; 6A and 6B illustrate a structure of a display device described in Embodiment 2. 4A and 4B illustrate a structure of a flip-flop shown in Embodiment 3. 24 is a timing chart illustrating operation of the flip-flop illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 3; 26 is a timing chart illustrating operation of the shift register illustrated in FIG. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 4; 28 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. FIG. 6 is a top view of the flip-flop illustrated in FIG. FIG. 11 is a diagram illustrating a configuration of a buffer illustrated in FIG. 10. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. FIG. 32 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 31. FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 34 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 8A and 8B illustrate a structure of a display device described in Embodiment 7. 8A and 8B illustrate a process for manufacturing a semiconductor device according to the present invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 6A and 6B illustrate a structure of a display device of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. FIG. 6 is a top view of a pixel of a semiconductor device according to the present invention. FIG. 6 is a top view of a pixel of a semiconductor device according to the present invention. FIG. 6 is a top view of a pixel of a semiconductor device according to the present invention. 4 illustrates a pixel layout example of a semiconductor device according to the present invention. 4 illustrates a pixel layout example of a semiconductor device according to the present invention. 4 illustrates a pixel layout example of a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 4A and 4B each illustrate a structure of a pixel of a semiconductor device according to the invention. 4A and 4B each illustrate a structure of a pixel of a semiconductor device according to the invention. 4A and 4B each illustrate a structure of a pixel of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. FIG. 11 is a diagram illustrating a configuration of a buffer illustrated in FIG. 10. The figure explaining the structure and timing of the flip-flop of a prior art.

Explanation of symbols

101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 141 node 142 node 501 wiring 502 wiring 503 wiring 504 wiring 505 wiring 506 wiring 507 wiring

Claims (8)

Having first to eighth transistors and first to sixth wirings;
A first electrode of the first transistor is directly connected to the fifth wiring; a second electrode of the first transistor is directly connected to the third wiring;
A first electrode of the second transistor is directly connected to the fourth wiring; a second electrode of the second transistor is directly connected to the third wiring;
A first electrode of the third transistor is directly connected to the sixth wiring; a second electrode of the third transistor is directly connected to a gate electrode of the second transistor; and Are directly connected to the sixth wiring,
A first electrode of the fourth transistor is directly connected to the fourth wiring; a second electrode of the fourth transistor is directly connected to a gate electrode of the second transistor; and A gate electrode of the first transistor is directly connected to the gate electrode of the first transistor;
The first electrode of the fifth transistor is directly connected to the first wiring, the second electrode of the fifth transistor is directly connected to the gate electrode of the first transistor, and the fifth transistor The gate electrode is directly connected to the first wiring,
The first electrode of the sixth transistor is directly connected to the fourth wiring, the second electrode of the sixth transistor is directly connected to the gate electrode of the first transistor, and the sixth transistor Is directly connected to the gate electrode of the second transistor,
A first electrode of the seventh transistor is directly connected to the fourth wiring; a second electrode of the seventh transistor is directly connected to a gate electrode of the first transistor; and The gate electrode is directly connected to the second wiring,
A first electrode of the eighth transistor is directly connected to the fourth wiring, a second electrode of the eighth transistor is directly connected to a gate electrode of the second transistor, and the eighth transistor The gate electrode is directly connected to the first wiring ,
The value of W / L (W is the channel width and L is the channel length) of the seventh transistor is a value that is not less than 1/40 times and not more than 1/10 times the W / L value of the first transistor. A semiconductor device comprising: In claim 1,
Having ninth and tenth transistors and seventh to ninth wirings;
The first electrode of the ninth transistor is directly connected to the eighth wiring, the second electrode of the ninth transistor is directly connected to the seventh wiring, and the gate electrode of the ninth transistor Is directly connected to the gate electrode of the first transistor,
The first electrode of the tenth transistor is directly connected to the ninth wiring, the second electrode of the tenth transistor is directly connected to the seventh wiring, and the gate electrode of the tenth transistor Is directly connected to the gate electrode of the second transistor. In claim 1 or claim 2 ,
The value of W / L (W is the channel width and L is the channel length) of the first transistor is the largest of the W / L values of the first to eighth transistors. . In any one of Claims 1 thru | or 3,
Each of the first to eighth transistors includes an oxide semiconductor. In any one of Claims 1 thru | or 3,
Each of the first to eighth transistors includes ZnO. A semiconductor device according to any one of claims 1 to 5 and a pixel,
The pixel has a display element,
The display device is characterized in that the pixel is electrically connected to the third wiring. A semiconductor device according to any one of claims 1 to 5 and a pixel,
The pixel has a light emitting element,
The display device is characterized in that the pixel is electrically connected to the third wiring. A semiconductor device according to any one of claims 1 to 5 and a pixel,
The pixel has a liquid crystal element,
The liquid crystal display device, wherein the pixel is electrically connected to the third wiring.

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