JP5463529B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor made of a nitride compound used as a power electronics device or a high frequency amplification device, and a method for manufacturing the same.

  Wide bandgap semiconductors typified by III-V nitride compounds have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity, so they are very useful as semiconductor devices for high-temperature, high-power, or high-frequency semiconductor devices. Attractive. Particularly, in a field effect transistor (FET) having an AlGaN / GaN heterostructure, a two-dimensional electron gas is generated at the interface due to the piezoelectric effect. This two-dimensional electron gas has high electron mobility and carrier density, and has attracted much attention. In addition, a heterojunction FET (HFET) using an AlGaN / GaN heterostructure has a low on-resistance and a high switching speed, and can operate at a high temperature. These features are very suitable for power switching applications. However, a normal AlGaN / GaN HFET is a normally-on type device in which a current flows when no bias is applied to the gate and the current is interrupted by applying a negative potential to the gate. On the other hand, in power switching applications, in order to ensure safety when the device breaks, a normally-off type device in which no current flows when no bias is applied to the gate and a current flows by applying a positive potential to the gate Is preferred.

In order to realize a normally-off type device, it is necessary to adopt a MOSFET structure. FIG. 12 is a schematic cross-sectional view of a conventional MOSFET (see Non-Patent Document 1). In this MOSFET 800, a p-GaN layer 803 is formed on a substrate 801 with a buffer layer 802 interposed therebetween. Further, n ⁺ -GaN regions 805 and 806 are formed in a part of the p-GaN layer 803 by ion implantation as a contact layer for making ohmic contact between the source / drain regions. Further, an n ⁻ -GaN region 804 called a RESURF (REduced SURface Field) layer is formed between the gate and the drain by an ion implantation method in order to relax the electric field between the gate and the drain and improve the breakdown voltage of the device. Has been. In addition, an oxide film 807 made of SiO ₂ or the like is formed, and a gate electrode 808 is formed on the oxide film 807. As the gate electrode 808, poly-Si is generally used, but a metal electrode such as Ni / Au or WSi may be used. Further, a source electrode 809 and a drain electrode 810 are formed on the n ⁺ -GaN regions 805 and 806. As the source electrode 809 and the drain electrode 810, a metal such as Ti / Al or Ti / AlSi / Mo that forms an ohmic contact with n ⁺ -GaN is used.

By the way, in the MOSFET, in order to improve the channel mobility, it is important to keep the interface state at the interface between the oxide film and the semiconductor low. In a normal Si-based MOSFET, a SiO ₂ thermal oxide film formed by thermally oxidizing Si is used as an oxide film, and a very good interface with a low interface state is realized. On the other hand, in the case of a nitride compound MOSFET, since a good thermal oxide film cannot be obtained, it is common to form an oxide film made of SiO ₂ or the like by the p-CVD method.

Here, as described above, conventionally, an ion implantation method is used to form the n ⁺ -GaN region and the n ⁻ -GaN region. In the ion implantation method, after the implantation of predetermined impurity ions, annealing for recovering crystal defects and activating the implanted impurities is performed. When the semiconductor material is, for example, GaN, the crystal bond is strong, so that it is necessary to perform annealing at a high temperature of about 1000 ° C.

Matocha. K, Chow. T.P, Gutmann. R.J., “High-voltage normally off GaN MOSFETs on sapphire substrates”, IEEE Transaction on Electron Devices. Vol. 52, No. 1 2005 pp. 6-10

However, the activation rate of impurities depends on the dose amount of impurities, and the greater the dose amount, the higher the activation rate. As a result, even if the annealing conditions are such that the impurity is completely activated in the n ⁺ -GaN region where the dose is large, the activation rate of the impurity is not 100% in the n ⁻ -GaN region. Will not be enough. If the activation of the n ⁻ -GaN region is insufficient, the leakage current increases due to the inert impurity, or the electron mobility of the n ⁻ −GaN region which is the RESURF layer is deteriorated by the inert impurity. , There is a problem that the resistance of the n ⁻ -GaN region is increased. Furthermore, even when the crystal defects are not sufficiently recovered, there are problems of increased leakage current and degradation of electron mobility in the n ⁻ -GaN region.

In order to solve this problem, in order to completely activate the n ⁻ -GaN region, it is necessary to anneal at a high temperature of 1300 ° C. or more, for example. However, if annealing is performed for a long time at a high temperature of 1300 ° C. or more, pits are generated on the surface of the GaN crystal, the quality of the interface of GaN / SiO ₂ becomes insufficient, and the mobility of the channel deteriorates. There was a problem.

On the other ^hand, n - to compensate for the electron mobility of the deterioration of -GaN region, increasing the dose of the ^impurity, n + -GaN region and ^{the n} - the difference in electron density between -GaN area is small, n ^- There was a problem that the effect of relaxing the electric field in the -GaN region was reduced, and the desired pressure resistance could not be ensured.

  The present invention has been made in view of the above, and an object thereof is to provide a field effect transistor having a high electron mobility, a small leakage current, and a low on-resistance, and a method for manufacturing the field effect transistor.

  In order to solve the above-described problems and achieve the object, a field effect transistor according to the present invention is a field effect transistor having a MOS structure, which includes a p-type nitride compound semiconductor layer formed on a substrate, a source electrode, An n-type contact region located under the drain electrode and formed by ion implantation and laminated on the p-type nitride compound semiconductor layer by epitaxial growth, and one end thereof is adjacent to the n-type contact region on the drain electrode side, And an electric field relaxation layer formed of an n-type nitride compound semiconductor having a carrier concentration lower than that of the n-type contact region, wherein the other end is overlapped with the drain electrode side of the gate electrode. To do.

  In the field effect transistor according to the present invention as set forth in the invention described above, the electric field relaxation layer is formed so that the resistance increases stepwise or continuously from the drain electrode side to the gate electrode side. Features.

  In the field effect transistor according to the present invention as set forth in the invention described above, the electric field relaxation layer is formed such that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. It is characterized by.

  The field effect transistor according to the present invention is a field effect transistor having a MOS structure, and is formed by ion implantation, located under a p-type nitride compound semiconductor layer formed on a substrate, and a source electrode and a drain electrode. The n-type contact region is stacked by epitaxial growth on the p-type nitride compound semiconductor layer, one end is adjacent to the n-type contact region on the drain electrode side, and the other end is on the drain electrode side of the gate electrode And an AlGaN layer formed so as to overlap, and has an electric field relaxation region formed by a two-dimensional electron gas in the vicinity of the interface between the p-type nitride compound semiconductor layer and the AlGaN layer. .

  In the field effect transistor according to the present invention, in the above invention, the AlGaN layer is formed so that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. Features.

  The field effect transistor manufacturing method according to the present invention is a method for manufacturing a field effect transistor having a MOS structure, wherein a p-type layer forming step of forming a p-type nitride compound semiconductor layer on a substrate, and the p-type An epitaxial growth step of epitaxially growing an n-type nitride compound semiconductor layer on the nitride compound semiconductor layer, and one end of the n-type nitride compound semiconductor layer overlapping a region where a drain electrode is formed in a region where a gate electrode is formed An electric field relaxation layer forming step of forming the n-type nitride compound semiconductor layer to form an electric field relaxation layer, and ion implantation into a region for forming the p-type nitride compound semiconductor layer or the source electrode and the drain electrode of the electric field relaxation layer To form an n-type contact region having a carrier concentration higher than that of the n-type nitride compound semiconductor layer. And forming step, characterized in that it comprises a.

  The field effect transistor manufacturing method according to the present invention is a method for manufacturing a field effect transistor having a MOS structure, wherein a p-type layer forming step of forming a p-type nitride compound semiconductor layer on a substrate, and the p-type An epitaxial growth process for epitaxially growing an AlGaN layer on a nitride compound semiconductor layer, and electric field relaxation for molding the AlGaN layer so that one end of the AlGaN layer overlaps a region where a drain electrode is formed in a region where a gate electrode is formed A region forming step, and a contact region forming step of forming an n-type contact region by performing ion implantation in a region where the source electrode and the drain electrode of the p-type nitride compound semiconductor layer or the AlGaN layer are to be formed. Features.

  According to the present invention, it is possible to realize a field effect transistor having a high electron mobility, a small leakage current, and a low on-resistance, and a method for manufacturing the field effect transistor.

FIG. 1 is a schematic cross-sectional view of a MOSFET according to the first embodiment. FIG. 2 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 3 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 4 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 5 is a schematic cross-sectional view of the MOSFET according to the second embodiment. FIG. 6 is a schematic cross-sectional view of a MOSFET according to the third embodiment. FIG. 7 is a schematic cross-sectional view of a MOSFET according to the fourth embodiment. FIG. 8 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 9 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 10 is a schematic cross-sectional view of a MOSFET according to the fifth embodiment. FIG. 11 is a schematic cross-sectional view of a MOSFET according to the sixth embodiment. FIG. 12 is a schematic cross-sectional view of a conventional MOSFET.

  Embodiments of a field effect transistor and a method for manufacturing the same according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a MOSFET according to Embodiment 1 of the present invention. In this MOSFET 100, a buffer layer 102 and a p-GaN layer 103, which are formed by alternately laminating AlN layers and GaN layers, are formed on a substrate 101 made of sapphire, SiC, Si, or the like. Further, n ⁺ -GaN regions 105 and 106 are formed in part of the p-GaN layer 103, and an n ⁻ -GaN layer 104 is formed in part on the p-GaN layer 103. Further, a source electrode 109 and a drain electrode 110 are formed on the n ⁺ -GaN regions 105 and 106, respectively. An SiO ₂ film 107 is formed on the p-GaN layer 103 and the n ⁻ -GaN layer 104. A gate electrode 108 is formed on the SiO ₂ film 107. The n ⁻ -GaN layer 104 is formed so that one end is adjacent to the n ⁺ -GaN region 106 and the other end overlaps the drain electrode 110 side of the gate electrode 108 and functions as a RESURF layer. .

In this MOSFET 100, an n ⁻ -GaN layer 104 that is a RESURF layer is formed by epitaxial growth, and the n ⁺ -GaN regions 105 and 106 are formed by an ion implantation method. As a result, this MOSFET 100 is a MOSFET having a high electron mobility, a small leakage current, and a low on-resistance because the n ⁻ -GaN layer 104 has very few inert impurities.

Next, a method for manufacturing MOSFET 100 will be described with reference to FIGS. First, the buffer layer 102, the p-GaN layer 103, and the n ⁻ -GaN layer 104 are epitaxially grown on the substrate 101 by MOCVD. The dopant added to the p-GaN layer 103 is Mg, and the addition concentration is about 5 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . On the other hand, the n ⁻ -GaN layer 104 has a thickness of 1 μm, the dopant to be added is Si, and the addition concentration is 1 × 10 ¹³ cm ⁻² .

Next, a part of the n ⁻ -GaN layer 104 is patterned by photolithography. Then, using this patterning as a mask, a part of the n ⁻ -GaN layer 104 is removed by etching to expose a part of the p-GaN layer 103 as shown in FIG. Note that it is preferable to use a dry etching method such as ICP for the etching.

Next, an ion implantation mask for forming the n ⁺ -GaN regions 105 and 106 is formed in the source / drain regions as follows. First, the SiO ₂ film 111 is deposited by 1000 nm on the entire surface by the p-CVD method. Next, the SiO ₂ film 111 immediately above the portion where the n ⁺ -GaN regions 105 and 106 are to be formed is removed by etching using a mask formed by photolithography. Next, a surface protecting SiO ₂ film 112 is deposited on the entire surface by 20 nm. Next, as shown in FIG. 4, Si ions are implanted into the substrate on which the mask has been formed by the above-described steps to form n ⁺ -GaN regions 105 and 106. The dose during ion implantation is typically about 3 × 10 ¹⁵ cm ⁻² .

Next, the SiO ₂ films 111 and 112 are entirely removed by BHF (Buffered HF), and a protective cap layer for annealing for newly activating impurities is deposited on the entire surface. The cap layer is made of SiO _2, AlN, may consist of graphite. Next, annealing for activating the impurities contained in the n ⁺ -GaN regions 105 and 106 is performed. This annealing is performed in an N ₂ atmosphere for 5 minutes using an annealing furnace at a temperature of 1100 ° C. In this manufacturing method, it is only necessary to activate the n ⁺ -GaN regions 105 and 106 that have a relatively large dose and are likely to activate impurities, so that annealing does not need to be performed at a high temperature for a long time. Therefore, pits are not generated on the surface of the GaN crystal, and channel mobility does not deteriorate. After the annealing, the cap layer is removed by an appropriate method such as using BHF.

Next, an SiO ₂ film 107 for forming a MOS structure is deposited to 100 nm on the entire surface, and annealing is performed in a N ₂ atmosphere for 30 minutes at a temperature of 900 ° C. in order to reduce the interface state. Next, 650 nm of poly-Si serving as a gate electrode is deposited. Thereafter, the substrate is annealed in a POCl ₃ atmosphere for 20 minutes in a furnace with an in-furnace temperature of 900 ° C., so that poly Si is doped with P to make the poly Si n ⁺ type. Further, photolithography for defining the gate region is performed, unnecessary poly-Si is removed by etching by RIE, and the gate electrode 108 is formed. Note that the gate electrode 108 is formed so as to partially overlap the n ⁻ -GaN layer 104.

Further, a part of the SiO ₂ film 107 on the n ⁺ -GaN regions 105 and 106 is removed by etching to form the source electrode 109 and the drain electrode 110, whereby the MOSFET 100 is completed.

(Embodiment 2)
FIG. 5 is a schematic sectional view of a MOSFET according to the second embodiment of the present invention. In the MOSFET 200, as in the MOSFET 100, a buffer layer 202 and a p-GaN layer 203 are formed on a substrate 201. Further, n ⁺ -GaN regions 205 and 206 are formed in a part of the p-GaN layer 203, and an n ⁻ -GaN layer 204 is formed in a part on the p-GaN layer 203. Further, a source electrode 209, a drain electrode 210, a SiO ₂ film 207, and a gate electrode 208 are formed. The n ⁻ -GaN layer 204 is formed such that one end is adjacent to the n ⁺ -GaN region 206 and the other end overlaps the drain electrode 210 side of the gate electrode 208 and functions as a RESURF layer.

In this MOSFET 200, an n ⁻ -GaN layer 204 which is a RESURF layer is formed by epitaxial growth, and the n ⁺ -GaN regions 205 and 206 are formed by an ion implantation method. A MOSFET with low current and low on-resistance is obtained.

^Further, n - -GaN layer ^{204, n} adjacent to n + -GaN region 206 - and -GaN layer ^204a, n - ⁿ adjacent -GaN layer 204a - it is composed of two layers of a -GaN layer 204b Yes. Here, although the n ⁻ -GaN layer 204a and the n ⁻ -GaN layer 204b have the same carrier density, the n ⁻ −GaN layer 204b is formed thinner than the n ⁻ −GaN layer 204a. Yes. Therefore, the sheet resistance of the n ⁻ -GaN layer 204b is higher than that of the n ⁻ −GaN layer 204a. As a result, the n ⁻ -GaN layer 204, which is a RESURF layer, has a higher resistance from the drain side to the gate side, so that the concentration of the electric field is further eased. Therefore, the MOSFET 200 has higher withstand voltage. In the MOSFET 200, the n ⁻ -GaN layer 204 is composed of two layers having different thicknesses. However, the n ⁻ −GaN layer is composed of two layers having the same thickness and different carrier concentrations, and is formed from the drain side. The resistance may be increased toward the gate side, or it may be composed of three or more layers.

Such an n ⁻ -GaN layer 204 is formed by first forming an n ⁻ -GaN layer having a uniform thickness and then partially etching the gate side of the formed n ⁻ −GaN layer to reduce the layer thickness. This can be achieved.

(Embodiment 3)
FIG. 6 is a schematic sectional view of a MOSFET according to the third embodiment of the present invention. In the MOSFET 300, as in the MOSFET 100, a buffer layer 302 and a p-GaN layer 303 are formed on a substrate 301. Further, n ⁺ -GaN regions 305 and 306 are formed in part of the p-GaN layer 303. Further, a source electrode 309, a drain electrode 310, a SiO ₂ film 307, and a gate electrode 308 are formed. However, unlike MOSFET 100, n ⁺ -AlGaN layer 313 is formed on n ⁺ -GaN region 306. Further, the AlGaN layer 304 is formed on the p-GaN layer 303 so that one end is adjacent to the n ⁺ -AlGaN layer 313 and the other end overlaps the drain electrode 310 side of the gate electrode 308. .

  In this MOSFET 300, an AlGaN layer 304 is formed on a p-GaN layer 303 by epitaxial growth. As a result, an AlGaN / GaN heterostructure is formed, and two-dimensional electron gas is generated near the interface between the p-GaN layer 303 and the AlGaN layer 304 by spontaneous polarization and piezoelectric polarization. In the MOSFET 300, the region where the two-dimensional electron gas is generated functions as a RESURF region, and the MOSFET has a very high electron mobility, a small leakage current, and a low on-resistance.

The MOSFET 300 can be manufactured by the same method as the MOSFET 100 described above, except that after the AlGaN layer 304 is epitaxially grown instead of the n ⁻ -GaN layer 104, a part thereof is etched away. Note that the n ⁺ -AlGaN layer 313 is formed when the n ⁺ -GaN region 306 is formed by ion implantation. Further, as in the MOSFET 100, the annealing need only be performed on the n ⁺ -GaN regions 305 and 306, so that the annealing need not be performed at a high temperature for a long time. Therefore, pits are not generated on the surface of the GaN crystal, and channel mobility does not deteriorate.

  In the MOSFET 300, as in the MOSFET 200, the AlGaN layer 304 may be formed so that the layer thickness decreases from the drain side to the gate side. When the AlGaN layer 304 is formed in this way, the density of the two-dimensional electron gas generated in the p-GaN layer 303 decreases from the drain side to the gate side, that is, the resistance increases. As a result, in the MOSFET 300, the concentration of the electric field is further relaxed and the pressure resistance is higher.

(Embodiment 4)
FIG. 7 is a schematic cross-sectional view of a MOSFET according to Embodiment 4 of the present invention. In the MOSFET 400, a buffer layer 402 and a p-GaN layer 403 are formed on a substrate 401 as in the MOSFET 100, but unlike the MOSFETs 100 to 300, an n ⁺ − is formed on a part of the n ⁻ −GaN layer 404. A GaN region 406 is formed. A field oxide film 407a for electric field relaxation made of SiO ₂ is formed on the end of the n ⁻ -GaN layer 404 where the gate electrode 408 overlaps. An interlayer insulating film 414 made of SiO ₂ is formed on the SiO ₂ film 407. This MOSFET 400 also has a high electron mobility, a small leakage current, and a low on-resistance because the n ⁻ -GaN layer 404 that is a RESURF layer is formed by epitaxial growth.

The MOSFET 400 can be manufactured by the same method as the MOSFET 100 described above, except for the following points. That is, after removing the protective cap layer, a SiO ₂ film is formed to a thickness of 500 nm on the entire surface. Thereafter, as shown in FIG. 8, patterning is performed so that the field oxide film 407 a remains at the end of the n ⁻ -GaN layer 404. Thereafter, as shown in FIG. 9, a SiO ₂ film 407 and a gate electrode 408 are formed. Thereafter, a SiO ₂ film to be an interlayer insulating film 414 is formed on the entire surface with a thickness of 1 μm. Next, patterning is performed by photolithography, the SiO ₂ film of the source / drain electrode portion is opened by etching, an interlayer insulating film 414 is formed, and a source electrode 409 and a drain electrode 410 are formed by a lift-off method. A Ti / Au (50 nm / 200 nm) electrode or the like is used as the electrode. Next, an opening for the gate electrode 408 is formed in the interlayer insulating film 414, and wiring with an electrode such as Ti / Mo / Au is performed, whereby the MOSFET 400 is completed.

(Embodiment 5)
FIG. 10 is a schematic sectional view of a MOSFET according to the fifth embodiment of the present invention. In the MOSFET 500, the buffer layer 502 and the p-GaN layer 503 are formed on the substrate 501, and the n ⁺ -GaN region 506 is formed in part of the n ⁻ -GaN layer 504, as in the MOSFET 400. In addition, a field oxide film 507a for electric field relaxation and an interlayer insulating film 514 are formed. Furthermore, like the MOSFET ^200, n - -GaN layer ^504, n - and -GaN layer ^504a, n - is composed of two layers of a -GaN layer ^504b, n - sheet resistance of -GaN layer 504b is n ^- - The sheet resistance of the GaN layer 504a is higher. Therefore, the MOSFET 500 has a higher withstand voltage like the MOSFET 200.

(Embodiment 6)
FIG. 11 is a schematic cross-sectional view of a MOSFET according to the sixth embodiment of the present invention. In the MOSFET 600, a buffer layer 602 and an i-GaN layer 603 are formed on a substrate 601. Further, n ⁺ -GaN regions 605 and 606 are formed in a part of the i-GaN layer 603, and AlGaN layers 615 and 604 are formed so as to be adjacent to the n ⁺ -GaN regions 605 and 606, respectively. . A groove 616 having a depth reaching the i-GaN layer 603 is formed between the AlGaN layers 604 and 615. Further, a source electrode 609, a drain electrode 610, a SiO ₂ film 607, a gate electrode 608, and an interlayer insulating film 614 are formed.

  In this MOSFET 600, an AlGaN layer 604 is formed on an i-GaN layer 603 by epitaxial growth. As a result, an AlGaN / GaN heterostructure is formed, a two-dimensional electron gas is generated in the vicinity of the interface between the i-GaN layer 603 and the AlGaN layer 604, and the region where the two-dimensional electron gas is generated functions as a RESURF region. . Therefore, the MOSFET 600 is a MOSFET having extremely high electron mobility, low leakage current, and low on-resistance.

  When manufacturing this MOSFET 600, after an AlGaN layer is epitaxially grown on the i-GaN layer 603, the AlGaN layer is formed by extending a part extending from a region where a RESURF region is formed to a part of a region where a drain electrode is formed to a source electrode. The AlGaN layers 615 and 604 are formed by etching away leaving a portion adjacent to the region where the layer is to be formed.

100-600 MOSFET
101-601 Substrate 102-602 Buffer layer 103-503 p-GaN layer 104, 204, 204a, 204b, 404, 504, 504a, 504b n ⁻ -GaN layer 105-605, 106-606 n ⁺ -GaN region 107- 607, 111, 112 SiO ₂ film 108-608 Gate electrode 109-609 Source electrode 110-610 Drain electrode 304, 604, 615 AlGaN layer 313 n ⁺ -AlGaN layer 407a, 507a Field oxide film 414-614 Interlayer insulating film 603 i -GaN layer 616 groove

Claims (3)

A method of manufacturing a field effect transistor having a MOS structure,
A p-type layer forming step of forming a p-type nitride compound semiconductor layer on the substrate;
An epitaxial growth step of epitaxially growing an n-type nitride compound semiconductor layer on the p-type nitride compound semiconductor layer;
Electric field relaxation for forming an electric field relaxation layer by molding the n-type nitride compound semiconductor layer so that one end of the n-type nitride compound semiconductor layer overlaps a region where a drain electrode is formed in a region where a gate electrode is formed A layer forming step;
Ions are implanted into a region for forming the source electrode and the drain electrode of the p-type nitride compound semiconductor layer or the electric field relaxation layer to form an n-type contact region having a carrier concentration higher than that of the n-type nitride compound semiconductor layer. A region forming step;
A method of manufacturing a field effect transistor comprising: The electric field relaxation layer is claim 1, characterized in that it is formed as stepwise or continuously resistance increases toward the region side to form the drain electrode region side forming the gate electrode A method for producing the field effect transistor according to 1 . The electric field relaxation layer, claims, characterized in that it is formed as stepwise or continuously thickness becomes thinner toward the region side to form the drain electrode region side forming the gate electrode 3. A method for producing the field effect transistor according to 2.

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