JP5454784B2 - Nonvolatile memory element and control method thereof - Google Patents

Description

  The present invention relates to a nonvolatile memory element and a control method thereof, and more particularly, to a nonvolatile memory element using an SRAM (Static Random Access Memory) capable of high-speed operation and a control method thereof.

  Conventionally, research and development of a nonvolatile memory element that can operate at high speed using a volatile SRAM and a variable element and can retain a value even when the power is cut off have been performed. (For example, refer nonpatent literature 1).

  Non-Patent Document 1 describes a technique in which a variable element is connected to each of two terminals of an inverter unit constituting an SRAM memory cell. As a result, the value held in the inverter unit by changing the resistance value or the capacitance value of the variable element according to the value held in the inverter unit, that is, the potential of the two terminals, before the power supply is cut off. It is held by two variable elements.

“Design and Application of Ferroelectric Memory Based Nonvolatile SRAM” IEICE TRANS.ELECTRON., VOL. E87-C, NO. 11 NOVEMBER 2004

  However, according to the above prior art, there is a problem that the failure rate and power consumption at the time of use and manufacture cannot be sufficiently reduced.

  Specifically, according to the above prior art, since one cell has two nonvolatile variable elements, if one of them fails, this cell is not connected even if the other variable element is normal. It cannot be used. Moreover, since it is necessary to change the resistance value or the amount of electric charge of two variable elements, much power consumption is also required.

  Therefore, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory element that can sufficiently reduce a failure rate and power consumption and a control method thereof.

  In order to solve the above problems, a nonvolatile memory element according to the present invention is a nonvolatile memory element in which a plurality of memory cells are arranged, and each of the plurality of memory cells includes a first terminal, a second terminal, An inverter unit including: a first selection switching element that is disposed between the first terminal and the first bit line and switches between conduction and non-conduction between the first terminal and the first bit line; A second selection switching element disposed between the terminal and the second bit line and switching between conduction and non-conduction between the second terminal and the second bit line; and a first terminal having one end connected to the first terminal A fixed resistor, a first control switching element disposed between the other end of the first fixed resistor and the signal line, and for switching between conduction and non-conduction between the other end of the first fixed resistor and the signal line; and one end Is connected to the second terminal. A non-volatile variable resistor that can be higher or lower in resistance than the first fixed resistor, and disposed between the other end of the variable resistor and the signal line, and the other end of the variable resistor and the signal line And a second control switching element that switches between conduction and non-conduction.

  Thereby, since the memory cell includes one variable resistor and one fixed resistor, the failure rate and the power consumption can be sufficiently reduced as compared with the conventional technique including two variable resistors. In other words, according to the nonvolatile memory element according to the present invention, the nonvolatile memory element can be realized by one variable element. Therefore, compared with the conventional case where two variable elements are provided, the memory is deteriorated due to element degradation. Can reduce the possibility of failure. In addition, the power consumption can be reduced by rewriting the value of one variable element, rather than rewriting the value of two variable elements.

  The second control switching element includes an nMOS having a gate connected to the first control line, one of a source and a drain connected to the other end of the variable resistor, and the other of the source and the drain connected to the signal line. A (Metal Oxide Semiconductor) transistor, a pMOS transistor having a gate connected to the second control line, one of a source and a drain connected to the other end of the variable resistor, and the other of the source and the drain connected to the signal line And voltages having different polarities may be applied to the first control line and the second control line.

  Thereby, by using a switch in which a pMOS transistor and an nMOS transistor are connected in parallel, a voltage applied to the switch can be reduced, and power consumption can be reduced. In the configuration of the nonvolatile memory element according to the present invention, the nMOS transistor is preferably used as a switch when the signal line is set to a low potential, and the pMOS transistor is used as a switch when the signal line is set to a high potential. It is preferable to use it. Therefore, the voltage applied to the switch can be reduced by connecting the pMOS transistor and the nMOS transistor in parallel and simultaneously switching between conduction and non-conduction.

  In addition, at least one memory cell among the plurality of memory cells further includes a second fixed resistor having one end connected to the first fixed resistor, and the other end of the second fixed resistor and the signal line. And a third control switching element that switches between conduction and non-conduction between the other end of the second fixed resistor and the signal line.

  Thus, a plurality of values can be held by using a plurality of fixed resistors. Therefore, for example, by configuring all memory cells with memory cells having two fixed resistors, the storage capacity can be doubled. Further, the area of the memory cell array can be reduced by using one of the plurality of memory cells as a memory cell having two fixed resistors.

  The non-volatile memory element control method according to the present invention is the non-volatile memory element control method described above, wherein a predetermined voltage is applied to the first bit line and the second bit line, or A potential generating step of generating a different potential at the first terminal and the second terminal by flowing a current through the first fixed resistor and the variable resistor, and connecting to the inverter unit A power-on step for supplying power to the power line.

  As a result, a potential corresponding to the resistance value of the variable resistor and the resistance value of the fixed resistor is generated at the first terminal and the second terminal, respectively. Therefore, the magnitude relationship between the resistance values of the variable resistor and the fixed resistor is set in advance. Thus, the potential relationship between the first terminal and the second terminal after power-on can be reliably determined. For example, when the resistance value of the variable resistor is larger than the resistance value of the fixed resistor, the potential of the second terminal is larger than the potential of the first terminal, and when the resistance value of the variable resistor is smaller than the resistance value of the fixed resistor, Since the potential at the two terminals is smaller than the potential at the first terminal, the magnitude relationship between the resistance values can be written in the inverter unit.

  Further, in the potential generating step, the predetermined voltage is applied to the first bit line and the second bit line, the first selection switching element and the second selection switching element are made conductive, and the first selection switching element is made conductive. Different currents may be generated at the first terminal and the second terminal by controlling the currents flowing through the first fixed resistor and the variable resistor by the control switching element and the second control switching element.

  Thus, by controlling the amount of current flowing through the variable resistor and the fixed resistor using the control switching element, the potential corresponding to the resistance value of the variable resistor and the resistance value of the fixed resistor is respectively applied to the first terminal and the second terminal. Therefore, by setting in advance the magnitude relationship between the resistance values of the variable resistor and the fixed resistor, the potential relationship between the first terminal and the second terminal after power-on can be determined reliably.

  In the potential generation step, the predetermined current is passed through the first bit line and the second bit line, and the first selection switching element, the second selection switching element, and the first control switching element Further, different potentials may be generated at the first terminal and the second terminal by conducting the second control switching element.

  As a result, a potential corresponding to the resistance value of the variable resistor and the resistance value of the fixed resistor is generated at the first terminal and the second terminal, respectively. Therefore, the magnitude relationship between the resistance values of the variable resistor and the fixed resistor is set in advance. Thus, the potential relationship between the first terminal and the second terminal after power-on can be reliably determined.

  In the power-on step, the power may be turned on with the current flowing through the first bit line and the second bit line.

  Thereby, a value can be stably written in the inverter unit from the variable resistor and the fixed resistor.

  The method for controlling the nonvolatile memory element may further include lowering the signal line than the potential of the second terminal when the potential of the second terminal is higher than the potential of the first terminal after supplying the power. The variable resistance is set to be lower in resistance than the first fixed resistance by setting the potential, turning off the second selection switching element, turning on the second control switching element, and passing a current through the variable resistance. An initialization step may be included.

  Thereby, it is possible to initialize the resistance value in advance (to reduce the resistance) in preparation for when the power is shut off.

  Further, in the above-described non-volatile memory element control method, when the potential of the second terminal is higher than the potential of the first terminal, the variable resistor is set to have a higher resistance than the first fixed resistor, and the second When the terminal potential is lower than the first terminal potential, a store step may be included in which the variable resistance is lower than the first fixed resistance.

  Thereby, the potential difference appearing at the two terminals of the inverter unit can be held as a magnitude relationship between the resistance values of the variable resistor and the fixed resistor.

  In the storing step, when the potential of the second terminal is higher than the potential of the first terminal, the signal line is set to a potential lower than the potential of the second terminal, and the second control switching element is The variable resistor may be made higher in resistance than the first fixed resistor by conducting the current to the variable resistor.

  As a result, using the variable resistor whose resistance value changes depending on the direction or magnitude of the current, the value held at the two terminals of the inverter unit is held as the magnitude relationship between the resistance value of the variable resistor and the fixed resistor. Can do.

  In the storing step, when the potential of the second terminal is higher than the potential of the first terminal, the signal line is set to a potential lower than the potential of the second terminal, and the second bit line is set to the first bit. While setting the electric potential more than the electric potential of 2 terminals, you may make an electric current flow through the said variable resistance by making the said 2nd selection switching element and the said 2nd control switching element into conduction.

  Thereby, the current supply capability can be increased by using the bit line.

  In the storing step, when the potential of the second terminal is lower than the potential of the first terminal, the signal line is set to a potential higher than the potential of the second terminal, and the second control switching element is The variable resistor may be made lower in resistance than the first fixed resistor by conducting the current to the variable resistor.

  As a result, using the variable resistor whose resistance value changes depending on the direction or magnitude of the current, the value held at the two terminals of the inverter unit is held as the magnitude relationship between the resistance value of the variable resistor and the fixed resistor. Can do.

  In the storing step, when the potential of the second terminal is lower than the potential of the first terminal, the signal line is set to a potential higher than the potential of the second terminal, and the second bit line is set to the first bit. The potential may be set to a potential equal to or lower than the potential of the two terminals, and the second selection switching element and the second control switching element may be turned on to pass a current through the variable resistor.

  Thereby, the current supply capability can be increased by using the bit line.

  According to the present invention, the failure rate and power consumption can be sufficiently reduced.

3 is a diagram illustrating an example of a circuit configuration of a nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining a recall operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining a recall operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining an example of initialization processing (set operation) of the nonvolatile memory element according to Embodiment 1. FIG. 7 is a diagram for explaining an example of a reset operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining an example of a setting operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining another example of the setting operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining another example of the setting operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram for explaining another example of the setting operation of the nonvolatile memory element according to Embodiment 1. FIG. 6 is a diagram illustrating an example of a circuit configuration of a nonvolatile memory element according to Embodiment 2. FIG. 6 is a diagram illustrating an example of a circuit configuration of a nonvolatile memory element according to Embodiment 3. FIG. 12 is a diagram for explaining a process of optimizing the resistance value of the nonvolatile memory element according to Embodiment 3. FIG. 12 is a diagram for explaining a process of optimizing the resistance value of the nonvolatile memory element according to Embodiment 3. FIG. 6 is a diagram showing another example of a circuit configuration of a nonvolatile memory element according to Embodiment 3. FIG. 6 is a schematic diagram illustrating an example of a cell arrangement of a nonvolatile memory element according to Embodiment 3. FIG. 6 is a schematic diagram illustrating an example of a cell arrangement of a nonvolatile memory element according to Embodiment 3. FIG.

  Hereinafter, a nonvolatile memory element and a control method thereof according to the present invention will be described in detail based on embodiments.

(Embodiment 1)
The nonvolatile memory element according to Embodiment 1 is a nonvolatile memory element in which a plurality of memory cells are arranged, and each of the plurality of memory cells includes an inverter unit having a first terminal and a second terminal; A first selection switching element that switches between conduction and non-conduction between the first terminal and the first bit line; and a conduction between the second terminal and the second bit line, disposed between the second terminal and the second bit line. A second selection switching element for switching non-conduction, a fixed resistor having one end connected to the first terminal, and the other end of the fixed resistor and the signal line are arranged, and the other end of the fixed resistor and the signal line are electrically connected. And a first control switching element for switching between non-conduction, a variable resistor having one end connected to the second terminal and capable of being higher or lower than the first fixed resistor, the other end of the variable resistor, and a signal line Placed between the other end of the variable resistor Characterized in that it comprises a second control switching element for switching conduction and non-conduction of the signal line. That is, a fixed resistor is connected to one of the two terminals of the inverter unit, a variable resistor is connected to the other, and even if the power supply is shut off by changing the resistance value of the variable resistor, the inverter unit It is characterized by holding the held value.

  FIG. 1 is a diagram illustrating an example of a circuit configuration of the nonvolatile memory element 100 according to the first embodiment. Note that the nonvolatile memory element 100 according to Embodiment 1 is configured by two-dimensionally arranging a plurality of memory cells, and FIG. 1 shows one of the plurality of memory cells. ing.

  As shown in FIG. 1, one memory cell includes an inverter unit 110, selection transistors 120 and 121, control transistors 122 and 123, a fixed resistor 130, and a variable resistor 131.

  The inverter unit 110 includes a first terminal (terminal A) and a second terminal (terminal B), and stores a 1-bit value based on a potential difference appearing between the terminal A and the terminal B. For example, as shown in FIG. 1, the inverter unit 110 includes pMOS transistors 111 and 113 and nMOS transistors 112 and 114. That is, the inverter unit 110 is configured by connecting two CMOS inverters, that is, a CMOS inverter composed of a pMOS transistor 111 and an nMOS transistor 112 and a CMOS inverter composed of a pMOS transistor 113 and an nMOS transistor 114.

  Specifically, the gate of the pMOS transistor 111 and the gate of the nMOS transistor 112 are connected to the terminal B. The source of the pMOS transistor 111 is connected to the power supply line 142. The drain of the pMOS transistor 111 is connected to the terminal A and the drain of the nMOS transistor 112. The source of the nMOS transistor 112 is grounded.

  The gate of the pMOS transistor 113 and the gate of the nMOS transistor 114 are connected to the terminal A. The source of the pMOS transistor 113 is connected to the power supply line 142. The drain of the pMOS transistor 113 is connected to the terminal B and the drain of the nMOS transistor 114. The source of the nMOS transistor 114 is grounded.

  The selection transistor 120 is an example of a first selection switching element, and is an example of a switching element for selecting a memory cell when writing or reading a value. The selection transistor 120 is disposed between the terminal A and the bit line 140 and switches between conduction and non-conduction between the bit line 140 and the terminal A. That is, the selection transistor 120 electrically connects or disconnects the bit line 140 and the terminal A.

  For example, the selection transistor 120 is an nMOS transistor, and the gate of the selection transistor 120 is connected to the word line 143. One of the source and the drain of the selection transistor 120 is connected to the bit line 140 and the other is connected to the terminal A.

  The selection transistor 121 is an example of a second selection switching element, and is an example of a switching element for selecting a memory cell when writing or reading a value. The selection transistor 121 is disposed between the terminal B and the bit line 141 and switches between conduction and non-conduction between the bit line 141 and the terminal B.

  For example, the selection transistor 121 is an nMOS transistor, and the gate of the selection transistor 121 is connected to the word line 143. In addition, one of the source and the drain of the selection transistor 121 is connected to the bit line 141, and the other is connected to the terminal B.

  The control transistor 122 is an example of a first control switching element, and is an example of a switching element for selecting whether or not a current flows through the fixed resistor 130. The control transistor 122 is disposed between the fixed resistor 130 and the signal line 144 and switches between conduction and non-conduction between the fixed resistor 130 and the signal line 144.

  For example, the control transistor 122 is an nMOS transistor, and the gate of the control transistor 122 is connected to the control line 145. One of the source and the drain of the control transistor 122 is connected to the fixed resistor 130, and the other is connected to the signal line 144.

  The control transistor 123 is an example of a second control switching element, and is an example of a switching element for selecting whether or not to pass a current through the variable resistor 131. The control transistor 123 is disposed between the variable resistor 131 and the signal line 144 and switches between conduction and non-conduction between the variable resistor 131 and the signal line 144.

  For example, the control transistor 123 is an nMOS transistor, and the gate of the control transistor 123 is connected to the control line 145. One of the source and drain of the control transistor 123 is connected to the variable resistor 131, and the other is connected to the signal line 144.

  Fixed resistor 130 has a predetermined fixed resistance value. One end of the fixed resistor 130 is connected to the terminal A, and the other end is connected to one of the source and the drain of the control transistor 122.

  The variable resistor 131 is a nonvolatile variable resistor that can be higher or lower in resistance than the fixed resistor 130. Note that the nonvolatile variable resistance is a resistance that can maintain a resistance state even when power is not supplied. One end of the variable resistor 131 is connected to the terminal B, and the other end is connected to one of the source and drain of the control transistor 123.

  For example, the variable resistor 131 is a phase change type resistance element, and specifically, is composed of a chalcogenide semiconductor. Note that the chalcogenide semiconductor is an amorphous semiconductor containing a chalcogen element (S (sulfur), Se (selenium), Te (tellurium), or the like). A chalcogenide semiconductor has several hundreds kΩ in a high resistance state and several hundreds to several kΩ in a low resistance state.

  When the variable resistor 131 is formed of a chalcogenide semiconductor, the variable resistor 131 transitions to a high resistance state by flowing a high current (for example, 100 μA), and the variable resistor 131 is flowed by flowing a low current (for example, 50 μA). Transitions to a low resistance state. As will be described later, setting the variable resistor 131 to a high resistance state is called a reset operation, and setting the variable resistor 131 to a low resistance state is called a set operation.

  The variable resistor 131 may be an oxide that changes between a high resistance state and a low resistance state according to the direction of the flowing current, that is, the polarity of the applied voltage, or a magnetoresistive change element.

  With the above configuration, the nonvolatile memory element 100 according to Embodiment 1 can execute reading and writing of values (SRAM operation) at high speed using the inverter unit 110 during the period when the power is turned on. In the period when the power is cut off, the fixed resistor 130 and the variable resistor 131 can be used to hold the value.

  The bit lines 140 and 141, the power supply line 142, the word line 143, the signal line 144, and the control line 145 are arranged in the memory cell arrangement direction (vertical and horizontal directions), respectively. Each line is connected to a control unit (not shown) having a voltage source or a current source.

  Subsequently, the operation of the nonvolatile memory element 100 according to Embodiment 1 will be described. The operation of the nonvolatile memory element 100 according to Embodiment 1 is roughly divided into three operations: (1) recall operation, (2) SRAM operation, and (3) store operation. Hereinafter, these operations will be described in order.

(1. Recall operation)
First, the recall operation will be described.

  The recall operation is an operation in which a value held in the nonvolatile memory unit during a period in which the power is cut off is written to the inverter unit 110 when the power is turned on. Note that the nonvolatile memory unit refers to the fixed resistor 130 and the variable resistor 131. Specifically, due to the magnitude relationship between the resistance value of the fixed resistor 130 and the resistance value of the variable resistor 131, the nonvolatile memory unit holds the value even during a period in which the power supply is shut off.

  In the period in which the power supply is shut off, the bit lines 140 and 141, the power supply line 142, the word line 143, the signal line 144, and the control line 145 are all set to a low level (for example, potential 0).

  First, as shown in FIG. 2A, by applying a constant voltage to the bit lines 140 and 141 and setting the word line 143 to a high level, the selection transistors 120 and 121 are turned on, and the control line 145 is set to a predetermined level. By setting the potential, the current flowing through the control transistors 122 and 123, that is, the current flowing through the variable resistor 131 and the fixed resistor 130 is controlled. For example, a low voltage of 1 to 3 V is applied to the bit lines 140 and 141, and a voltage of 0.4 to 1.0 V is applied to the word line 143 and the control line 145. That is, even when the voltage applied to the bit lines 140 and 141 is fixed, the current flowing through the fixed resistor 130 and the variable resistor 131 can be controlled by controlling the voltage applied to the control line 145. The same applies to a store operation and an initialization operation described later.

  In the description of the embodiment, the conduction of the switching element includes an operation in a linear region. Thereby, the amount of current flowing through the switching element can be controlled.

  Alternatively, the selection transistors 120 and 121 and the control transistors 122 and 123 may be turned on by passing a constant current through the bit lines 140 and 141 and setting the word line 143 and the control line 145 to a high level. For example, a constant current of 0.05 to 0.2 μA is applied to the bit lines 140 and 141, and a voltage of 0.4 to 1.0 V is applied to the word line 143 and the control line 145. The above values are merely examples, and may be appropriately changed depending on the element size and the like.

  In other words, the bit line 140 and one end of the fixed resistor 130 (that is, the terminal A) are electrically connected, and the other end of the fixed resistor 130 and the signal line 144 are electrically connected. Similarly, the bit line 141 and one end (that is, the terminal B) of the variable resistor 131 are made conductive, and the other end of the variable resistor 131 and the signal line 144 are made conductive. At this time, the signal line 144 remains set to the Low level.

  2A, the current flowing through the bit line 140 flows through the fixed resistor 130 to the signal line 144, and the current flowing through the bit line 141 flows through the variable resistor 131 to the signal line 144. By flowing constant currents of the same magnitude through the bit line 140 and the bit line 141, potentials corresponding to the resistance value of the fixed resistor 130 and the resistance value of the variable resistor 131 are generated at the terminal A and the terminal B, respectively. .

  For example, as shown in FIG. 2A, when the variable resistor 131 is in a high resistance state, that is, when the resistance value Rref of the fixed resistor 130 is smaller than the resistance value Rch of the variable resistor 131, the potential Va generated at the terminal A is It becomes smaller than the potential Vb generated at the terminal B. On the other hand, when the resistance value Rref of the fixed resistor 130 is larger than the resistance value Rch of the variable resistor 131, the potential Va generated at the terminal A is higher than the potential Vb generated at the terminal B.

  In this way, a potential difference corresponding to the difference in resistance value between the fixed resistor 130 and the variable resistor 131 is generated between the terminal A and the terminal B. That is, different potentials are generated at the terminal A and the terminal B according to the difference in resistance value between the fixed resistor 130 and the variable resistor 131, respectively.

  When the potential difference occurs, as shown in FIG. 2B, power is supplied to the power line 142 (power is turned on), and the selection transistors 120 and 121 and the control transistors 122 and 123 are made non-conductive. For example, Vdd (> 0 V) is applied to the power supply line 142, and a voltage of 0 V is applied to the word line 143 and the control line 145 to make each transistor conductive.

  Note that the potential difference between the terminal A and the terminal B can be stabilized by turning on the power in a state where a current is passed through the bit lines 140 and 141.

  Thereby, for example, when Va <Vb, the nMOS transistor 112 whose gate is connected to the terminal B is turned on, the terminal A is grounded, and accordingly, the pMOS transistor 113 whose gate is connected to the terminal A is turned on. , Terminal B is set to Vdd.

  As described above, the value held in the nonvolatile memory unit, that is, the magnitude relationship between the resistance values of the fixed resistor 130 and the variable resistor 131 can be written to the inverter unit 110, that is, the recall operation is performed. Can do.

  Thereby, according to the nonvolatile memory element 100 according to the first embodiment, there is an effect that a margin at the time of recall is large and a margin can be easily estimated at the time of design. This is because, since only one variable resistor is used, stable operation is possible even if there is a variation in the elements, compared to the case where two variable resistors are used.

(2. SRAM operation)
Next, the SRAM operation will be described.

  The SRAM operation is an operation of reading and writing values using the inverter unit 110. When reading / writing values from / to the memory cell after turning on the power, the fixed resistor 130 and the variable resistor 131 do not contribute to the value writing process.

  Specifically, by applying a voltage of 0 V to the control line 145, the control transistors 122 and 123 are turned off. Thereby, even when the selection transistors 120 and 121 are turned on, no current flows through the fixed resistor 130 and the variable resistor 131. For this reason, the fixed resistor 130 and the variable resistor 131 do not affect the operation of the inverter unit 110. Therefore, the nonvolatile memory element 100 according to the first embodiment can realize the same operation as that of the conventional SRAM.

(3. Store operation)
Next, the store operation will be described.

  The store operation is an operation in which a value held in the inverter unit 110 is held in the nonvolatile memory unit before the power is turned off. Specifically, by changing the magnitude relationship between the resistance value of the fixed resistor 130 and the resistance value of the variable resistor 131, the nonvolatile memory unit holds the value.

  Specifically, when the potential of the terminal B is higher than the potential of the terminal A, the variable resistor 131 is made higher than the fixed resistor 130, and when the potential of the terminal B is lower than the potential of the terminal A, the variable resistor 131 is set. Is lower than the fixed resistance 130. Specific operations are shown below.

  First, after the recall operation is finished, the resistance of the variable resistor 131 is lowered (initialization operation). Here, when the potential of the terminal B to which the variable resistor 131 is connected is high (High) during the recall operation, that is, at the end of the recall operation, the variable resistor 131 is in the high resistance state. The case will be described.

  As shown in FIG. 3, the signal line 144 is set to a potential lower than the potential of the terminal B, the selection transistor 121 is turned off, and the control transistor 123 is turned on, so that the variable resistance 131 is passed from the terminal B. Current flows through the signal line 144. Specifically, a low voltage (for example, 0 V) is applied to the signal line 144, the word line 143 is set to a low level (low potential), and the control line 145 is set to a high level (high potential). The selection transistor 121 can be turned off, and the control transistor 123 can be turned on. At this time, since the variable resistor 131 is in a high resistance state, a low current flows through the variable resistor 131. Therefore, the variable resistor 131 is in a low resistance state.

  Note that the amount of current flowing through the variable resistor 131 can be controlled by the voltage value applied to the gate of the control transistor 123, that is, the potential set on the control line 145. For example, when a large current flows through the variable resistor 131, a large voltage may be applied to the gate of the control transistor 123. Conversely, when a small current is passed through the variable resistor 131, a small voltage may be applied to the gate of the control transistor 123.

  As described above, the initialization process (here, the set operation) is executed. When the potential of the terminal B is low (Low) during the recall operation, that is, when the variable resistor 131 is in the low resistance state during the recall operation, it is not necessary to perform the initialization process.

  Next, the non-volatile memory unit holds the value held in the inverter unit 110 before the power is turned off. First, the case where the terminal B is at a higher potential than the terminal A will be described.

  As shown in FIG. 4, the signal line 144 is set to a potential lower than the potential of the terminal B, the selection transistor 121 is made non-conductive, and the control transistor 123 is made conductive so that the variable resistor 131 is passed from the terminal B. Current flows through the signal line 144. Specifically, by applying a low voltage (for example, 0 V) to the signal line 144, setting the word line 143 to a low level, and setting the control line 145 to a high level, the selection transistor 121 is turned off, In addition, the control transistor 123 can be made conductive. At this time, since the variable resistor 131 is initialized and is in a low resistance state, a high current flows through the variable resistor 131. Therefore, the variable resistor 131 is in a high resistance state.

  Accordingly, the value held in the inverter unit 110, that is, the fact that the terminal B is at a high potential can be reflected in the resistance value of the variable resistor 131, and can be held in the nonvolatile memory unit. That is, the store operation is completed. If the variable resistor 131 is in a high resistance state, as described above, the potential of the terminal B can be made larger than the potential of the terminal A by flowing a current from the bit line 141 at the time of recall. It can be returned to the state.

  When the terminal B is at a lower potential than the terminal A, the store operation is not necessary because the variable resistor 131 is already in the low resistance state by the initialization process.

  As described above, the store operation (reset operation) is executed. That is, when the potential of the terminal B to which the variable resistor 131 is connected is high, the resistance value of the variable resistor 131 is set higher than that of the fixed resistor 130. Further, when the potential of the terminal B is low, the resistance value of the variable resistor 131 is set to be lower than that of the fixed resistor 130.

  The initialization process is desirably executed immediately after the recall, but may be performed immediately before the store operation.

  Further, the store operation may be executed as follows.

  For example, the resistance value of the variable resistor 131 does not change according to the amount of current as in the case of a phase change resistance element, but the resistance value changes depending on the direction of the flowing current (or the polarity of the applied voltage). Alternatively, when a magnetoresistive change element or the like is used, high resistance (reset operation) and low resistance (set operation) can be executed by the following method.

  Note that the resistance of the variable resistor 131 is increased when a current flows from the terminal B to the signal line 144 and is decreased when a current flows from the signal line 144 to the terminal B.

  When the terminal B is at a high potential (High), it is necessary to increase the resistance of the variable resistor 131 before turning off the power. Specifically, as shown in FIG. 4, the signal line 144 is set to a potential lower than the potential of the terminal B (for example, 0 V is applied to the signal line 144), the selection transistor 121 is made non-conductive, and By making the control transistor 123 conductive, a current flows from the terminal B through the variable resistor 131 to the signal line 144. Therefore, the resistance of the variable resistor 131 is increased.

  On the other hand, when the terminal B is at a low potential (Low), it is necessary to reduce the resistance of the variable resistor 131 before turning off the power. Specifically, as shown in FIG. 5, the signal line 144 is set to a potential higher than the potential of the terminal B (for example, Vdd is applied to the signal line 144), the selection transistor 121 is made non-conductive, and By making the control transistor 123 conductive, a current flows from the signal line 144 through the variable resistor 131 to the terminal B. Therefore, the resistance of the variable resistor 131 is reduced.

  When the resistance value of the variable resistor 131 changes according to the magnitude of the flowing current, such as a phase change resistance element, the reset operation and the set operation are performed by adjusting the voltage value applied to the signal line 144. And execute. For example, at the time of setting, the voltage applied to the signal line 144 is set low so that a low current flows through the variable resistor 131. Further, the current flowing through the variable resistor 131 may be controlled by fixing the voltage of the signal line 144 (for example, Vdd) and controlling the potential of the control line 145.

  Further, as a modification of the store operation, it can be executed as follows.

  First, as shown in FIG. 6A, the value held in the inverter unit 110 is read. Note that FIG. 6A shows the case where the terminal A has a low potential and the terminal B has a high potential.

  Specifically, by setting the word line 143 to a high level, the terminal A and the bit line 140 are brought into conduction, and the terminal B and the bit line 141 are brought into conduction through the bit lines 140 and 141. Read the potentials at terminals A and B. By reading the potentials of the terminal A and the terminal B, it can be seen that the terminal B is at a high potential. Therefore, it is determined that the resistance of the variable resistor 131 needs to be increased (reset operation is performed).

  Therefore, next, the reset operation of the variable resistor 131 is executed. Specifically, as shown in FIG. 6B, the signal line 144 is set to a potential lower than that of the terminal B, and the control line 145 is set to a high potential, so that the signal line 144 passes through the variable resistor 131 from the terminal B. Current is passed through. At this time, since the selection transistor 121 is in a conductive state, current can be supplied from the bit line 141 to the variable resistor 131 by setting the bit line 141 to a potential equal to or higher than the potential of the terminal B.

  In addition, when the value held in the inverter unit 110 is read out and the terminal B is at a low potential, the setting operation of the variable resistor 131, that is, the resistance reduction is necessary. Specifically, as shown in FIG. 6C, the signal line 144 is set to a higher potential than the terminal B, and the control line 145 is also set to a higher potential, so that the terminal B passes through the variable resistor 131 from the signal line 144. Current is passed through. At this time, since the selection transistor 121 is in a conductive state, current can be supplied to the bit line 141 by setting the bit line 141 to a potential equal to or lower than the potential of the terminal B.

  In general, since a large current is required for rewriting the resistance variable element, the current from the bit line 141 can also be used in the store operation, so that a larger current can flow. That is, the current drive capability of the nonvolatile memory element 100 can be improved.

  As described above, in the nonvolatile memory element 100 according to Embodiment 1, the fixed resistor 130 is connected to the first terminal (terminal A) of the inverter unit 110, and the variable resistor 131 is connected to the second terminal (terminal B). To do. Even if the power supply of the inverter unit 110 is shut off by reflecting the potential difference between the terminal A and the terminal B of the inverter unit 110 in the magnitude relationship between the resistance values of the variable resistor 131 and the fixed resistor 130, The nonvolatile memory element 100 according to Embodiment 1 can hold a value.

  In addition, when the power of the inverter unit 110 is turned on, a constant current is passed through the variable resistor 131 and the fixed resistor 130, so that the difference in resistance value between the variable resistor 131 and the fixed resistor 130 is changed between the terminal A and the terminal B. And appear as a potential difference. As a result, the value stored as the magnitude relationship between the resistance values of the variable resistor 131 and the fixed resistor 130 can be returned to the inverter unit 110.

  According to the nonvolatile memory element 100 according to the first embodiment, since one memory cell includes only one variable element, the failure rate and the consumption are reduced as compared with the conventional case where two variable elements are provided. Electric power can be further reduced. For example, since the number of variable elements that can cause element degradation is half that of the prior art, the failure rate can be reduced. Further, compared to the conventional case where the values of two variable elements are rewritten, only the value of one variable element needs to be rewritten, so that the power consumption required for rewriting can be reduced.

(Embodiment 2)
The nonvolatile memory element according to Embodiment 2 is characterized in that the control switching element connected in series to the variable resistor includes an nMOS transistor and a pMOS transistor connected in parallel to each other.

  FIG. 7 is a diagram illustrating an example of a circuit configuration of the nonvolatile memory element 200 according to Embodiment 2. Note that the nonvolatile memory element 200 according to the second embodiment is configured by two-dimensionally arranging a plurality of memory cells as in the first embodiment, and FIG. 7 illustrates the plurality of memory cells. One of the memory cells is shown.

  The memory cell of the nonvolatile memory element 200 according to the second embodiment is different from the memory cell of the nonvolatile memory element 100 according to the first embodiment shown in FIG. 1 in that a control transistor 224 is further provided. . In the following, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

  The control transistor 224 is an example of a switching element for selecting whether or not to pass a current through the variable resistor 131. The control transistor 224 is disposed between the variable resistor 131 and the signal line 144 and switches between conduction and non-conduction between the variable resistor 131 and the signal line 144.

  For example, the control transistor 224 is a pMOS transistor, and the gate of the control transistor 224 is connected to the control line 246. One of the source and drain of the control transistor 224 is connected to the variable resistor 131, and the other is connected to the signal line 144.

  In addition, voltages having different polarities are applied to the control line 246 and the control line 145. As a result, the control transistor 123 and the control transistor 224 are switched between conduction and non-conduction at the same time.

  Thus, the control transistor 224 is connected in parallel with the control transistor 123, and constitutes an example of the second control switching element according to the present invention together with the control transistor 123.

  With the above configuration, as shown in FIG. 7 in particular, when the resistance of the variable resistor 131 is lowered (set operation), the control line 123 and the pMOS transistor, which are nMOS transistors, are set by setting the signal line 144 to a high potential. The voltage applied to the control transistor 224 can be reduced as compared with the case where only the control transistor 123 is an nMOS transistor.

  Note that when the signal line 144 is set to a low potential, the nMOS transistor is preferably used as a switch, and when the signal line 144 is set to a high potential, the pMOS transistor is preferably used as a switch. Therefore, the control transistor 123, which is an nMOS transistor, and the control transistor 224, which is a pMOS transistor, are connected in parallel, and at the same time switching between conduction and non-conduction, not only when the signal line 144 is set at a low potential, Even in the case of setting, the voltage applied to the control transistors 123 and 224 can be reduced.

  From the above, according to the nonvolatile memory element 200 according to Embodiment 2, even if the voltage applied to the signal line 144 is the same, a larger voltage is applied to the variable resistor 131 (a larger current flows). Power consumption can be reduced.

(Embodiment 3)
The nonvolatile memory element according to Embodiment 3 includes a plurality of fixed resistors, and holds a value of a plurality of bits depending on the difference in resistance value.

  FIG. 8 is a diagram illustrating an example of a circuit configuration of the nonvolatile memory element 300 according to Embodiment 3. Note that the nonvolatile memory element 300 according to Embodiment 3 is configured by two-dimensionally arranging a plurality of memory cells, as in Embodiment 1, and FIG. One memory cell is shown.

  Compared with the memory cell of the nonvolatile memory element 100 according to the first embodiment shown in FIG. 1, the memory cell of the nonvolatile memory element 300 according to the third embodiment further includes control transistors 322a and 322b and a fixed resistor 330a. And 330b. In the following, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

  The control transistors 322a and 322b are an example of a third control switching element.

  The control transistor 322a is an example of a switching element for selecting whether or not to pass a current through the fixed resistor 330a. The control transistor 322a is disposed between the fixed resistor 330a and the signal line 144, and switches between conduction and non-conduction between the fixed resistor 330a and the signal line 144.

  For example, the control transistor 322a is an nMOS transistor, and the gate of the control transistor 322a is connected to the control line 345a. In addition, one of the source and the drain of the control transistor 322a is connected to the fixed resistor 330a, and the other is connected to the signal line 144.

  The control transistor 322b is an example of a switching element for selecting whether or not to pass a current through the fixed resistor 330b. The control transistor 322b is disposed between the fixed resistor 330b and the signal line 144, and switches between conduction and non-conduction between the fixed resistor 330b and the signal line 144.

  For example, the control transistor 322b is an nMOS transistor, and the gate of the control transistor 322b is connected to the control line 345b. One of the source and drain of the control transistor 322b is connected to the fixed resistor 330b, and the other is connected to the signal line 144.

  The gate of the control transistor 123 connected to the variable resistor 131 is connected to the control line 145, and the gate of the control transistor 122 connected to the fixed resistor 130 is connected to the control line 345. Thus, since the gates of the control transistors 123, 122, 322a, and 322b are connected to different control lines, the control transistors 123, 122, 322a, and 322b can be switched between conduction and non-conduction independently. .

  Each of the fixed resistors 330a and 330b is an example of a second fixed resistor, and one end thereof is connected to the terminal A. The other end of the fixed resistor 330a is connected to the source or drain of the control transistor 322a, and the other end of the fixed resistor 330b is connected to the source or drain of the control transistor 322b.

  The resistance values of the fixed resistors 130, 330a, and 330b are desirably different from each other. By switching between conduction and non-conduction of the control transistors 122, 322a and 322b, the combined resistance of the fixed resistors 130, 330a and 330b has a maximum of eight types of resistance values (including the case where all of them are open). Can take.

  Therefore, the memory cell shown in FIG. 8 can hold eight types of values (3 bits) according to the resistance value of the combined resistance. That is, the memory cell can hold three values of the inverter unit 110. Therefore, for example, by changing one of the three memory cells constituting the nonvolatile memory element 300 according to the third embodiment to a memory cell capable of holding 3 bits as shown in FIG. Can be reduced.

  Below, the process which optimizes the value of the fixed resistance connected to the terminal A is demonstrated. For simplicity, the case where two fixed resistors are connected to the terminal A will be described.

  9A and 9B are diagrams for explaining optimization of the fixed resistance. Here, one resistance value of the two fixed resistors is Ra, and the other resistance value is Rb. 9A and 9B show the resistance value Rb of the other fixed resistor when one resistance value Ra = 100 of the fixed resistor and the combined resistance (parallel) Ra // Rb of the two resistors. .

  In the case of two fixed resistors, four types of resistance values of 0, Ra, Rb, and Ra // Rb are conceivable. In order to prevent malfunction of the memory cell, it is desirable that these four types of resistance values are sufficiently different from each other. Specifically, Ra-Rb = Rb-Ra // Rb as shown in FIG. 9A, or Rb-Ra // Rb = Ra // Rb as shown in FIG. 9B. Next, Ra and Rb are determined.

  Solving Ra-Rb = Rb-Ra // Rb gives Rb = 0.62Ra, and solving Rb-Ra // Rb = Ra // Rb gives Rb = 0.71Ra. Therefore, the values of Ra and Rb may be determined so as to satisfy the range of 0.67Ra ≦ Rb ≦ 0.71Ra. Here, the calculation is performed while ignoring the influence of transistors and wirings included in the memory cell, but it is desirable to take these influences into consideration.

  In the third embodiment, a circuit configuration in which a plurality of fixed resistors are connected in parallel as shown in FIG. 8 has been described. However, as shown in FIG. 10, a plurality of fixed resistors may be connected in series. Good.

  FIG. 10 is a diagram illustrating another example of the circuit configuration of the nonvolatile memory element according to Embodiment 3. Note that the nonvolatile memory element 400 according to the modification of the third embodiment is configured by two-dimensionally arranging a plurality of memory cells as in the first embodiment, and FIG. One of the memory cells is shown.

  Compared with the memory cell of the nonvolatile memory element 100 according to the first embodiment shown in FIG. 1, the memory cell of the nonvolatile memory element 400 according to the modification of the third embodiment further includes control transistors 422a and 422b, The difference is that fixed resistors 430a and 430b are provided. In the following, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

  The control transistors 422a and 422b are an example of a third control switching element.

  The control transistor 422a is an example of a switching element for selecting whether or not to pass a current through the fixed resistor 430a. The control transistor 422a is disposed between the fixed resistor 430a and the signal line 144, and switches between conduction and non-conduction between the fixed resistance 430a and the signal line 144.

  For example, the control transistor 422a is an nMOS transistor, and the gate of the control transistor 422a is connected to the control line 445a. One of the source and the drain of the control transistor 422a is connected to the fixed resistor 430a, and the other is connected to the signal line 144.

  The control transistor 422b is an example of a switching element for selecting whether or not to pass a current through the fixed resistor 430b. The control transistor 422b is disposed between the fixed resistor 430b and the signal line 144, and switches between conduction and non-conduction between the fixed resistor 430b and the signal line 144.

  For example, the control transistor 422b is an nMOS transistor, and the gate of the control transistor 422b is connected to the control line 445b. One of the source and the drain of the control transistor 422b is connected to the fixed resistor 430b, and the other is connected to the signal line 144.

  The fixed resistor 430 a is an example of a second fixed resistor, and one end is connected to the other end of the fixed resistor 130, that is, a connection point between the fixed resistor 130 and one of the source and the drain of the control transistor 122. The other end of the fixed resistor 430a is connected to the source and drain of the control transistor 422a.

  One end of the fixed resistor 430b is connected to the other end of the fixed resistor 430a, that is, the connection point between the fixed resistor 430a and one of the source and drain of the control transistor 422a. The other end of the fixed resistor 430b is connected to the source or drain of the control transistor 422b.

  Note that the gate of the control transistor 123 connected to the variable resistor 131 is connected to the control line 145, and the gate of the control transistor 122 connected to the fixed resistor 130 is connected to the control line 445. As described above, since the gates of the control transistors 123, 122, 422a, and 422b are connected to different control lines, the control transistors 123, 122, 422a, and 422b can be switched between conduction and non-conduction independently. .

  Note that the resistance values of the fixed resistors 130, 430a, and 430b are preferably different from each other. By switching between conduction and non-conduction of the control transistors 122, 422a and 422b, the resistance value of the combined resistance of the fixed resistors 130, 430a and 430b can take up to four types of resistance values. That is, there are four types of values: no resistance (all open), only the resistance value of the fixed resistor 130, the combined resistance value of the fixed resistors 130 and 430a, and the combined resistance value of the fixed resistors 130, 430a and 430b. is there.

  Therefore, the memory cell shown in FIG. 10 can hold four types of values (2 bits) according to the resistance value of the combined resistance, similarly to the memory cell shown in FIG. That is, the memory cell can hold two values of the inverter unit 110.

  As described above, according to the nonvolatile memory element 300 according to Embodiment 3, at least one memory cell among the plurality of memory cells constituting the nonvolatile memory element 300 is as shown in FIG. 8 or FIG. And a plurality of fixed resistors. Thus, the memory cell can hold a plurality of bits. That is, since the amount of data that can be stored per cell can be increased and the area of the entire cell array can be reduced, the problem that the cell area is increased by adding an element to the SRAM can be solved.

  For example, the effect of the case where the nonvolatile memory element according to Embodiment 3 includes two fixed resistors having different resistance values and a memory cell (multi-value cell) that can hold a 2-bit value will be described. To do.

  As shown in FIG. 11A, when half of the plurality of memory cells constituting the nonvolatile memory element 500a are configured by multi-value cells, for example, the values of adjacent memory cells can be held in the multi-value cells. The cell array size can be reduced.

  In addition, as shown in FIG. 11B, when all of the plurality of memory cells constituting the nonvolatile memory element 500b are constituted by multi-value cells, the storage capacity is twice that of the nonvolatile memory element constituted by normal memory cells. Can have.

  As described above, the nonvolatile memory element and the control method thereof according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which carried out the various deformation | transformation which those skilled in the art can think to the said embodiment, and the form constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  For example, in the above embodiment, the configuration using the CMOS inverter has been described as the configuration of the inverter unit 110. However, the inverter unit 110 is configured using an nMOS inverter using two nMOS transistors and two resistors. May be.

  In the above embodiment, nMOS transistors are used as the selection transistors 120 and 121 and the control transistors 122 and 123. However, pMOS transistors or bipolar transistors may be used.

  Further, the magnitudes of current and voltage described in the above embodiment are merely examples, and any values can be used as long as the switching element can be turned on and off, or the resistance value of the variable resistor can be rewritten. It may be a value.

  As described above, the present invention can be realized not only as a nonvolatile memory element and a control method thereof but also as a program for causing a computer to execute the nonvolatile memory element control method of the present embodiment. Good. Moreover, you may implement | achieve as recording media, such as computer-readable CD-ROM which records the said program. Furthermore, it may be realized as information, data, or a signal indicating the program. These programs, information, data, and signals may be distributed via a communication network such as the Internet.

  The nonvolatile memory element according to the present invention has an effect that the failure rate and the power consumption can be sufficiently reduced, and can be used, for example, for various memories mounted on computers and mobile phones.

100, 200, 300, 400, 500a, 500b Nonvolatile memory element 110 Inverter unit 111, 113 pMOS transistor 112, 114 nMOS transistor 120, 121 Select transistor 122, 123, 224, 322a, 322b, 422a, 422b Control transistor 130, 330a, 330b, 430a, 430b Fixed resistor 131 Variable resistor 140, 141 Bit line 142 Power line 143 Word line 144 Signal line 145, 246, 345, 345a, 345b, 445, 445a, 445b Control line

Claims (13)

A non-volatile memory element in which a plurality of memory cells are arranged,
Each of the plurality of memory cells includes
An inverter unit having a first terminal and a second terminal;
A first selection switching element that is disposed between the first terminal and the first bit line and switches between conduction and non-conduction between the first terminal and the first bit line;
A second selective switching element that is disposed between the second terminal and the second bit line and switches between conduction and non-conduction between the second terminal and the second bit line;
A first fixed resistor having one end connected to the first terminal;
A first control switching element disposed between the other end of the first fixed resistor and the signal line, and switches between conduction and non-conduction between the other end of the first fixed resistor and the signal line;
A non-volatile variable resistor having one end connected to the second terminal and capable of having a higher or lower resistance than the first fixed resistor;
A second control switching element that is disposed between the other end of the variable resistor and the signal line, and switches between conduction and non-conduction between the other end of the variable resistor and the signal line ;
The second control switching element is
An nMOS (Metal Oxide Semiconductor) transistor having a gate connected to a first control line, one of a source and a drain connected to the other end of the variable resistor, and the other of the source and the drain connected to the signal line;
A pMOS transistor having a gate connected to a second control line, one of a source and a drain connected to the other end of the variable resistor, and the other of the source and the drain connected to the signal line,
A nonvolatile memory element in which voltages having different polarities are applied to the first control line and the second control line . A non-volatile memory element in which a plurality of memory cells are arranged,
Each of the plurality of memory cells includes
An inverter unit having a first terminal and a second terminal;
A first selection switching element that is disposed between the first terminal and the first bit line and switches between conduction and non-conduction between the first terminal and the first bit line;
A second selective switching element that is disposed between the second terminal and the second bit line and switches between conduction and non-conduction between the second terminal and the second bit line;
A first fixed resistor having one end connected to the first terminal;
A first control switching element disposed between the other end of the first fixed resistor and the signal line, and switches between conduction and non-conduction between the other end of the first fixed resistor and the signal line;
A non-volatile variable resistor having one end connected to the second terminal and capable of having a higher or lower resistance than the first fixed resistor;
A second control switching element that is disposed between the other end of the variable resistor and the signal line, and switches between conduction and non-conduction between the other end of the variable resistor and the signal line ;
At least one memory cell of the plurality of memory cells further includes:
A second fixed resistor having one end connected to the first fixed resistor;
A non- volatile memory including a third control switching element that is disposed between the other end of the second fixed resistor and the signal line and switches between conduction and non-conduction between the other end of the second fixed resistor and the signal line. element. A method for controlling a nonvolatile memory element in which a plurality of memory cells are arranged ,
Each of the plurality of memory cells includes
An inverter unit having a first terminal and a second terminal;
A first selection switching element that is disposed between the first terminal and the first bit line and switches between conduction and non-conduction between the first terminal and the first bit line;
A second selective switching element that is disposed between the second terminal and the second bit line and switches between conduction and non-conduction between the second terminal and the second bit line;
A first fixed resistor having one end connected to the first terminal;
A first control switching element disposed between the other end of the first fixed resistor and the signal line, and switches between conduction and non-conduction between the other end of the first fixed resistor and the signal line;
A non-volatile variable resistor having one end connected to the second terminal and capable of having a higher or lower resistance than the first fixed resistor;
A second control switching element that is disposed between the other end of the variable resistor and the signal line, and switches between conduction and non-conduction between the other end of the variable resistor and the signal line;
The method for controlling the nonvolatile memory element includes:
Applying a predetermined voltage to the first bit line and the second bit line or flowing a predetermined current to flow a current through the first fixed resistor and the variable resistor, so that the first terminal And a potential generating step for generating different potentials at the second terminal,
And a power-on step of supplying power to a power supply line connected to the inverter unit. A method for controlling a nonvolatile memory element according to claim 1 or 2 ,
Applying a predetermined voltage to the first bit line and the second bit line or flowing a predetermined current to flow a current through the first fixed resistor and the variable resistor, so that the first terminal And a potential generating step for generating different potentials at the second terminal,
And a power-on step of supplying power to a power supply line connected to the inverter unit. In the potential generation step, the predetermined voltage is applied to the first bit line and the second bit line, the first selection switching element and the second selection switching element are made conductive, and the first control switching is performed. by controlling the current flowing through the first fixed resistor and the variable resistor by said the element second control switching device, according to claim 3 or 4, wherein generating a different potential to the first terminal and the second terminal Method for controlling a nonvolatile memory element of In the potential generation step, the predetermined current is passed through the first bit line and the second bit line, the first selection switching element, the second selection switching element, and the first
5. The method of controlling a nonvolatile memory element according to claim 3 , wherein different potentials are generated at the first terminal and the second terminal by conducting the control switching element and the second control switching element. 6. The method for controlling a nonvolatile memory element according to claim 6, wherein, in the power-on step, the power is turned on in a state where the current flows through the first bit line and the second bit line. The method for controlling the nonvolatile memory element further includes:
After supplying the power, when the potential of the second terminal is higher than the potential of the first terminal, the signal line is set to a potential lower than the potential of the second terminal, and the second selective switching element is turned off. to conduct, the second control switching element is rendered conductive, a current is passed to the variable resistor, any claim 3-7 comprising an initialization step of the variable resistance in the low resistance than the first fixed resistor The method for controlling a nonvolatile memory element according to claim 1. A method for controlling a nonvolatile memory element according to claim 1 or 2 ,
When the potential of the second terminal is higher than the potential of the first terminal, the variable resistor is made higher than the first fixed resistor, and when the potential of the second terminal is lower than the potential of the first terminal, A control method for a nonvolatile memory element, comprising a store step of making the variable resistance lower than the first fixed resistance. In the store step,
When the potential of the second terminal is higher than the potential of the first terminal, the signal line is set to a potential lower than the potential of the second terminal, and the second control switching element is made conductive, so that the variable resistor The method for controlling a nonvolatile memory element according to claim 9, wherein the variable resistor is set to have a higher resistance than the first fixed resistor by causing a current to flow therethrough. In the store step,
When the potential of the second terminal is higher than the potential of the first terminal, the signal line is set to a potential lower than the potential of the second terminal, and the second bit line is set to a potential equal to or higher than the potential of the second terminal. 11. The method of controlling a nonvolatile memory element according to claim 10, wherein the second selection switching element and the second control switching element are turned on to pass a current through the variable resistor. In the store step,
When the potential of the second terminal is lower than the potential of the first terminal, the signal line is set to a potential higher than the potential of the second terminal, and the second control switching element is made conductive, so that the variable resistor The method for controlling a nonvolatile memory element according to claim 9, wherein the variable resistor is set to have a lower resistance than the first fixed resistor by causing a current to flow therethrough. In the store step,
When the potential of the second terminal is lower than the potential of the first terminal, the signal line is set to a potential higher than the potential of the second terminal, and the second bit line is set to a potential equal to or lower than the potential of the second terminal. 13. The method of controlling a nonvolatile memory element according to claim 12, wherein the second selection switching element and the second control switching element are turned on to pass a current through the variable resistor.

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