JP5448530B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor using a group III nitride semiconductor.

  AlGaN / GaN HEMTs and GaN MOSFETs are known as field effect transistors using Group III nitrides. In particular, AlGaN / GaN HEMTs have been widely studied, but conventionally, the threshold voltage has been as low as about +1 V (for example, Non-Patent Document 1).

Regarding GaN-based MOSFETs, devices with a high mobility of 167 cm ² / Vs, devices with a withstand voltage close to 1000 V, and the like have been reported (for example, Non-Patent Document 2).

M. Kuraguchi et al., “Normally-off GaN-MISFET with well-controlled threshold voltage,” International Workshop on Nitride Semiconductors 2006 (IWN2006), Oct. 22-27, 2006, Kyoto, Japan, WeED1-4. Huang W, Khan T, Chow T P: Enhancement-Mode n-Channel GaN MOFETs on p and n- GaN / Sapphire substrates.In: 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2006 (Italy), 10-1.

  The present inventors examined the application of the GaN-based MOSFET to power devices such as automobiles and power supply circuits for home appliances. In the case where a passivation film is not provided between the gate and the drain, the on-resistance is remarkably increased during energization. In this case, it becomes difficult to continuously flow a large current thereafter.

Further, when a MOSFET having a passivation film (SiO ₂ ) was manufactured, even in this case, an increase in on-resistance occurred due to continuous energization. Although the increase in on-resistance is moderate as compared with the case where no passivation film is formed, it is required to further suppress this increase in on-resistance for stable device operation.

  An object of this invention is to provide the field effect transistor which can flow a large electric current stably and continuously.

To achieve the above object, the present invention provides a source and drain formed in a surface region of a semiconductor active layer made of a group III nitride semiconductor, and a gate electrode formed on the semiconductor active layer via a gate oxide film. And a field effect transistor comprising a passivation film formed on the semiconductor active layer between the gate electrode and the drain,
Quality of silicon dioxide constituting the passivation film state, and are density roughness than the film quality of the silicon dioxide constituting the gate oxide film, respectively a passivation film and the gate oxide film, at 20 ° C., the concentration of NH 4 _F 22 The field effect transistor is characterized in that the etching rate when etched with 1% buffered hydrofluoric acid is 3-5 nm / s and 1.5-3 nm / s .

  In the field effect transistor of the present invention, a large current can be stably passed continuously by suppressing an increase in on-resistance generated by continuous energization.

1 is a cross-sectional view showing a configuration of a field effect transistor according to a first embodiment of the present invention. Sectional drawing which shows the structure of the modification of the field effect transistor shown in FIG. The graph which shows the relationship between the presence or absence of a passivation film, an etching rate, and the increase rate of on-resistance. The graph which shows the withstand voltage test result corresponding to the etching rate of a passivation film. Sectional drawing which shows the structure of the field effect transistor which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the structure of the field effect transistor which concerns on the 3rd Embodiment of this invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to a first embodiment of the present invention. The field effect transistor 10 includes, for example, a sapphire substrate (sapphire) 11, a buffer layer (BL) 12 made of a composite layer of AlN / GaN formed on the sapphire substrate 11, and a group III nitride semiconductor on the buffer layer 12. Corresponding to a p-type semiconductor active layer (p-GaN) 13 formed using, a gate electrode 15 formed on the semiconductor active layer 13 via a gate oxide film (SiO ₂ ) 14, and the gate electrode 15 An n-type source contact layer (n ⁺ -GaN) 18s and a drain contact layer (n ⁺ -GaN) 18d that are in ohmic contact with the source electrode 16 and the drain electrode 17, respectively, and a surface electric field relaxation layer (RES: Resurf layer) 19.

  Here, a portion of the semiconductor active layer 13 between the source contact layer 18s and the RESURF layer 19, that is, a portion corresponding to the gate electrode 15 operates as a channel region.

A RESURF (Reduced Surface Field) 19 is formed between the channel region and the drain contact layer 18 d, and relaxes the electric field between the source electrode 16, the gate electrode 15, and the drain electrode 17. Improve the withstand voltage of the transistor. The RESURF layer 19 is an n ⁻ -GaN layer formed by implanting an n-type impurity such as Si into the semiconductor active layer 13 which is a p-GaN layer by an ion implantation method. The impurity concentration of the RESURF layer 19 is lower than that of the drain contact layer 18d.

Further, the field effect transistor 10 includes a passivation film (SiO ₂ ) 20. The passivation film 20 is formed on the resurf layer 19 so as to cover the semiconductor active layer 13 between the gate electrode 15 and the drain contact layer 18d. In addition, the field effect transistor 10 provided with each said structure is called RES-MOSFET.

Hereinafter, a method for manufacturing the field effect transistor 10 of the first embodiment will be described. First, a GaN buffer layer 12 is grown to a thickness of 1 μm on a sapphire substrate 11 as a growth substrate by MOCVD (metal organic chemical vapor deposition). Next, p-GaN is grown to a thickness of 2 μm. Mg is used as the p-type dopant, and the Mg concentration is controlled to 1 × 10 ¹⁷ cm ⁻³ .

  Here, instead of the MOCVD method, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method) or the like may be used. Further, Si, SiC, ZnO, ZrB2 or the like may be used for the growth substrate. Further, Be, Zn, C, or the like may be used as the p-type dopant.

[Element isolation]
Next, a photoresist is applied to the semiconductor surface, and a pattern for element isolation is applied to the photoresist through a photolithography process. Subsequently, the semiconductor layer is etched to a depth of 200 nm using a dry etching apparatus (ICP, RIE, etc.). Next, the photoresist is removed with acetone.

[Resurf layer (RES) formation]
Next, a SiO ₂ mask is formed to a thickness of about 1000 nm. Subsequently, an opening pattern for forming RESURF is formed by a photolithography process, and opening is performed with a hydrofluoric acid aqueous solution. Next, Si ions are implanted. The total dose of Si is 1 × 10 ¹⁴ cm ⁻² . Next, the entire surface of the SiO ₂ mask is removed with a hydrofluoric acid aqueous solution.

[Contact layer (n ⁺ -GaN) formation]
Next, a SiO ₂ mask is formed to a thickness of about 1000 nm. Subsequently, an opening pattern for forming an n ⁺ -GaN layer to be a source contact layer and a drain contact layer is formed by a photolithography process, and opening is performed with a hydrofluoric acid aqueous solution. Next, Si ions are implanted. The total dose of Si is 3 × 10 ¹⁵ cm ⁻² . Next, the entire surface of the SiO ₂ mask is removed with a hydrofluoric acid aqueous solution.

Subsequently, a 500 nm thick SiO ₂ cap layer is deposited on the entire surface. Next, activation annealing is performed in a nitrogen atmosphere at 1300 ° C. for 30 seconds by RTA (instantaneous thermal annealing). Next, the entire surface of the SiO ₂ cap layer is removed with a hydrofluoric acid aqueous solution.

[Gate oxide (SiO ₂ ) deposition]
Next, a 60 nm thick SiO ₂ film is deposited on the entire surface of the semiconductor layer by PECVD. Next, annealing is performed in an atmosphere of nitrogen at 900 ° C. for 30 minutes using an electric furnace. This annealing process is performed in order to reduce the interface state between the channel region and the gate oxide film. The gate oxide film 14 formed as described above has an etching rate of 1.5-3 nm / s when etched with buffered hydrofluoric acid (BHF) having a NH ₄ F concentration of 22% at 20 ° C. .

[Passivation film (SiO ₂ ) formation]
Next, the SiO ₂ film between the gate and the drain is removed by a photolithography process and a BHF process. Subsequently, a passivation film SiO ₂ is deposited between the gate and the drain by a photolithography process and PCVD. The passivation film 20 formed by this process has an etching rate of 3-5 nm / s when etched with buffered hydrofluoric acid (BHF) having a NH ₄ F concentration of 22% at 20 ° C.

Here, the etching rate of the passivation film 20 is larger than the etching rate of the gate oxide film 14. This means that the film quality of SiO ₂ constituting the passivation film 20 is higher than the film quality of SiO ₂ constituting the gate oxide film 14. It means that the density is coarse.

[Formation of source electrode and drain electrode]
Next, openings for the source electrode and the drain electrode are formed in the SiO ₂ film by a photolithography process. Subsequently, a source electrode 16 and a drain electrode 17 made of Ti / Al are formed on the p-type layer exposed from the opening of the insulating film. The source electrode 16 and the drain electrode 17 may be electrodes other than Ti / Al as long as ohmic contact with the source contact layer 18s and the drain contact layer 18d can be realized.

[Gate electrode formation]
Subsequently, polysilicon (poly-Si) is deposited on the entire surface of the device by LPCVD, sputtering, or the like. Next, doping is performed at 900 ° C. for 20 minutes in a thermal diffusion furnace in which poly-Si is filled with POCl ₃ gas. Next, a photolithography process is performed so that poly-Si remains between the source electrode 16 and the drain electrode 17. Thereby, the gate electrode 15 is formed. Here, the poly-Si doping method may be a thermal diffusion method after P deposition. The gate electrode 15 may be Au, Pt, Ni or the like.

  Through the above steps, the field effect transistor 10 shown in FIG. 1 can be manufactured.

  The RES-MOSFET is not limited to the field effect transistor 10 and may be a field effect transistor 10A having the configuration shown in FIG. The field effect transistor 10A of FIG. 2 uses the silicon substrate 11A as a growth substrate, and the above-described electric field is that the semiconductor active layer 13A is formed on the silicon substrate 11A without forming a buffer layer. Different from the effect transistor 10.

  If the etching rate when the gate oxide film 14 is etched with BHF (22%) at 20 ° C. is 1.5-3 nm / s as described above, the present inventors It has been found that a low interface state can be obtained, and if the etching rate when the passivation film 20 is etched with BHF (22%) is 3-5 nm / s as described above, an increase in on-resistance can be suppressed during energization. It was. Hereinafter, a detailed description will be given with reference to FIGS. 3 and 4.

  FIG. 3 is a graph showing the relationship between the presence / absence of the passivation film 20 and the etching rate and the resistance increase rate. The horizontal axis is energization time (seconds), and the vertical axis is the on-resistance increase rate (a.u.) during energization. First, graph A shows a case where the passivation film 20 is not provided. As shown in the figure, the resistance increase rate rapidly increases to about 3.89 in a short time.

  Graph B shows the case where the passivation film 20 is provided and the etching rate is 2.7 nm / s, and the on-resistance increase rate is smaller than that of graph A, for example, around 1.317 around 200 seconds. It was.

  Graph C shows the case where the passivation film 20 is provided and the etching rate is 4.2 nm / s, and the on-resistance increase rate is smaller than that of the graph B. For example, around 200 seconds, it is about 1.004. became.

  From the graphs A to C, if the etching rate of the passivation film 20 when etching is performed under the above conditions is at least 3.0 nm / s or more, an increase in on-resistance during energization is suppressed, that is, resistance over time. It can be seen that the fluctuation can be reduced. Next, the upper limit of the etching rate of the passivation film 20 will be described with reference to FIG.

FIG. 4 is a graph showing the results of a withstand voltage test corresponding to the etching rate of the passivation film 20. The horizontal axis is the electric field intensity E (MV / cm), and the vertical axis is the current I (A). First, the graph shown by a solid line shows a case where the etching rate of the passivation film 20 is 2.2 nm / s, and the current I gradually increases until the electric field strength reaches about 8 MV / cm, and thereafter It rose to about 1.30 × 10 ⁻⁰⁶ (A).

Next, a graph indicated by a dotted line shows a case where the etching rate of the passivation film 20 is 3.4 nm / s, and the current I gradually increases until the electric field strength reaches about 8 MV / cm, and thereafter 1.00 × 10 ⁻⁰⁵ (A).

Furthermore, the graph indicated by the alternate long and short dash line shows a case where the etching rate of the passivation film 20 is 5.5 nm / s, and the current I increases sharply while the electric field strength reaches about 1.4 MV / cm. Thus, it was about 9.99 × 10 ⁻⁰⁶ (A).

  From the graph shown in FIG. 4, it can be seen that the withstand voltage decreases when the etching rate of the passivation film 20 is 5.5 nm / s or more. That is, if the etching rate of the passivation film 20 by BHF (22%) is 3-5 nm / s, an increase in on-resistance during energization can be suppressed without reducing the withstand voltage.

  In the following, consideration will be given to the relationship between the etching rate and the increase in on-resistance during energization. First, by performing annealing (that is, by reducing the etching rate), the interface state near the conduction band is lowered. However, on the other hand, it is considered that the interface state near the mid gap increases. Here, when the energy level at the bottom in the conduction band of GaN is denoted by Ec and the energy level at the top of the valence band is denoted by Ev, the mid gap is, for example, from Ec-1 eV to Ev-1 eV Between. Note that when an interface state exists, electrons in the conduction band are trapped in the interface state. For this reason, the current decreases and the on-resistance increases.

  The interface state in the vicinity of the mid gap has a long time for capturing electrons, and does not affect the resistance fluctuation in a short time, but leads to an increase in on-resistance in a long time. For this reason, when the etching rate is low, it is considered that the on-resistance has increased due to energization for a long time.

  On the other hand, if the etching rate is increased, the interface state in the vicinity of the mid gap is high, and it is considered that an increase in on-resistance is observed due to long-time energization. Here, the upper limit of the etching rate is defined in consideration of the fact that the withstand voltage is reduced as shown in FIG.

  Next, the etching rate of the gate oxide film 14 will be described. If the etching rate of the gate oxide film 14 is smaller than 1.5 nm / s, for example, pinholes are likely to occur, and the withstand voltage may decrease. On the other hand, when the etching rate of the gate oxide film 14 is larger than 3 nm / s, it is difficult to obtain a low interface state. That is, when the etching rate of the gate oxide film 14 is 1.5-3 nm / s, a low interface state is obtained and the channel mobility is increased. The present inventors have already filed an application in Japanese Patent Application No. 2007-244250 regarding the relationship between the etching rate of the gate oxide film and the interface state.

In the field effect transistors 10 and 10A of this embodiment, the film quality of SiO ₂ constituting the passivation film 20 is coarser than the film quality of SiO ₂ constituting the gate oxide film 14, and the gate oxide film 14 and Since the etching rate of the passivation film 20 is within the above range, an increase in on-resistance can be suppressed during energization, and a large current can be flowed stably and continuously. Further, since the RESURF layer 19 is provided, the withstand voltage can be increased. As a result, the field effect transistors 10 and 10A can be suitably used for power devices such as automobiles and power supply circuits for home appliances.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing a configuration of a field effect transistor according to the second embodiment of the present invention. The field effect transistor 10B includes, for example, a silicon substrate (Si) 11B, a buffer layer (BL) 12B formed on the silicon substrate 11B, and a semiconductor activity formed on the buffer layer 12B using a group III nitride semiconductor. A layer (P-GaN) 13B, a gate electrode 15B formed in the recess groove on the semiconductor active layer 13B via a gate oxide film (SiO ₂ ) 14B, a source electrode formed corresponding to the gate electrode 15B 16 and the drain electrode 17 are provided. Here, the semiconductor active layer 13B is composed of an undoped GaN growth layer 21 and an undoped AlGaN growth layer 22 formed on the undoped GaN growth layer 21, and has a heterojunction interface. The heterojunction interface is constituted by an electron transit layer made of GaN and an electron supply layer made of AlGaN.

Further, the field effect transistor 10B includes a passivation film (SiO ₂ ) 20B. The passivation film 20 </ b> B is formed so as to cover the undoped AlGaN growth layer 22 between the gate electrode 15 </ b> B and the drain electrode 17. In addition, the field effect transistor 10B provided with each said structure is called Hybrid MOSHEMT.

  Hereinafter, a manufacturing method of the field effect transistor 10B of the second embodiment will be described. First, a buffer layer 12B having a laminated structure of AlGaN and GaN is grown on a silicon substrate 11B as a growth substrate by MOCVD (metal organic chemical vapor deposition).

Next, p-GaN is grown to a thickness of 1.5 μm. Mg is used as the dopant, and the Mg concentration is controlled to 1 × 10 ¹⁷ cm ⁻³ . Subsequently, undoped GaN is grown to a thickness of 100 nm, and undoped AlGaN (Al = 22%) is grown to a thickness of 20 nm.

  Here, instead of the MOCVD method, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method) or the like may be used. Further, sapphire, SiC, ZrB2 or the like may be used as the growth substrate. Further, Be, Zn, C, or the like may be used as the dopant.

[Element isolation]
Next, a photoresist is applied to the semiconductor surface, and a pattern for element isolation is applied to the photoresist through a photolithography process. Next, the semiconductor layer is etched to a depth of 200 nm using a dry etching apparatus (ICP, RIE, etc.). Subsequently, the photoresist is removed with acetone.

[Gate recess]
Next, a SiO ₂ mask is formed to a thickness of about 300 nm. Next, an opening pattern for a gate recess is formed by a photolithography process, and opening is performed with a hydrofluoric acid aqueous solution. Subsequently, etching is performed at a depth of 60 nm using a dry etching apparatus. Next, the entire surface of the SiO ₂ mask is removed with a hydrofluoric acid aqueous solution.

[Gate oxide deposition]
Next, SiO ₂ having a thickness of 60 nm is deposited on the entire surface of the semiconductor layer by PECVD. Next, annealing is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes using an electric furnace. This annealing process is performed in order to reduce the interface state of the channel region. The gate oxide film (SiO ₂ ) 14B formed as described above has an etching rate of 1.5-3 nm / s when etched with BHF (22%) at 20 ° C.

[Passivation film formation]
Next, SiO ₂ between the gate and the drain is removed by a photolithography process and BHF treatment. Next, a passivation film (SiO ₂ ) 20B is deposited between the gate and the drain by a photolithography process and PCVD. The passivation film (SiO ₂ ) 20B formed by this process has an etching rate of 3-5 nm / s when etched with BHF (22%) at 20 ° C.

[Formation of source electrode and drain electrode]
Next, openings for a source electrode and a drain electrode are formed in the insulating film by a photolithography process. Subsequently, a source electrode 16 and a drain electrode 17 made of Ti / Al are formed on the p-type layer exposed from the opening of the insulating film. Further, the source electrode 16 and the drain electrode 17 may be electrodes other than Ti / Al as long as ohmic contact can be realized.

[Gate electrode formation]
Next, polysilicon (poly-Si) is deposited on the entire surface of the device by LPCVD, sputtering, or the like. Next, poly-Si is doped at 900 ° C. for 20 minutes in a thermal diffusion furnace in which POCl ₃ gas is sealed. Subsequently, a photolithography process is performed so that poly-Si remains between the source electrode 16 and the drain electrode 17. Thereby, the gate electrode 15B is formed. Here, the poly-Si doping method may be a thermal diffusion method after P deposition. The gate electrode 15B may be Au, Pt, Ni, or the like.

  Through the above steps, the field effect transistor 10B shown in FIG. 5 can be manufactured.

  In the field effect transistor 10B of this embodiment, a large current can be stably and continuously flowed, and two-dimensional electron gas at the heterojunction interface between the undoped GaN growth layer 21 and the undoped AlGaN growth layer 22 is used as a carrier. By doing so, high mobility can be obtained.

(Third embodiment)
FIG. 6 is a cross-sectional view showing a configuration of a field effect transistor according to the third embodiment of the present invention. The field effect transistor 10C includes, for example, a silicon substrate (Si) 11C, a buffer layer (BL) 12C formed on the silicon substrate 11C, and a semiconductor activity formed on the buffer layer 12C using a group III nitride semiconductor. A layer (p-GaN) 13C, a gate electrode 15C formed in the recess groove on the semiconductor active layer 13C via a gate oxide film (SiO ₂ ) 14C, a source electrode formed corresponding to the gate electrode 15C An n-type source contact layer (n ⁺ -GaN) 18s and a drain contact layer (n ⁺ -GaN) 18d that are in ohmic contact with the drain electrode 17 and the drain electrode 17, respectively, and a Si-doped GaN (n ⁻ -GaN) layer that is a RESURF layer 23.

Further, the field effect transistor 10C includes a passivation film (SiO ₂ ) 20C. The passivation film 20C is formed so as to cover the Si-doped GaN (n ⁻ -GaN) layer 23 between the gate electrode 15C and the drain contact layer 18d. The field effect transistor 10C having the above-described configurations is referred to as an Epi-RES MOSFET.

  A method for manufacturing the field effect transistor 10C of the third embodiment will be described below. First, a buffer layer 12C having a laminated structure of AlGaN and GaN is grown on a silicon substrate 11C as a growth substrate by MOCVD (metal organic chemical vapor deposition).

Next, 1.5 μm of p-GaN is grown. Mg is used as the dopant, and the Mg concentration is controlled to 1 × 10 ¹⁷ cm ⁻³ . Next, Si-doped GaN is grown to 100 nm.

  Here, instead of the MOCVD method, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method) or the like may be used. Further, sapphire, SiC, ZrB2 or the like may be used for the growth substrate. Further, Be, Zn, C, or the like may be used as the dopant.

[Element isolation]
Next, a photoresist is applied to the semiconductor surface, and a pattern for element isolation is applied to the photoresist through a photolithography process. Next, the semiconductor layer is etched to a depth of 200 nm using a dry etching apparatus (ICP, RIE, etc.). Subsequently, the photoresist is removed with acetone.

[Contact layer (n ⁺ -GaN layer) formation]
Next, a SiO ₂ mask is formed to a thickness of about 1000 nm. Next, an opening pattern for forming an n ⁺ -GaN layer is formed by a photolithography process, and opening is performed using a hydrofluoric acid aqueous solution. Next, Si ion implantation is performed. The total dose of Si is 3 × 10 ¹⁵ cm ⁻² . Subsequently, the entire surface of the SiO ₂ mask is removed with a hydrofluoric acid aqueous solution.

[Gate recess]
Next, a SiO ₂ mask is formed to a thickness of about 300 nm. Next, an opening pattern for a gate recess is formed by a photolithography process, and opening is performed with a hydrofluoric acid aqueous solution. Subsequently, etching is performed at a depth of 60 nm using a dry etching apparatus. Next, the entire surface of the SiO ₂ mask is removed with a hydrofluoric acid aqueous solution.

[Gate oxide deposition]
Next, SiO ₂ having a thickness of 60 nm is deposited on the entire surface of the semiconductor layer by PECVD. Next, annealing is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes using an electric furnace. This annealing process is performed in order to reduce the interface state of the channel region. The gate oxide film (SiO ₂ ) 14C formed as described above has an etching rate of 1.5-3 nm / s when etched with BHF (22%) at 20 ° C.

[Passivation film formation]
Next, SiO ₂ between the gate and the drain is removed by a photolithography process and BHF treatment. Next, a passivation film (SiO ₂ ) 20C is deposited between the gate and the drain by a photolithography process and PCVD. The passivation film 20C formed by this process has an etching rate of 3-5 nm / s when etched with BHF (22%) at 20 ° C.

[Formation of source electrode and drain electrode]
Next, openings for a source electrode and a drain electrode are formed in the insulating film by a photolithography process. Next, a source electrode 16 and a drain electrode 17 made of Ti / Al are formed on the p-type layer exposed from the opening of the insulating film. Further, the source electrode 16 and the drain electrode 17 may be electrodes other than Ti / Al as long as ohmic contact can be realized.

[Gate electrode formation]
Next, polysilicon (poly-Si) is deposited on the entire surface of the device by LPCVD, sputtering, or the like. Next, poly-Si is doped at 900 ° C. for 20 minutes in a thermal diffusion furnace in which POCl ₃ gas is sealed. Subsequently, a photolithography process is performed so that poly-Si remains between the source electrode 16 and the drain electrode 17. Thereby, the gate electrode 15C is formed. The poly-Si doping method may be a thermal diffusion method after P deposition. Further, the gate electrode 15C may be Au, Pt, Ni or the like.

  Through the above steps, the field effect transistor 10C shown in FIG. 6 can be manufactured.

  In the field effect transistor 10C of the present embodiment, a large current can be stably flowed, and since the RESURF layer is formed by epitaxial growth, the manufacturing process becomes easier compared to the case of forming by ion implantation. In addition, the withstand voltage can be increased.

  Although the present invention has been described based on the preferred embodiment, the field effect transistor of the present invention is not limited to the configuration of the above embodiment, and various modifications and changes can be made from the configuration of the above embodiment. Those subjected to are also included in the scope of the present invention.

10, 10A to 10C: field effect transistors 11, 11A to 11C: substrates 12, 12B, 12C: buffer layers 13, 13A to 13C: semiconductor active layers 14, 14B, 14C: gate oxide films 15, 15B, 15C: gate electrodes 16: Source electrode 17: Drain electrode 18s: Source contact layer 18d: Drain contact layer 19, 23: RESURF layer (electric field relaxation layer)
20, 20B, 20C: Passivation film 21: Undoped GaN growth layer 22: Undoped AlGaN growth layer

Claims (5)

A source and drain formed in a surface region of a semiconductor active layer made of a group III nitride semiconductor, a gate electrode formed on the semiconductor active layer via a gate oxide film, and between the gate electrode and the drain In a field effect transistor comprising a passivation film formed on the semiconductor active layer,
The passivation film quality of the silicon dioxide constituting it, the gate oxide film Ri der density roughness than the film quality of the silicon dioxide constituting the passivation film and the gate oxide film, respectively, at 20 ° C., of NH 4 _F A field effect transistor having an etching rate of 3-5 nm / s and 1.5-3 nm / s when etched with a buffered hydrofluoric acid having a concentration of 22% . The field effect transistor according to claim 1 , wherein the group III nitride semiconductor is GaN. Wherein with the semiconductor active layer is a recess groove, wherein the gate electrode is formed via a gate oxide film formed on the recessed groove surface, the field effect transistor according to claim 1 or 2. The field effect transistor according to any one of claims 1 to 3 , wherein the semiconductor active layer has a heterojunction interface constituted by an electron transit layer made of GaN and an electron supply layer made of AlGaN. An electric field relaxation layer in the semiconductor active layer between the gate electrode and the drain;
The passivation layer is formed on the field relaxation layer, the field-effect transistor according to any one of claims 1-3.

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