JP5445562B2 - モジュール - Google Patents
モジュール Download PDFInfo
- Publication number
- JP5445562B2 JP5445562B2 JP2011246149A JP2011246149A JP5445562B2 JP 5445562 B2 JP5445562 B2 JP 5445562B2 JP 2011246149 A JP2011246149 A JP 2011246149A JP 2011246149 A JP2011246149 A JP 2011246149A JP 5445562 B2 JP5445562 B2 JP 5445562B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring
- hole
- heat
- heat conducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
第1の実施形態では、電気伝導部が基板の表面側に設けられた例を説明する。
第2の実施形態では、基板の表面側に設けられた電気伝導部が挿入端子部及びスルーホールを介して基板の配線に接続された例を説明する。
第3の実施形態では、電気伝導部が基板の反対側の面に設けられた例を説明する。
上記各実施形態では、熱伝導部21,23,322,422の周囲全体からはみ出るような電気伝導部22,322,422が形成されているが、熱伝導部21,23,322,422の周囲から部分的にはみ出るように電気伝導部22,324,424が形成されていてもよい。
3,330,430 素子
11,302,402 表面
303,403 反対側の面
12,304,404 貫通孔
13,305,405,605 配線
21,23,322,422 熱伝導部
22,324,424 電気伝導部
211 表面
310,410,610 スルーホール
326,626 挿入端子部
408 裏面配線
424a 張出し部分
525 突部
526 半田層
Claims (1)
- 配線(405,605)が形成された表面(402)と、前記表面(402)とは反対側の面(403)であって前記配線と電気的に接続された裏面配線(408)が形成された面と、貫通孔(404)とを有する基板(401)と、
前記貫通孔に埋設される熱伝導部(422)と、
前記基板の前記反対側の面と同じ側にある前記熱伝導部の表面の少なくとも一部を覆うと共に前記基板の前記反対側の面に接触可能な張出し部分(424a)を有し、前記基板の前記反対側の面側から前記裏面配線に重ねるように配設されて、前記裏面配線に半田付けされ、前記配線に電気的に接続される電気伝導部(424)と、
前記基板の前記表面側で前記熱伝導部上に載置され、前記熱伝導部を通じて前記電気伝導部に電気的に接続される素子(430)と、
を備え、
前記電気接続部の前記張出し部分(424a)のうち前記基板の前記反対側の面に対向する部分に突部(525)が形成され、
前記突部(525)を前記反対側の面の前記裏面配線(408)に接触させた状態で、前記張出し部分が前記基板の前記反対側の面の配線に半田付けされる、モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011246149A JP5445562B2 (ja) | 2005-08-18 | 2011-11-10 | モジュール |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005237515 | 2005-08-18 | ||
JP2005237515 | 2005-08-18 | ||
JP2011246149A JP5445562B2 (ja) | 2005-08-18 | 2011-11-10 | モジュール |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006210708A Division JP4899700B2 (ja) | 2005-08-18 | 2006-08-02 | モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012028826A JP2012028826A (ja) | 2012-02-09 |
JP5445562B2 true JP5445562B2 (ja) | 2014-03-19 |
Family
ID=45781293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011246149A Expired - Fee Related JP5445562B2 (ja) | 2005-08-18 | 2011-11-10 | モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5445562B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112021005646T5 (de) | 2020-12-28 | 2023-08-10 | Hitachi Astemo, Ltd. | Leistungshalbleitervorrichtung |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5285352A (en) * | 1992-07-15 | 1994-02-08 | Motorola, Inc. | Pad array semiconductor device with thermal conductor and process for making the same |
JP3281220B2 (ja) * | 1994-12-14 | 2002-05-13 | 株式会社東芝 | 回路モジュールの冷却装置 |
JP3653460B2 (ja) * | 2000-10-26 | 2005-05-25 | 三洋電機株式会社 | 半導体モジュールおよびその製造方法 |
JP2002190540A (ja) * | 2000-12-20 | 2002-07-05 | Kyocera Corp | 半導体素子収納用パッケージ |
JP2003282771A (ja) * | 2002-03-20 | 2003-10-03 | Kyocera Corp | 放熱板付き配線基板 |
JP2003338577A (ja) * | 2002-05-21 | 2003-11-28 | Murata Mfg Co Ltd | 回路基板装置 |
JP2003347487A (ja) * | 2002-05-29 | 2003-12-05 | Nec Kansai Ltd | 半導体装置 |
-
2011
- 2011-11-10 JP JP2011246149A patent/JP5445562B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112021005646T5 (de) | 2020-12-28 | 2023-08-10 | Hitachi Astemo, Ltd. | Leistungshalbleitervorrichtung |
Also Published As
Publication number | Publication date |
---|---|
JP2012028826A (ja) | 2012-02-09 |
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