JP5442272B2 - Field effect transistor and method of manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor and a field effect transistor manufacturing method.

  Non-Patent Document 1 Masaaki Kuzuhara et al., “Current Status and Prospects of High-Power AlGaN / GaN Heterojunction FETs” include conventional representative field effect transistors (FETs) using nitride-based materials. : Field Effect Transistor) device structure is shown. An example is shown in FIG. FIG. 5 is a cross-sectional view showing an example of a cross-sectional structure of a conventional nitride field effect transistor described in Non-Patent Document 1.

  In the nitride field effect transistor shown in FIG. 5, a nitride semiconductor layer made of undoped GaN is formed as a channel layer 2 on a substrate 1 via a buffer layer 2A, and an electron supply made of undoped AlGaN is formed on the channel layer 2. The device has a device structure in which the layer 5 is formed, and has a high electron mobility transistor (HEMT) structure in which a heterojunction interface between the channel layer 2 and the electron supply layer 5 is formed.

  Positive fixed charges are generated at the heterojunction interface between the channel layer 2 and the electron supply layer 5. Correspondingly, a two-dimensional electron gas 3 A as free electrons is formed in the channel layer 2 immediately below the heterojunction interface. Induced, a channel region is formed. A source electrode 8, a gate electrode 9, and a drain electrode 10 are formed on the electron supply layer 5 to constitute a field effect transistor.

  However, in the device structure shown in Non-Patent Document 1, the mutual conductance is about 150 mS / mm, which is significantly lower than the original performance (intrinsic mutual conductance) that nitride materials generally have. The reason is that from the contact portion between the source electrode 8 and the undoped AlGaN electron supply layer 5 to the channel region (region in the vicinity of the junction interface between the electron supply layer 5 and the channel layer 2) immediately below the gate electrode 9 where the transistor actually operates. This is because it is affected by the parasitic resistance (that is, source resistance) existing until now. Since transconductance is one of the important device performance indicators, this reduction in source resistance is essential in the device.

  On the other hand, in the “reduction in on-resistance of low gate leakage current Si ion-implanted GaN / AlGaN / GaN HEMT” by Kazutaka Nomoto et al. In Non-Patent Document 2, by adopting a manufacturing method as shown in FIG. The source resistance is reduced. FIG. 6 is a cross-sectional view showing an example different from FIG. 5 of the cross-sectional structure of the conventional nitride field effect transistor described in Non-Patent Document 2 and shows the manufacturing process.

  As shown in FIG. 6A, an undoped GaN channel layer 2, an undoped Al0.25Ga0.75N electron supply layer 5, and an undoped GaN electrode formation region 6A are sequentially formed on a sapphire (0001) substrate 1. After the growth, a SiNx surface protective film 7A is formed. Thereafter, as shown in FIG. 6B, after a photoresist mask 8A is formed, Si ions are implanted into the electrode formation region 6A and the source region and drain region of the electron supply layer 5 to increase the concentration. The ion implantation region 4A is formed, and further, ion activation annealing is performed at 1000 ° C. or more to activate the implanted ions, improve the carrier concentration, and reduce the source resistance.

  In the device having the structure shown in FIG. 6, when the distance between the gate electrode 9 and the source electrode 8 is 3 μm, the Si resistance is 15 Ωmm when Si ions are not implanted. When the high-concentration ion-implanted region 4A is formed by ion implantation of Si ions, the source resistance is successfully reduced to 1.6Ωmm, which is about (1/10).

  However, while the intrinsic transconductance in the device structure shown in FIG. 6 is about 200 mS / mm, the actual device still has a low value of 147 mS / mm.

  Here, the source resistance mainly includes the contact resistance of the source electrode 8 and the contact region of the source electrode 8 to the channel region (the junction interface between the electron supply layer 5 and the channel layer 2 directly under the gate electrode 9 that actually operates as a transistor). It refers to both of the access resistances that exist up to the neighboring area. Therefore, in order to reduce the source resistance, it is essential to reduce both the contact resistance and the access resistance.

  In the case of the device structure as shown in FIG. 6, the contact resistance of the source electrode 8 is certainly reduced by forming the high concentration ion implantation region 4A and forming the source electrode 8 in the source region having a low resistance. Can do. However, since there is still a high access resistance between the source region (ie, the high concentration ion implantation region 4A) that has become low resistance due to ion implantation and the channel region, the source resistance is sufficient. However, the transconductance remains low.

  On the other hand, in order to prevent an access resistance from interposing between the high concentration ion implantation region 4A and the channel region, a high concentration is formed by a self-alignment method using a gate electrode material for forming the gate electrode 9 as a mask. It is effective to form an ion implantation region. However, since the temperature required for the ion activation heat treatment of the nitride-based material is a high temperature of 1000 ° C. or higher, the material of the gate electrode 9 having heat resistance enough to withstand the heat treatment of 1000 ° C. or higher is obtained without deteriorating the device characteristics. Does not exist.

Masaaki Kuzuhara et al., “Current Status and Prospects of High-Power AlGaN / GaN Heterojunction FETs”, IEICE Transactions C, VOL. J86-C, NO. 4, pp. 396-403, April 2003 Kazutaka Nomoto et al., “Low gate leakage current Si ion implantation GaN / AlGaN / GaN HEMT on-resistance reduction”, IEEJ Transactions C, VOL. 128, NO. 6, pp. 885-889, 2008

  As described above, in a field effect transistor using a nitride semiconductor, it is important to reduce source resistance and drain resistance. However, under the present situation, as described above, there are the following problems.

  (1) The conventional typical nitride field effect transistor has a large source resistance and drain resistance. Therefore, the mutual conductance is lower than the original performance (intrinsic mutual conductance) that a nitride material has. It was very low.

  (2) Even when ion implantation is performed on the source region and the drain region to reduce the contact resistance of the source electrode and the drain electrode, parasitic resistance still exists, and the source resistance and drain The resistance has not been reduced sufficiently. The reason is that, as described above, the high concentration ion implantation region formed by ion implantation is not formed in a self-aligned manner, and there is an access resistance between the channel region and the high concentration ion implantation region. It is because it is doing.

  (3) As a countermeasure against the problem caused in the item (2), as described above, it is effective not to interpose the access resistance by performing ion implantation by the self-alignment method using the gate electrode as a mask. However, since the ion activation heat treatment of the nitride-based material is at a high temperature of 1000 ° C. or higher, there is no gate electrode having a heat resistance enough to withstand the heat treatment of 1000 ° C. or higher without deterioration of device characteristics. .

  (4) In a device having a gate length of sub-μm that realizes high-frequency operation, the influence of parasitic resistance is particularly significant.

  The present invention has been made to solve the above-described problems, and the problems to be solved by the present invention are that the source resistance is greatly reduced and the problem of heat resistance of the gate electrode material is overcome. A field effect transistor and a manufacturing method thereof are provided.

  In order to solve the above-described problems, the present invention has a structure of a field effect transistor manufactured by using the following two methods together.

  (1) By ion implantation, a high-concentration ion implantation region (first high-concentration carrier region) is formed in either or both of the source region for forming the source electrode and the drain region for forming the drain electrode. Forming and reducing contact resistance.

  (2) Further, the gate electrode material is formed adjacent to and / or partially overlapping with a high concentration ion implantation region formed in one or both of the source region and the drain region by a thermal diffusion method. By forming a thermal diffusion region (second high-concentration carrier region) as a mask in a self-aligned manner, a high-concentration ion implantation region (first high-concentration carrier region) and a channel region directly below the gate electrode are formed. The access region between the source electrode, the drain electrode, and the channel region immediately below the gate electrode includes a high-concentration ion implantation region (first high-concentration carrier region) and a thermal diffusion region (second high-concentration region). As a result, the access resistance is drastically reduced.

  (3) Here, since the thermal diffusion method can perform heat treatment at a temperature lower than that of the ion implantation method, for example, tungsten, tungsten alloy, molybdenum, molybdenum alloy, etc. that have a proven record as an arsenic phosphorus compound semiconductor device The heat-resistant gate electrode material can be used to form the gate electrode.

  More specifically, the present invention comprises the following technical means.

A first technical means is a field effect transistor configured using a nitride-based semiconductor, and includes a source region and a drain in which contacts are made with a source electrode and a drain electrode arranged with a gate electrode interposed therebetween. A first high-concentration carrier region, which is an ion implantation region formed by ion activation after high-concentration ion implantation in one or both of the regions, and the gate electrode A field effect transistor comprising a second high concentration carrier region which is a thermal diffusion region in which carriers are diffused by heat treatment in a region between a channel region formed immediately below and the first high concentration carrier region. The one high concentration carrier region and the second high concentration carrier region are adjacent to each other and / or partially overlap each other, and The first high-concentration carrier region is formed deeper than the second high-concentration carrier region, the second high-concentration carrier region and the channel region are adjacent to each other, and the second high-concentration carrier region The high concentration carrier region is formed deeper than the channel region , and the gate electrode is after the ion activation of the first high concentration carrier region and before the formation of the second high concentration carrier region. It is characterized by being formed .

  According to a second technical means, in the field effect transistor according to the first technical means, the carrier concentration of the first high-concentration carrier region is higher than that of the second high-concentration carrier region, The carrier concentration of the second high concentration carrier region is higher than that of the channel region.

  According to a third technical means, in the field effect transistor according to the first or second technical means, the second high-concentration carrier region is formed in a self-aligned manner using the gate electrode. Features.

  According to a fourth technical means, in the field effect transistor according to any one of the first to third technical means, a first nitride-based semiconductor layer in which a channel is formed and a second nitride for supplying electrons. And the channel region is formed in the vicinity of a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

  According to a fifth technical means, in the field effect transistor according to any one of the first to fourth technical means, a recess region is formed in a region where the gate electrode is formed, and the gate electrode is formed in the recess region. It is characterized by being.

  Sixth technical means is the field effect transistor according to any one of the first to fifth technical means, wherein the material of the gate electrode is any one of tungsten, tungsten alloy, molybdenum, molybdenum alloy, or It consists of a combination of a plurality of materials.

  According to a seventh technical means, in the field effect transistor according to any one of the first to sixth technical means, the carrier to be thermally diffused to form the second high-concentration carrier region is silicon or tin. It is either of these.

  An eighth technical means is a field effect transistor manufacturing method for manufacturing a field effect transistor configured using a nitride semiconductor, and includes a first step of forming a first nitride semiconductor layer on a substrate. And a second step of forming a channel region by forming an electron supply layer made of a second nitride semiconductor on the first nitride semiconductor layer formed in the first step. Of the first nitride-based semiconductor layer and the electron supply layer formed in the first and second steps, any one of a source region and a drain region for forming a source electrode and a drain electrode, respectively Alternatively, in the third step, ions of a substance serving as a dopant are implanted into both regions to form the ion-implanted region as a first high-concentration carrier region, and the third step. A fourth step of performing an ion activation heat treatment for activating the ions implanted in the formed first high concentration carrier region; and after the fourth step, a gate electrode is formed on the electron supply layer. The carrier is thermally diffused in a self-aligned manner with respect to the fifth step to be formed and the gate electrode formed in the fifth step, so that the first high concentration carrier region is adjacent and / or the same. And at least a sixth step of forming a thermal diffusion region adjacent to the channel region directly below the gate electrode as a second high-concentration carrier region.

  According to a ninth technical means, in the field effect transistor manufacturing method according to the eighth technical means, as the sixth step, the carrier concentration of the second high-concentration carrier region is changed to the first high-concentration carrier. It is characterized by being formed lower than the region and higher than the channel region.

  A tenth technical means is the field effect transistor manufacturing method according to the eighth or ninth technical means, wherein the tenth technical means is formed in the fifth process between the fifth process and the sixth process. A method of manufacturing a field effect transistor, comprising a step of forming a sidewall on a side portion of the gate electrode.

  An eleventh technical means is the field effect transistor manufacturing method according to any one of the eighth to tenth technical means, wherein the gate electrode is formed between the fourth step and the fifth step. And a step of forming a recess region in the region to be processed.

  A twelfth technical means is the field effect transistor manufacturing method according to any of the eighth to eleventh technical means, wherein the first high-concentration carrier region formed in the third step is the first The second high-concentration carrier region is formed deeper than the second high-concentration carrier region formed in step 6, and the second high-concentration carrier region is formed deeper than the channel region formed in the second step. It is characterized by.

  A thirteenth technical means is the field effect transistor manufacturing method according to any one of the eighth to twelfth technical means, wherein the material of the gate electrode is any one of tungsten, tungsten alloy, molybdenum, and molybdenum alloy. It consists of a material or a combination of a plurality of materials.

  Fourteenth technical means is the field effect transistor manufacturing method according to any one of the seventh to thirteenth technical means, wherein the carrier thermally diffused to form the second high-concentration carrier region is silicon. Or tin.

  According to the field effect transistor and the field effect transistor manufacturing method of the present invention, the following effects can be obtained.

  (1) Adjacent to and / or adjacent to a high-concentration ion-implanted region (first high-concentration carrier region) formed in one or both of the source region for forming the source electrode and the drain region for forming the drain electrode. A thermal diffusion region (second high-concentration carrier region) obtained by a thermal diffusion method in a partially overlapping state and adjacent to the channel region immediately below the gate electrode in a self-aligned manner with respect to the gate electrode material Therefore, even a field effect transistor having a sub-μm class fine gate length can achieve high transconductance.

  (2) A thermal diffusion region that is a high-concentration carrier region in a self-aligned manner with respect to the gate electrode material by using a thermal diffusion method that can be processed at a temperature lower than the temperature required for the activation heat treatment for ion implantation. Since the (second high-concentration carrier region) is formed, the selection range of the heat-resistant material used as the gate electrode can be widened.

  (3) In the ion implantation method, the source resistance and drain resistance can be greatly reduced by making the temperature and time of the implantation ion activation heat treatment appropriate, rather than the carrier dose by the thermal diffusion method. Therefore, by using both the ion implantation method and the thermal diffusion method, it is possible to simultaneously achieve a significant reduction in source resistance and drain resistance by the ion implantation method and formation of a self-aligned gate by the thermal diffusion method.

  Therefore, the field effect transistor according to the present invention enables a nitride field effect transistor having a sub-μm class fine gate length, a high-speed digital integrated circuit composed of the nitride field effect transistor, and a high output, high-speed integration. A circuit or the like can be easily realized.

It is sectional drawing which shows the cross-section of 1st Embodiment of the field effect transistor which concerns on this invention. It is sectional drawing which shows the cross-section of 2nd Embodiment of the field effect transistor which concerns on this invention. It is explanatory drawing which shows an example of the manufacturing method which manufactures the field effect transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing method which manufactures the field effect transistor shown in FIG. It is sectional drawing which shows an example of the cross-sectional structure of the conventional nitride field effect transistor. It is sectional drawing which shows the example different from FIG. 5 of the cross-sectional structure of the conventional nitride field effect transistor.

  Hereinafter, an example of the best embodiment of a field effect transistor and a method for producing a field effect transistor according to the present invention will be described in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention makes it possible to improve the characteristics of a field effect transistor (FET) composed of a nitride compound semiconductor, in particular, mutual conductance.

  In general, nitride compound semiconductors are difficult to form low-resistance ohmic contacts as compared to other compound semiconductors, and have low electrode resistance (contact resistance and access resistance). It is difficult to realize a field effect transistor having a mutual conductance that is closer to the intrinsic mutual conductance that it originally has.

  In order to solve such a problem, the present invention forms a first high-concentration carrier region directly under and around one or both of the source electrode and drain electrode before electrode formation, A field effect transistor having a structure in which a second high concentration carrier region is formed adjacent to and / or partially overlapping with one high concentration carrier region and in the region up to the vicinity of the gate electrode is realized.

  That is, according to the present invention, ion activation after ion implantation is used to form a high concentration carrier region (second high concentration carrier region) in the vicinity of the gate by a self-alignment process (self-alignment process) using a gate electrode material. Uses a thermal diffusion method that can be processed at a temperature lower than the temperature required for heat treatment, and high-concentration carriers to the source electrode, drain electrode, or both of the electrodes before and around the electrodes before electrode formation For the formation of the region (first high-concentration carrier region), an ion implantation method capable of forming a high-concentration doped region having a concentration obtained by a thermal diffusion method and a doping depth or higher is used.

  Thus, by combining these two doping methods, from the source electrode and the drain electrode, a high concentration ion implantation region (first high concentration carrier region), a thermal diffusion region (second high concentration carrier region). A field effect transistor with a structure in which a high-concentration carrier region is formed up to the channel region (region formed near the heterojunction interface between the electron supply layer and the channel layer) directly under the gate electrode where the transistor actually operates doing.

  As a result, the field effect transistor according to the present invention can reduce the resistance from the source electrode or drain electrode to the channel region immediately below the gate electrode without deteriorating the gate electrode by heat treatment. Compared with a field effect transistor using a ride compound semiconductor, a field effect transistor having a mutual conductance closer to the intrinsic mutual conductance inherent in the nitride compound semiconductor can be realized.

(First embodiment)
First, an example of a field effect transistor according to the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a cross-sectional structure of a first embodiment of a field effect transistor according to the present invention.

  As shown in FIG. 1, on a substrate 1 made of sapphire, SiC, Si or the like, a channel layer 2 made of, for example, undoped GaN or the like is laminated as a first nitride semiconductor layer in which a channel is formed. 2, an electron supply layer 5 made of, for example, AlGaN, InGaN, or InAlN, which is a second nitride semiconductor layer that supplies electrons, is stacked, and the electron supply layer 5 and the channel layer 2 form a heterojunction. ing. In FIG. 1, a channel region 4 made of a two-dimensional electron gas (2DEG) is formed on the channel layer 2 side immediately below the heterojunction interface.

  Further, for example, Si (silicon) or Sn (tin) ion implantation and subsequent heat treatment (ion activation) are performed in regions where the source electrode 8 and the drain electrode 10 are formed on both sides of the gate electrode 9. The source region 3 and the drain region 6 with increased carrier concentration are formed as the first high-concentration carrier region.

  As a result, the carrier concentration of the source region 3 (in the case of FIG. 1, the carrier concentration of the drain region 6) is higher than the carrier concentration of the channel region 4 by an increase due to ion implantation and subsequent ion activation heat treatment. In addition, the source region 3 and the drain region 6 are formed deeper than the heterojunction interface between the electron supply layer 5 and the channel layer 2 as shown in FIG.

  Furthermore, a gate electrode 9 made of, for example, W (tungsten), W alloy, Mo (molybdenum), or Mo alloy is formed on the electron supply layer 5. Here, as shown in FIG. 1, the channel region 4 is formed in the vicinity of the heterojunction interface immediately below the gate electrode 9.

  Further, a thermal diffusion region 7 in which, for example, Si or Sn impurities (carriers) are thermally diffused with respect to the electrode material of the gate electrode 9 is formed as the second high-concentration carrier region. The carrier concentration in the thermal diffusion region 7 is higher than the carrier concentration in the channel region 4 by an increase due to impurity diffusion and subsequent heat treatment. The thermal diffusion region 7 is adjacent to and / or partially overlaps with the source region 3 (including the drain region 6 in the case of FIG. 1) formed as the first high-concentration carrier region, and directly below the gate electrode 9. It is formed so as to be adjacent to the formed channel region 4 and serves to reduce the access resistance existing from the source region 3 (including the drain region 6 in the case of FIG. 1) to the channel region 4. Plays.

  As shown in FIG. 1, the thermal diffusion region 7 is also formed deeper than the heterojunction interface between the electron supply layer 5 and the channel layer 2, but is formed by ion implantation as the first high-concentration carrier region. It is formed shallower than the source region 3 (including the drain region 6 in the case of FIG. 1). That is, the thermal diffusion region 7 that forms the second high-concentration carrier region is formed deeper than the channel region 4 formed immediately below the gate electrode 9, but the source region 3 ( In the case of FIG. 1, it is formed so as to remain in a shallower range (including the drain region 6).

  Further, a source electrode 8 and a drain electrode 10 which are ohmic electrodes are formed on the source region 3 and the drain region 6, respectively, and the source region 3 is formed in the nitride semiconductor together with the above-described components. A field effect transistor having a channel region 4, a thermal diffusion region 7, and a drain region 6 is formed.

  In FIG. 1, ion implantation is performed as a first high-concentration carrier region in both the source region 3 where the contact with the source electrode 8 is formed and the drain region 6 where the contact with the drain electrode 10 is formed. Although the ion implantation region is formed, the ion implantation region in which the ion implantation is performed as the first high-concentration carrier region only in one of the source region 3 and the drain region 6 may be formed. .

  In the above example, Si or Sn is used as ions implanted into the source region 3 (including the drain region 6 in the case of FIG. 1). However, any other ion species that can reduce the source resistance and the drain resistance by implanting ions into the source region 3 and the drain region 6 and performing an ion activation heat treatment will be used. Any ion species may be used for ion implantation.

  The material of the gate electrode 9 has heat resistance equal to or higher than the thermal diffusion processing temperature (about 800 ° C.), for example, any one material or a plurality of materials of W, W alloy, Mo, or Mo alloy. A combination is used. However, any other material that can withstand a thermal diffusion processing temperature (about 800 ° C.) and has a Schottky barrier height of 0.5 eV or more at the interface between the electron supply layer 5 and the gate electrode 9 can be used. Any material may be used for the electrode 9.

  Further, for example, the thickness of the electron supply layer 5 is 10 nm to 60 nm, and the thickness of the source region 3 (including the thickness of the drain region 6 in FIG. 1) is 40 nm to 200 nm. The source region 3 is formed thicker than the electron supply layer 5 (including the drain region 6 in the case of FIG. 1). The thickness of the thermal diffusion region 7 is also made thicker than that of the electron supply layer 5.

For example, the sheet carrier concentration of the channel region 4 is 1 × 10 ¹⁰ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . The carrier concentration of the thermal diffusion region 7 is ^{1 × 10 16 cm -3 ~1 ×} 10 21 cm -3. The carrier concentration of the source region 3 formed by ion implantation (including the carrier concentration of the drain region 6 in the case of FIG. 1) is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²² cm ⁻³ . The carrier concentration of the source region 3 that is the first high concentration carrier region (ion implantation region) (including the carrier concentration of the drain region 6 in FIG. 1) is the thermal diffusion that is the second high concentration carrier region. It is formed so as to be higher than the carrier concentration in region 7.

Further, the carrier concentration of the source region 3 (including the carrier concentration of the drain region 6 in the case of FIG. 1) and the carrier concentration of the thermal diffusion region 7 are formed higher than the carrier concentration of the channel region 4. For example, when the carrier concentration of the channel region 4 is set to a concentration at which the gate threshold voltage is shallower than −1 V (1 × 10 ¹² cm ⁻³ or less), the carrier concentration of the source region 3 is (in the case of FIG. 1, It may be 5 × 10 ¹⁸ cm ⁻³ or more (including the carrier concentration of the drain region 6).

  The substrate structure of FIG. 1 may be as follows. A channel layer 2 made of, for example, undoped GaN, which is a nitride-based semiconductor layer, is stacked on the substrate 1, and an electron supply layer, made of, for example, AlGaN, InGaN, InAlN, or the like, which is a nitride-based semiconductor layer, is formed on the channel layer 2. 5 are stacked. The electron supply layer 5 is doped with Si or Sn to form a high concentration carrier region in the electron supply layer 5. In such a substrate structure, it becomes possible to supply a carrier having a higher density than a carrier by a two-dimensional electron gas formed on the heterojunction interface, for example, on the side of the electron supply layer 5 made of AlGaN.

  Alternatively, the substrate structure of FIG. 1 may be as follows. A buffer layer made of, for example, undoped GaN, which is a nitride-based semiconductor layer, is stacked on the substrate 1, and a channel layer having a high concentration carrier such as, for example, GaN doped with Si or Sn is formed on the buffer layer. It is formed. On the channel layer, an electron supply layer 5 made of, for example, AlGaN, InGaN, or InAlN, which is a nitride semiconductor layer, is stacked. In such a substrate structure, it becomes possible to supply a carrier having a higher density than a carrier by a two-dimensional electron gas formed on the heterojunction interface, for example, on the side of the electron supply layer 5 made of AlGaN.

  Even if the substrate material or the substrate structure is not described above, it is possible to apply the technology as described above if the reduction of the source resistance and the drain resistance is directly linked to the improvement of the device performance. it is obvious.

  In the field effect transistor having the device structure as described above, one or both of the source region 3 where the contact with the source electrode 8 is formed and the drain region 6 where the contact with the drain electrode 10 is formed. The gate electrode 9 is adjacent to and / or partially overlaps with the high-concentration ion implantation region (first high-concentration carrier region) formed on the gate electrode 9 and adjacent to the channel region 4 immediately below the gate electrode 9. Therefore, a field diffusion transistor having a sub-μm class fine gate length can be formed in a self-aligned manner with respect to the above material by a thermal diffusion region (second high concentration carrier region) by a thermal diffusion method. Also, high transconductance can be realized.

(Second Embodiment)
Next, another example of the field effect transistor according to the present invention will be described with reference to FIG.

  FIG. 2 is a sectional view showing a sectional structure of a second embodiment of the field effect transistor according to the present invention. The basic structure of the field effect transistor shown in FIG. 2 is the same as that of the field effect transistor shown in FIG. 1 as the first embodiment, but in the second embodiment, the region where the gate electrode 9 is formed. The gate electrode 9 is formed after the electron supply layer 5 is sufficiently thinned by recess etching, and the thermal diffusion region 7 is formed in a self-aligning manner using the gate electrode 9. This is different from the case of FIG.

  That is, when the electron supply layer 5 is thicker than the thermal diffusion region 7, by adding a step of recess etching, the electron supply layer 5 in the region for forming the gate electrode 9 is made sufficiently thin, and then The gate electrode 9 is formed, and a thermal diffusion region 7 (second high-concentration carrier region) is formed by thermal diffusion processing by a self-alignment process using the gate electrode material. By adopting such a device structure, the channel region 4 (the electron supply layer 5 and the channel layer 2 of the electron supply layer 5 and the channel layer 2) from the source electrode 8 (including the drain region 6 in the case of FIG. 2) to the gate electrode 9 actually operating as a transistor. As in the case of FIG. 1, it is possible to form a structure in which a high-concentration carrier region is continuously present, and the access resistance due to the formation of the thermal diffusion region 7 is reduced to the region formed near the heterojunction interface). Sufficient reduction can be achieved.

(Third embodiment)
Next, as a third embodiment, an example of a field effect transistor manufacturing method according to the present invention will be described with reference to FIG. FIG. 3 is an explanatory view showing an example of the manufacturing method for manufacturing the field effect transistor shown in FIG. 1 as an example of the method of manufacturing the field effect transistor according to the present invention.

  First, as shown in FIG. 3A, as a first step, for example, undoped GaN, which is a first nitride-based semiconductor, is epitaxially grown on a substrate 1 such as a sapphire substrate, a SiC substrate, or a Si substrate. By doing so, the first nitride-based semiconductor layer, that is, the channel layer 2 is formed. Thereafter, as a second step, the second nitride semiconductor, for example, undoped AlGaN, InGaN, or InAlN, is epitaxially grown on the first nitride semiconductor layer, that is, the channel layer 2. The nitride semiconductor layer, that is, the electron supply layer 5 is formed. As a result, a channel region 4 made of a two-dimensional electron gas is formed on the channel layer 2 side of the heterojunction interface between the channel layer 2 and the electron supply layer 5.

  Next, as shown in FIG. 3B, an ion implantation process is performed on the second nitride semiconductor layer, ie, the electron supply layer 5, on the outermost surface by using a photoresist, SiO2, SiN, W, WSiN, Ni, or the like. A mask pattern to be used sometimes, that is, an ion implantation mask 12 is formed.

  Subsequently, as a third step, as an ion implantation (ion implantation for source region and / or drain region) step, a portion to be the source region 3 (in the case of FIG. 3B, the drain region 6 is formed). The ion implantation of a substance (for example, Si (silicon) or Sn (tin)) that becomes an n-type dopant (impurity) is performed. After the ion implantation, the previously formed mask pattern, that is, the ion implantation mask 12 is removed.

  Further, as the fourth step, the semiconductor substrate on which the second nitride semiconductor layer on the outermost surface, that is, the electron supply layer 5 and the source region 3 (including the drain region 6 in the case of FIG. 3B) is formed. A protective film for high-temperature heat treatment such as SiO 2, SiN, or WSiN is formed thereon, and then the semiconductor substrate is subjected to heat treatment (ion activation heat treatment) at a temperature of 1000 ° C. or higher to form the source region 3 (FIG. 3 ( In the case of b), the ions implanted into the drain region 6) are activated, and the carrier concentration in the ion implanted portion is increased to form the first high concentration carrier region.

In the ion implantation step into the source region 3 in FIG. 3B (including the drain region 6 in the case of FIG. 3B), for example, the acceleration voltage is 30 to 200 kV and the dose is 1 × 10. ¹³ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . As a result, the carrier concentration of the source region 3 (including the drain region 6 in the case of FIG. 3B) is higher than the carrier concentration of the channel region 4 by an increase due to ion implantation and subsequent ion activation heat treatment. Become. At the end of the fourth step, the high temperature heat treatment protective film is removed.

  Next, as shown in FIG. 3C, as a fifth step, for example, W, WN, WAl, WSi, or WSiN is deposited on the gate electrode formation region of the semiconductor substrate by sputtering, and the gate is formed by dry etching. Electrode 9 is formed.

  Subsequently, sidewalls 11 made of, for example, SiO 2 or SiN are formed on the gate electrode 9. The sidewall 11 is formed by performing surface etching after forming SiO 2 or SiN, for example, over the entire surface of the semiconductor substrate. In the sidewall 11, Si or Sn diffuses into the channel region 4 immediately below the gate electrode 9 during a heat treatment for diffusion of Si or Sn in a later step, and the source electrode and the drain electrode are short-circuited. It plays a role to prevent that.

  Next, as shown in FIG. 3D, as a sixth step, a thin film using, for example, Si or Sn as the diffusion material 13 is formed on the entire outermost surface of the semiconductor substrate, and the temperature is 800 ° C. or higher. The channel region 4 is diffused to a region deeper than the channel region 4 in the semiconductor substrate and shallower than the source region 3 (including the drain region 6 in the case of FIG. 3D). In the removed region, the thermal diffusion region 7 is formed as a second high-concentration carrier region in a self-aligned manner with respect to the gate electrode 9.

  The thermal diffusion region 7 is formed adjacent to and / or partially overlaps with the source region 3 (including the drain region 6 in the case of FIG. 3D) and adjacent to the channel region 4 immediately below the gate electrode 9. Thus, it plays a role of reducing the access resistance existing from the source region 3 (including the drain region 6 in the case of FIG. 3D) to the channel region 4.

  Here, since the side wall 11 exists on the side portion of the gate electrode 9, it is possible to prevent impurities (carriers) from diffusing up to the channel region 4 immediately below the gate electrode 9 during diffusion by heat treatment. After the heat treatment diffusion, the thin film formed using, for example, Si or Sn as the diffusion material 13 is removed.

  The carrier concentration of the thermal diffusion region 7 is higher than the carrier concentration of the channel region 4, and the source region 3 formed as the first high concentration carrier region (including the drain region 6 in the case of FIG. 3D). It is formed to be lower than the carrier concentration.

  Finally, as shown in FIG. 3E, if the source electrode 8 is formed on the source region 3 and the drain electrode 10 is formed on the drain region 6, the field effect according to the present invention shown in FIG. A transistor is completed.

  The source electrode 8 and the drain electrode 10 are formed as ohmic electrodes by forming a Ti / Al or Al / Ti / Al electrode by vapor deposition and lift-off and then heat-treating them at a temperature of 600 ° C. or higher to form an alloy. Just do it. However, the ohmic electrode is formed using any material as long as it is a combination of materials in which the contact resistance with the source region 3 and the drain region 6 is about 10 Ωmm or less by heat treatment at about 600 ° C. It doesn't matter.

  In the above example, photoresist, SiO2, SiN, W, WSiN, or Ni is used as the mask pattern during ion implantation, that is, the ion implantation mask 12. However, the ion implantation mask 12 is removed to the extent that it functions as a mask for preventing the ion beam from reaching the surface of the semiconductor substrate and does not seriously affect the surface of the semiconductor substrate after ion implantation. Any material that can be used may be used as a mask pattern at the time of ion implantation.

  In the above-described example, SiO2, SiN, WSiN, or the like is used for the high-temperature heat treatment protective film used for the heat treatment for activating the implanted ions. However, any material can be used as the protective film for high-temperature heat treatment as long as it is a material that can withstand heat treatment at 1000 ° C. or more and has a function of protecting the semiconductor substrate from heat treatment.

  In the above example, W, WN, WAl, WSi, WSiN or the like is used as the material of the gate electrode 9, but Mo or Mo alloy may be used, or these materials may be used in combination. good. However, any other material that can withstand a thermal diffusion processing temperature (a temperature of 800 ° C. or higher) and that has a Schottky barrier height at the interface between the electron supply layer 5 and the gate electrode 9 of 0.5 eV or higher. Any material may be used as the material of the gate electrode 9.

  When Mo or Mo alloy is used as the material of the gate electrode 9, as described above, instead of forming the gate electrode 9 by dry etching after depositing the gate electrode material of Mo or Mo alloy by sputtering, vapor deposition is performed. Alternatively, the gate electrode 9 may be formed by lift-off.

  In the above example, SiO 2 or SiN is used as the material of the sidewall 11 formed on the side portion of the gate electrode 9. However, other than this, during the heat treatment for forming the thermal diffusion region 7, Si or Sn is diffused into the channel region 4 immediately below the gate electrode 9 to prevent a short circuit between the source electrode and the drain electrode. Any material can be used as the material of the sidewall 11 as long as it can play a role.

  Note that when the influence of thermal diffusion directly under the gate electrode 9 is not serious, that is, Si or Sn diffuses into the channel region 4 and a short circuit occurs between the source electrode and the drain electrode. If not, the step of forming the sidewall 11 can be omitted.

  Further, in the third and fourth steps in FIG. 3B, both the source region 3 in which the contact with the source electrode 8 is formed and the drain region 6 in which the contact with the drain electrode 10 is formed Although the ion implantation region is formed as the first high concentration carrier region, the ion implantation is performed as the first high concentration carrier region only in one of the source region 3 and the drain region 6. An ion implantation region may be formed.

  In the field effect transistor manufacturing method as described above, the material of the gate electrode 9 is self-aligned by using a thermal diffusion method that can be processed at a temperature lower than the temperature required for the ion implantation activation heat treatment. In particular, since the thermal diffusion region 7 (second high concentration carrier region) which is a high concentration carrier region is formed, the range of selection of the heat resistant material used as the gate electrode 9 can be widened.

  In the ion implantation method, the source resistance and the drain resistance can be greatly reduced as compared with the carrier dose by the thermal diffusion method by making the temperature and time of the implantation ion activation heat treatment appropriate. Therefore, by using both the ion implantation method and the thermal diffusion method, it is possible to simultaneously achieve a significant reduction in source resistance and drain resistance by the ion implantation method and formation of a self-aligned gate by the thermal diffusion method.

(Fourth embodiment)
Next, as a fourth embodiment, another example of the field effect transistor manufacturing method according to the present invention will be described with reference to FIG. FIG. 4 is an explanatory view showing an example of a manufacturing method for manufacturing the field effect transistor shown in FIG. 2 as another example of the method for manufacturing the field effect transistor according to the present invention.

  The basic steps of the method of manufacturing the field effect transistor shown in FIG. 4 are the same as those of the method of manufacturing the field effect transistor shown in FIG. 3, but as shown in FIG. In the embodiment, the step of making the electron supply layer 5 sufficiently thin by recess etching the electron supply layer 5 in the region where the gate electrode 9 is to be formed to form the recess region 14 has been described with reference to FIG. Further added to the manufacturing method.

  That is, in the step shown in FIG. 4C, the electron supply layer 5 is dry-etched to form the recess region 14. In this way, by forming the recess region 14, even if the electron supply layer 5 is thicker than the thermal diffusion region 7, the source region 3 (including the drain region 6 in the case of FIG. 4) to the channel region 4. Can be connected in a low resistance region.

  The step of forming the recess region 14 in FIG. 4C is after the ion implantation / activation heat treatment in the third and fourth steps described in FIG. 3 and before the formation of the gate electrode 9 in the fifth step. In addition, after the electron supply layer 5 is sufficiently thinned by the step of forming the recess region 14, the gate electrode 9 is formed in the same manner as in the manufacturing method shown in FIG. 3, and the channel immediately below the formed gate electrode 9 is formed. The thermal diffusion region 7 is formed as a second high-concentration carrier region in a region other than the region 4 in a self-aligned manner with respect to the formed gate electrode 9.

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Channel layer (nitride semiconductor layer), 2A ... Buffer layer, 3 ... Source region, 3A ... Two-dimensional electron gas, 4 ... Channel region, 4A ... High concentration ion implantation region, 5 ... Electron supply Layer 6, drain region 6 A electrode formation region 7 heat diffusion region 7 A surface protective film 8 source electrode 8 A photoresist mask 9 gate electrode 10 drain electrode 11 sidewall .

Claims (14)

A field-effect transistor configured using a nitride-based semiconductor, and one of a source region and a drain region in which a contact with each of a source electrode and a drain electrode arranged with a gate electrode interposed therebetween is formed Or a first high concentration carrier region which is an ion implantation region formed by ion activation after performing high concentration ion implantation in both regions, and a channel region formed immediately below the gate electrode; In a field effect transistor comprising a second high-concentration carrier region that is a thermal diffusion region in which carriers are diffused by heat treatment in a region between the first high-concentration carrier region,
The first high concentration carrier region and the second high concentration carrier region are adjacent to each other and / or partially overlap each other, and the first high concentration carrier region is more than the second high concentration carrier region. Is also deeply formed,
The second high concentration carrier region and the channel region are adjacent to each other, and the second high concentration carrier region is formed deeper than the channel region ,
The field effect transistor , wherein the gate electrode is formed after the ion activation of the first high concentration carrier region and before the formation of the second high concentration carrier region. .   2. The field effect transistor according to claim 1, wherein a carrier concentration of the first high concentration carrier region is higher than that of the second high concentration carrier region, and a carrier concentration of the second high concentration carrier region is set. Is a field effect transistor having a higher concentration than the channel region.   3. The field effect transistor according to claim 1, wherein the second high-concentration carrier region is formed in a self-aligned manner using the gate electrode.   4. The field effect transistor according to claim 1, comprising at least a first nitride semiconductor layer in which a channel is formed and a second nitride semiconductor layer for supplying electrons, and the channel region. Is formed in the vicinity of a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.   5. The field effect transistor according to claim 1, wherein a recess region is formed in a region where the gate electrode is formed, and the gate electrode is formed in the recess region. .   6. The field effect transistor according to claim 1, wherein the material of the gate electrode is made of any one material of tungsten, tungsten alloy, molybdenum, molybdenum alloy or a combination of a plurality of materials. A characteristic field effect transistor.   7. The field effect transistor according to claim 1, wherein the carrier thermally diffused to form the second high concentration carrier region is one of silicon and tin. Effect transistor. A field effect transistor manufacturing method for manufacturing a field effect transistor configured using a nitride semiconductor,
A first step of forming a first nitride semiconductor layer on a substrate;
A second step of forming a channel region by forming an electron supply layer made of a second nitride semiconductor on the first nitride semiconductor layer formed in the first step;
Of the first nitride-based semiconductor layer and the electron supply layer formed in the first and second steps, either a source region or a drain region for forming a source electrode and a drain electrode, respectively, or A third step of implanting ions of a substance serving as a dopant in both regions to form the ion implantation region as a first high-concentration carrier region;
A fourth step of performing an ion activation heat treatment for activating the ions implanted in the first high-concentration carrier region formed in the third step;
A fifth step of forming a gate electrode on the electron supply layer after the fourth step;
Carriers are thermally diffused in a self-aligned manner with respect to the gate electrode formed in the fifth step so as to be adjacent to and / or partially overlap with the first high-concentration carrier region, and the gate electrode And a sixth step of forming a thermal diffusion region adjacent to the channel region directly below as a second high-concentration carrier region.   9. The field effect transistor manufacturing method according to claim 8, wherein, as the sixth step, a carrier concentration of the second high-concentration carrier region is lower than that of the first high-concentration carrier region and is lower than that of the channel region. A method of manufacturing a field effect transistor, characterized by being formed high.   10. The field effect transistor manufacturing method according to claim 8, wherein a sidewall is formed on a side portion of the gate electrode formed in the fifth step between the fifth step and the sixth step. 11. A method of manufacturing a field effect transistor, comprising the step of forming.   11. The field effect transistor manufacturing method according to claim 8, further comprising a step of forming a recess region in a region where the gate electrode is formed between the fourth step and the fifth step. A field effect transistor manufacturing method characterized by the above.   12. The field effect transistor manufacturing method according to claim 8, wherein the first high-concentration carrier region formed in the third step is formed in the second step. A field effect transistor manufacturing method, wherein the field effect transistor is formed deeper than a high concentration carrier region, and the second high concentration carrier region is formed deeper than the channel region formed in the second step.   13. The field effect transistor manufacturing method according to claim 8, wherein the material of the gate electrode is made of any one material of tungsten, tungsten alloy, molybdenum, molybdenum alloy or a combination of a plurality of materials. A method of manufacturing a field effect transistor.   14. The field effect transistor manufacturing method according to claim 8, wherein the carrier to be thermally diffused to form the second high-concentration carrier region is either silicon or tin. A field effect transistor manufacturing method.

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