JP5428142B2 - Manufacturing method of display panel - Google Patents

Description

  The present invention relates to a display panel and a manufacturing method thereof, and more particularly to a display panel including a display pixel having a light emitting element such as an organic electroluminescence element, and a manufacturing method of the display panel.

  2. Description of the Related Art In recent years, as a next-generation display device following a liquid crystal display (LCD), self-luminous elements such as organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) and light-emitting diodes (LEDs) are two-dimensionally arranged. Research and development for full-scale practical application and popularization of display devices equipped with such light-emitting element type display panels have been actively conducted.

  Such a light emitting element type display device has excellent display characteristics such as a faster display response speed and less viewing angle dependency than a liquid crystal display device. It has the characteristic on the apparatus structure that a light and a light guide plate are not required. Therefore, application to various electronic devices is expected in the future.

  In such a display device, a pixel circuit (pixel drive circuit) for causing a light emitting element (organic EL element or the like) to emit light with a desired luminance gradation for each display pixel arranged in the display panel. There is known an active matrix driving system provided with the. Here, as a pixel circuit, as described in, for example, Patent Document 1, a pixel circuit including a circuit element (switching element) such as a thin film transistor and a wiring layer is known.

  In addition, in a display panel in which light emitting elements constituting each display pixel are formed on one surface side of the light emitting element substrate, top emission type light emission that emits light from above the light emitting element substrate according to the device structure of the light emitting element. A structure and a bottom emission type light emitting structure that emits light from a lower side of a light emitting element substrate are known. That is, as described in Patent Document 1, for example, in a top emission type light emitting structure, light emitted from a light emitting element provided on the light emitting element substrate is emitted upward without passing through the light emitting element substrate. On the other hand, the bottom emission type light emitting structure has a light emitting structure in which light emitted from the light emitting element is transmitted through the substrate and emitted downward.

  As a display panel having such an active top emission type light emitting structure, for example, as described in Patent Document 1, a planarization film is formed on a substrate on which each circuit element (transistor or the like) of a pixel circuit is formed. A panel structure in which a light emitting element (organic EL element) is formed is provided. Here, the planarizing film is provided with a contact hole for electrically connecting a pixel circuit (transistor or the like) and a light emitting element (pixel electrode).

JP, 2005-222759, A (3rd page, 8th page-9th page, FIG. 3, FIG. 4)

The display panel having the panel structure as described above has the following problems.
That is, in the planarization film provided between the pixel circuit and the light emitting element, the step generated on the substrate surface is reduced by forming each circuit element or wiring layer of the pixel circuit, and the light emitting element (pixel electrode). For forming a highly flat (smooth) surface suitable for forming a pixel, and for electrically connecting a pixel circuit (transistor, etc.) and a light emitting element (pixel electrode). When forming the contact hole, it is required that the influence (for example, peeling or deterioration) on the electrode layer or the wiring layer of the pixel circuit is small.

Accordingly, in view of the above-described problems, the present invention achieves a display excellent in display characteristics and reliability by achieving both improvement in flatness of a flattening film and good formation of a contact hole in the flattening film. It aims at providing the manufacturing method of a panel.

According to a first aspect of the present invention, there is provided a method for manufacturing a display panel, comprising: forming a conductive barrier layer in a predetermined region on an electrode layer of a functional element provided on a substrate; and covering the barrier layer. Forming a planarizing film on the substrate, forming an opening exposing the barrier layer on the planarizing film using an etching mask, and removing the etching mask using a predetermined mask stripper; Forming a pixel electrode connected to the electrode layer through the barrier layer in the opening and extending from the opening onto the planarizing film, and the etching mask includes the electrode The barrier layer is formed of a conductive material that is resistant to an etchant used for patterning the electrode layer. Characterized in that it is.
According to a second aspect of the present invention, there is provided a display panel manufacturing method comprising: forming a conductive barrier layer in a predetermined region on a terminal of a wiring provided on a substrate; and flattening the barrier layer so as to cover the barrier layer. Forming an opening for exposing the barrier layer to the planarizing film using an etching mask, removing the etching mask using a predetermined mask remover, and then opening the opening. Forming a terminal pad layer connected to the terminal through the barrier layer and extending from the opening on the planarization film in a portion, and the etching mask includes at least the wiring The barrier layer is formed of a conductive material having resistance to an etching solution used when patterning the wiring. And wherein the Rukoto.

According to a third aspect of the present invention, in the method for manufacturing a display panel according to the first or second aspect, the planarizing film is formed of a non-photosensitive organic material.
According to a fourth aspect of the present invention, in the method for manufacturing a display panel according to any one of the first to third aspects, the functional element and the pixel electrode are formed so as to overlap in a plane via the planarizing film. It is characterized by being.
According to a fifth aspect of the present invention, in the method for manufacturing a display panel according to any one of the first to fourth aspects, the display panel includes a plurality of display pixels, and the display pixels include the functional elements. It has a pixel drive circuit for supplying a predetermined drive current, and a light emitting element that includes the pixel electrode and emits light at a luminance gradation corresponding to the drive current.
According to a sixth aspect of the present invention, in the method for manufacturing a display panel according to any one of the first to fifth aspects, the light emitting element is disposed to face the light emitting functional layer with the light emitting functional layer interposed therebetween. It is an organic electroluminescent element having a pixel electrode and a counter electrode.
According to a seventh aspect of the present invention, in the method for manufacturing a display panel according to the sixth aspect , the pixel electrode includes a conductive layer that reflects light emitted from the light emitting functional layer, and the counter electrode includes the The light-emitting functional layer is formed of a conductive layer that transmits light emitted.

  According to the display panel and the manufacturing method thereof according to the present invention, both the improvement of the flatness of the flattening film and the good formation of the contact hole in the flattening film are achieved, and the excellent display characteristics and reliability are achieved. Can be realized.

  Hereinafter, a display panel and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments. Here, in the embodiments described below, a case will be described in which an organic EL element including an organic EL layer formed by applying an organic compound-containing liquid is applied as a light emitting element constituting a display pixel.

<Display panel>
First, a display panel (organic EL panel) according to the present invention and display pixels arranged in the display panel will be described.
FIG. 1 is a schematic plan view showing an example of a pixel arrangement state of a display panel according to the present invention, and FIG. 2 is a display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged in the display panel according to the present invention. It is an equivalent circuit diagram showing an example of the circuit configuration. In the plan view shown in FIG. 1, for convenience of explanation, pixel electrodes provided in each display pixel (color pixel) viewed from one surface side (organic EL element formation side) of the display panel (or substrate). In order to show only the relationship between the arrangement and the arrangement structure of each wiring layer, and the arrangement relationship with banks (partitions) that define the formation region of each display pixel, The display of the transistors and the like in the pixel driving circuit shown in FIG. 2 provided in each display pixel is omitted. Further, in FIG. 1, the pixel electrodes, the respective wiring layers, and the banks are hatched for the sake of convenience in order to clarify the arrangement.

  As shown in FIG. 1, the display panel 10 according to the present embodiment has a plurality of display pixels PIX arranged in a matrix on one surface side (front side of the paper surface) of an insulating substrate 11 such as a glass substrate. A plurality of data lines Ld are arranged in the vertical direction of the display panel 10 (that is, in the column direction), and a plurality of selection lines Ls are arranged in the horizontal direction of the drawing (that is, in the row direction) orthogonal to the data line Ld. A plurality of power supply voltage lines (for example, anode lines) Lv are provided. The selection line Ls is provided with a terminal pad PLs at one end, and the power supply voltage line Lv is provided with a terminal pad PLv at one end.

  Here, when the display device including the display panel 10 is compatible with color display, for example, display pixels that are color pixels of three colors of red (R), green (G), and blue (B), for example. PIX (denoted as PXr, PXg, and PXb in the drawing for convenience) are sequentially and repeatedly arranged in the horizontal direction of the drawing, and a plurality of display pixels PIX of the same color are arranged in the vertical direction of the drawing. In this case, one set of three RGB display pixels PIX (PXr, PXg, PXb) adjacent in the horizontal direction of the drawing constitutes one pixel. In the case of a display device including a display panel (monocolor display panel) having only single color light emitting color pixels, one display pixel PIX is one pixel.

  And in the display panel 10 corresponding to a color display, as shown in the manufacturing method mentioned later, in the case of forming the organic EL layer by applying a solution containing a high molecular or low molecular organic material, As shown in FIG. 1, for example, banks (partition walls) 18 made of an insulating material protrude from one surface side of the substrate 11, and have a fence shape or a lattice shape so as to surround each formation region for each display pixel (color pixel) PIX. It is arrange | positioned with the planar shape. Thereby, the formation region of the organic EL element OLED (EL element formation region Rel shown in FIG. 3) in the pixel formation region Rpx shown in FIG. 3 is defined. Here, in the case of the bank 18 having a fence-like planar shape as shown in FIG. 1, the pixel electrodes of a plurality of display pixels (color pixels) PIX of the same color arranged in the vertical direction (column direction) in the drawing. (For example, an anode electrode) 16 is included in one EL element formation region Rel.

  Specifically, each display pixel (color pixel) PIX is, for example, as shown in FIG. 2, a pixel driving circuit (corresponding to the above-described pixel circuit) DC having a plurality of transistors (thin film transistors and the like) on the substrate 11. A circuit configuration including an organic EL element (light emitting element) OLED that emits light when a light emission driving current (driving current) generated by the pixel driving circuit DC is supplied to the pixel electrode 16 is applied. be able to.

  Specifically, for example, as shown in FIG. 2, the pixel drive circuit DC has a gate terminal on the selection line Ls arranged in the row direction of the display panel 10 (substrate 11), and a drain terminal on the column of the display panel 10. A transistor (select transistor) Tr11 whose source terminal is connected to the contact N11, a gate terminal is connected to the contact N11, and a drain terminal is arranged in the row direction of the display panel 10 on the data line Ld arranged in the direction. The power supply voltage line Lv includes a transistor (drive transistor; functional element) Tr12 whose source terminal is connected to the contact N12, and a capacitor Cs connected between the gate terminal and the source terminal of the transistor Tr12.

Here, an n-channel field effect transistor (thin film transistor) having a thin film structure is applied to each of the transistors Tr11 and Tr12. The thin film transistor may be an amorphous silicon thin film transistor or a polysilicon thin film transistor. Note that if the transistors Tr11 and Tr12 are p-channel transistors, the source terminal and the drain terminal are opposite to each other.
The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. is there. Therefore, if the transistor Tr12 is a p-channel type, one of the capacitors Cs is connected not to the organic EL element OLED side but to the power supply voltage line Lv side.

  In the organic EL element OLED, an anode terminal (pixel electrode 16 serving as an anode electrode) is connected to the contact N12 (output terminal of the pixel drive circuit DC) of the pixel drive circuit DC, and a cathode terminal (cathode electrode) is connected to the counter electrode 20. It is integrally formed and is connected directly or indirectly to a predetermined reference voltage Vcom (for example, ground potential Vgnd). Here, the counter electrode 20 is formed by a single electrode layer (solid electrode) so as to face the pixel electrodes 16 of the plurality of display pixels PIX arranged two-dimensionally on the substrate 11. . Thereby, the reference voltage Vcom is commonly applied to the plurality of display pixels PIX.

  In the display pixel PIX (pixel drive circuit DC and organic EL element OLED) shown in FIG. 2, the selection line Ls is in a display region in which the substrate 11 is not shown via the terminal pad PLs shown in FIG. A selection signal Ssel that is connected to a selection driver provided in the periphery and that sets a plurality of display pixels PIX arranged in the row direction of the display panel 10 at a predetermined timing is applied. The data line Ld is connected to a data driver provided around the display area of the substrate 11 (not shown), and the gradation signal Vpix corresponding to the display data is synchronized with the selection state of the display pixel PIX. Is applied. The gradation signal Vpix is a voltage signal that sets the light emission luminance gradation of the organic EL element OLED.

  Further, the power supply voltage line Lv is directly or indirectly connected to, for example, a predetermined high potential power supply via the terminal pad PLv shown in FIG. 1, and the pixel electrode 16 of the organic EL element OLED provided in each display pixel PIX. A predetermined high voltage (power supply voltage Vdd) having a higher potential than the reference voltage Vcom applied to the counter electrode 20 of the organic EL element OLED is applied in order to flow a light emission driving current according to display data.

  That is, in the pixel drive circuit DC shown in FIG. 2, the transistor Tr12 and the organic EL element OLED that are connected in series in each display pixel PIX are connected to both ends (the drain terminal of the transistor Tr12 and the cathode terminal of the organic EL element OLED). A power supply voltage Vdd and a reference voltage Vcom are respectively applied to apply a forward bias to the organic EL element OLED so that the organic EL element OLED can emit light, and further flows to the organic EL element OLED according to the gradation signal Vpix. The current value of the light emission drive current is controlled.

  In the drive control operation in the display pixel PIX having such a circuit configuration, first, a selection driver (not shown) selects a selection level (on level; for example, high level) for a selection line Ls during a predetermined selection period. By applying the selection signal Ssel, the transistor Tr11 is turned on and set to the selected state. In synchronization with this timing, control is performed so that a gradation signal Vpix having a voltage value corresponding to display data is applied to the data line Ld from a data driver (not shown). As a result, a potential corresponding to the gradation signal Vpix is applied to the contact N11 (that is, the gate terminal of the transistor Tr12) via the transistor Tr11.

  In the pixel drive circuit DC having the circuit configuration shown in FIG. 2, the current value of the drain-source current of the transistor Tr12 (that is, the light emission drive current flowing through the organic EL element OLED) is the potential difference between the drain-source and the gate. -Determined by the potential difference between the sources. Here, since the power supply voltage Vdd applied to the drain terminal (drain electrode) of the transistor Tr12 and the reference voltage Vcom applied to the cathode terminal (cathode electrode) of the organic EL element OLED are fixed values, the drain of the transistor Tr12 The potential difference between the sources is fixed in advance by the power supply voltage Vdd and the reference voltage Vcom. Since the potential difference between the gate and source of the transistor Tr12 is uniquely determined by the potential of the gradation signal Vpix, the current value of the current flowing between the drain and source of the transistor Tr12 is controlled by the gradation signal Vpix. be able to.

  In this way, the transistor Tr12 is turned on in a conductive state corresponding to the potential of the contact N11 (that is, a conductive state corresponding to the gradation signal Vpix), and the transistor Tr12 and the organic EL element OLED are turned on from the power supply voltage Vdd on the high potential side. Since a light emission driving current having a predetermined current value flows through the reference voltage Vcom (ground potential Vgnd) on the low potential side through the organic EL element OLED, the luminance gradation corresponding to the gradation signal Vpix (that is, display data) The flash operates with. At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation signal Vpix applied to the contact N11.

  Next, in a non-selection period after the end of the selection period, by applying a selection signal Ssel of a non-selection level (off level; for example, low level) to the selection line Ls, the transistor Tr11 of the display pixel PIX is turned off and non-selected. The selected state is set, and the data line Ld and the pixel drive circuit DC (specifically, the contact N11) are electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that the voltage corresponding to the gradation signal Vpix is held at the gate terminal of the transistor Tr12 (that is, the potential difference between the gate and the source is held). It becomes a state.

  Accordingly, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the power supply voltage Vdd to the organic EL element OLED via the transistor Tr12, and the light emission operation state is continued. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation signal Vpix is applied (written). Then, such a drive control operation is sequentially executed for every row, for example, for all the display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, thereby obtaining desired image information. An image display operation to be displayed can be executed.

  In FIG. 2, the pixel driving circuit DC provided in the display pixel PIX is written in each display pixel PIX (specifically, the gate terminal of the transistor Tr12 of the pixel driving circuit DC; the contact N11) according to display data. A voltage designation type gradation control method for controlling the current value of the light emission drive current to flow through the organic EL element OLED by adjusting (specifying) the voltage value of the gradation signal Vpix so that the light emission operation is performed at a desired luminance gradation. Although the circuit configuration corresponding to is shown, by adjusting (specifying) the current value of the current supplied (written) to each display pixel PIX according to the display data, the current value of the light emission drive current passed through the organic EL element OLED It is also possible to have a circuit configuration of a current designation type gradation control system that controls light emission and performs light emission operation at a desired luminance gradation.

  Further, in the pixel driving circuit DC shown in FIG. 2, a circuit configuration in which two n-channel transistors Tr11 and Tr12 are applied is shown, but the display panel according to the present invention is not limited to this. It may have another circuit configuration to which three or more transistors are applied, a circuit configuration to which only a p-channel transistor is applied, or both n-channel and p-channel channels A transistor having polarity may be mixed.

  Here, as shown in FIG. 2, when only an n-channel transistor is applied as the pixel driving circuit DC, the operation characteristics are stabilized by using the amorphous silicon semiconductor manufacturing technology that has already been established. A transistor can be easily manufactured, and a pixel driving circuit in which variation in light emission characteristics of the display pixel is suppressed can be realized.

(Device structure of display pixel)
Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (pixel driving circuit and organic EL element) having the circuit configuration as described above will be described.

  FIG. 3 is a plan layout diagram showing an example of display pixels applicable to the display panel according to the present invention. Here, the layer in which each transistor and wiring layer of the pixel driving circuit DC are formed is mainly shown, and hatching is shown for convenience in order to clarify the arrangement and planar shape of each wiring layer and each electrode. It was. 4 is an IVA-IVA line in the display pixel PIX having the planar layout shown in FIG. 3 (in this specification, as a symbol corresponding to the Roman numeral “4” shown in FIG. 4 (a) is a schematic cross-sectional view showing a cross section along the line IV), FIG. 4 (a) is a first example of the IVA-IVA cross section of the display pixel PIX, and FIG. 4 (b) is a display pixel PIX. It is a 2nd example of the IVA-IVA cross section in. 5 (a) and 5 (b) are respectively VB-VB lines (in this specification, the Roman numeral “5” shown in FIG. 3) in the display pixel PIX having the planar layout shown in FIG. For convenience, “V” is used as a corresponding symbol), and is a schematic cross-sectional view showing a cross section along the line VC-VC.

  Specifically, the display pixels (color pixels) PIX shown in FIG. 2 are arranged in edge regions above and below the pixel formation region Rpx set on one surface side of the substrate 11, for example, as shown in FIG. The selection line Ls and the power supply voltage line Lv are respectively arranged so as to extend in the left-right direction (row direction) of the drawing, and in the edge region on the left side of the drawing so as to be orthogonal to these lines Ls, Lv. Data lines Ld are arranged so as to extend in the vertical direction (column direction). A bank 18 is disposed in the right edge region of the planar layout so as to extend in the column direction across the display pixels PIX adjacent on the right side.

  For example, as shown in FIGS. 3 to 5, the data line Ld is provided on the lower layer side (substrate 11 side) than the selection line Ls and the power supply voltage line Lv, and the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12. By patterning the gate metal layer for forming the gate electrodes Tr11g and Tr12g, the gate electrodes are formed in the same process. The data line Ld is connected to the drain electrode Tr11d of the transistor Tr11 through a contact hole CH11 provided in the gate insulating film 12 formed thereon.

  Note that the gate metal layer is formed of, for example, aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper ( Cu), zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten ( W), platinum (Pt), gold (Au) alone, or a metal layer containing a compound or alloy containing the same can be favorably applied.

  The selection line Ls and the power supply voltage line Lv are provided on the upper layer side than the data line Ld and the gate electrodes Tr11g and Tr12g, and are sources for forming the source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12. By patterning the drain metal layer, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d are formed in the same process. In the line direction in which the power supply voltage line Lv extends, a contact hole CH15 is provided in the gate insulating film 12 except for a region where the data line Ld is provided.

  The selection line Ls is connected to the gate electrode Tr11g via a contact hole CH12 provided in the gate insulating film 12 located at both ends of the gate electrode Tr11g of the transistor Tr11. The power supply voltage line Lv is formed integrally with the drain electrode Tr12d of the transistor Tr12.

  Here, as described above, the selection line Ls and the power supply voltage line Lv are formed by patterning the source and drain metal layers, and the source and drain metal layers are formed of, for example, aluminum (like the above-described gate metal layer). Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), zirconium ( Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), gold ( It is possible to satisfactorily apply a metal layer containing Au) alone or a compound or alloy containing it. As a specific example, an aluminum alloy such as aluminum alone (Al), aluminum-titanium (AlTi), aluminum-neodymium-titanium (AlNdTi), or a single low-resistance metal for reducing wiring resistance such as copper (Cu). It may be formed by a layer or an alloy layer, or a laminated structure in which a transition metal layer for reducing migration such as chromium (Cr) or titanium (Ti) is provided below the low resistance metal layer. You may have. In particular, a two-layer structure of AlTi / Cr and a two-layer structure of AlNdTi / Cr are preferable. Note that in the case where the gate metal layer and the source and drain metal layers are formed using the same sputtering apparatus or the like, the gate metal layer may have the same material structure and the same layer structure as the source and drain metal layers.

  Further, for example, as shown in FIG. 5, the selection line Ls and the power supply voltage line Lv have a wiring structure in which lower wiring layers Ls1, Lv1 and upper wiring layers Ls2, Lv2 are stacked in order to reduce resistance. It may be. For example, the lower wiring layers Ls1, Lv1 are in the same layer as the gate electrodes Tr11g, Tr12g of the transistors Tr11, Tr12, and the gate electrode Tr11g is formed by patterning a gate metal layer for forming the gate electrodes Tr11g, Tr12g. , Tr12g is formed in the same process. Further, as described above, the upper wiring layers Ls2 and Lv2 are both in the same layer as the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, and the source electrodes Tr11s and Tr12s and the drain electrodes. By patterning the source and drain metal layers for forming Tr11d and Tr12d, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d are formed in the same process.

  Therefore, the lower wiring layers Ls1 and Lv1 in this case have the same wiring structure as the gate electrodes Tr11g and Tr12g (or the gate metal layer) described above, and the upper wiring layers Ls2 and Lv2 include the source electrode Tr11s described above. , Tr12s and drain electrodes Tr11d, Tr12d (or source and drain metal layers) have the same wiring structure, and as one specific example, a transition metal layer for reducing migration of chromium (Cr), titanium (Ti), etc. And, it may have a laminated structure in which a low resistance metal layer for reducing the wiring resistance such as the above-mentioned aluminum simple substance or aluminum alloy is provided in the lower layer of the transition metal layer.

  More specifically, for example, as shown in FIG. 3, the pixel drive circuit DC is arranged such that the transistor Tr11 shown in FIG. 2 extends in the horizontal direction (row direction) in the drawing, and the transistor Tr12. Are arranged so as to extend in the vertical direction (column direction) in the drawing. Here, a field effect transistor having a well-known thin film structure can be applied to each of the transistors Tr11 and Tr12. For example, the gate electrodes Tr11g and Tr12g formed on the substrate 11 and the gate electrodes Tr11g and Tr12g The semiconductor layer SMC is formed on the gate insulating film 12 coated on the gate electrode Tr11g and in a region corresponding to the gate electrodes Tr11g and Tr12g, and extends on both sides of the channel of the semiconductor layer SMC. The inverted stagger structure includes source electrodes (electrode layers) Tr11s and Tr12s and drain electrodes Tr11d and Tr12d.

  Note that, on the channel of the semiconductor layer SMC in which the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12 and the drain electrodes Tr11d and Tr12d are arranged to face each other, in order to prevent etching damage to the semiconductor layer SMC in the manufacturing process. A channel protective layer (block layer) BL of silicon oxide or silicon nitride is formed, and the semiconductor layer SMC on both sides of the channel of the semiconductor layer SMC where the source electrodes Tr11s, Tr12s and the drain electrodes Tr11d, Tr12d are in contact An impurity layer OHM for realizing ohmic connection between the layer SMC and the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d is formed.

  Then, to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. 2, the transistor Tr11 is selected via the contact hole CH12 in which the gate electrode Tr11g is provided in the gate insulating film 12, as shown in FIG. The drain electrode Tr11d is connected to the line Ls, and is connected to the data line Ld through a contact hole CH11 provided in the gate insulating film 12.

  As shown in FIGS. 3 and 4, the transistor Tr12 has a gate electrode Tr12g connected to the source electrode Tr11s of the transistor Tr11 through a contact hole CH13 provided in the gate insulating film 12, and the drain electrode Tr12d connected to the power supply voltage. The organic EL element OLED is formed integrally with the line Lv, and the source electrode Tr12s (the output end of the pixel driving circuit) is connected to the protective insulating film 13 and the planarizing film 15 through a contact hole (opening) CH14. It is connected to the pixel electrode 16.

  Here, in this embodiment, a barrier metal (barrier layer) 14 is provided between the source electrode Tr12s (or an electrode Ecb of the capacitor Cs described later) and the pixel electrode 16. The barrier metal 14 covers and protects the surface of the source electrode Tr12s, and is a metal mask used for forming the contact hole CH14 (CH14b) in the planarizing film 15 in the manufacturing method of the display panel described later. (Etching mask) A metal material having etching resistance against a mask stripping solution (etching solution) applied when stripping MSK is used. Specifically, when an aluminum alloy layer such as aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi), which is the same metal layer as the source and drain metals, is applied as the metal mask MSK, Chromium (Cr) or the like having a selective ratio to the source and drain metals with respect to the etchant can be favorably applied as the barrier metal 14.

  3 and 4, the capacitor Cs includes an electrode Eca integrally formed with the gate electrode Tr12g of the transistor Tr12 on the substrate 11, and a source electrode Tr12s of the transistor Tr12 on the gate insulating film 12. The integrally formed electrode Ecb is provided so as to face the gate insulating film 12. Further, as described above, the protective insulating film 13 and the planarization film 15 on the electrode Ecb are provided with the contact hole CH14, and are connected to the pixel electrode 16 of the organic EL element OLED through the contact hole CH14.

  As shown in FIGS. 3 to 5, the organic EL element OLED is provided on the upper surface of the protective insulating film 13 and the planarizing film 15 that are laminated so as to cover the transistors Tr11 and Tr12, and the protective insulating film 13. In the contact hole CH14 provided through the planarizing film 15, the barrier metal 14 is interposed and connected to the source electrode Tr12s (output terminal of the pixel driving circuit) of the transistor Tr12 to supply a predetermined light emission driving current. Layer formed in a region (boundary region) between the pixel electrode (for example, an anode electrode) 16 having light reflection characteristics and the planarizing film 15 between the pixel electrode 16 of the adjacent display pixel PIX. It is defined by the insulating film 17 and the bank 18 disposed so as to continuously protrude on the interlayer insulating film 17 (in a region surrounded by the bank 18). For example, an organic EL layer (light emitting functional layer) 19 formed of, for example, a hole transport layer 19a and an electron transporting light emitting layer 19b formed in the EL element forming region Rel, and each display pixel PIX two-dimensionally arranged on the substrate 11 Are formed by sequentially laminating a counter electrode (for example, a cathode electrode) 20 made of a single electrode layer (solid electrode) having a light transmission characteristic provided so as to be opposed to the pixel electrode 16 in common. .

  Here, the counter electrode 20 is provided so as to extend not only to each EL element formation region Rel but also to the bank 18 that defines the EL element formation region Rel. Further, around the EL element formation region Rel, the bank 18 is formed in the boundary region with the display pixel PIX (EL element formation region Rel) adjacent in the horizontal direction of the planar layout shown in FIG. Ld, the selection line Ls, a part of the power supply voltage line Lv, and the transistors Tr11 and Tr12 overlap the bank 18 in a planar manner. Therefore, the bank 18 reduces the influence of the parasitic capacitance due to the counter electrode 20 formed on the bank 18. As shown in FIGS. 4A and 4B, the data line Ld overlaps with the pixel electrode 16 in plan view, so that the parasitic capacitance with the counter electrode 20 is reduced. The data line Ld does not overlap the pixel electrode 16 in plan view, and the parasitic capacitance between the data line Ld and the counter electrode 20 cannot be sufficiently relaxed only by the protective insulating film 13 and the planarizing film 15. If there is a possibility that the display characteristics are adversely affected, the parasitic capacitance can be reduced by positioning the data line Ld below the bank 18.

  Here, in the panel structure shown in FIGS. 3 to 5, the selection line Ls and the power supply voltage line Lv are stacked wiring structures, and the upper wiring layers Ls2 and Lv2 are the source electrodes Tr11s and Tr12s and drain electrodes of the transistors Tr11 and Tr12. The source and drain metal layers for forming Tr11d and Tr12d are formed by patterning, the selection line Ls is connected to the gate electrode Tr11g of the transistor Tr11 via the contact hole CH12, and the power supply voltage line Lv is connected to the drain of the transistor Tr12. The electrode Tr12d is formed integrally, and the data line Ld is formed by patterning a gate metal layer for forming the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12, and the contact hole CH11 is formed. It is connected to the drain electrode Tr11d of the transistor Tr11 to. Here, the contact hole CH12 is provided in the extending direction of the selection line Ls except for the region where the gate electrode Tr11g of the transistor Tr11 is provided and the region where the data line Ld is provided. Therefore, as shown in FIGS. 5A and 5B, the selection line Ls is composed of the lower wiring layer Ls1 and the upper wiring layer Ls2 in a region where the contact hole CH12 exists, and in the region overlapping the data line Ld. The upper wiring layer Ls2 is not formed in the region where the gate electrode Tr11g is provided, and is connected to both ends of the gate electrode Tr11g of the transistor Tr11. The contact hole CH15 is provided in the extending direction of the power supply voltage line Lv except for the region where the data line Ld is provided. Therefore, as shown in FIGS. 5A and 5B, the power supply voltage line Lv is composed of the lower wiring layer Lv1 and the upper wiring layer Lv2 in a region where the contact hole CH15 exists, and overlaps the data line Ld. The upper wiring layer Lv2 is used. The selection line Ls and the power supply voltage line Lv are not limited to the above configuration, and the gate metal layer is patterned to form the lower layer of the gate insulating film 12, and the data line Ld is formed from the source and drain metal layers. Is formed in the upper layer of the gate insulating film 12 without patterning, so that the selection line Ls is integrated with the gate electrode Tr11g and the data line Ld is integrated with the drain electrode Tr11d without providing the contact holes CH11 and CH12. You may make it provide in.

  As a structure for electrically connecting the pixel electrode 16 and the source electrode Tr12s of the transistor Tr12 of the pixel drive circuit DC (or the electrode Ecb on the other side of the capacitor Cs), as shown in FIG. An electrode material for forming the pixel electrode 16 is embedded in a contact hole CH14 provided through the protective insulating film 13 and the planarizing film 15, and the pixel electrode 16 and the source electrode Tr12s are electrically connected via the barrier metal 14. As shown in FIG. 4B, a contact metal CML made of a conductive material different from that of the pixel electrode 16 is embedded in the contact hole CH14, so that the pixel electrode 16 and the source electrode Tr12s are connected. May be electrically connected via the contact metal CML and the barrier metal 14.

  The bank 18 is a boundary region (specifically, a region between the pixel electrodes 16) between a plurality of display pixels (color pixels) PIX that are two-dimensionally arranged on the display panel 10. (The display panel 10 as a whole has a rail shape surrounding the plurality of pixel electrodes 16 as shown in FIG. 1 or a grid-like planar shape surrounding each pixel electrode 16).

  Here, as shown in FIG. 3 and FIG. 4, the transistor Tr12 extends in the column direction of the display panel 10 (substrate 11) in the boundary region, and the bank 18 is, for example, The transistor Tr12 is substantially covered, and is formed on the interlayer insulating film 17 formed between the pixel electrodes 16 so as to continuously protrude from the surface of the substrate 11 in the height direction. Thereby, in FIG. 1, the region surrounded by the bank 18, that is, the region including the pixel electrodes 16 of the plurality of display pixels PIX arranged in the column direction (vertical direction in the drawing) is the organic EL in the manufacturing method described later. Application region (that is, EL element formation region) of a solvent (organic compound-containing solution) of a solution or suspension containing an organic compound material when forming the layer 19 (for example, the hole transport layer 19a and the electron transporting light emitting layer 19b) Rel).

  The bank 18 is formed using, for example, a photosensitive resin material, and at the time of forming the organic EL layer 19, at least the surface (side surface and upper surface) is an organic compound material applied to the EL element formation region Rel. It preferably has liquid repellency with respect to the solvent of the solution or suspension containing.

  Then, as shown in FIGS. 4 and 5, for example, as shown in FIGS. 4 and 5, the entire surface of the substrate 11 on which the pixel driving circuit DC, the organic EL element OLED, and the bank 18 are formed has a function as a protective insulating film. A sealing layer 21 having a coating is formed. Furthermore, a sealing substrate made of a glass substrate or the like not shown so as to face the substrate 11 may be bonded.

  In such a display panel 10 (display pixel PIX), the light emission drive current having a predetermined current value is generated from the source of the transistor Tr12 based on the gradation signal Vpix corresponding to the display data supplied via the data line Ld. By flowing between the drain and being supplied to the pixel electrode 16 of the organic EL element OLED, the organic EL element OLED of each display pixel (color pixel) PIX emits light with a desired luminance gradation corresponding to the display data. .

  Here, in the display panel 10 according to the present embodiment, the pixel electrode 16 has light reflection characteristics (high reflectance with respect to visible light), and the counter electrode 20 has light transmission characteristics (with respect to visible light). By having a high transmittance, the light emitted from the organic EL layer 19 of each display pixel PIX is directly emitted to the visual field side (upper side of FIGS. 4 and 5) through the counter electrode 20 having light transmission characteristics. At the same time, the light is reflected by the pixel electrode 16 having light reflection characteristics and emitted to the field of view through the counter electrode 20.

That is, since the display panel 10 according to the present embodiment has a top emission type light emitting structure, each circuit element or wiring layer of the pixel driving circuit DC formed on the substrate 11 is replaced with the protective insulating film 13. In addition, the organic EL element OLED formed on the planarizing film 15 can be arranged so as to overlap in a plane. Accordingly, it is possible to increase the pixel aperture ratio, reduce power consumption and extend the panel life, and increase the degree of freedom in pixel circuit layout design.
The terminal pads PLs and PLv and the terminal pad of the data line Ld are respectively connected to terminals of an IC chip (not shown).

(Display panel manufacturing method)
Next, a method for manufacturing a display panel according to this embodiment will be described.
6 to 9 are process cross-sectional views illustrating an example of a method for manufacturing a display panel according to the present embodiment. Here, in order to clarify the characteristics of the manufacturing method of the display panel according to the present invention, the cross section along the IVA-IVA line and the display panel along the VB-VB line shown in FIG. 1 (transistor Tr12, capacitor Cs, organic EL element OLED, selection line Ls, power supply voltage line Lv), and terminal pad PLs provided at the end of selection line Ls shown in FIG. The manufacturing process will be described by showing a structure in which the terminal pad PLv provided at the end of the power supply voltage line Lv is extracted for convenience.

  In the method of manufacturing the display panel described above, first, as shown in FIG. 6A, the display pixel (color pixel) PIX set on one surface side (upper surface side in the drawing) of the insulating substrate 11 such as a glass substrate is used. In the pixel formation region Rpx, wiring layers such as the transistors Tr11 and Tr12, the capacitor Cs, the data line Ld, the selection line Ls, and the power supply voltage line Lv of the pixel driving circuit DC are formed (see FIGS. 3 to 5).

  Specifically, on the substrate 11, the gate electrodes Tr11g, Tr12g, the electrode Eca on one side of the capacitor Cs formed integrally with the gate electrode Tr12g, the data line Ld, and the lower wiring layer Ls1 of the selection line Ls. And the lower wiring layer PLs1 of the terminal pad PLs connected to the selection line Ls, the lower wiring layer Lv1 of the power supply voltage line Lv, and the lower wiring layer PLv1 of the terminal pad PLv connected to the power supply voltage line Lv to the same gate. The metal layer is simultaneously formed by patterning using A-1 manufactured by Nagase ChemteX Co., Ltd. as an etchant, and then a gate insulating film 12 is formed over the entire substrate 11. As shown in FIG. 3, in a region where the data line Ld, the selection line Ls, and the power supply voltage line Lv intersect, for example, a contact hole CH12 and a contact hole CH15 for the selection line Ls and the power supply voltage line Lv are formed. So that they are not electrically connected (insulated) to each other. A contact hole is formed in the gate insulating film 12 on the terminal portion of the data line Ld (not shown) together with the contact hole CH12 and the contact hole CH15.

  Next, in a region corresponding to each gate electrode Tr11g, Tr12g on the gate insulating film 12, for example, a semiconductor layer SMC made of amorphous silicon, polysilicon or the like, and a channel protective layer BL made of silicon nitride or the like are formed, Source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are formed on both ends of the semiconductor layer SMC via an impurity layer OHM for ohmic connection.

  Here, as shown in FIGS. 2 and 3, the drain electrode Tr11d of the transistor Tr11 is connected to the data line Ld through the contact hole CH11 formed in the gate insulating film 12, and the source electrode Tr11s is connected to the gate insulating film. 12 is connected to the gate electrode Tr12g of the transistor Tr12 through a contact hole CH13 formed in the transistor 12.

  At this time, the electrode Ecb on the other side of the capacitor Cs connected to the source electrode Tr12s is formed by patterning with the same source and drain metal layers as an etchant using A-1 manufactured by Nagase ChemteX Corporation. At the same time, the upper wiring layers Ls2 and PLs2 of the selection line Ls and the terminal pad PLs, and the upper wiring layers Lv2 and PLv2 of the power supply voltage line Lv and the terminal pad PLv are simultaneously formed. Terminal pads made of source and drain metal layers are formed in contact holes on the terminal portions of the line Ld.

  Here, each of the upper wiring layers Ls2 and PLs2 of the selection line Ls and the terminal pad PLs is connected to the selection line Ls and the terminal pad through a groove-shaped opening (contact hole CH12) formed in the gate insulating film 12, respectively. It is formed so as to be electrically connected to each lower wiring layer Ls1, PLs1 of PLs. Further, the upper wiring layers Lv2 and PLv2 of the power supply voltage line Lv and the terminal pad PLv are also connected to the power supply voltage line Lv and the terminal pad through a groove-like opening (contact hole CH15) formed in the gate insulating film 12. It is formed so as to be electrically connected to each lower wiring layer Lv1, PLv1 of PLv. As a result, the selection line Ls having a laminated wiring structure composed of the upper wiring layer Ls2 and the lower wiring layer Ls1, and the power supply voltage line Lv having the laminated wiring structure composed of the upper wiring layer Lv2 and the lower wiring layer Lv1 are formed.

  The source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 described above, the electrode Ecb on the other side of the capacitor Cs, and the upper wiring layer Ls2 of the selection line Ls (including the upper wiring layer PLs2 of the terminal pad PLs). The upper wiring layer Lv2 (including the upper wiring layer PLv2 of the terminal pad PLv) and the terminal pad on the terminal portion of the data line Ld reduce the wiring resistance as shown in FIG. For the purpose of reducing migration, for example, a laminated wiring structure comprising an aluminum alloy layer such as aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi) as an upper layer and a transition metal layer such as chromium (Cr) as a lower layer have.

  Next, as shown in FIG. 6B, the entire region of the one surface side of the substrate 11 including the transistors Tr11 and Tr12, the capacitor Cs, the upper wiring layer Ls2 of the selection line Ls and the upper wiring layer Lv2 of the power supply voltage line Lv is covered. As described above, the protective insulating film 13 made of silicon nitride (SiN) or the like is formed, and then the protective insulating film 13 is etched (dry-etched) so that the source electrode Tr12s of the transistor Tr12 (or the electrode on the other side of the capacitor Cs) Ecb), the contact hole CH14a from which the upper surface is exposed, the upper layer wiring layer PLs2 of the terminal pad PLs of the selection line Ls, and the openings CHs1, CHv1, from which the upper surface of the upper layer wiring layer PLv2 of the terminal pad PLv of the power supply voltage line Lv is exposed. In addition, an opening on the terminal of the data line Ld is formed at the same time.

  Next, as shown in FIG. 6C, on the protective insulating film 13 including the contact hole CH14a and the openings CHs1, CHv1, etc., a sputtering method or the like is used, and resistance to chromium (Cr), titanium (Ti), etc. A metal thin film made of a corrosive metal material or an alloy material containing these as a main component is formed, and then the metal thin film is patterned using a photolithography method, so that at least the contact hole CH14a and the opening CHs1 are formed. , CHv1 are connected to the exposed source electrode Tr12s (or the electrode Ecb on the other side of the capacitor Cs) and the upper wiring layers PLs2 and PLv2 of the terminal pads PLs and PLv, respectively, Individual barrier metals 14 and 14s having predetermined planar shapes whose end portions extend to the protective insulating film 13 To form a 14v. Similarly, a barrier metal that is connected to the opening of the terminal of the data line Ld while covering the data line Ld is formed together with the barrier metals 14, 14s, and 14v.

  Here, the barrier metal 14 has openings on the terminals of the contact hole CH14b, the openings CHs2, CHv2, and the data line Ld in the planarizing film 15 in the steps described later (see FIGS. 7A to 7C). As long as it is a metal material having etching resistance with respect to a mask stripping solution (etching solution) applied when stripping the metal mask MSK used for forming, other than the above chromium (Cr) and titanium (Ti) Even if it is a metal material of this, it can apply favorably. Note that since the same metal material as at least the uppermost layer of the source and drain metal layers described above is applied as a metal mask MSK described later, it is possible to prevent the film formation apparatus from becoming complicated. The barrier metal 14 has etching resistance not only to the etching solution used for patterning the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, but also to the etching solution for removing the metal mask MSK. A metal material (conductive material) can be applied.

  Next, as shown in FIG. 6D, the barrier metal 14, 14s, 14v, the contact hole CH14a, the openings CHs1, CHv1, and the opening provided in the protective insulating film 13 on the terminal of the data line Ld are included. A planarization film 15 is formed so as to cover the entire area of one surface of the substrate 11. Here, the planarization film 15 relaxes the surface step due to the transistors Tr11 and Tr12 and the wiring layers of the pixel driving circuit DC formed on the substrate 11, and improves the planarity of the surface of the planarization film 15. Thus, the planarizing film material and its thickness are set appropriately. Specifically, as a planarizing film material applicable to the present embodiment, a thermosetting organic material (for example, an acrylic resin, an epoxy resin, a polyimide resin, etc.) can be favorably applied, For example, SRK-762 manufactured by Nagase ChemteX Corp. is applied as a non-photosensitive thermosetting organic material having high step relaxation performance, and the planarizing film 15 having a film thickness of, for example, about 1 μm to 10 μm is formed. .

  Next, as shown in FIG. 7A, by using a sputtering method or the like on the planarizing film 15, for example, aluminum-titanium (AlTi) or aluminum that is the same as at least the uppermost layer of the source and drain metal layers described above. -A metal thin film made of an aluminum alloy material such as neodymium-titanium (AlNdTi) is formed, and then the metal thin film is patterned using a photolithography method and a wet etching method, and at least on the barrier metals 14, 14s, 14v. A metal mask (etching mask) MSK having a mask pattern exposing the planarizing film 15 on the barrier metal formed in the opening provided in the protective insulating film 13 on the terminal of the data line Ld is formed.

  Next, as shown in FIG. 7B, the planarization film 15 is subjected to reactive ion etching (dry etching) with oxygen plasma using the metal mask MSK, and at least the upper surfaces of the barrier metals 14, 14s, 14v. The contact hole CH14b exposing the openings CHs2 and CHv2 are formed simultaneously. Thereafter, the substrate 11 is immersed in an etching solution for aluminum, and the metal mask MSK is peeled off and removed as shown in FIG. At this time, the barrier metal formed in the opening provided in the protective insulating film 13 on the barrier metal 14, 14 s, 14 v and the terminal of the data line Ld exposed in the contact hole CH 14 b and the openings CHs 2 and CHv 2 is as described above. Since it has etching resistance to the etching solution (mask stripping solution), the surface of the source electrode Tr12s (or the electrode Ecb on the other side of the capacitor Cs) below the barrier metals 14, 14s, 14v, The surfaces of the upper wiring layers PLs2 and PLv2 of the terminal pads PLs and PLv are not peeled off or deteriorated. Here, the etchant (mask stripper) may be the same as the etchant of the source, drain metal layer, and gate metal layer, and for example, A-1 manufactured by Nagase ChemteX Corporation can be applied.

  Next, a metal material such as silver (Ag) or aluminum (Al), or aluminum-neodymium-titanium (AlNdTi) is formed on the planarizing film 15 including the contact hole CH14b and the openings CHs2 and CHv2 by sputtering or the like. After forming a metal thin film having light reflection characteristics (more specifically, having a high reflectance in the visible light region) made of an alloy material such as), the metal thin film is patterned, and FIG. ), The planar shape corresponding to the EL element formation region Rel in each display pixel PIX is electrically connected to the source electrode Tr12s of the transistor Tr12 through the barrier metal 14 in the contact hole CH14b. A reflective layer (reflective metal layer) 16a extending on the planarizing film 15 and having openings CHs2, C The metal layers (reflective metal layers) 16s and 16v are formed so as to be electrically connected to the upper wiring layers PLs2 and PLv2 of the terminal pads PLs and PLv via the barrier metals 14s and 14v in the v2, Further, a similar metal layer is formed on the barrier metal on the terminal of the data line Ld.

Next, on the planarizing film 15 including the reflective layer 16a and the metal layers 16s and 16v, tin-doped indium oxide (ITO) or zinc-doped indium oxide (Indium) is formed by using a sputtering method or the like.
Zinc Oxide (IZO), tungsten-doped indium oxide (Indium Tungsten Oxide; IWO), tungsten-zinc-doped indium oxide (Indium Tungsten Zinc)
After forming a thin conductive metal oxide layer (having light transmission characteristics) made of a transparent electrode material such as Oxide (IWZO), the conductive metal oxide layer is patterned, as shown in FIG. At least the upper surface and end surfaces (side surfaces) of the reflective layer 16a are covered to form a transparent electrode layer 16b having a planar shape corresponding to each EL element formation region Rel, and the upper surfaces and end surfaces of the metal layers 16s and 16v are formed. The electrode layers 16t and 16w that are individually covered are formed, and similarly, the electrode layer that covers the upper surface and the end surface of the metal layer on the terminal of the data line Ld is formed.

  As a result, the pixel electrode 16 having a laminated electrode structure having the reflective layer 16a and the transparent electrode layer 16b and electrically connected to the source electrode Tr12s of the transistor Tr12 through the barrier metal 14 is formed, and the lower layer wiring is formed. A terminal pad PLs electrically connected to the selection line Ls, and a lower wiring layer PLv1, an upper layer, having a laminated wiring structure having a layer PLs1, an upper wiring layer PLs2, a barrier metal 14s, a metal layer 16s, and an electrode layer 16t A gate metal layer having a laminated wiring structure having a wiring layer Lv2, a barrier metal 14v, a metal layer 16v and an electrode layer 16w, and a terminal pad PLv electrically connected to the power supply voltage line Lv and a terminal portion of the data line Ld. A terminal pad having a source, drain metal layer, barrier metal, metal layer and electrode layer is formed.

  In the formation process of the pixel electrode 16, the reflective layer 16a formed in each EL element formation region Rel is completely covered with the transparent electrode layer 16b made of a conductive metal oxide layer, and the terminal pad PLs. The metal layers 16s and 16v of PLv are formed by etching the conductive metal oxide layer in a state where the upper and side surfaces are completely covered with the electrode layers 16t and 16w made of the conductive metal oxide layer so as not to be exposed. Since the patterning is performed, it is possible to prevent a battery reaction between the conductive metal oxide layer (ITO or the like) and the reflective layer 16a or the metal layers 16s and 16v, and the reflective layer 16a or the metal layers 16s and 16v. Can be prevented from being over-etched or subjected to etching damage.

  Next, an inorganic insulating material such as a silicon oxide film or a silicon nitride film is formed on the planarizing film 15 including the pixel electrode 16 and the electrode layers 16t and 16w by using a chemical vapor deposition method (CVD method) or the like. After forming the insulating layer made of the above, by patterning, as shown in FIG. 4A and FIG. 8C, the boundary region with the adjacent display pixel (color pixel) PIX (that is, the adjacent pixel electrode 16). Interlayer insulation having an opening that exposes the upper surface of the pixel electrode 16 in each pixel formation region Rpx and an opening that exposes the electrode layers 16t and 16w of the terminal pads PLs and PLv. A film 17 is formed.

  Next, as shown in FIG. 9A, on the interlayer insulating film 17 formed in the boundary region between the adjacent display pixels PIX (pixel electrodes 16), for example, a polyimide-based or acrylic-based photosensitive resin. A bank 18 made of a material is formed. Specifically, by patterning a photosensitive resin layer formed so as to cover the entire area of one surface of the substrate 11 including the interlayer insulating film 17 and the pixel electrode 16, as shown in FIG. A bank (partition wall) 18 having a fence-like planar shape including a region extending in the column direction of the display panel 10, which is a boundary region between display pixels PIX adjacent to each other, and projects continuously in the height direction. Form. As a result, the EL element formation region Rel of the plurality of display pixels (color pixels) PIX of the same color arranged in the column direction of the display panel 10 is defined by being surrounded by the bank 18 and the interlayer insulating film 17. The upper surface of the pixel electrode 16 of each display pixel PIX is exposed in the formation region Rel.

Next, after cleaning the substrate 11 with pure water, the surface of each pixel electrode 16 exposed in the EL element formation region Rel is subjected to, for example, oxygen plasma treatment, UV ozone treatment, etc. The organic compound-containing liquid of the transportable light emitting material is subjected to a lyophilic process, and then the surface of the bank 18 is subjected to CF ₄ plasma treatment to make the surface of the bank 18 liquid repellent with respect to the organic compound-containing liquid. If the bank 18 itself contains fluorine atoms in advance, the above liquid repellency treatment need not necessarily be performed.

  As a result, only the surface of the bank 18 is subjected to lyophobic treatment on the same substrate 11, and the surface of the pixel electrode 16 exposed to each pixel formation region Rpx defined by the bank 18 is not lyophobized (parent). As described later, even when the organic EL layer 19 (electron transporting light emitting layer 19b) is formed by applying an organic compound-containing liquid, the adjacent EL element forming region Rel is used. It is possible to prevent the organic compound-containing liquid from leaking over and overcoming, and to suppress color mixture between adjacent pixels, thereby enabling red (R), green (G), and blue (B) colors to be separately applied.

  “Liquid repellency” used in the present embodiment means an organic compound-containing liquid containing a hole transport material to be a hole transport layer 19a described later, and an electron transport light emission to be an electron transport light-emitting layer 19b. When the contact angle is measured by dropping an organic compound-containing liquid containing the material or an organic solvent used in these solutions onto a substrate or the like and the contact angle is measured, it is defined as a state where the contact angle is 50 ° or more. To do. In addition, “lyophilic” as opposed to “liquid repellency” is defined in the present embodiment as a state in which the contact angle is 40 ° or less, preferably 10 ° or less.

  Next, after applying the solution or dispersion of the hole transport material to the EL element formation region Rel of each color surrounded (delimited) by the bank 18 by applying an inkjet method, a nozzle printing method, or the like. The hole transport layer 19a is formed by heating and drying. Subsequently, a solution or dispersion of an electron transporting light emitting material is applied onto the hole transporting layer 19a, and then heated and dried to form the electron transporting light emitting layer 19b. As a result, as shown in FIG. 9B, the organic EL layer 19 including the hole transport layer 19 a and the electron transport light-emitting layer 19 b is stacked on the pixel electrode 16.

  Specifically, as an organic compound-containing liquid containing an organic polymer-based hole transport material, for example, a polyethylenedioxythiophene / polystyrenesulfonic acid aqueous solution (PEDOT / PSS; polyethylenedioxythiophene PEDOT which is a conductive polymer) and a dopant A dispersion of polystyrene sulfonic acid PSS, which is dispersed in an aqueous solvent, is applied onto the pixel electrode 16 and then subjected to a heat drying treatment to remove the solvent, whereby an organic polymer is formed on the pixel electrode 16. The positive hole transport material is fixed to form the hole transport layer 19a as the carrier transport layer.

  In addition, as an organic compound-containing liquid containing an organic polymer-based electron-transporting light-emitting material, for example, a light-emitting material containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene is used as tetralin, tetramethylbenzene, or mesitylene. An organic solvent such as xylene or a solution dissolved in water is applied onto the hole transport layer 19a, and then subjected to a heat drying treatment to remove the solvent, whereby an organic polymer system is formed on the hole transport layer 19a. The electron transporting light emitting material is fixed to form an electron transporting light emitting layer 19b which is a carrier transporting layer and also a light emitting layer.

  Thereafter, as shown in FIG. 9C, a light-transmissive conductive layer (transparent electrode layer) is formed on the substrate 11 including at least the EL element formation region Rel of each display pixel PIX, and the organic EL layer 19 is formed. A common counter electrode (for example, a cathode electrode) 20 that faces the pixel electrode 16 of each display pixel PIX is formed via (the hole transport layer 19a and the electron transport light emitting layer 19b).

  Specifically, the counter electrode 20 is formed, for example, by forming a thin film made of a metal material such as barium, magnesium, or lithium that serves as an electron injection layer by vapor deposition or the like, and then forming a transparent electrode layer such as ITO on the upper layer by sputtering or the like. A transparent film structure can be applied in the thickness direction. Here, the counter electrode 20 is formed not only as a region facing the pixel electrode 16 but also as a single conductive layer (solid electrode) extending to the bank 18 that defines each EL element formation region Rel. .

  Next, after the counter electrode 20 is formed, a sealing layer 21 made of a silicon oxide film, a silicon nitride film, or the like is formed as a protective insulating film (passivation film) over the entire surface of the one surface of the substrate 11 using a CVD method or the like. As a result, the display panel 10 having a cross-sectional structure as shown in FIGS. 4A and 5 is completed. Although not shown, in addition to the panel structure as shown in FIGS. 4A and 5, a sealing lid or a sealing substrate made of a glass substrate or the like is further bonded so as to face the substrate 11. It may be what has been done.

  According to such a display panel manufacturing method, the organic EL element OLED (light emitting element) is formed on the substrate 11 on which the circuit elements and wiring layers of the pixel driving circuit DC are formed via the planarization film 15. In the panel structure, a barrier metal 14 is formed in the contact hole CH14 that connects the pixel drive circuit DC (source electrode Tr12s of the transistor Tr12) and the organic EL element OLED (pixel electrode 16), thereby forming the contact hole CH14. In the step of removing the metal mask MSK for forming the gate electrode, it is possible to prevent damage (peeling and deterioration) to the electrode layer of the pixel driving circuit DC (source electrode Tr12s of the transistor Tr12) by the mask stripping solution. The circuit DC and the organic EL element OLED can be electrically connected in a good bonded state.

More specific description will be given below.
As described in the background art described above, as in the case of having a top emission type light emitting structure, a light emitting element (organic EL element) is formed on the upper side of a pixel driving circuit including a circuit element such as a thin film transistor formed on a substrate. ) Is formed, it is indispensable to form a planarizing film in order to reduce the level difference on the substrate surface. In this case, conductive layers (on the upper layer side and lower layer side of the planarizing film) For example, it is necessary to provide a contact hole in the planarization film in order to establish electrical continuity between the thin film transistor of the pixel drive circuit and the pixel electrode of the organic EL element.

  Here, photosensitive (photo-curable) and non-photosensitive organic materials having thermosetting properties are known as commercially available planarizing film materials. The photosensitive organic material can be directly patterned by irradiating it with ultraviolet light after film formation on the substrate, so that the manufacturing process can be simplified, but the flatness (level difference relaxation property) can be achieved. It has the characteristic of being somewhat inferior. On the other hand, a non-photosensitive organic material is superior in leveling property compared to a photosensitive organic material, but has a feature that it needs to be processed by a dry etching method after film formation on a substrate. Yes.

  In a panel structure in which a light emitting element is formed on a planarization film like a top emission type light emitting structure, it is necessary to form the electrode layer and the light emitting layer of the light emitting element with a uniform film thickness on a smooth surface. Since the flattening film is required to have a particularly high step reduction performance, it is desirable to apply a non-photosensitive organic material to the flattening film. A thermosetting and non-photosensitive material cannot directly expose and develop the planarizing film, so that it is necessary to form an etching process on the planarizing film. At this time, the flattening film has a problem that it is difficult to satisfactorily pattern by etching because the film thickness is considerably thick.

  As described above, when a non-photosensitive organic material is applied to the planarization film, a contact hole for electrically connecting the upper side light emitting element and the lower layer side pixel drive circuit to the planarization film. In the case of forming, a process of forming a mask on the planarizing film and performing dry etching is necessary for anisotropically etching the planarizing film having a large film thickness. Here, as a method for forming a mask for dry etching, for example, a method of forming a resist mask by patterning after applying an organic resist, a method of forming a metal mask by patterning after forming a metal film, etc. It has been known.

  In the method using an organic resist as a mask, the manufacturing process can be simplified (the number of steps can be reduced). However, when dry etching is performed in order to form a contact hole in the planarizing film, a flat layer made of an organic material is used. The resist mask (organic resist) is etched together with the chemical film, and there is a problem that the flatness of the flat film and the shape of the contact hole are impaired. Therefore, it has been necessary to set the etching rate of the organic resist slower than that of the planarization film by examining the etching conditions and gas types.

  On the other hand, in the dry etching method using a metal mask, the etching rate with the planarizing film is greatly different, so that the selection range of etching conditions and gas types (degree of freedom of manufacturing conditions) can be expanded. In addition, as a metal film used as a metal mask, a gate electrode or a source, a sputtering machine used in a process of forming a gate electrode or a source and a drain electrode to be the transistors Tr11 and Tr12 that form the pixel driving circuit, and a gate electrode or a source, By using the same material as at least a part of the drain electrode, for example, a laminated structure including an aluminum alloy layer such as aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi) and a transition metal layer such as chromium (Cr) The same manufacturing apparatus can be applied, and the apparatus system can be simplified.

Here, it is conceivable to use a chromium single layer structure as a metal mask, but in this case, it is impossible to form a thick film because of high film tension, and dry etching is performed in an oxygen (O ₂ ) atmosphere. However, there is a problem in that it is oxidized and peeled off. On the other hand, when the above-described aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi) is used as a metal mask, a thick film can be formed, so that it is peeled off by dry etching in an oxygen (O ₂ ) atmosphere. However, if it is immersed in a mask stripping solution (etching solution) to strip the metal mask after dry etching, the lower layer side that is electrically connected to the light emitting device (organic EL device) on the upper layer side of the planarization film Since the surface of the electrode layer (source electrode Tr12 of the transistor Tr12) of the pixel driving circuit is formed of a transition metal layer of an aluminum alloy layer such as aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi), the metal When the electrode layer peels off or deteriorates along with the mask It had a cormorant problem.

  Therefore, in the present invention, as shown in the above-described embodiment, the substrate on which the circuit elements (transistors Tr11, Tr12, etc.) and wiring layers (data lines Ld, selection lines Ls, etc.) of the pixel drive circuit DC are formed. In the display panel 10 having a panel structure in which an organic EL element OLED (light emitting element) is formed on a flat film 15 made of a non-photosensitive organic material on the electrode layer 11 of the pixel driving circuit DC (transistor Prior to the step of forming the contact hole CH14 (CH14b) connecting the source electrode Tr12s of Tr12 and the organic EL element OLED (pixel electrode 16) in the planarization film 15, a metal mask for forming the contact hole CH14 is formed. The barrier metal 14 having etching resistance against the mask stripper used in the process of removing MSK is defined. A manufacturing method of forming on the electrode layer of the elementary drive circuit DC is applied.

  Thus, after the contact hole CH14 (CH14b) is formed in the planarizing film 15, the metal mask MSK formed on the planarizing film 15 is removed by the mask stripping solution in order to form the contact hole CH14 (CH14b). In the process, the electrode layer of the pixel driving circuit DC is covered with the barrier metal 14, and only the barrier metal 14 is exposed in the contact hole CH14 (CH14b), so that the electrode layer of the pixel driving circuit DC is directly exposed to the mask stripping solution. Damage (peeling or deterioration) due to the contact between the pixel driving circuit DC and the organic EL element OLED can be electrically connected in a good bonded state.

  Therefore, the planarity of the planarization film formed between the pixel driving circuit and the light emitting element can be improved by applying a planarization film made of a non-photosensitive organic material. The light-emitting layer can be formed on a smooth surface with a uniform film thickness to achieve good display characteristics, and when forming contact holes in the planarization film, a metal mask can be applied to free the manufacturing conditions. In addition, the pixel drive circuit and the light-emitting element can be connected electrically and efficiently under efficient manufacturing conditions. And a highly reliable display panel can be realized.

  In the above-described embodiment, the display panel (organic EL element) having a top emission type light emitting structure has been described. However, the present invention is not limited to this, and the organic EL element OLED has light transmission characteristics. By applying the pixel electrode 16 having the pixel electrode 16 and the counter electrode 20 having the light reflection characteristic, the light emitted from the organic EL layer 19 is reflected directly or by the counter electrode 20, and the pixel electrode 16 and the transparent planarizing film are reflected. 15 and a light emitting element having a bottom emission type light emitting structure that is emitted to the other side of the substrate 11 (display panel 10) (downward in FIGS. 4 and 5) through the transparent substrate 11 and the transparent substrate 11. There may be.

  In the above-described embodiment, the device structure in which the hole transport layer 19a and the electron transporting light emitting layer 19b are stacked as the organic EL layer 19 which is a light emitting functional layer has been described. However, the present invention is not limited to this. Without a hole transporting light emitting layer and an electron transporting layer, or a single layer of a hole transporting and electron transporting light emitting layer, or a hole transporting layer, a light emitting layer, an electron transporting It may have a three-layer structure of layers, or may have a laminated structure having other intervening layers such as an interlayer.

In the above-described embodiment, the case where the pixel electrode 16 is the anode electrode of the organic EL element OLED has been described. However, the present invention is not limited to this and may be a cathode electrode. . In this case, the organic EL layer 19 may be such that the carrier transport layer in contact with the pixel electrode 16 is an electron transport layer.
In the embodiment described above, the barrier metal 14s, 14v is provided in the terminal pad PLs connected to the selection line Ls and the terminal pad PLv connected to the power supply voltage line Lv, and further, protective insulation is provided on the terminal of the data line Ld. An opening is provided in the film 13 so that it can be protected by forming a barrier metal similar to the barrier metal 14 so as to cover the surface of the terminal of the data line Ld, but the electrode of the transistor connected to the pixel electrode, A barrier metal may be formed on only one of the selection line Ls, the power supply voltage line Lv, and the data line Ld, or a barrier metal may be formed by appropriately combining a plurality of them.

It is a schematic plan view which shows an example of the pixel array state of the display panel which concerns on this invention. FIG. 3 is an equivalent circuit diagram illustrating a circuit configuration example of display pixels (light emitting elements and pixel driving circuits) two-dimensionally arranged on the display panel according to the present invention. It is a plane layout figure which shows an example of the display pixel applicable to the display panel which concerns on this invention. It is a schematic sectional drawing which shows the IVA-IVA cross section in the display pixel which has the planar layout which concerns on this embodiment. It is a schematic sectional drawing which shows the VB-VB cross section in the display pixel which has the planar layout which concerns on this embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display panel which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display panel which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display panel which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the display panel which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 11 Substrate 12 Gate insulating film 13 Protective insulating film 14 Barrier metal 15 Planarizing film 16 Pixel electrode 17 Interlayer insulating film 18 Bank 19 Organic EL layer 20 Counter electrode DC pixel drive circuit OLED Organic EL element Ld Data line Ls Selection line Lv power supply voltage line MSK metal mask

Claims (7)

Forming a conductive barrier layer in a predetermined region on the electrode layer of the functional element provided on the substrate;
Forming a planarization film so as to cover the barrier layer;
Forming an opening through which the barrier layer is exposed in the planarizing film using an etching mask;
After removing the etching mask using a predetermined mask remover, the pixel electrode is connected to the electrode layer through the barrier layer in the opening and extends from the opening onto the planarizing film. Forming a step;
And the etching mask is formed of the same conductive material as at least the uppermost layer of the electrode layer, and the barrier layer is a conductive material having resistance to an etching solution used for patterning the electrode layer. A method of manufacturing a display panel, characterized by being made of a material. Forming a conductive barrier layer in a predetermined region on the terminal of the wiring provided on the substrate;
Forming a planarization film so as to cover the barrier layer;
Forming an opening through which the barrier layer is exposed in the planarizing film using an etching mask;
After removing the etching mask using a predetermined mask remover, the terminal pad layer is connected to the terminal through the barrier layer in the opening and extends from the opening onto the planarizing film. Forming a step;
The etching mask is made of the same conductive material as at least the uppermost layer of the wiring , and the barrier layer is made of a conductive material resistant to an etchant used for patterning the wiring. A method for producing a display panel, wherein the display panel is formed. 3. The method for manufacturing a display panel according to claim 1, wherein the planarizing film is formed of a non-photosensitive organic material. 4. The method for manufacturing a display panel according to claim 1, wherein the functional element and the pixel electrode are formed so as to overlap in a planar manner with the planarizing film interposed therebetween. In the display panel, a plurality of display pixels are arranged,
The display pixel includes the functional element and includes a pixel driving circuit that passes a predetermined driving current, and a light emitting element that includes the pixel electrode and emits light at a luminance gradation corresponding to the driving current. The method for manufacturing a display panel according to claim 1, wherein the display panel is a display panel. 6. The organic electroluminescence element according to claim 1, wherein the light-emitting element is an organic electroluminescence element having a light-emitting functional layer, and the pixel electrode and the counter electrode arranged to face each other with the light-emitting functional layer interposed therebetween. The manufacturing method of the display panel in any one. The pixel electrode includes a conductive layer that reflects light emitted from the light emitting functional layer, and the counter electrode is formed from a conductive layer that transmits light emitted from the light emitting functional layer. A method for manufacturing a display panel according to claim 6.

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