JP5423071B2 - Data transfer device and imaging device - Google Patents

Description

  The present invention relates to a data transfer apparatus and an imaging apparatus that perform phase adjustment with a reference signal in data transfer.

  Conventionally, in the high-speed transfer of digital data, especially in the case of high-speed serial communication, the data signal of the digital data and the clock signal that is the reference signal are affected by the heat generated by the continuous operation of the data transfer device and the circuit configuration. The phase shift occurs. Therefore, various techniques have been developed to avoid such problems.

  For example, in Patent Document 1, an input data signal is input to each of a plurality of threshold setting circuits, and based on two clock signals of phase 0 degrees and 90 degrees generated by a clock signal generation circuit by a logic circuit. The two combinations of the reproduction data signal and the two phase comparison signals are output, and the selector circuit selects one of the two combinations based on the result of the reproduction data of the previous cycle. A technique is disclosed in which a combination is selected and phase adjustment is performed based on the reproduction data signal of the selected combination and two phase comparison signals.

JP 2008-124714 A

  However, in the case of Patent Document 1, which is a conventional technique, since one combination is selected and phase adjustment is performed based on the reproduction data of the previous cycle, for example, the environment in which an imaging apparatus such as a digital camera is used or Phase adjustment is difficult when the temperature inside the imaging apparatus changes greatly between the previous cycle and the current cycle due to an imaging mode such as copying or moving image imaging.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a technology capable of performing phase adjustment at high speed in real time in data transfer.

One aspect of a data transfer device illustrating the present invention receives a signal of image data having a known synchronization code together with a reference signal, and receives a phase adjustment unit that performs phase adjustment of the signal of the image data with respect to the reference signal A shift unit that shifts a synchronization signal of a known synchronization code among image data signals by a predetermined amount smaller than one cycle of the reference signal and the shifted synchronization signal and the reference signal are compared, and the amount of deviation is within a predetermined range. A shift determination unit that determines whether or not the phase is within, and a phase control unit that controls an adjustment amount for phase adjustment in the phase adjustment unit based on a determination result by the shift determination unit.

The reference signal and the image data signal may be received in synchronization.
In addition , the shift determination unit may include a code generation unit that generates a code associated with a known synchronization code, and transmits the determination result of whether or not the deviation amount is within a predetermined range to the phase control unit.

Moreover, further comprising a counter unit for counting the number of received number or image data in synchronization codes already known image data, shift unit, depending on the number of the counter unit, the reference signal a signal of the image data, advances Alternatively, a predetermined amount may be shifted in the delaying direction.

The phase control further includes a temperature monitoring unit that measures and monitors the temperature of the data transfer device, and a storage unit that records the determination result of the shift determination unit in association with the temperature measured and monitored by the temperature monitoring unit. The unit determines a temperature range in which the number of determination results in which the deviation amount is determined to be out of the predetermined range is equal to or less than the predetermined number based on the recorded temperature and the determination result associated with the temperature, When the temperature measured and monitored by the monitoring unit is within the temperature range, the adjustment amount in the phase adjustment unit is maintained, and when the temperature is not within the temperature range, the adjustment amount in the phase adjustment unit may be changed. .

Another aspect of the data transfer apparatus illustrating the present invention includes a phase adjustment unit that receives a data signal together with a reference signal and adjusts the phase of the data signal with respect to the reference signal, and the received data signal is one of the reference signals. A shift unit that shifts a predetermined amount smaller than the period , a shift determination unit that compares the signal of the shifted data with the reference signal, and determines whether the shift amount is within a predetermined range, and a determination by the shift determination unit And a phase control unit for controlling an adjustment amount for phase adjustment in the phase adjustment unit.

  An imaging apparatus of the present invention includes an imaging unit that captures an image of a subject and generates and outputs an image, and the data transfer apparatus of the present invention.

  According to the present invention, phase adjustment can be performed at high speed in real time in data transfer.

1 is a schematic diagram showing a configuration example of a data transfer apparatus 100 according to an embodiment of the present invention. The figure which shows an example of the format of the raw data of the image output from the image pick-up element 10. The schematic diagram which shows the structural example of the phase adjustment part 21 which concerns on one Embodiment of this invention. The schematic diagram which shows the structural example of the shift part 22 which concerns on one Embodiment of this invention. Timing chart showing phase adjustment processing of data transfer apparatus 100 A timing chart showing the processing in step S102 of the phase adjustment processing of the data transfer apparatus 100 The figure which shows an example of the flow of the process in the shift part 22 and the shift determination part 23 of this embodiment. The figure which shows an example of the histogram of the frequency | count of the phase adjustment flag ON / OFF determined by the shift determination part 23 with respect to the temperature measured by the temperature monitoring part 26. The figure which shows the other example of the format of the raw data of the image applicable to this invention.

  FIG. 1 is a schematic diagram illustrating a configuration example of a data transfer apparatus 100 according to an embodiment of the present invention. FIG. 1 illustrates a configuration example when the imaging unit 1 of the digital camera is a transmission unit and the signal processing circuit 20 of the digital camera is a reception unit.

  The imaging unit 1 of the present embodiment includes an imaging element 10 having a light receiving surface in which a plurality of light receiving elements are two-dimensionally arranged, and an A / D conversion circuit (not shown), and is configured by an imaging optical system (not shown). A subject imaged on the light receiving surface is imaged based on a timing pulse generated by a timing generator based on a command from a digital camera control unit (not shown), and RAW data of the image is acquired. The imaging unit 1 outputs the image signal of the RAW data as a digital data signal.

  FIG. 2 shows a format of RAW data output from the imaging unit 1. That is, at the beginning and end of each line (in this embodiment, the horizontal scanning direction), Start of Active Video (SAV) and End of Active Video (EAV), which are codes describing known contents to be described later, are displayed. And between the SAV and the EAV, image data sandwiched between blank areas which are empty data is arranged.

  In the imaging unit 1 of the present embodiment, one end of one data signal line DATA that outputs an image signal for each line is connected to one end of a clock signal line CLK that outputs a clock signal that is a reference signal. The The other end of each signal line is connected to the signal processing circuit 20. That is, the data transfer between the imaging unit 1 and the signal processing circuit 20 in this embodiment is a serial method using one channel.

  The signal processing circuit 20 is a preprocess circuit that performs various types of image processing on the digital image signal input from the imaging unit 1. The signal processing circuit 20 includes a phase adjustment unit 21, a shift unit 22, a shift determination unit 23, a phase control unit 24, a counter unit 25, a temperature monitoring unit 26, a storage unit 27, and an image processing unit 28. The input data signal is phase-adjusted by the phase adjustment unit 21 via the data signal line DATA, and then input to the shift unit 22 and the counter unit 25 together with the clock signal. At the same time, the phase-adjusted data signal is also transferred to the image processing unit 28. The image processing unit 28 performs various types of image processing (defective pixel correction, color interpolation, tone correction, white correction) on the RAW data of the image. Balance adjustment, edge enhancement, etc.). Although not shown, between the phase adjustment unit 21 and the image processing unit 28 is a capturing unit that captures a value indicated by the data signal in synchronization with the rising or falling timing of the clock signal.

  The phase adjustment unit 21 is a circuit that adjusts the phase shift amount of the data signal with respect to the clock signal. FIG. 3 is a schematic diagram illustrating a configuration example of the phase adjustment unit 21. The phase adjustment unit 21 includes a plurality of delay elements 30 (inverters or the like) connected in series in a plurality of stages, a plurality of paths 31 connected to the output side of each delay element 30, and a phase adjustment set in the phase control unit 24. The selector 32 is configured to select the path 31 according to the adjustment amount. Therefore, the data signal is phase-adjusted according to the path 31 selected by the selector 32 and is output to the shift unit 22, the counter unit 25, and the image processing unit 28. The number of delay elements 30 is preferably designed to correspond to several times the data transfer period.

  The shift unit 22 has a circuit configuration as shown in FIG. 4, and uses a delay element 40 to make a determination based on the amount of phase shift between the clock signal and the data signal in the shift determination unit 23 described later. , Out of the data signal, the synchronization signal portion of the synchronization code SAV added to the head is 0 shift that does not shift the phase with respect to the clock signal, and the phase shift (+ shift) in the forward direction or the phase shift (− Shift). Then, the selector 42 of the shift unit 22 selects and outputs either the + shifted signal or the −shifted synchronization signal in accordance with an instruction from the counter unit 25.

  Here, in this embodiment, with respect to the synchronization signal output from the phase adjustment unit 21, the synchronization signal output to the path 41 through the two-stage delay element 40 has no phase shift (0 shift). ) Signal. Therefore, the shift unit 22 also passes the two-stage delay element 40 for the clock signal. Then, a signal that has been further passed through two delay elements 40 is defined as a + shifted synchronization signal, and a signal that has not been passed through any delay element 40 is defined as a -shifted synchronization signal. The predetermined amount of delay of the + shift or -shifted synchronization signal with respect to the 0-shift synchronization signal in the present embodiment is, for example, ¼ period of the clock signal. This delay amount is preferably determined according to the size of the input image data, the accuracy of phase adjustment, or the processing capability of the signal processing circuit 20. It is preferable to determine the number of delay elements 40 accordingly.

  As will be described later, the shift determination unit 23 obtains the amount of deviation between the clock signal and the + shifted or -shifted synchronization signal, and if the amount of deviation is within an allowable range, the shift determining unit 23 determines the next phase control unit 24. Then, a code corresponding to the phase adjustment flag OFF indicating the current adjustment amount maintenance is transmitted, and if it is out of the range, a code corresponding to the phase adjustment flag ON indicating the adjustment amount change instruction is transmitted.

  The phase control unit 24 does nothing to the selector 32 of the phase adjustment unit 21 when the code is the phase adjustment flag OFF from the shift determination unit 23. On the other hand, when the code of the phase adjustment flag ON is received from the shift determination unit 23, an adjustment amount for phase adjustment is obtained according to the received code, and + shift or -shift is performed according to the count value of the counter unit 25 It is set in the selector 32 of the phase adjustment unit 21 so that the phase is adjusted in the direction to be adjusted. In the present embodiment, as will be described later, not only the determination result from the shift determination unit 23 but also the temperature by the temperature monitoring unit 26 or the temperature recorded in the storage unit 27 and the shift determination unit 23 corresponding thereto. Depending on the determination result, the adjustment amount of the phase adjustment set in the selector 32 of the phase adjustment unit can also be controlled. The phase adjustment unit 24 can use a CPU of a general computer.

  In the RAW data output from the image sensor 10 as shown in FIG. 2, the counter unit 25 adds a synchronization code SAV added to the head of each line in the horizontal scanning direction or a synchronization code EAV added to the end. Based on the number of lines, the count value is output.

  The temperature monitoring unit 26 measures and monitors the temperature of the data transfer device 100 periodically (when the count value of the counter unit 25 increases in this embodiment), and outputs it to the phase adjustment unit 24. At the same time, the temperature monitoring unit 26 records the measured temperature in the storage unit 27. A general temperature sensor can be appropriately selected and used for the temperature monitoring unit 26.

  The storage unit 27 stores data on the delay amount of the phase adjustment unit 21 and the shift unit 22 (the number of delay stages of the delay element 30 or the delay element 40), the temperature measured and monitored by the temperature monitoring unit 26, and the like. For the storage unit 27, a storage medium such as a register or a flash RAM can be appropriately selected and used.

  Next, phase adjustment processing in the data transfer apparatus 100 according to the present embodiment will be described based on the flowcharts of FIGS. 5 and 6. This process is executed at a timing at which RAW data of an image captured by the image sensor 10 of the imaging unit 1 is transferred. Note that when the data signal of the RAW data transferred through the data signal line DATA and the clock signal transferred through the clock signal line CLK are output from the imaging device 10 of the imaging unit 1, they are synchronized with each other in advance at the time of manufacture. Is assumed. Therefore, assuming that the initial value of the adjustment amount of the phase adjustment recorded in the storage unit 27 is 0, and the selector 32 of the phase adjustment unit 21 is set to the adjustment amount 0 by the phase control unit 24. The phase adjustment process will be described. In addition, the phase adjustment for each line of the RAW data in the present embodiment is performed based on the determination result of the shift determination unit 23 for the data signal of the previous line except for the first line.

  Step S101: The imaging device 10 of the imaging unit 1 is RAW for each line in synchronization with a clock signal based on a timing pulse generated by a timing generator based on a command from a control unit of a digital camera (not shown). Data is output to the data signal line DATA. The phase adjustment unit 21 controls the delay element 30 based on the adjustment amount set in the selector 32 with respect to the data signal of each line transferred via the reception unit (not shown) of the signal processing circuit 20. To adjust the phase. The phase adjusting unit 21 outputs the phase-adjusted RAW data of each line to the shift unit 22, the counter unit 25, and the image processing unit 28, respectively.

  Step S102: Based on the SAV code at the head of each line of the RAW data, the shift unit 22 converts the phase states of the transferred data signal and clock signal into the process shown in the flowchart shown in FIG. Confirm based on. The processing procedure shown in FIG. 6 in step S102 will be described in detail later.

  Step S103: The phase control unit 24 receives the image data sandwiched between the blank areas together with the blank area in each line, and confirms that EAV indicating the end is finally detected.

  Step S104: After the EAV is detected in Step S103, the phase control unit 24 outputs the adjustment based on the shift amount between the synchronization signal shifted by the shift unit 22 and the clock signal by the shift determination unit 23 described later. It is determined whether or not a code corresponding to the phase adjustment flag ON indicating the amount change instruction has been received. When the phase control unit 24 receives the code corresponding to the phase adjustment flag ON, the phase control unit 24 proceeds to step S105 (YES side). On the other hand, when the phase control unit 24 receives a code corresponding to the phase adjustment flag OFF indicating the current adjustment amount maintenance, the phase control unit 24 proceeds to step S106 (NO side).

  Step S105: The phase control unit 24 obtains the adjustment amount of the phase adjustment in the phase adjustment unit 21 based on the determination result from the shift determination unit 23, and adjusts the phase of the new adjustment amount when reading the RAW data of the next line. Set in the selector 32 of the unit 21. That is, in the case of + shift, the phase control unit 24 reads the data signal of the next line by -shifting, and in the case of -shift, the data signal of the next line is read by shifting +. Then, the adjustment amount of the selector 32 is set. At the same time, the phase control unit 24 records the value of the adjustment amount in the storage unit 27.

  Step S106: The phase control unit 24 determines whether all the image data up to the last line of the RAW data has been read based on the count number from the counter unit 25. If the phase control unit 24 determines that all lines of the RAW data have not been read, the phase control unit 24 proceeds to step S102 (YES side). Then, the phase adjustment unit 21 reads the data signal of the next line and performs the processing from step S102 to step S105. On the other hand, when the phase control unit 24 determines that all the lines of the RAW data have been read (NO side), the phase processing by the series of data transfer devices 100 ends.

  The above is the description of the phase adjustment process in the data transfer apparatus 100.

  Next, as described above, a procedure in which the data transfer apparatus 100 obtains an adjustment amount for phase adjustment in the phase adjustment unit 21 in step S102 of FIG. 5 will be described with reference to the flowchart of FIG. In this embodiment, when the imaging device 10 of the imaging unit 1 outputs each line of the RAW data, the SAV synchronization code added to the head of each line has four 8 bits (= 4 bytes). It is assumed that a code “0xff0000ff” consisting of

  Step S201: As described above, the shift unit 22 receives the data signal phase-adjusted for each RAW data line in the phase adjustment unit 21 in Step S101 (FIG. 7A), and the synchronization added to the head. When the code SAV is detected, the delay element 40 is used for the synchronization signal of the synchronization code SAV, and a predetermined amount of + shift, 1/4 shift, and a predetermined amount of −for 1/4 period of the clock signal. A shifted synchronization signal is generated and transmitted to the selector 42. At the same time, as shown in FIG. 7A, when the counter unit 25 detects the synchronization code SAV of each line, the counter unit 25 determines that a data signal of a new line of RAW data has been input and counts it. The counter unit 25 determines whether or not the count value is an odd number. The counter unit 25 proceeds to step S202 (YES side) when the count is an odd number, and proceeds to step S203 (NO side) when the count is an even number. The clock signal is shifted by 0 in the shift unit 22 and output to the shift determination unit 23 as described above.

  7A, the data signal of each line of the RAW data whose phase is adjusted in the phase adjustment unit 21 in step S101 and the 4-byte synchronization code SAV is added to the head is sent to the shift unit 22. This is a schematic representation of how it is transferred. Data 50 indicates a blank area, image data, and EAV data of each line following the synchronization code SAV.

  Step S202: The selector 42 of the shift unit 22 outputs the synchronization signal of the synchronization code SAV shifted by + to the shift determination unit 23.

  Step S203: The selector 42 of the shift unit 22 outputs the synchronization signal of the -shifted synchronization code SAV to the shift determination unit 23.

  Step S204: The shift determination unit 23 obtains a shift amount between the clock signal that is the reference signal and the synchronization signal that has been + shifted or −shifted by the shift unit 22 in step S201. Based on the shift amount, the shift determination unit 23 determines whether or not it is necessary to change the adjustment amount for phase adjustment of the phase adjustment unit 21 by the phase control unit 24 (abnormality detection). In the present embodiment, for example, when the shift amount is smaller than one cycle of the clock signal (for example, the synchronization signal on the first line in FIG. 7B), the shift determination unit 23 receives the clock signal and the data signal. Is determined to be normally synchronized and the process proceeds to step S206 (NO side). On the other hand, when the shift amount is equal to or longer than one cycle of the clock signal (for example, the synchronization signal on the second line or the third line in FIG. 7B), the shift determination unit 23 determines that the clock signal and the data signal are It determines with not synchronizing normally, and transfers to step S205 (YES side).

  Step S205: The shift determination unit 23 generates a code based on the synchronization code SAV in order to hold the information on the shift amount and the shifted direction of the synchronization signal with respect to the clock signal obtained in Step S204, and the phase control unit 24 Send to. Specifically, the shift determination unit 23 performs four cycles of “0xff0000ff”, which is the same as the synchronization code SAV, for one cycle with respect to the clock signal, for example, the synchronization signal on the third line in FIG. If the shift is in the + direction, the code “0xfe0001fe” is generated by shifting it to the left by 1 bit (FIG. 7C). Then, the shift determination unit 23 transmits the code as a code indicating the phase adjustment flag ON to the phase control unit 24 (FIG. 7D). Similarly, the shift determination unit 23 shifts the clock signal by one cycle to the right by one bit when the clock signal is shifted in the negative direction by about one cycle like the second line synchronization signal in FIG. 7B. A code “0x7f80007f” is generated (FIG. 7C). The shift determination unit 23 transmits the code indicating the phase adjustment flag ON to the phase control unit 24 (FIG. 7D).

  Step S206: The shift determination unit 23 transmits a code of “0xff0000ff”, which is the same as the synchronization code SAV, to the phase control unit 24 as a code indicating the phase adjustment flag OFF (first line in FIGS. 7C and 7D). Synchronization signal).

  Step S207: The temperature monitoring unit 27 measures the temperature of the data transfer apparatus 100 and records it in the storage unit 27 when the counter unit 25 counts based on the reception of the synchronization code SAV in Step S201. Then, the data transfer apparatus 100 proceeds to step S103.

  The above is the procedure in which the data transfer apparatus 100 obtains the adjustment amount for phase adjustment in the phase adjustment unit 21 in step S102.

  As described above, in this embodiment, the synchronization signal of the synchronization code SAV added for each line of the RAW data is shifted + shift or −shift with respect to the clock signal as the reference signal to determine the synchronization state. Therefore, even if the clock signal and the data signal of the RAW data are set so as to be synchronized in consideration of the temperature, wiring, etc. in the manufacturing stage, it can be performed at high speed in real time according to the subsequent use environment. Phase adjustment can be performed.

Further, since the phase state is monitored for each line, the phase adjustment can be finely adjusted frequently.
≪Supplementary items of embodiment≫
In the present embodiment, in step S104, the phase control unit 24 maintains the setting of the adjustment amount of the phase adjustment for the phase adjustment unit 21 based on the phase adjustment flag ON / OFF, which is the determination result by the shift determination unit 23. Although changes have been made, the present invention is not limited to this. For example, in step S207 of step S102, triggered by the count in the counter unit 25, the temperature of the data transfer device 100 measured and monitored by the temperature monitoring unit 26 is recorded in the storage unit 27 and shifted in correspondence with the temperature. If the phase adjustment flag ON / OFF that is the determination result of the determination unit 23 is also recorded, for example, as shown in FIG. 8, the horizontal axis indicates the temperature, and the vertical axis indicates the number of times the phase adjustment flag is turned ON or OFF. A histogram can be created. In step S <b> 104, the phase control unit 24 determines whether or not to perform phase adjustment for the phase adjustment unit 21, along with the determination result of the shift determination unit 23, of the data transfer device 100 measured by the temperature monitoring unit 26. The temperature is determined from, for example, the histogram of FIG. 8, and the temperature range (range B) corresponding to a temperature range (range A) in which only the phase adjustment flag OFF is set or the number of times of the phase adjustment flag ON is equal to or less than a predetermined number. ) Is also determined. The phase control unit 24 adjusts the adjustment amount of the phase adjustment with respect to the phase adjustment unit 21 according to the determination results (for example, the determination result of the shift determination unit 23 is the phase adjustment flag ON, but the data transfer apparatus 100 In the range A or range B, the adjustment amount of the phase adjustment unit 21 is maintained), so that not only the determination result of the shift determination unit 23 but also the temperature state It is possible to perform more flexible phase adjustment of the data transfer apparatus 100 in consideration.

  Further, by using the histogram as shown in FIG. 8, the phase control unit 24 performs the phase adjustment performed for each line, the data signal for every several lines or tens of lines, or the raw data of the image. The phase adjustment can be performed based on the data signal of only the first line, and the phase adjustment can be performed at higher speed in real time.

  In the present embodiment, the phase adjustment for the phase adjustment unit 21 by the phase control unit 24 is performed based on the determination result of the shift determination unit 23 for each line, and is applied to the data signal of the line to be read next. However, the present invention is not limited to this. For example, when it is expected that there is no large temperature change in the data transfer apparatus 100 while reading RAW data of one image, the phase adjustment by the phase control unit 24 is performed only for the first line of each RAW data. The phase of the unit 21 may be adjusted.

  In this embodiment, the + shift by the shift unit 22 is applied to the data signal of the odd line, and the -shift is applied to the data signal of the even line. However, the present invention is not limited to this. Alternatively, a + shift may be applied to even line data signals and a -shift may be applied to odd line data signals.

  In this embodiment, the predetermined amount of + shift or −shift by the shift unit 22 is set to ¼ period of the frequency of the clock signal. However, the present invention is not limited to this, and required phase adjustment is performed. It can be determined as appropriate according to the accuracy and processing speed.

  In the present embodiment, in step S204, the shift determination unit 23 uses a shift amount as a reference for determining whether or not the phase adjustment unit 21 needs to adjust the phase by the phase control unit 24 as one cycle of the clock signal. However, the present invention is not limited to this, and can be appropriately determined according to the required phase adjustment accuracy and processing speed.

  In the present embodiment, a line in the horizontal scanning direction is used as a direction for reading out the RAW data line of the image. However, the present invention is not limited to this, and the line may be read out for each line in the vertical scanning direction. However, in this case, the synchronization codes SAV and EAV for each line need to be added in the horizontal scanning direction.

  In this embodiment, the description of the synchronization code SAV added to the head of each line of the RAW data is “0xff0000ff”, but the present invention is not limited to this, and the required phase adjustment accuracy and Depending on the processing speed or the like, a code consisting of four 16 bits or the like can be used as the synchronization code SAV. Also, the content described in the synchronization code SAV is not limited to “0xff0000ff”, and any content may be described as long as it is a known content.

  In the present embodiment, the RAW data format shown in FIG. 5 is used. However, the present invention is not limited to this, and for example, the formats shown in FIGS. 9A to 9C. The present invention can also be applied to RAW data of images having the above.

  Note that, in the present embodiment, only an image to which a known synchronization code SAV is added as data to be transferred by the data transfer apparatus 100 has been described, but the present invention is not limited to this. For example, when transferring data other than an image to which a known synchronization code or character string is added in advance, the present invention can be applied to the present invention provided in a computer, a printer, or the like.

  The present invention can be implemented in various other forms without departing from the spirit or main features thereof. For this reason, the above-described embodiment is merely an example in all respects and should not be construed in a limited manner. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

CLK clock signal line, DATA data signal line, 1 imaging unit, 10 imaging device, 20 signal processing circuit, 21 phase adjustment unit, 22 shift unit, 23 shift determination unit, 24 phase control unit, 25 counter unit, 26 temperature monitoring unit 27 Memory unit 28 Image processing unit 30, 40 Delay element 31, 41 path 32, 42 Selector 100 Data transfer device

Claims (7)

A phase adjustment unit that receives a signal of image data having a known synchronization code together with a reference signal, and performs phase adjustment of the signal of the image data with respect to the reference signal;
A shift unit that shifts the synchronization signal of the known synchronization code among the received signals of the image data by a predetermined amount smaller than one cycle of the reference signal ;
A shift determination unit that compares the shifted synchronization signal and the reference signal to determine whether the amount of deviation is within a predetermined range;
A phase control unit that controls an adjustment amount for the phase adjustment in the phase adjustment unit based on a determination result by the shift determination unit;
A data transfer device comprising: The data transfer device according to claim 1, wherein
A data transfer apparatus wherein the reference signal and the signal of the image data, characterized in that you have been received in synchronism. In the data transfer device according to claim 1 or 2 ,
The shift determining portion, the shift amount is the determination result in whether the predetermined range, Ru comprise code generating unit to be transmitted to the phase control unit generates a code associated with the known synchronization code A data transfer device. The data transfer device according to claim 2 , wherein
A counter unit that counts the number of received synchronization codes of the image data or the number of the image data;
The shift unit, depending on the number of the counter, on the image data signal to the reference signal, Ru is the predetermined shift amount in advance or retard direction
Data transfer apparatus according to claim and this. The data transfer device according to any one of claims 1 to 4, wherein
A temperature monitoring unit for measuring and monitoring the temperature of the data transfer device;
A storage unit that records the determination result of the shift determination unit in association with the temperature together with the temperature measured and monitored by the temperature monitoring unit;
The phase control unit is configured such that, based on the recorded temperature and the determination result associated with the temperature, the number of determination results in which the deviation amount is determined to be out of a predetermined range is equal to or less than a predetermined number. When a temperature range is determined and the temperature measured and monitored by the temperature monitoring unit is within the temperature range, the adjustment amount in the phase adjustment unit is maintained, and the temperature is not within the temperature range The data transfer device is characterized in that the adjustment amount in the phase adjustment unit is changed. A phase adjustment unit that receives a data signal together with a reference signal and performs phase adjustment of the data signal with respect to the reference signal;
A shift unit that shifts the received signal of the data by a predetermined amount smaller than one cycle of the reference signal ;
A shift determination unit that compares the shifted signal of the data with the reference signal to determine whether the amount of deviation is within a predetermined range;
A phase control unit that controls an adjustment amount for the phase adjustment in the phase adjustment unit based on the determination by the shift determination unit;
A data transfer device comprising: An imaging unit that images a subject and generates and outputs an image;
A data transfer device according to any one of claims 1 to 5,
An imaging apparatus comprising:

Images