JP5422718B2 - Wiring board and semiconductor package - Google Patents

Description

  The present invention relates to a wiring board and a semiconductor package.

  Conventionally, a semiconductor package in which a semiconductor chip is mounted on a wiring board via solder bumps or the like is known. In such a semiconductor package, it is extremely important to improve the connection reliability between the wiring board and the semiconductor chip. In the conventional semiconductor package, in order to improve the connection reliability between the wiring board and the semiconductor chip, for example, the wiring board is provided with a metal layer (projecting part) protruding from one surface of the wiring board, and the protruding metal A solder bump is formed on the layer. Hereinafter, an example of a conventional wiring board provided with a metal layer protruding from one surface of the wiring board will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an example of a conventional wiring board. Referring to FIG. 1, a wiring substrate 100 includes a first insulating layer 130a, a second insulating layer 130b, a third insulating layer 130c, a first wiring layer 140a, a second wiring layer 140b, and a protruding metal layer. 160 and solder bumps 170.

  In the wiring substrate 100, a first wiring layer 140a and a second wiring layer 140b are formed on the second insulating layer 130b, and the first wiring layer 140a and the second wiring layer 140b are electrically connected via the first via hole 150a. It is connected. A first insulating layer 130a having an opening 130x exposing a part of the first wiring layer 140a is formed on one surface of the second insulating layer 130b so as to cover the first wiring layer 140a.

  A third insulating layer 130c is formed on the other surface of the second insulating layer 130b so as to cover the second wiring layer 140b. A protruding metal layer 160 that partially protrudes from one surface 100a of the wiring substrate 100 is formed in the opening 130y of the third insulating layer 130c. The protruding metal layer 160 includes a Cu layer 161 and a Ni layer 162. The Cu layer 161 protrudes approximately 30 μm from one surface 100 a of the wiring substrate 100, and a Ni layer 162 having a thickness of approximately 5 μm is formed on the surface of the Cu layer 161. The Cu layer 161 and the second wiring layer 140b are electrically connected through the second via hole 150b. Solder bumps 170 are formed on the protruding metal layer 160.

  Then, the manufacturing method of the wiring board 100 is demonstrated. 2-6 is a figure which shows the example of the manufacturing process of the conventional wiring board. 2 to 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, in the step shown in FIG. 2, a carrier metal (metal plate) 110 made of SUS and having a thickness of about 500 μm is prepared. Then, an etching resist layer 120a having a predetermined pattern having an opening 120x at a position corresponding to the protruding metal layer 160 of the wiring board 100 is formed on the surface 110a of the prepared carrier metal 110 by a known photolithography method. A solid etching resist layer 120b is formed on the back surface 110b of the carrier metal 110.

  Next, in the step shown in FIG. 3, an etching solution for dissolving SUS is sprayed to etch the surface 110a of the carrier metal 110 exposed in the opening 120x of the etching resist layer 120a. Then, a recess 110x having a substantially circular shape in plan view and a depth of about 20 μm is formed on the surface 110a of the carrier metal 110.

  Next, in the step shown in FIG. 4, a protruding metal layer 160a protruding beyond the surface 110a from the inside of the recess 110x of the carrier metal 110 is formed. Specifically, first, in the Au plating step, electrolytic Au plating is performed to form an Au plating layer 163 having a thickness of about 0.5 μm on the inner wall surface of the recess 110x. Thereafter, in the Ni plating step, electrolytic Ni plating is performed to form a Ni plating layer 162 having a thickness of about 5 μm on the surface of the Au plating layer 163.

  Further, electrolytic Cu plating is performed to form a Cu layer 161 having a thickness (height) of about 30 μm on the surface of the Ni layer 162, and the hole formed by the Ni layer 162 is filled with the Cu layer 161. In this step, it is preferable to use a Cu electrolytic plating solution for forming filled vias in order to easily fill the holes formed by the Ni layer 162. Through these three plating steps, the protruding metal layer 160a composed of the Au layer 163, the Ni layer 162, and the Cu layer 161 is formed. The protruding metal layer 160a is obtained by forming the Au plating layer 163 on the protruding metal layer 160.

  Next, in the step shown in FIG. 5, after the etching resist layers 120a and 120b shown in FIG. 4 are removed, the surface 110a and the protruding metal layer 160a of the carrier metal 110 are applied to the protruding metal layer 160a by a known method. A third insulating layer 130c having an opening 130y and a second via hole 150b, and a Cu layer 161 constituting a protruding metal layer 160a on the third insulating layer 130c via the second via hole 150b; A second wiring layer 140b that is electrically connected is formed.

  Next, a second insulating layer 130b having a first via hole 150a is formed on the third insulating layer 130c so as to cover the second wiring layer 140b. Further, the first wiring layer 140a electrically connected to the second wiring layer 140b through the first via hole 150a is formed on the second insulating layer 130b. Further, a first insulating layer 130a having an opening 130x exposing a part of the first wiring layer 140a is formed on the second insulating layer 130b so as to cover the first wiring layer 140a.

  Next, in the step shown in FIG. 6, the entire carrier metal 110 shown in FIG. 5 is removed by etching, and the protruding metal layer 160a and the entire one surface 100a of the wiring substrate 100 are exposed. Next, solder bumps 170 are formed on the protruding metal layer 160a (see FIG. 1). At this time, since the Au plating layer 163 diffuses into the solder, the solder bump 170 is formed on the Ni layer 162 (on the protruding metal layer 160). In this way, the wiring substrate 100 shown in FIG. 1 is manufactured.

  As described above, the wiring board 100 has the protruding metal layer 160 protruding beyond the one surface 100a of the wiring board 100 from the opening 130y of the third insulating layer 130c. A solder bump 170 is formed on the protruding metal layer 160.

  FIG. 7 is a cross-sectional view showing another example of a conventional wiring board. Referring to FIG. 7, the wiring substrate 200 includes an etching stop layer 210b, a first wiring layer 220, a Cu layer 240, a second wiring layer 250, a Ni layer 260, a first insulating layer 270, a first insulating layer 270, and a first insulating layer 270. Two insulating layers 270a, protruding metal layers 280, reinforcing portions 290, and solder bumps 300 are provided.

  In the wiring substrate 200, the first wiring layer 220 and the second wiring layer 250 are formed on the first insulating layer 270, and the first wiring layer 220 and the second wiring layer 250 are interposed via the Cu layer 240 and the Ni layer 260. Electrically connected. An etching stop layer 210b is formed on the first wiring layer 220, and a protruding metal layer 280 protruding from one surface 200a of the wiring substrate 200 is formed on the etching stop layer 210b. Further, solder bumps 300 are formed on the protruding metal layer 280. On the first insulating layer 270, a second insulating layer 270a having an opening 270x exposing a part of the second wiring layer 250 is formed so as to cover the second wiring layer 250.

  Then, the manufacturing method of the wiring board 200 is demonstrated. 8 to 12 are diagrams showing another example of the manufacturing process of the conventional wiring board. 8 to 12, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, in the process shown in FIG. 8, a metal substrate 210 having a three-layer structure is prepared. The metal substrate 210 includes a metal layer 210a, an etching stop layer 210b, and a metal layer 210c. The metal layer 210a is made of copper or a copper alloy, and is a metal film having a thickness of about 80 to 150 μm, for example. The etching stop layer 210b is made of a material that can have a sufficient etching selectivity with respect to copper or a copper alloy in etching with respect to copper or a copper alloy (for example, etching using a hydrochloric acid-based etching solution). The metal layer 210c is a thin metal film made of copper laminated on the surface of the etching stop layer 210b, and later becomes the first wiring layer 220.

  Next, in a step shown in FIG. 9, the first wiring layer 220 is formed by patterning the metal layer 210c of the metal substrate 210 having a three-layer structure by photoetching. Then, a circuit forming substrate 230 is prepared, and the circuit forming substrate 230 is aligned with the metal substrate 210. The circuit forming substrate 230 is a substrate in which a Ni layer 260 and a Cu layer 240 are stacked in this order on a metal layer 210d and covered with a first insulating layer 270. However, the Cu layer 240 is exposed from the first insulating layer 270. The metal layer 210d will later become the second wiring layer 250.

  Next, in the step shown in FIG. 10, the circuit forming substrate 230 is laminated on the metal substrate 210. Specifically, the Cu layer 240 of the circuit forming substrate 230 is laminated by thermocompression bonding to the first wiring layer 220 of the metal substrate 210 via the first insulating layer 270. A portion other than the Cu layer 240 is bonded to the circuit forming substrate 230 and the metal substrate 210 via an insulating layer 270.

  Next, in the step shown in FIG. 11, the second wiring layer 250 is formed by photo-etching the metal layer 210d of the circuit forming substrate 230. Then, a second insulating layer 270 a having an opening 270 x exposing a part of the second wiring layer 250 is formed on the first insulating layer 270 so as to cover the second wiring layer 250. Ni plating, Au plating, or the like may be performed on the second wiring layer 250 exposed from the opening 270x.

  Next, in the process shown in FIG. 12, the protruding metal layer 280 and the reinforcing portion 290 are formed by selectively etching the metal layer 210a made of copper shown in FIG. 11 from the back surface side. Reference numeral 300 denotes a solder film (thickness, for example, 10 to 50 μm) used as an etching mask in the selective etching, which is formed by plating. Since the solder film 300 can be patterned by selectively removing it by alkali etching using a resist layer or the like as a mask, it can be used as an etching mask in the etching for forming the protruding metal layer 280 and the reinforcing portion 290. Next, a reflow process is performed on the solder film 300 to form solder bumps 300, whereby the wiring substrate 200 shown in FIG. 7 is manufactured.

  Thus, the wiring board 200 has the protruding metal layer 280 that protrudes from the one surface 200a of the wiring board 200. A solder bump 300 is formed on the protruding metal layer 280.

JP 2003-218286 A JP 2002-43506 A JP 2001-177010 A

  However, the protruding metal layer formed on the conventional wiring board has an effect of functioning as a reliable connection terminal having a sufficient height. On the other hand, if this effect is maintained, an adjacent protruding metal layer is used. There has been a problem that it is difficult to narrow the interval of. Hereinafter, this problem will be described with reference to the drawings.

  In FIG. 3 and the like described above, the recess 110x formed by etching the carrier metal 110 is drawn in a rectangular shape in cross section, but it is known that it does not actually have a rectangular shape in cross section. FIG. 13 is a cross-sectional view illustrating the actual shape of the recess formed by etching. As shown in FIG. 13, the cross section parallel to the XZ plane of the recess 110y formed by etching is not a rectangular shape like the recess 110x, but a dome shape.

Further, since the etching proceeds not only in the Z direction but also in the X direction and the Y direction, if the opening 120x is circular in plan view (as viewed from the Z direction), the maximum of the recess 110y of the etching resist layer 120a is maximum. diameter phi ₁ is larger than the diameter phi ₂ of the opening 120x. Further, the maximum diameter phi ₁ of the recess 110y increases as deepening the maximum depth _{D 1} of the recess 110y. This becomes a problem particularly when the pitch of the adjacent concave portions 110y becomes narrow. This will be described with reference to FIG.

FIG. 14 is a cross-sectional view illustrating a state in which the pitch of adjacent concave portions in FIG. 13 is narrowed. As shown in FIG. 14, the pitch _{P 1} between adjacent concave portions 110y becomes narrower, the higher the possibility that the adjacent recesses 110y come into contact with each other. For adjacent recesses 110y each other to avoid contact must shallower maximum depth D _1. As described above, it is difficult to increase the aspect ratio (D ₁ / φ ₁ ) of the recess 110 y formed by etching. That is, since the protruding metal layer 160 is formed in the recess 110y, it is difficult to increase the aspect ratio of the protruding metal layer 160.

  Further, since the protruding metal layer 280 of the wiring substrate 200 is also formed by etching in the same manner as the recess 110x of the wiring substrate 100, the cross section thereof does not become rectangular as shown in FIG. As shown in FIG. 7 and the like, the diameter of the upper surface of the protruding metal layer 280 is smaller than the diameter of the lower surface (etching stop layer 210b side). Therefore, when the area of the upper surface of the protruding metal layer 280 is increased in order to improve connection reliability, there is a high possibility that adjacent protruding metal layers 280 come into contact with each other. In order to prevent the adjacent protruding metal layers 280 from contacting each other, the height of the protruding metal layer 280 must be reduced. Therefore, it is difficult to increase the aspect ratio of the protruding metal layer 280 formed by etching.

  As described in detail above, in the conventional method for manufacturing a wiring board, the protruding metal layer is formed by etching, so that the cross section of the protruding metal layer is not rectangular and it is difficult to increase the aspect ratio. As a result, if the protruding metal layer is caused to function as a connection terminal having a sufficient height and high connection reliability, it is impossible to realize a narrow pitch between adjacent protruding metal layers. On the other hand, if an attempt is made to reduce the pitch between adjacent protruding metal layers, the height of the protruding metal layer cannot be sufficiently secured, and the connection reliability is lowered.

  In view of the above, it is an object of the present invention to provide a wiring board having a connection terminal that has high connection reliability and can cope with a narrow pitch, and a semiconductor package having the wiring board.

One form of the present wiring board includes one surface and the other surface which is the opposite surface, and an insulating layer disposed on the outermost layer so that the other surface is the surface of the wiring substrate; and has a columnar protrusion protruding from the other surface, wherein the protrusions have a top surface and a bottom surface, covered the lower surface of the front Symbol lower and side surfaces within the insulation layer, wherein the upper surface side of the insulating layer A connection terminal projecting from the other surface, wherein the projecting portion includes a second metal layer and a third metal layer, wherein the third metal layer is partially embedded in the insulating layer, and the remaining portion is the insulating layer The portion of the third metal layer embedded in the insulating layer has a rectangular cross section in the upper surface and lower surface directions, and protrudes from the other surface of the insulating layer of the third metal layer. The cross-sections in the upper and lower surface directions of the portion that has been buried are embedded in the insulating layer of the third metal layer And the second metal layer covers the upper surface and the side surface of the portion of the third metal layer protruding from the other surface of the insulating layer. The insulating layer is provided with a via hole that exposes the lower surface of the protruding portion, and a wiring layer connected to the lower surface of the protruding portion via the via hole is provided on one surface of the insulating layer. Is a requirement.

  According to the disclosed technology, it is possible to provide a wiring board having a connection terminal that has high connection reliability and can cope with a narrow pitch, and a semiconductor package having the wiring board.

It is sectional drawing which shows the example of the conventional wiring board. It is FIG. (1) which shows the example of the manufacturing process of the conventional wiring board. It is FIG. (2) which shows the example of the manufacturing process of the conventional wiring board. It is FIG. (3) which shows the example of the manufacturing process of the conventional wiring board. It is FIG. (4) which shows the example of the manufacturing process of the conventional wiring board. It is FIG. (5) which shows the example of the manufacturing process of the conventional wiring board. It is sectional drawing which shows the other example of the conventional wiring board. It is FIG. (1) which shows the other example of the manufacturing process of the conventional wiring board. It is FIG. (2) which shows the other example of the manufacturing process of the conventional wiring board. It is FIG. (3) which shows the other example of the manufacturing process of the conventional wiring board. It is FIG. (4) which shows the other example of the manufacturing process of the conventional wiring board. It is FIG. (5) which shows the other example of the manufacturing process of the conventional wiring board. It is sectional drawing which illustrates the actual shape of the recessed part formed by the etching. It is sectional drawing which illustrates a mode that the pitch of the adjacent recessed part in FIG. 13 became narrow. It is sectional drawing which illustrates the wiring board which concerns on 1st Embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 9 is a diagram (No. 4) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 14 is a view (No. 7) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 8) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 9) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a view (No. 10) illustrating the manufacturing step of the wiring board according to the first embodiment; FIG. 11 is a diagram (No. 11) illustrating the manufacturing process of the wiring substrate according to the first embodiment; FIG. 12 is a view (No. 12) illustrating the manufacturing step of the wiring board according to the first embodiment; It is FIG. (The 13) which illustrates the manufacturing process of the wiring board which concerns on 1st Embodiment. It is FIG. (The 14) which illustrates the manufacturing process of the wiring board which concerns on 1st Embodiment. FIG. 18 is a view (No. 15) illustrating the manufacturing step of the wiring board according to the first embodiment; It is sectional drawing which illustrates the wiring board which concerns on 2nd Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. FIG. 9 is a second diagram illustrating a manufacturing process of a wiring board according to the second embodiment; It is FIG. (The 3) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. FIG. 11 is a diagram (No. 4) for exemplifying the manufacturing process for the wiring board according to the second embodiment; It is sectional drawing which illustrates the wiring board which concerns on 3rd Embodiment. It is sectional drawing which illustrates the wiring board which concerns on 4th Embodiment. 10 is a cross-sectional view illustrating a semiconductor package according to a fifth embodiment; FIG. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on 5th Embodiment. It is FIG. (The 2) which illustrates the manufacturing process of the semiconductor package which concerns on 5th Embodiment. It is sectional drawing which illustrates the semiconductor package which concerns on 6th Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.

<First Embodiment>
The first embodiment shows an example in which the present invention is applied to a wiring board having a multilayer wiring layer (build-up wiring layer).

[Structure of Wiring Board According to First Embodiment]
First, the structure of the wiring board according to the first embodiment will be described. FIG. 15 is a cross-sectional view illustrating the wiring board according to the first embodiment. Referring to FIG. 15, the wiring substrate 10 includes a first insulating layer 12a, a second insulating layer 12b, a third insulating layer 12c, a first wiring layer 13a, a second wiring layer 13b, and a third wiring. The wiring board includes a buildup wiring layer having a layer 13 c, a solder resist layer 14, a connection terminal 16, and a fourth metal layer 17.

  A connection terminal 16 that functions as a connection terminal connected to the semiconductor chip is formed on one surface 10a side of the wiring substrate 10. The connection terminal 16 is a solder formed so as to cover a protruding metal layer 11 partially protruding from one surface 10 a of the wiring substrate 10 and a portion of the protruding metal layer 11 protruding from one surface 10 a of the wiring substrate 10. And a bump 15. The protruding metal layer 11 includes a second metal layer 11a and a third metal layer 11b. Hereinafter, the portion of the protruding metal layer 11 protruding from the one surface 10a of the wiring substrate 10 may be referred to as a protruding portion 11x for convenience. Further, the surface of the protruding portion 11x opposite to the surface in contact with the first insulating layer 12a may be referred to as a surface 11y. The surface 11y is a portion where the protruding portion 11x comes into contact with the electrode pad of the semiconductor chip via solder when the semiconductor chip is mounted on the wiring substrate 10.

  A first wiring layer 13a is formed on the first insulating layer 12a (on the side opposite to the formation surface of the protruding portion 11x). Further, a second insulating layer 12b is formed so as to cover the first wiring layer 13a and the first insulating layer 12a, and a second wiring layer 13b is formed on the second insulating layer 12b. Further, a third insulating layer 12c is formed so as to cover the second wiring layer 13b and the second insulating layer 12b, and a third wiring layer 13c is formed on the third insulating layer 12c.

  The first wiring layer 13a and the third metal layer 11b constituting the protruding metal layer 11 are electrically connected through a first via hole 12x formed in the first insulating layer 12a. The first wiring layer 13a and the second wiring layer 13b are electrically connected through a second via hole 12y formed in the second insulating layer 12b. The second wiring layer 13b and the third wiring layer 13c are electrically connected through a third via hole 12z formed in the third insulating layer 12c.

  A solder resist layer 14 having an opening 14x is formed so as to cover the third wiring layer 13c and the third insulating layer 12c. A fourth metal layer 17 is formed on the third wiring layer 13 c exposed in the opening 14 x of the solder resist layer 14. The fourth metal layer 17 functions as an electrode pad connected to a motherboard or the like.

In the wiring board 10, the protruding portion 11 x has a rectangular cross section parallel to the XZ plane, unlike the protruding metal layer (dome shape or the like) of the conventional wiring board. While the protrusion amount _{L 10} from the surface 10a of the wiring substrate 10 of the protruding portion 11x may be, for example 30 to 50 [mu] m. The shape of the protruding portion 11x may be, for example, a cylindrical (e.g., diameter φ ₁₀ = φ60~70μm surface 11y). Pitch _{P 10} of the protruding portion 11x may be, for example 150 [mu] m. However, the shape of the protrusion 11x is not limited to a columnar shape, and may be a columnar shape. That is, the shape of the protruding portion 11x is not a columnar shape, and may be, for example, an elliptical column shape or a rectangular column shape (a square column, a hexagonal column, or the like). In addition, in this application, column shape means the solid which has the upper surface and lower surface (bottom surface) of substantially parallel and substantially the same area.

  As a material of the second metal layer 11a constituting the protruding metal layer 11, for example, Au can be used. The second metal layer 11a constituting the protruding metal layer 11 is composed of a Ni / Au layer in which a Ni layer and an Au layer are laminated from the side of the third metal layer 11b constituting the protruding metal layer 11, or a Ni layer and a Pd layer. And a Ni / Pd / Au layer in which an Au layer is laminated. For example, Cu or the like can be used as the material of the third metal layer 11b constituting the protruding metal layer 11. As a material of the solder bump 15, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

In this way, since the protrusion 11x has a rectangular cross section parallel to the XZ plane, the aspect ratio (L ₁₀ / φ ₁₀ ) can be increased, and a connection terminal that can cope with a narrow pitch is realized. be able to. Further, since the projecting portion 11x has a rectangular cross section parallel to the XZ plane, the area of the surface 11y that becomes a portion that contacts the electrode pad of the semiconductor chip through solder when mounting the semiconductor chip can be increased. A connection terminal with high connection reliability can be realized. The above is the structure of the wiring board according to the first embodiment.

[Method for Manufacturing Wiring Board According to First Embodiment]
Next, a method for manufacturing a wiring board according to the first embodiment will be described. 16 to 30 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. 16 to 30, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, in the step shown in FIG. 16, a support 21 is prepared. Reference numeral 21 a denotes one surface of the support 21. In this embodiment, Cu foil is used as the support 21. The thickness of the support body 21 can be 35-100 micrometers, for example. Next, in the step shown in FIG. 17, a resist layer 22 is formed on one surface 21a of the support 21 (actually, the surface opposite to the one surface 21a of the support 21 is also covered with the resist layer). . For example, a dry film can be used as the resist layer 22. The thickness of the resist layer 22 can be set to, for example, 30 to 50 μm.

Next, in the process shown in FIG. 18, a patterning process is performed on the resist layer 22, leaving only the resist layer 22 corresponding to the formation position of the protruding metal layer 11, and removing the resist layer 22 in other portions. . The shape of the remaining resist layer 22 can be, for example, a columnar shape (for example, a cross-sectional diameter φ ₁₀ = φ60 to 70 μm). However, the shape of the remaining resist layer 22 is not limited to a columnar shape, and may be a columnar shape. That is, the shape of the remaining resist layer 22 is not a columnar shape, but may be, for example, an elliptical column shape or a rectangular column shape (a square column, a hexagonal column, or the like). The pitch _{P 10} of the remaining resist layer 22 may be, for example, 150 [mu] m.

Next, in the step shown in FIG. 19, the first metal layer 23 is formed on one surface 21 a of the support 21 by an electrolytic plating method using the support 21 as a plating power feeding layer. The first metal layer 23 is formed in a region where the resist layer 22 of the one surface 21a of the support 21 is not formed. Since the first metal layer 23 is removed by etching together with the support 21 in the step shown in FIG. 30 described later, the support 21 and the first metal layer 23 are made of a material that can be removed by the same etching solution. It is preferable. Specifically, since Cu foil is used as the support 21 in the present embodiment, the material of the first metal layer 23 is preferably Cu. The thickness _{T 10} of the first metal layer 23 may be, for example 30 to 50 [mu] m. The thickness _{T 10} of the first metal layer 23, determines the amount of protrusion _{L 10} from one surface 10a of the wiring substrate 10 of the protruding portion 11x. That is, while the protruding amount _{L 10} from the surface 10a of the wiring substrate 10 of the protruding portion 11x is made substantially the same as the thickness _{T 10} of the first metal layer 23.

  Next, in a step shown in FIG. 20, the resist layer 22 shown in FIG. 19 is removed to form an opening 23x. As a result, the first metal layer 23 having the opening 23x which is a columnar through hole exposing the one surface 21a of the support 21 is formed on the one surface 21a of the support 21. Next, in a step shown in FIG. 21, a resist layer 24 is formed on the first metal layer 23. In the resist layer 24, an opening having a shape corresponding to the opening 23x is formed. As the resist layer 24, for example, a dry film or the like can be used. The thickness of the resist layer 24 can be set to 30 to 50 μm, for example.

  Next, in the step shown in FIG. 22, the second metal layer 11a and the third metal layer 11b are formed in this order in the opening 23x by an electrolytic plating method using the support 21 and the first metal layer 23 as a plating power feeding layer. The protruding metal layer 11 is formed by stacking. The second metal layer 11a is formed so as to cover one surface 21a of the support 21 exposed from the opening 23x and the inner wall surface of the opening 23x. The third metal layer 11b is formed on the second metal layer 11a so as to completely fill at least the opening 23x. As a material of the second metal layer 11a, for example, Au or the like can be used. For example, Cu or the like can be used as the material of the third metal layer 11b (FIG. 22A).

  The second metal layer 11a may have a structure in which a plurality of metal layers made of different materials are stacked. FIG. 22B is an example of the second metal layer 11a having a structure in which a plurality of metal layers made of different materials are stacked. In the second metal layer 11a shown in FIG. 22B, for example, the metal layer 11c is an Au layer (for example, layer thickness≈1 μm), the metal layer 11d is a Pd layer (for example, layer thickness≈1 μm), and the metal layer 11e is an Ni layer ( For example, the layer thickness can be approximately 5 μm). Another example of the second metal layer 11a having a structure in which a plurality of metal layers made of different materials are stacked includes an Au / Ni layer in which an Au layer and a Ni layer are stacked in this order.

  Next, in a step shown in FIG. 23, the resist layer 24 shown in FIG. 22 is removed. Next, in the step shown in FIG. 24, the first insulating layer 12 a is formed on the first metal layer 23 so as to cover the third metal layer 11 b constituting the protruding metal layer 11. As a material of the first insulating layer 12a, a resin material such as an epoxy resin or a polyimide resin can be used. As an example of a method for forming the first insulating layer 12a, after laminating a resin film on the first metal layer 23, the resin film is pressed (pressed) and then heat-treated at a temperature of about 190 ° C. to be cured. Thus, the first insulating layer 12a can be obtained.

  Next, in the step shown in FIG. 25, the first insulating layer 12a formed on the support 21 is first exposed so that the third metal layer 11b constituting the protruding metal layer 11 is exposed using a laser processing method or the like. A first via hole 12x that penetrates the insulating layer 12a is formed. Alternatively, a method may be used in which a photosensitive resin film is used as the first insulating layer 12a and is patterned by photolithography to form the first via hole 12x, or a resin film provided with an opening is patterned by screen printing. Alternatively, a method of forming the first via hole 12x may be used.

  Next, in the step shown in FIG. 26, the first wiring layer 13a electrically connected to the third metal layer 11b constituting the protruding metal layer 11 exposed in the via hole 12x is formed on the first insulating layer 12a. As a material of the first wiring layer 13a, for example, Cu or the like can be used. The first wiring layer 13a is formed by, for example, a semi-additive method.

  An example in which the first wiring layer 13a is formed by a semi-additive method will be described in more detail. First, a Cu seed layer (see FIG. 5) in the first via hole 12x and on the first insulating layer 12a by an electroless plating method or a sputtering method. After forming, a resist layer (not shown) having an opening corresponding to the first wiring layer 13a is formed. Next, a Cu layer pattern (not shown) is formed in the opening of the resist layer by electroplating using the Cu seed layer as a plating power supply layer.

  Subsequently, after removing the resist layer, the first wiring layer 13a is obtained by etching the Cu seed layer using the Cu layer pattern as a mask. In addition, as a formation method of the 1st wiring layer 13a, various wiring formation methods, such as a subtractive method other than the semi-additive method mentioned above, can be used.

  Next, in the step shown in FIG. 27, the first wiring layer 13a to the third wiring layer 13c and the first insulating layer 12a to the third insulating layer 12c are stacked by repeating the same steps as described above. That is, after forming the second insulating layer 12b covering the first wiring layer 13a and the first insulating layer 12a, the second via hole 12y is formed in the portion of the second insulating layer 12b on the first wiring layer 13a.

  Further, a second wiring layer 13b connected to the first wiring layer 13a through the second via hole 12y is formed on the second insulating layer 12b. For example, Cu or the like can be used as the second wiring layer 13b. The second wiring layer 13b is formed by, for example, a semi-additive method.

  Further, after forming the third insulating layer 12c covering the second wiring layer 13b and the second insulating layer 12b, the third via hole 12z is formed in the portion of the third insulating layer 12c on the second wiring layer 13b. Further, a third wiring layer 13c connected to the second wiring layer 13b through the third via hole 12z is formed on the third insulating layer 12c. For example, Cu or the like can be used as the third wiring layer 13c. The third wiring layer 13c is formed by, for example, a semi-additive method.

  In this way, a predetermined buildup wiring layer is formed on one surface 21a of the support 21. In this embodiment, three build-up wiring layers (first wiring layer 13a to third wiring layer 13c) are formed. However, even if an n-layer (n is an integer of 1 or more) build-up wiring layer is formed. Good.

  28, a solder resist is applied on the third insulating layer 12c so as to cover the third wiring layer 13c, and the solder resist layer 14 is formed. As a material of the solder resist layer 14, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used.

  Next, in a step shown in FIG. 29, the opening 14x is formed by exposing and developing the solder resist layer 14. Thereby, a part of the third wiring layer 13 c is exposed in the opening 14 x of the solder resist layer 14. Further, the fourth metal layer 17 is formed on the third wiring layer 13c exposed in the opening 14x of the solder resist layer 14 by, for example, an electroless plating method. The fourth metal layer 17 functions as an electrode pad connected to a motherboard or the like.

  Examples of the fourth metal layer 17 include an Au layer, a Ni / Au layer in which Ni layers / Au layers are stacked in this order, a Ni / Pd / Au layer in which Ni layers / Pd layers / Au layers are stacked in this order, and the like. Can be mentioned. Further, instead of the fourth metal layer 17, OSP (Organic Solderability Preservative) processing may be performed on the third wiring layer 13 c exposed in the opening 14 x of the solder resist layer 14.

Next, in the step shown in FIG. 30, the support 21 and the first metal layer 23 shown in FIG. 29 are removed, and at least a part of the protruding metal layer 11 (the second metal layer 11a and the third metal layer 11b) is removed from the first. A columnar protruding portion 11x is formed to protrude from the insulating layer 12a. Projection amount _{L 10} here projecting portion 11x corresponds to the thickness _{T 10} of the first metal layer 23 shown in FIG. 19, for example a 30 to 50 [mu] m.

  When Cu is selected as the material of the support 21 and the first metal layer 23, the support 21 and the first metal layer 23 can be removed with the same etching solution. For example, the support 21 and the first metal layer 23 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the second metal layer 11a of the protruding metal layer 11 is made of a material other than Cu (for example, Au or the like), the support 21 and the first metal layer 23 are selectively used with respect to the second metal layer 11a. It can be removed by etching.

  Next, by forming the solder bump 15 so as to cover the protruding portion 11x of the protruding metal layer 11, the wiring board 10 shown in FIG. 15 is manufactured. The solder bump 15 can be formed by printing and reflowing a solder paste so as to cover the protruding portion 11x of the protruding metal layer 11, for example. As a material of the solder bump 15, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The protruding metal layer 11 and the solder bump 15 constitute a connection terminal 16, and the connection terminal 16 functions as a connection terminal connected to the semiconductor chip.

  Note that the solder bumps 15 are not necessarily formed on the wiring board 10. For example, it is possible to form solder bumps on the electrode pads of the semiconductor chip mounted on the wiring board 10 and to electrically connect the solder bumps formed on the semiconductor chip and the protruding portions 11x of the protruding metal layer 11 of the wiring board 10. It is. The above is the manufacturing method of the wiring board according to the first embodiment.

  As described above, according to the first embodiment, since the opening for forming the protruding metal layer is not formed by the etching method as in the prior art but is formed by the plating method, the wiring substrate of the protruding metal layer is formed. The shape of the portion protruding from one surface (protruding portion) can be a columnar shape (the cross section of the protruding portion is not a dome shape but a rectangular shape). As a result, the aspect ratio of the protruding portion of the protruding metal layer can be increased, and a connection terminal that can cope with a narrow pitch can be realized. In addition, since the area of the protruding portion of the protruding metal layer that contacts the electrode pad of the semiconductor chip via the solder when mounting the semiconductor chip can be increased, a connection terminal with high connection reliability can be realized. .

<Second Embodiment>
The second embodiment shows another example in which the present invention is applied to a wiring board having a multilayer wiring layer (build-up wiring layer). In the second embodiment, description of parts common to the first embodiment is omitted, and parts different from the first embodiment are mainly described.

[Structure of Wiring Board According to Second Embodiment]
First, the structure of the wiring board according to the second embodiment will be described. FIG. 31 is a cross-sectional view illustrating a wiring board according to the second embodiment. Referring to FIG. 31, the wiring board 30 includes a first insulating layer 12a, a second insulating layer 12b, a third insulating layer 12c, a first wiring layer 13a, a second wiring layer 13b, and a third wiring. The wiring board includes a build-up wiring layer having a layer 13 c, a solder resist layer 14, a connection terminal 36, and a fourth metal layer 17.

  A connection terminal 36 that functions as a connection terminal connected to the semiconductor chip is formed on one surface 30 a of the wiring substrate 30. The connection terminal 36 includes a protruding metal layer 31 protruding from one surface 30 a of the wiring substrate 30 and a solder bump 35 formed so as to cover the protruding metal layer 31. The first wiring layer 13a and the protruding metal layer 31 are electrically connected through a first via hole 12x formed in the first insulating layer 12a. Hereinafter, the portion of the protruding metal layer 31 protruding from the one surface 30a of the wiring board 30 may be referred to as a protruding portion 31x for convenience. Further, the surface of the protruding portion 31x opposite to the surface in contact with the first insulating layer 12a may be referred to as a surface 31y. The surface 31y is a portion where the protruding portion 31x contacts the electrode pad of the semiconductor chip via solder when the semiconductor chip is mounted on the wiring substrate 30.

In the wiring board 30, the protruding portion 31 x has a rectangular cross section parallel to the XZ plane, unlike the protruding metal layer (dome shape or the like) of the conventional wiring board. The protruding amount L30 of the protruding portion 31x from the one surface 30a of the wiring board 30 can be set to, for example, ₃₀ to 50 μm. The shape of the protrusion 31x can be, for example, a columnar shape (for example, the diameter of the surface 31y φ ₃₀ = φ60 to 70 μm). Pitch _{P 30} of the protruding portion 31x may be, for example 150 [mu] m. However, the shape of the protrusion 31x is not limited to a columnar shape, and may be a columnar shape. That is, the shape of the protruding portion 31x is not a columnar shape, and may be, for example, an elliptical column shape or a rectangular column shape (a square column, a hexagonal column, or the like).

  As a material of the protruding metal layer 31, for example, Cu or the like can be used. As a material of the solder bump 35, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

Thus, since the protrusion 31x has a rectangular cross section parallel to the XZ plane, the aspect ratio (L ₃₀ / φ ₃₀ ) can be increased, and a connection terminal that can cope with a narrow pitch is realized. be able to. Further, since the protrusion 31x has a rectangular cross section parallel to the XZ plane, the area of the surface 31y that becomes a portion that contacts the electrode pad of the semiconductor chip via solder when mounting the semiconductor chip can be increased. A connection terminal with high connection reliability can be realized. The above is the structure of the wiring board according to the second embodiment.

[Manufacturing Method of Wiring Board According to Second Embodiment]
Then, the manufacturing method of the wiring board based on 2nd Embodiment is demonstrated. 32 to 35 are diagrams illustrating the manufacturing process of the wiring board according to the second embodiment. 32 to 35, parts that are the same as those in FIG. 31 are given the same reference numerals, and descriptions thereof may be omitted.

  First, the same steps as those shown in FIGS. 16 to 21 of the first embodiment are executed. Next, in the step shown in FIG. 32, the second metal layer 11a and the protruding metal layer 31 are laminated in this order in the opening 23x by an electrolytic plating method using the support 21 and the first metal layer 23 as a plating power feeding layer. To do. The second metal layer 11a is formed so as to cover one surface 21a of the support 21 exposed from the opening 23x and the inner wall surface of the opening 23x. The protruding metal layer 31 is formed on the second metal layer 11a so as to completely fill at least the opening 23x.

  The second metal layer 11a needs to be made of a material that cannot be removed by the etching solution for removing the support 21 and the first metal layer 23 in the step shown in FIG. Further, the second metal layer 11a needs to be made of a material that can be selectively etched with respect to the protruding metal layer 31 in a process shown in FIG. For example, when Cu is used as the material of the support 21, the first metal layer 23, and the protruding metal layer 31, Ni can be used as the material of the second metal layer 11a.

Next, the same steps as those shown in FIGS. 23 to 29 of the first embodiment are performed to produce the structure shown in FIG. Next, in the step shown in FIG. 34, the support 21 and the first metal layer 23 shown in FIG. 33 are removed, and at least a part of the second metal layer 11a and the protruding metal layer 31 is protruded from the first insulating layer 12a. Here the protrusion amount _{L 31} of the portion protruding from the first insulating layer 12a of the second metal layer 11a and the protruding metal layer 31 corresponds to the thickness _{T 10} of the first metal layer 23 shown in FIG. 19, for example 30 50 μm.

  When Cu is selected as the material of the support 21 and the first metal layer 23, the support 21 and the first metal layer 23 can be removed with the same etching solution. For example, the support 21 and the first metal layer 23 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the second metal layer 11a is made of a material (for example, Ni) that cannot be removed by the etching solution for removing the support 21 and the first metal layer 23, the second metal layer 11a supports the second metal layer 11a. The body 21 and the first metal layer 23 can be selectively etched and removed.

Next, in a step shown in FIG. 35, the second metal layer 11a shown in FIG. 34 is removed. At this time, the second metal layer 11a is made of a material (for example, Ni) that can be selectively etched with respect to the protruding metal layer 31 (for example, Cu). Only the two metal layers 11a can be selectively etched and removed. Thereby, a part of the protruding metal layer 31 protrudes from the first insulating layer 12a. Here, since the thickness of the second metal layer 11a is about several [mu] m, the protrusion amount _{L 30} of the protruding portion 31x is approximately equal to for example 30~50μm the protrusion amount _{L 31} shown in FIG. 34.

  For example, when the protruding metal layer 31 is Cu and the second metal layer 11a is Ni, only the second metal layer 11a can be selectively removed by wet etching using a nickel release agent. As the nickel stripping agent, for example, Evastrip (manufactured by Sugawara Eugelite), Melstrip (manufactured by Meltex Co., Ltd.), Mekkuri Mova (manufactured by Mec Co., Ltd.) and the like known as commercially available nickel stripping agents can be used. .

  Next, by forming solder bumps 35 so as to cover the protruding metal layer 31, the wiring board 30 shown in FIG. 31 is manufactured. The solder bump 35 can be formed by printing and reflowing a solder paste so as to cover the protruding portion 31x of the protruding metal layer 31, for example. As a material of the solder bump 35, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The protruding metal layer 31 and the solder bump 35 constitute a connection terminal 36, and the connection terminal 36 functions as a connection terminal connected to the semiconductor chip.

  Note that the solder bumps 35 are not necessarily formed on the wiring board 30. For example, it is possible to form solder bumps on the electrode pads of the semiconductor chip mounted on the wiring board 30 and to electrically connect the solder bumps formed on the semiconductor chip and the protruding portions 31x of the protruding metal layer 31 of the wiring board 30. It is. The above is the manufacturing method of the wiring board according to the second embodiment.

  As described above, according to the second embodiment, since the opening for forming the protruding metal layer is formed by the plating method without forming the opening by the etching method as in the prior art, the wiring substrate of the protruding metal layer is formed. The shape of the portion protruding from one surface (protruding portion) can be a columnar shape (the cross section of the protruding portion is not a dome shape but a rectangular shape). As a result, the aspect ratio of the protruding portion of the protruding metal layer can be increased, and a connection terminal that can cope with a narrow pitch can be realized. In addition, since the area of the protruding portion of the protruding metal layer that contacts the electrode pad of the semiconductor chip via the solder when mounting the semiconductor chip can be increased, a connection terminal with high connection reliability can be realized. .

<Third Embodiment>
The third embodiment shows another example in which the present invention is applied to a wiring board having a multilayer wiring layer (build-up wiring layer). In the third embodiment, description of parts common to the first embodiment will be omitted, and parts different from the first embodiment will be mainly described.

[Structure of Wiring Board According to Third Embodiment]
First, the structure of the wiring board according to the third embodiment will be described. FIG. 36 is a cross-sectional view illustrating a wiring board according to the third embodiment. Referring to FIG. 36, the wiring board 50 includes a first insulating layer 12a, a second insulating layer 12b, a third insulating layer 12c, a first wiring layer 13a, a second wiring layer 13b, and a third wiring. The wiring board includes a build-up wiring layer having a layer 13 c, a solder resist layer 14, a connection terminal 56, and a fourth metal layer 17.

Unlike the wiring substrate 10, the wiring substrate 50 has a semiconductor chip mounting surface on the side where the fourth metal layer 17 is formed, and the fourth metal layer 17 functions as a connection terminal connected to the semiconductor chip. Therefore, the pitch of the fourth metal layer 17 is formed in accordance with the pitch (for example, 150 μm) of the electrode pads of the semiconductor chip to be mounted. On the other hand, the connection terminal 56 functions as a connection terminal connected to a motherboard or the like. Thus, the pitch P ₅₀ of the connection terminals 56 (wider than the pitch of the fourth metal layer 17) in accordance with the pitch of the connection terminals such as a motherboard is formed.

  A connection terminal 56 is formed on one surface 50 a of the wiring substrate 50. The connection terminal 56 is a solder formed so as to cover a protruding metal layer 51 partially protruding from one surface 50 a of the wiring substrate 50 and a portion of the protruding metal layer 51 protruding from one surface 50 a of the wiring substrate 50. And a bump 55. Hereinafter, the portion of the protruding metal layer 51 that protrudes from the one surface 50a of the wiring board 50 may be referred to as a protruding portion 51x for convenience. Further, the surface of the protruding portion 51x opposite to the surface in contact with the first insulating layer 12a may be referred to as a surface 51y. The surface 51y is a portion where the projecting portion 51x comes into contact with an electrode pad such as a mother board via solder when connecting the wiring board 50 and the mother board or the like.

In the wiring board 50, the protruding portion 51x has a rectangular cross section parallel to the XZ plane, unlike the protruding metal layer (dome shape or the like) of the conventional wiring board. While the protrusion amount _{L 50} from the surface 50a of the wiring board 50 of the protruding portion 51x may be, for example 30 to 50 [mu] m. The shape of the protrusion 51x can be, for example, a cylindrical shape (for example, the diameter of the surface 51y φ ₅₀ = φ100 to 200 μm). Pitch _{P 50} of the protruding portion 51x may be, for example, 500 [mu] m. However, the shape of the protrusion 51x is not limited to a columnar shape, and may be a columnar shape. That is, the shape of the protruding portion 51x is not a columnar shape, and may be, for example, an elliptical column shape or a rectangular column shape (a square column, a hexagonal column, or the like).

  The protruding metal layer 51 includes a second metal layer 51a and a third metal layer 51b. As the material of the second metal layer 51a, for example, Au can be used. The second metal layer 51a is a Ni / Au layer in which a Ni layer and an Au layer are stacked from the third metal layer 51b side, and a Ni layer, a Pd layer, and an Au layer are stacked from the third metal layer 51b side. A Ni / Pd / Au layer or the like may be used. As a material of the third metal layer 51b, for example, Cu or the like can be used. As a material of the solder bump 55, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

  Since the configuration of the other parts of the wiring board 50 is the same as that of the wiring board 10, the description thereof is omitted. Moreover, since the manufacturing method of the wiring board 50 is the same as the manufacturing method of the wiring board 10, the description thereof is omitted.

  As described above, according to the third embodiment, the opening for forming the protruding metal layer is formed by the plating method without forming the opening by the etching method as in the prior art. The shape of the portion protruding from one surface (protruding portion) can be a columnar shape (the cross section of the protruding portion is not a dome shape but a rectangular shape). As a result, in the protruding metal layer, the area of the portion that contacts the connection terminal of the mother board or the like via solder when connecting to the mother board or the like can be increased, so that a connection terminal with high connection reliability can be realized.

<Fourth embodiment>
The fourth embodiment shows another example in which the present invention is applied to a wiring board having a multilayer wiring layer (build-up wiring layer). In the fourth embodiment, description of parts common to the second embodiment is omitted, and parts different from the second embodiment will be mainly described.

[Structure of Wiring Board According to Fourth Embodiment]
First, the structure of the wiring board according to the fourth embodiment will be described. FIG. 37 is a cross-sectional view illustrating a wiring board according to the fourth embodiment. Referring to FIG. 37, the wiring substrate 60 includes a first insulating layer 12a, a second insulating layer 12b, a third insulating layer 12c, a first wiring layer 13a, a second wiring layer 13b, and a third wiring. The wiring board includes a build-up wiring layer having a layer 13 c, a solder resist layer 14, a connection terminal 66, and a fourth metal layer 17.

Unlike the wiring substrate 30, the wiring substrate 60 has a semiconductor chip mounting surface on the side where the fourth metal layer 17 is formed, and the fourth metal layer 17 functions as a connection terminal connected to the semiconductor chip. Therefore, the pitch of the fourth metal layer 17 is formed in accordance with the pitch (for example, 150 μm) of the electrode pads of the semiconductor chip to be mounted. On the other hand, the connection terminal 66 functions as a connection terminal connected to a motherboard or the like. Therefore, the pitch P ₆₀ of the connection terminals 66 is formed in accordance with the pitch of the connection terminals such as a mother board (wider than the pitch of the fourth metal layer 17).

  A connection terminal 66 is formed on one surface 60 a of the wiring board 60. The connection terminal 66 is a solder formed so as to cover a protruding metal layer 61 partially protruding from one surface 60 a of the wiring substrate 60 and a portion of the protruding metal layer 61 protruding from one surface 60 a of the wiring substrate 60. And a bump 65. Hereinafter, the portion of the protruding metal layer 61 that protrudes from one surface 60a of the wiring board 60 may be referred to as a protruding portion 61x for convenience. In addition, the surface on the opposite side of the surface in contact with the first insulating layer 12a of the protrusion 61x may be referred to as a surface 61y. The surface 61y is a portion where the projecting portion 61x comes into contact with an electrode pad such as a mother board via solder when connecting the wiring board 60 and the mother board or the like.

In the wiring board 60, the protruding portion 61x has a rectangular cross section parallel to the XZ plane, unlike the protruding metal layer (dome shape or the like) of the conventional wiring board. The protrusion amount L ₆₀ of the protrusion 61x from the one surface 60a of the wiring board 60 can be set to, for example, 30 to ₅₀ μm. The shape of the protrusion 61x can be, for example, a cylindrical shape (for example, the diameter of the surface 61y φ ₆₀ = φ100 to 200 μm). Pitch _{P 60} of the protruding portion 61x may be, for example, 500 [mu] m. However, the shape of the protrusion 61x is not limited to a columnar shape, and may be a columnar shape. That is, the shape of the protruding portion 61x is not a columnar shape, and may be, for example, an elliptical column shape or a rectangular column shape (a square column, a hexagonal column, or the like).

  As a material of the protruding metal layer 61, for example, Cu or the like can be used. As a material of the solder bump 65, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

  Since the structure of the other part of the wiring board 60 is the same as that of the wiring board 30, the description thereof is omitted. Moreover, since the manufacturing method of the wiring board 60 is the same as the manufacturing method of the wiring board 30, the description thereof is omitted.

  As described above, according to the fourth embodiment, since the opening for forming the protruding metal layer is formed by the plating method without being formed by the etching method as in the prior art, the wiring substrate of the protruding metal layer is formed. The shape of the portion protruding from one surface (protruding portion) can be a columnar shape (the cross section of the protruding portion is not a dome shape but a rectangular shape). As a result, in the protruding metal layer, the area of the portion that contacts the connection terminal of the mother board or the like via solder when connecting to the mother board or the like can be increased, so that a connection terminal with high connection reliability can be realized.

<Fifth embodiment>
The fifth embodiment shows an example in which the present invention is applied to a semiconductor package in which a semiconductor chip is mounted on a wiring board having a build-up wiring layer. In the fifth embodiment, description of portions common to the first embodiment is omitted, and portions different from the first embodiment are mainly described.

[Structure of Semiconductor Package According to Fifth Embodiment]
First, the structure of the semiconductor package according to the fifth embodiment will be described. FIG. 38 is a cross-sectional view illustrating a semiconductor package according to the fifth embodiment. 38, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof may be omitted. Referring to FIG. 38, the semiconductor package 70 includes the wiring substrate 10 shown in FIG. 15, a semiconductor chip 71, and an underfill resin 75.

  The semiconductor chip 71 has a main body 72 and electrode pads 73. The main body 72 is obtained by forming a semiconductor integrated circuit (not shown) or the like on a thin semiconductor substrate (not shown) made of silicon or the like. An electrode pad 73 is formed on the main body 72. The electrode pad 73 is electrically connected to a semiconductor integrated circuit (not shown). As a material of the electrode pad 73, for example, Au or the like can be used. The solder bumps 15 of the wiring board 10 are melted and electrically connected to the electrode pads 73 of the semiconductor chip 71. An underfill resin 75 is filled between the semiconductor chip 71 and one surface 10 a of the wiring substrate 10.

  Since the cross section of the protruding portion 11x of the wiring substrate 10 is rectangular, it is possible to increase the area of the surface 11y that is a portion facing the electrode pad 73 through a part of the melted solder bump 15, and thus the connection reliability A connection terminal with high performance can be realized. The above is the structure of the semiconductor package according to the fifth embodiment.

[Method of Manufacturing Semiconductor Package According to Fifth Embodiment]
Next, a method for manufacturing a semiconductor package according to the fifth embodiment will be described. FIG. 39 and FIG. 40 are diagrams illustrating the manufacturing process of the semiconductor package according to the fifth embodiment. 39 and 40, the same components as those in FIG. 38 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, the wiring board 10 shown in FIG. 15 is prepared. Next, in the step shown in FIG. 39, the side of the wiring substrate 10 where the connection terminals 16 are formed and the side of the semiconductor chip 71 where the electrode pads 73 are formed are opposed to each other. Place so that is at the corresponding position.

  Next, in the step shown in FIG. 40, the solder bump 15 constituting the connection terminal 16 is heated to, for example, 230 ° C. to melt the solder, thereby electrically connecting the protruding metal layer 11 constituting the connection terminal 16 and the electrode pad 73. Connect. In addition, when the solder is formed on the electrode pad 73, the solder on the electrode pad 73 and the solder bump 15 are melted to become an alloy, and one bump is formed. Next, the underfill resin 75 is filled between the semiconductor chip 71 and the one surface 10a of the wiring substrate 10, thereby completing the semiconductor package 70 shown in FIG.

  As described above, according to the fifth embodiment, a semiconductor package in which a semiconductor chip is mounted on a wiring board via a connection terminal is manufactured. At this time, the connection terminal of the wiring board has a columnar protrusion (the cross section of the protrusion is rectangular rather than dome-shaped). As a result, the area of the portion that contacts the electrode pad of the semiconductor chip via the solder of the protruding portion can be increased, so that the connection reliability between the wiring board and the semiconductor chip in the semiconductor package can be improved.

<Sixth embodiment>
The sixth embodiment shows another example in which the present invention is applied to a semiconductor package in which a semiconductor chip is mounted on a wiring board having a build-up wiring layer. In the sixth embodiment, description of parts common to the second embodiment is omitted, and parts different from the second embodiment are mainly described.

[Structure of Semiconductor Package According to Sixth Embodiment]
First, the structure of the semiconductor package according to the sixth embodiment will be described. FIG. 41 is a cross-sectional view illustrating a semiconductor package according to the sixth embodiment. 41, parts that are the same as the parts shown in FIG. 31 are given the same reference numerals, and explanation thereof is omitted. Referring to FIG. 41, the semiconductor package 80 includes the wiring substrate 30 shown in FIG. 31, a semiconductor chip 71, and an underfill resin 75.

  The semiconductor chip 71 has a main body 72 and electrode pads 73. The main body 72 is obtained by forming a semiconductor integrated circuit (not shown) or the like on a thin semiconductor substrate (not shown) made of silicon or the like. An electrode pad 73 is formed on the main body 72. The electrode pad 73 is electrically connected to a semiconductor integrated circuit (not shown). As a material of the electrode pad 73, for example, Au or the like can be used. The solder bumps 35 of the wiring board 30 are melted and electrically connected to the electrode pads 73 of the semiconductor chip 71. An underfill resin 75 is filled between the semiconductor chip 71 and the one surface 30 a of the wiring substrate 30.

  Since the cross section of the protruding portion 31x of the wiring board 30 is rectangular, it is possible to increase the area of the surface 31y which is a portion facing the electrode pad 73 through a part of the melted solder bump 35, and the connection reliability A connection terminal with high performance can be realized. The above is the structure of the semiconductor package according to the sixth embodiment. Note that the manufacturing method of the semiconductor package according to the sixth embodiment is the same as the manufacturing method of the semiconductor package according to the fifth embodiment, and thus description thereof is omitted.

  Thus, according to the sixth embodiment, a semiconductor package in which a semiconductor chip is mounted on a wiring board via a connection terminal is manufactured. At this time, the connection terminal of the wiring board has a columnar protrusion (the cross section of the protrusion is rectangular rather than dome-shaped). As a result, the area of the portion that contacts the electrode pad of the semiconductor chip via the solder of the protruding portion can be increased, so that the connection reliability between the wiring board and the semiconductor chip in the semiconductor package can be improved.

  The preferred embodiment has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and replacements are made to the above-described embodiment without departing from the scope described in the claims. Can be added.

  For example, in each embodiment, an example in which each wiring layer is formed by a semi-additive method has been described. However, each wiring layer can be formed by using various methods such as a subtractive method in addition to the semi-additive method. it can.

10, 30, 50, 60 Wiring board 10a, 30a, 50a, 60a One surface of the wiring board 11, 31, 51, 61 Protruding metal layer 11a, 51a Second metal layer 11b, 51b Third metal layer 11x, 31x, 51x, 61x Projection 12a First insulating layer 12b Second insulating layer 12c Third insulating layer 12x First via hole 12y Second via hole 12z Third via hole 13a First wiring layer 13b Second wiring layer 13c Third wiring layer 14 Solder resist Layer 14x Opening 15, 35, 55, 65 Solder bump 16, 36, 56, 66 Connection terminal 17 Fourth metal layer 21 Support 21a One side of support 22, 24 Resist layer 23 First metal layer 70, 80 The semiconductor package 71 semiconductor chip 72 body 73 the electrode pads 75 underfill resin L _{10, L 3 0, L} 50, _{L 60} projecting amount _{P 10, P 30, P 50} , P 60 pitch T ₁₀ thickness _{φ 10, φ 30, φ 50} , φ 60 diameter

Claims (9)

An insulating layer having one surface and the other surface being the opposite surface, and being disposed on the outermost layer so that the other surface is the surface of the wiring board;
A columnar protrusion protruding from the other surface of the insulating layer,
The protrusions have a top surface and a bottom surface, covered the lower surface of the front Symbol lower and side surfaces within the insulation layer, wherein the top side is a connecting terminal protruding from the other surface of the insulating layer,
The protrusion includes a second metal layer and a third metal layer,
A portion of the third metal layer is embedded in the insulating layer, and the remaining portion protrudes from the other surface of the insulating layer;
The portion embedded in the insulating layer of the third metal layer has a rectangular cross section in the upper surface and lower surface directions,
The cross section in the upper surface and lower surface direction of the portion of the third metal layer protruding from the other surface of the insulating layer is greater than the cross section in the upper surface and lower surface direction of the portion of the third metal layer embedded in the insulating layer. Is a narrow rectangle,
The second metal layer covers an upper surface and a side surface of a portion of the third metal layer protruding from the other surface of the insulating layer;
The insulating layer is provided with a via hole that exposes the lower surface of the protruding portion,
A wiring board in which a wiring layer connected to the lower surface of the protruding portion through the via hole is provided on one surface of the insulating layer.   The width of the cross section in the upper surface and lower surface direction of the portion protruding from the other surface of the insulating layer including the second metal layer and the third metal layer is embedded in the insulating layer of the third metal layer. The wiring board according to claim 1, wherein the width is equal to a width of a cross section of the portion in the upper surface and lower surface directions. The protrusion of the columnar wiring board according to claim 1 or 2, wherein a plurality of metal layers of different materials have been stacked. Said second metal layer, an Au layer, a Ni layer, a layer Au layer stacked on the Ni layer, or any of claims 1 to 3 Pd layer and an Au layer on the Ni layer is a layer which are successively stacked wiring board of one claim or. Wiring board set forth in any one of the third claims 1 to 4 the material of the metal layer is Cu. Wherein said portion protruding from the other surface of the insulating layer of the protrusion is cylindrical, elliptic cylindrical, or wiring board of any one of claims 1 to 5 which is prismatic. The wiring layer, other insulating layer and has the wiring layers are laminated, the wiring board of any one of claims 1 to 6 the electrode pads on the uppermost wiring layer is provided. A wiring board according to any one of claims 1 to 7 , and a semiconductor chip having an electrode pad,
A semiconductor package in which the protrusion and the electrode pad are electrically connected. The semiconductor package according to claim 8 , wherein the protruding portion and the electrode pad are connected via solder formed between opposing surfaces of the protruding portion and the electrode pad.

Images