JP5419660B2 - Imaging apparatus and driving method thereof - Google Patents

Description

  The present invention relates to an imaging apparatus and a driving method thereof.

  In a solid-state imaging device, an improvement in S / N ratio and an expansion of a dynamic range are required. In response to such a request, in Patent Document 1 below, a detection circuit for detecting the level of a pixel signal and an amplification circuit are provided for each column of pixels arranged in a matrix, and the amplification factor for the pixel signal is controlled for each pixel. doing. As a result, the dynamic range is expanded while maintaining the S / N ratio. In Patent Document 2 below, data obtained by AD-converting an output signal from an image sensor to capture a signal in a relatively bright region and an output signal from the image sensor in order to image a signal in a relatively dark region And AD-converted data are respectively stored in the memory unit, and inset synthesis is performed. As a result, the dynamic range of the image sensor can be used effectively.

JP 2004-015701 A JP-A-11-331709

  However, the technique disclosed in Patent Document 1 requires both pixel signal level detection means and feedback means for individually setting the amplification factor corresponding to each column of pixels, which complicates the sensor internal circuit. End up. In addition, since the amplification factor is controlled based on the detected result, there is a problem that a time delay of one frame occurs before the detection result is reflected. On the other hand, the technique disclosed in Patent Document 2 requires two memory units for accumulating both high-intensity correction signal and pixel signal images, which increases the circuit scale. In addition, the pixel signal and the high-intensity correction signal have a problem that the operation speed is slow because an exposure / readout operation for two frames having different accumulation times is required.

  In view of the above-described problems, an object of the present invention is to provide an imaging apparatus capable of improving an S / N ratio and expanding a dynamic range and a driving method thereof.

An imaging device according to the present invention is arranged in a two-dimensional matrix and is provided in each column of a plurality of pixels that generate signals using photoelectric conversion elements, and is multiplied by p with respect to the signal of the same pixel. A column amplifying unit that outputs a first pixel signal amplified at an amplification factor of q and a second pixel signal amplified at a q-times amplification factor different from the p-fold, and a plurality of column amplification units, respectively. provided Te, a holding portion for holding the output of the corresponding column amplifier provided in each column of the plurality of pixels, which is held by the holding portion, the first pixel that is amplified by the column amplifier A column AD converter that converts the signal and the second pixel signal from analog to digital, and a first pixel signal that is provided in each column of the plurality of pixels and converted by the column AD converter is less than a threshold value Select the first pixel signal converted by the column AD converter A replacement unit that selects the second pixel signal converted by the column AD conversion unit when the first pixel signal converted by the column AD conversion unit is larger than a threshold, and each column selected by the replacement unit the first have a horizontal scanning circuit for sequentially selecting the pixel signal or the second pixel signal of the column amplifier unit includes an operational amplifier, an input capacitance, and a plurality of feedback capacitors for switching the connection state The pixel is reset and at least two feedback capacitors are connected, the input / output terminal of the operational amplifier is short-circuited, and then one of the feedback capacitors is electrically disconnected from the feedback path, The holding unit holds the output of the column amplification unit in a state where the gain of the column amplification unit is q times, and then the other feedback capacitor is electrically disconnected from the feedback path, and the one feedback capacitor is further disconnected. The By electrically connecting to the return path, the holding unit holds the output of the column amplification unit in a state where the gain of the column amplification unit is multiplied by p, and then the gain of the column amplification unit is p times In this state, a signal based on the photoelectric conversion of the photoelectric conversion element is output from the pixel, the output of the column amplification unit is held by the holding unit, and then the one feedback capacitor is electrically disconnected from the feedback path. In addition, the holding unit holds the output of the column amplification unit in a state where the gain of the column amplification unit is q times by electrically connecting the other feedback capacitor to the feedback path. To do.

  According to the present invention, the S / N ratio can be improved and the dynamic range can be expanded.

It is a block diagram of the solid-state image sensor concerning 1st Embodiment. It is a figure which shows the signal component output from a column AD conversion part. FIG. 3 is an equivalent circuit diagram illustrating the configuration of the pixel unit according to the first embodiment in more detail. It is operation | movement explanatory drawing in 1 horizontal scanning period in 1st Embodiment. It is explanatory drawing of the column AD conversion part and substitution part in 1st Embodiment. It is explanatory drawing of the correction | amendment part, bit conversion part, and output part in 1st Embodiment. It is operation | movement explanatory drawing in 1st Embodiment. It is operation | movement explanatory drawing in 1st Embodiment. It is a figure which shows the process of the correction | amendment part and bit conversion part in 1st Embodiment. It is a figure which shows the process of the correction | amendment part and bit conversion part in 1st Embodiment. It is an equivalent circuit diagram in the second embodiment. It is operation | movement explanatory drawing in 1 horizontal scanning period in 2nd Embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a schematic configuration example of a solid-state imaging device (imaging device) according to the first embodiment of the present invention. First, the principle of improving the S / N ratio of the signal and expanding the dynamic range of the solid-state imaging device will be described. The solid-state imaging device 1 includes a pixel unit 10 in which pixels 101 are arranged in a matrix, and a column amplification unit 102, a noise removal unit 120, a column AD conversion unit 121, and a replacement unit 122 for each column. Further, in order to read out data for one screen from the pixel unit 10, the solid-state imaging device 1 includes a vertical scanning circuit 103 for selecting an arbitrary row, and a horizontal scanning circuit 104 for sequentially reading out signals from the one row. Prepare. The pixel unit 10 includes a plurality of pixels 101 that are arranged in a two-dimensional matrix and generate signals using the photoelectric conversion elements PD (FIG. 3). Further, the solid-state imaging device 1 further includes a correction unit 124, a bit conversion unit 125, and an output unit 126 in the subsequent stage of the horizontal output signal line group that sequentially selects and reads out signals of each column by the horizontal scanning circuit 104. . The pixel 101 includes a photoelectric conversion element that performs photoelectric conversion, and further includes a pixel output unit that converts a charge generated by the photoelectric conversion element into a voltage signal and outputs the voltage signal, a pixel selection unit for selecting the pixel 101, and the like. May be. For simplification of the figure, only nine pixels 101 are shown, but it is assumed that there are actually pixels 101 of m rows × n columns. Each column amplifying unit 102 can change the amplification factor for all the columns at once by the column amplifier amplification factor control signals φC1, φC2, and φC3. Here, when the signal is read twice for the same row, the amplification factor is changed and read. The noise removing unit 120 reads out both the noise component and the signal component including noise from the pixel 101, obtains a difference, and extracts the signal component. φCTS 1, φCTN 1, φCTS 2, φCTN 2, φCOLSEL 1, and φCOLSEL 2 indicate control pulses required in the noise removing unit 120. The column AD conversion unit 121 receives an AD control signal such as φADCLK and performs analog-digital (AD) conversion. Here, AD conversion is performed on signals read twice from the same row. The replacement unit 122 receives the replacement trigger signal φFLAGCHK, determines whether to replace the digital signal read out the first time with the digital signal read out the second time, and replaces the column when the condition is met. Run. As a result, the signals read out twice are combined. The correction unit 124 performs a correction calculation of the amplification factor error of the two types of signals read by changing the amplification factor. The bit conversion unit 125 performs digital amplification factor conversion on a signal derived from at least one of two types of signals read out by changing the amplification factor among the input signals, and outputs the signal by increasing the number of bits of the read signal. . The output unit 126 is an output circuit unit that transmits an image signal from the solid-state imaging device 1 to an external system. The output unit 126 converts the output signal into an output format such as a differential signal pair having a low voltage amplitude, and outputs the image signal to the outside. The timing generator 123 generates a drive pulse and a control signal to be sent to each unit by counting and decoding the clock input from the MCLKIN terminal. By adopting such a circuit configuration, the image signal amplified with two types of amplification factors can be synthesized in the solid-state imaging device 1.

  In the solid-state imaging device 1 shown in FIG. 1, the relationship between the signal component output from the column AD conversion unit 121 and the amount of light incident on the pixel 101 when the amplification factor of the column amplification unit 102 is 1 is shown in FIG. This is indicated by “signal (× 1)” in (a). In FIG. 2A, the horizontal axis represents the amount of incident light, and the vertical axis represents the output magnitude of the column AD conversion unit 121. When the amount of incident light exceeds Isat (× 1), the output is saturated and becomes Vsat. Here, whether the saturation level Vsat is the saturation level of the column amplification unit 102 or the saturation level of the column AD conversion unit 121, the following discussion can be applied. In the figure, a broken line indicates pixel noise n caused by the pixel 101, and an alternate long and short dash line indicates output noise N caused by the column AD conversion unit 121. As the pixel noise n, for example, noise generated in a pixel output unit or a pixel selection unit included in the pixel can be considered. More specifically, when the pixel output unit constitutes a source follower circuit with a constant current source provided on the vertical signal line VL, temporal fluctuations in the current value flowing through the constant current source, etc. It can be a factor of noise n. The output noise N includes, for example, noise generated by driving the column AD conversion unit 121. Note that the pixel noise n and the output noise N do not always become a constant level of noise, but vary with time. FIG. 2A shows the maximum level when each noise fluctuates with time. In the present specification, amplification with an amplification factor of 1 is included in the amplification.

  As shown in FIG. 2A, when the amplification factor in the column amplification unit 102 is 1, the output noise N is generally larger than the pixel noise n (× 1), so that the output noise N is dominant. Become. This is because the pixel 101 is driven at a low speed and has a low bandwidth because of horizontal scanning, and the output amplifier outputs signals sequentially, so that the pixel 101 is driven at a high speed and has a wide bandwidth. That is, a signal from the pixel 101 that has received an incident light amount such that the signal (× 1) is smaller than the output noise N cannot be correctly extracted from the solid-state imaging device 1 due to the influence of the output noise N. For example, assume that the output level output from the solid-state imaging device 1 is v0. At the timing when the output v0 is output, the level of noise is small and may be a level that correctly corresponds to the amount of incident light. Although the output is originally smaller than v0, it is output due to the influence of noise. May be v0.

  In FIG. 2A, it is considered that the signal output from the same pixel 101 that obtained the signal (× 1) is multiplied by a G-fold amplification factor by the column amplifier 102 (G> 1). . The relationship between the amount of incident light and the output from the column AD conversion unit 121 at this time is indicated by “signal (× G)” in FIG. The signal (× G) becomes the saturated output Vsat with a smaller incident light amount Isat (× G) than the signal (× 1). In other words, the greater the amplification factor of the column amplification unit 102, the greater the slope of the straight line representing the output of the column AD conversion unit 121 with respect to the incident light amount. Further, by changing the amplification factor of the column amplification unit 102, not only the signal component but also the pixel noise n is amplified by a G-times amplification factor, but the output noise N does not depend on the amplification factor of the column amplification unit 102. Therefore, when the amplification factor of the column amplification unit 102 is increased, the amplified pixel noise n exceeds the output noise N. That is, the pixel noise n amplified by increasing the amplification factor of the column amplification unit 102 by G becomes dominant, and the output noise N becomes relatively small. Therefore, it becomes possible to extract a signal at an incident light quantity that cannot be correctly extracted due to the output noise N that was dominant when the amplification factor of the column amplifier 102 is 1. A range of the incident light quantity that can be extracted by increasing the amplification factor of the column amplification unit 102 by G times is indicated as A. That is, it can be treated as synonymous with the expansion of the dynamic range of the solid-state imaging device 1 by the amount A of the incident light amount.

  Therefore, it is conceivable to use the signal (× G) in the range where the incident light amount is from 0 to Ia, and the signal (× 1) in the region where the incident light amount is larger than Ia. It will change greatly. Therefore, the signal (× G) output from the column AD converter 121 is multiplied by 1 / G by the processing circuit. This is shown in FIG. The signal (× G) becomes a signal (× G · 1 / G), which matches the characteristics of the signal (× 1). Similarly, the pixel noise n (× G) is multiplied by 1 / G to match the pixel noise n (× 1). On the other hand, the output noise N does not change even when the amplification factor of the column amplification unit 102 is multiplied by G. Therefore, when the processing circuit multiplies by 1 / G, the output noise N (1 / G) is obtained. In other words, the noise component due to the output noise N in the range from 0 to Isat is reduced by multiplying by 1 / G in the processing circuit, so that the signal (× G · 1 · G) is a signal having a higher S / N ratio to the output noise N.

  Further, as shown in FIG. 2B, when Isat (× G) is larger than Ia, the signal (× G · 1 / G) is also used for the range of the incident light quantity from Ia to Isat (× G). By doing so, a signal with a high S / N ratio can be obtained. In the region where the amount of incident light reaches Isat (× G), the subject is in a relatively dark state, so the effect of improving the S / N ratio is particularly significant.

  FIG. 2C summarizes what has been described above. The signal (× G · 1 / G) is used in the range where the incident light amount is from 0 to Isat, and the signal (× 1) is used in the range where the incident light amount is larger than Isat. Either may be used for the point where the amount of incident light is Isat, but the signal (× G · 1 / G) is used because the signal (× G · 1 / G) has a higher S / N ratio. It is preferable. Focusing on output noise and pixel noise, pixel noise n (× 1) is more dominant than output noise N in the range where the incident light quantity is from 0 to Isat, and output N is in the range where the incident light quantity is greater than Isat. It becomes more dominant than pixel noise n (× 1). In the range where the amount of incident light is smaller than the range of the amount of incident light indicated by A in FIG. 2C, the signal (× G · 1 / G) is at a level smaller than the pixel noise n (× 1). End up. Therefore, the signal output from the solid-state imaging device 1 is effective only in a range where the amount of incident light is larger than Ib. However, as described above, output noise and pixel noise have temporal fluctuations, and the maximum levels are shown in FIG. When images are continuously acquired like a moving image, noise components are averaged, so that the overall level is lower than the pixel noise n. For this reason, it becomes possible to recognize a part of an image in a region where the signal (× G · 1 / G) is smaller than the pixel noise n (× 1). In other words, by suppressing the output noise N in a range where the incident light amount is small, even if the incident light amount is lower than the pixel noise n (× 1) in FIG. It has the effect of increasing.

  In the above description, the signal that is amplified by two types of amplification factors with respect to the signal output from one pixel has been described. However, according to the idea of this embodiment, it is obvious that a signal output from one pixel may be amplified with three or more amplification factors. Thereby, the improvement of the S / N ratio can be realized over a wider range of incident light quantity.

  Moreover, although the case where the amplification factor in the column amplification unit 102 is set to 1 and G times has been described as an example, the combination of amplification factors is not limited. For example, a combination of 2 times and 16 times or a combination of 0.5 times and 4 times may be used.

  Further, in the above description, a process of multiplying the signal amplified by G times by 1 / G times, that is, the reciprocal of the amplification factor in the column amplification unit 102 is performed. However, this is for matching the characteristics of two signals obtained by amplification at different amplification factors (so that they are on the same straight line in FIG. 2), and must be multiplied by 1 / G. is not. For example, when one signal is amplified at the amplification factor of 2 and 16 by the column amplification unit 102, the other signal can be obtained by multiplying the signal obtained by amplification at the amplification factor of 16 to 1/8. And the characteristics can be matched. In addition, the characteristics can be matched even if the signal obtained by amplifying with the amplification factor of 2 is halved and the signal obtained by amplifying with the amplification factor of 16 is multiplied by 1/16. it can.

  The purpose of expanding the dynamic range and further improving the S / N ratio can be achieved without matching the above characteristics for the two signals. Of the two signals amplified at the amplification factor of 1 and G, the signal amplified at the amplification factor of G is not 1 / G, but is 1 / (2G), for example. Since the output noise N can be reduced, the dynamic range can be expanded and the S / N ratio can be further improved. However, in this case, it is desirable to perform offset correction because the continuity of characteristics is lost (offset occurs) at Isat (× G) in FIG.

  In summary, a signal amplified by a column amplification unit 102 with a gain of p times and an amplified signal with a gain of q times are obtained from one signal output from a certain pixel. Here, it is assumed that p> q and 1 <p. Further, the image signal output from the solid-state imaging device 1 is multiplied by a magnification less than 1 based on a signal amplified with a high amplification factor of p times. As a result, the dynamic range can be expanded and the S / N ratio can be further improved.

  Further, by setting the magnification below 1 to q / p times, it is possible to match the characteristics of the signal amplified with the amplification factor of q times. If a signal multiplied by a factor of q is further multiplied by r, the characteristics of the two signals can be matched by setting the magnification below 1 to (q / p) × r. . That is, it is sufficient that the magnification below 1 is a value having q / p as a divisor.

  An example of the solid-state imaging device 1 according to the first embodiment of the present invention and the schematic operation thereof will be described with reference to FIG. Pixels 101 provided in the same column are connected to the column amplifier 102 via the same vertical signal line VL. When the pixel row Vn of the signal φVn is selected by the vertical scanning circuit 103, a signal is output from the pixel 101 connected to the pixel row Vn to each vertical signal line VL, and amplification of the column amplifier amplification factor control signals φC1, φC2, and φC3 The signal is amplified by the column amplification unit 102 according to the rate setting. At this time, in order to remove noise due to pixel reset with the same amplification factor, the signal immediately after pixel reset and the signal after optical signal accumulation are amplified, and then the difference between the two is acquired by the noise removal unit 120. A signal from which noise has been removed by the noise removal unit 120 is AD converted by the column AD conversion unit 121 at a timing determined by the AD control signal φADCLK. Here, AD conversion is performed by changing the amplification factor from the same pixel row Vn and reading the signal after noise removal twice. The AD converted first digital signal and the second digital signal are sent to the replacement unit 122. The replacement unit 122 first stores the first digital signal, and then uses the signal φFLAGCHK as a trigger to determine, for each column, whether or not to replace the second digital signal. Replace the digital signal with a second digital signal. At this time, a flag indicating whether or not replacement is performed is also stored for each column. The horizontal scanning circuit 104 outputs signals φH1, φH2, φH3,... Of bus switches that connect the output bus DATA0 [12: 0] from the replacement unit 122 and the horizontal signal output bus DATA1 [12: 0]. Then, the bus switch is turned on, and the replaced digital signal from each column is sequentially input to the correction unit 124 in the column order.

The correction unit 124 performs necessary correction processing. The correction unit 124 refers to the flag to identify whether the original signal is the first digital signal or the second digital signal, and determines the amplification factor error caused by the column amplification unit 102 for the corresponding signal. Make corrections. The bit conversion unit 125 refers to the flag, determines whether the original signal is the first digital signal or the second digital signal, and applies a digital gain to one or both signals. Specifically, in the first digital signal multiplied by the amplification factor of p and the second digital signal multiplied by the amplification factor of q, the second digital signal is compared to the first digital signal. Thus, the amplification factor is approximately p / q times. The bit conversion unit 125 performs bit conversion that shifts n bits of one signal and applies an amplification factor equivalent to 2 ⁿ times. Here, the bit conversion unit 125 performs a 3-bit shift, and uses an input 13-bit signal as a 16-bit signal of DATA2 [15: 0]. The output unit 126 multiplexes, for example, an input DATA2 [15: 0] 16-bit bus width signal to reduce the number of signal lines and converts the signal into a low-amplitude differential pair signal to reduce noise. And output to the outside of the solid-state imaging device 1 as an output signal DATAOUT. The timing generation unit 123 supplies signals to the vertical scanning circuit 103 and the horizontal scanning circuit 104, and further supplies signals controlled by the column amplification unit 102, the noise removal unit 120, the column AD unit 121, and the replacement unit 122. May be. Note that the timing generation unit 106 may be provided outside the solid-state imaging device 1, or a part of the control signals may be supplied from the outside.

  In this manner, in the period in which the image signal for one row is output from the solid-state imaging device 1, the analog pixel signal is read out twice from the pixel row internally, amplified at different amplification factors, and then subjected to AD conversion. The digital signal and the second digital signal are synthesized for each column. Further, after sequentially reading from each column and serializing, correction and bit conversion are performed.

  The detailed configuration and operation of each unit will be described below. FIG. 3 is an equivalent circuit diagram showing the configuration of the column amplification unit 102 and the noise removal unit 120 in more detail with respect to one pixel 101 in FIG. The pixel 101 includes a photodiode PD that is a photoelectric conversion element and a transfer unit TX that transfers charges accumulated in the photodiode PD to a gate terminal of a MOS transistor that forms the pixel output unit SF. A gate terminal that is an input unit of the pixel output unit SF is connected to the power supply VDD via the reset unit RES. Further, the source terminal of the pixel output unit SF is connected to one terminal of the input capacitor C0 of the column amplification unit 102 via the pixel selection unit SEL and also to the constant current source Icnt. The column amplification unit 102 includes an operational amplifier Amp. The inverting input terminal of the operational amplifier Amp is connected to the other terminal of the input capacitor C0. The inverting input terminal and the output terminal of the operational amplifier Amp are provided such that feedback capacitors C1, C2, and C3 are connected via switches. Further, a switch for short-circuiting the inverting input terminal and the output terminal of the operational amplifier Amp is provided. A power supply Vref is applied to the non-inverting input terminal of the operational amplifier Amp. The signal output from the pixel 101 to the vertical signal line VL is determined by the ratio between the capacitance values of the feedback capacitors C1, C2, and C3 connected to the feedback path of the operational amplifier Amp and the capacitance value of the input capacitor C0. Amplification is applied at a high rate. Here, the capacitance values of the feedback capacitors C1, C2, and C3 are set to 1 times, 1/8 times, and 1/16 times the capacitance value of the input capacitor C0, respectively. In other words, in the present embodiment, each column amplifying unit includes a column amplifier having a variable amplification factor. As will be described later, noise caused by pixels is reduced by the input capacitance C0. Here, a first CDS (Correlated Double Sampling) circuit including the input capacitor C0, the operational amplifier Amp, and the switch to which the signal φC is input is used.

  The signal amplified by the column amplifier 102 is selectively transmitted to and held by the holding capacitors CTS1, CTN1, CTS2, and CTN2 in the noise removing unit 120. The holding capacitors CTS1 and CTS2 hold a signal based on charges obtained by photoelectric conversion by the photodiode PD, and the holding capacitors CTN1 and CTN2 hold a signal based on resetting the pixel output unit SF. The The signals held in the holding capacitors CTS1 and CTN1 are transferred to the differential amplifier D.D via a switch made conductive by the signal φCOLSEL1. Connected to different input terminals of Amp. The signals held in the holding capacitors CTS2 and CTN2 are supplied to the differential amplifier D.D via a switch that is turned on by the signal φCOLSEL2. Connected to different input terminals of Amp. Differential amplifier Amp1 outputs the difference between the signals held in the holding capacitors CTS1 and CTN1 and the difference between the signals held in the holding capacitors CTS2 and CTN2 in time series. Here, the second CDS circuit including the storage capacitor and the differential amplifier is used. The offset caused by the column amplifier 102 is reduced by the second CDS circuit.

  A method for driving the solid-state imaging device 1 in one horizontal scanning period according to the pixel 101, the column amplification unit 102, and the noise removal unit 120 illustrated in FIG. 3 will be described first with reference to FIG. Here, the feedback capacitors C1 and C2 are used, and the respective capacitance values are assumed to be 1 and 1/8 times the capacitance value of the input capacitor C0. That is, a case where one signal is amplified with an amplification factor of 1 and 8 will be described. In FIG. 3, signals input to the switches indicated by TX, RES, and SEL are represented by φTX, φRES, and φSEL, respectively, and the switch conducts when the signal is at a high level. Further, signals given to the switches existing between the feedback capacitors C1, C2, and C3 and the inverting input terminal of the operational amplifier Amp are represented as φC1, φC2, and φC3, respectively, and the switches are turned on when the signals are at a high level. To do. Signals applied to the switches between the holding capacitors CTS1, CTN1, CTS2, and CTN2 and the output terminal of the column amplifier 102 are represented as φCTS1, φCTN1, φCTS2, and φCTN2, respectively, and the switches are turned on when the signals are at a high level. Shall.

  First, at time t0, signals other than the signals φTX and φHn transition to a high level. Since the pixel selection unit SEL becomes conductive when the signal φSEL becomes high level, the source terminal of the pixel output unit SF and the constant current source Icnt are electrically connected to form a source follower circuit. Accordingly, a level corresponding to the potential of the gate terminal of the pixel output unit SF appears on the vertical signal line VL as a signal. Since the signal φRES is at the high level at this timing, a level corresponding to the state in which the gate terminal of the pixel output unit SF is reset appears on the vertical signal line VL. Further, when the signals φC, φC1, φC2, and φC3 are respectively set to the high level, the inverting input terminal and the output terminal of the operational amplifier Amp are short-circuited, and the feedback capacitors C1, C2, and C3 are reset. Due to the virtual grounding of the operational amplifier Amp, the potentials of both terminals of the feedback capacitors C1 and C2 can be regarded as the same potential as the power supply Vref. Since the signals φCTN1, φCTS1, φCTN2, and φCTS2 are at a high level, the holding capacitors CTN1, CTS1, CTN2, and CTS2 are reset by the output of the operational amplifier Amp.

  At time t1, the signal φRES transitions to a low level, and the reset state of the gate terminal of the pixel output unit SF is released. A noise component generated with the cancellation of the reset state contributes to the pixel noise n.

  At time t2, the signals φC1, φC2, φC3, φCTN1, φCTS1, φCTN2, and φCTS2 are at a low level, and the corresponding switches are turned off.

  Thereafter, the signal φC transitions to a low level at time t3, whereby the short-circuit state of the input / output terminals of the operational amplifier Amp is released. In the input capacitor C0, the level corresponding to the reset of the gate terminal of the pixel output unit SF is clamped by Vref.

  The signals φC1 and φCTN1 become high level at time t4, and the signal φCTN1 becomes low level at time t5, whereby the output of the column amplifier 102 at this time is held in the holding capacitor CTN1. Here, since the signal φC1 is at a high level, only the feedback capacitor C1 is electrically connected to the feedback path of the operational amplifier Amp. That is, the amplification factor of the column amplification unit 102 is C0 / C1 = C0 / C0 = 1. The signal held in the holding capacitor CTN1 includes an offset component caused by the column amplification unit 102.

  At time t6, the signal φC1 changes to low level, and at time t7, the signal φC2 changes to high level, so that only the feedback capacitor C2 is electrically connected to the feedback path of the operational amplifier Amp. That is, the amplification factor of the column amplification unit 102 is C0 / C2 = C0 / (C0 / 8) = 8.

  When the signal φCTN2 becomes a high level in a pulse shape from time t7 and the signal φCTN2 becomes a low level, a signal including an offset component caused by the column amplification unit 102 is held in the holding capacitor CTN2.

  When the signal φTX transits to a high level at time t8, the charge accumulated in the photodiode PD is transferred to the gate terminal of the pixel output unit SF. As a result, the potential at the gate terminal of the pixel output unit SF changes, so that the level appearing on the vertical signal line VL also changes. At this time, since the input capacitor C0 is in a floating state, only the change in potential from the level of the vertical signal line VL clamped at time t1 is input to the inverting input terminal of the operational amplifier Amp. That is, among the noise components generated before the clamp capacitance, the noise components correlated with the level of the vertical signal line VL at time t3 and the level at the timing after time t8 can be reduced by the clamping operation. it can. As a result, a signal based on photoelectric conversion is input to the operational amplifier Amp. However, fluctuations in the current flowing through the constant current source Icnt, noise called 1 / f noise generated in the pixel output unit SF, and the like are different at the time t1 and the time t8 (no correlation), and thus are reduced by the clamping operation. I can't. In the present embodiment, such a non-correlated noise component corresponds to the pixel noise n.

  At time t8, only the feedback capacitor C2 having a capacitance value that is 1/8 times the capacitance value of the input capacitor C0 is present in the feedback path of the operational amplifier Amp. Therefore, a signal based on photoelectric conversion is amplified with an amplification factor of 8 times. become. The signal φCTS2 is at a high level in a pulse shape from time t8, and the signal amplified eight times by the column amplifier 102 is held in the holding capacitor CTS2 when the signal φCTS2 transitions to a low level. The signal held in the holding capacitor CTS2 includes an offset caused by the column amplification unit 102, similarly to the holding capacitor CTN2.

  At time t9, the signal φC2 changes to low level, and at time t10, the signal φC1 changes to high level, so that only the feedback capacitor C1 is electrically connected to the feedback path of the operational amplifier Amp. Since the capacitance value of the feedback capacitor C1 is the same as the capacitance value of the input capacitor C0, the signal input to the column amplifier 102 is amplified with a gain of 1.

  When the signal φCTS1 changes to the high level from time t10 and changes to the low level, a signal obtained by amplifying the level appearing on the vertical signal line VL with the amplification factor of 1 is held in the holding capacitor CTS1. Here, the signal held in the storage capacitor CTS1 includes an offset caused by the column amplification unit 102 as in the case of the storage capacitor CTN1. Thereafter, when the signal φSEL becomes low level, the pixel selection unit SEL is turned off and the selection state of the pixel 101 is released.

  At time t11, the signal φCOLSEL2 becomes high level, so that the signals held in the holding capacitors CTS2 and CTN2 are changed to the differential amplifier D.D. The first pixel signal is output to the subsequent column AD conversion unit 121 via Amp.

  Subsequently, when the signal φCOLSEL1 becomes high level at time t13, the signals held in the holding capacitors CTS1 and CTN1 are changed to the differential amplifier D.D. The second pixel signal is output to the subsequent column AD conversion unit 121 via Amp. Since the signal held in each holding capacitor includes an offset caused by the column amplifier 102, the differential amplifier D.D. The offset component can be reduced by taking the difference by Amp. Differential amplifier Amp sequentially outputs a signal S2 amplified at an amplification factor of 8 and a signal S1 amplified at an amplification factor of 1. The signals S1 and S2 include the output noise N described above. The signals S1 and S2 here correspond to the output V in FIG. The first pixel signal and the second pixel signal are subjected to AD conversion by a column AD conversion unit 121 described later, and then one of the first pixel signal and the second pixel signal is selected as an output signal for each column by the replacement unit 122.

  Thereafter, at time t14, the replacement data of each column is sequentially read out to the subsequent correction unit 124 by the drive pulse φHCLK of the horizontal scanning circuit 104.

  The column amplifying unit 102 is provided in each column of the plurality of pixels 101, and is a first pixel signal amplified at a gain of p times (for example, 8) with respect to the signal of the same pixel and q times different from p times ( For example, the second pixel signal amplified by an amplification factor of 1 is output. In addition, the column amplification unit 102 outputs the first pixel signal and the second pixel signal in time series. The noise removal unit 120 is provided in each column of the plurality of pixels 101 at the subsequent stage of the column amplification unit 102. The noise removing unit 120 performs column AD conversion on a difference signal between the signal amplified by the column amplification unit 102 in the reset state of the pixel 101 and the signal amplified by the column amplification unit 102 in the reset release state of the pixel 101. Output to the unit 121. In the present embodiment, since the column amplification unit 102 and the noise removal unit 120 are provided in each column, it is possible to perform parallel processing on pixels for one row. In other words, the horizontal scanning circuit 104 can be driven at a lower speed than the case where the signal of each column is read out to the horizontal signal line in an analog manner, so that there is an advantage that it is difficult to generate a noise.

  Next, the configuration of the column AD conversion unit 121 and the replacement unit 122 will be described with reference to FIG. The column AD conversion unit 121 includes a reference signal generation unit 128 and a comparator 129. However, the reference signal generation unit 128 may be configured to supply the RAMP signal in common to each column outside the column AD conversion unit 121. Here, the reference signal generator 128 generates a ramp waveform whose level sequentially increases with the signal φADCLK as the RAMP signal.

  The comparator 129 compares the analog signal ASIG input to the column AD conversion unit 121 with the RAMP signal generated by the reference signal generation unit 128. The comparator 129 is reset by the CNTRST signal and outputs a high level as the output COMPOUT. After reset, the comparator output COMPOUT is maintained at a high level until the level of the RAMP signal input to the − terminal exceeds the level of the ASIG signal at the + terminal. After the level of the RAMP signal exceeds the level of the ASIG signal, the output COMPOUT transitions to a low level. Once the transition is made, the low level is maintained until reset regardless of the input signal.

  The replacement unit 122 includes a determination unit 127 and a 12-bit counter 130. A comparator output COMPOUT is connected to the count-up enable terminal CE of the 12-bit counter 130. Therefore, the counter 130 counts up and outputs the count value until the relationship of the level difference between the RAMP signal and the level of the input signal ASIG is reversed and the comparator output COMPOUT becomes low level. The obtained counter output value corresponds to a value obtained by AD converting the inputted ASIG signal. The counter output value is the lower 12 bits (DATA 0 [11: 0]) of the output of the replacement unit 122.

  The determination unit 127 determines whether to use the counter output as it is based on the result of the counter 130 or reset the counter 130 again to replace the count value, and controls a circuit necessary for the replacement. In addition, the determination unit 127 outputs a FLAG signal so that the determination result can be used for control of signal processing in the subsequent stage. The FLAG signal is the upper 1 bit (DATA0 [12]) of the output of the replacement unit 122. Here, first, the 12-bit decoder 131 decodes the output of the counter 130 obtained by AD-converting the ASIG signal read as the first pixel signal at an amplification factor of 8 times. This decoded value is input to the D-type flip-flop circuit (D-FF circuit) 132, but is reflected as an output of the D-FF circuit 132 only when the φFLAGCHK signal is input to the enable terminal (CE). The output of the D-FF circuit 132 is output as a FLAG signal, and is connected to a D-type flip-flop circuit (D-FF circuit) 133 at the next stage. Both the output of the D-FF circuit 132 and the inverted output of the D-FF circuit 133 are input to the AND circuit 134, and the output and the signal φHSTART are input to the OR circuit 135. The output of the OR circuit 135 is the signal CNTRST, which is input to the counter 130 and the reset terminal of the comparator 129.

  When the output of the counter 130 reaches an arbitrary condition at the timing when the φFLAGCHK signal is input, the output of the 12-bit decoder 131 is reflected in the subsequent stage, and the counter 130 and the comparator 129 are reset as the CNTRST signal. Subsequently, the input signal having the amplification factor of 1 as the second pixel signal is AD converted, and the value of the counter 130 is updated. When the output of the counter 130 does not reach an arbitrary condition, the counter 130 and the comparator 129 are not reset. Therefore, the second pixel signal that is subsequently input is not AD converted, and the value of the counter 130 is the first pixel signal. The value of is not updated.

  In this way, if the digital data after AD conversion of the first pixel signal has reached a certain condition, it is replaced with the digital data after AD conversion of the second pixel signal, and if not, the replacement is not performed. Digital data of one pixel signal is used. As specific examples of conditions set in the decoder 131, for example, a case where all the bits are 1 or a case where the upper 3 bits are 1 is set. In the example to be described later, the case where 4095 is reached is set as a condition, and this case corresponds to when all the output bits of the 12-bit counter 130 become 1. The decoder 131 prepares one 12-input AND circuit after the 12-bit counter 130.

  The column AD conversion unit 121 is provided in each column of the plurality of pixels 101, and the first pixel signal and the second pixel signal amplified by the column amplification unit 102 and noise-removed by the noise removal unit 120 are converted from analog to digital. Convert to The replacement unit 122 is provided in each column of the plurality of pixels 101, and the first pixel signal converted by the column AD conversion unit 121 when the first pixel signal converted by the column AD conversion unit 121 is less than a threshold value (for example, 4095). The pixel signal is selected. The replacement unit 122 selects the second pixel signal converted by the column AD conversion unit 121 when the first pixel signal converted by the column AD conversion unit 121 is equal to or greater than a threshold (for example, 4095). The horizontal scanning circuit 104 sequentially selects the first pixel signal or the second pixel signal of each column selected by the replacement unit 122. The output of the replacement unit 122 for each column is sequentially selected by the horizontal scanning circuit 104 and read to the correction unit 124 at the subsequent stage. In addition, although the case where it is less than a threshold value and the case where it is more than a threshold value was demonstrated to the example, it is the same also when it is below a threshold value and larger than a threshold value.

  FIG. 6 shows configurations of the correction unit 124, the bit conversion unit 125, and the output unit 126. The column amplifying unit 102 has errors such as variation in amplification factor for each solid-state imaging device 1, variation in amplification factor for each column in the solid-state imaging device 1, variation in ratio of different amplification factors, and the like. The correction unit 124 corrects such errors. In the correction unit 124, reference numeral 701 denotes a register for temporarily storing a flag signal input as DATA1 [12], and reference numeral 702 denotes a timing for matching the timing with the corresponding image data when the value of the register 701 is used in the subsequent stage. It is an adjustment circuit. A register 703 temporarily stores the replaced 12-bit image data input as DATA1 [11: 0]. The output of the register 703 is distributed to two paths, and different processing is simultaneously performed on the same signal. Reference numeral 704 denotes a timing adjustment circuit for matching the timing with the path of the multiplication circuit 705. Reference numeral 705 denotes an arithmetic circuit composed of a multiplier or the like, for example, a correction circuit that performs an operation using a value read from the ROM when the apparatus is activated as a correction coefficient by an external microcomputer (not shown) and communication means. Although a fine correction of the amplification factor requires a large calculation scale, it is not necessary to provide the correction processing circuit after being read out by the horizontal scanning circuit 104, and the circuit scale can be suppressed. It is said.

  In the bit conversion unit 125, 706 is a timing adjustment circuit for temporarily storing the flag signal transmitted from the correction unit 124, and its output is transmitted to the selection circuit 709 and the 16-bit register 710 with the timing adjusted. Reference numeral 707 denotes an upper bit addition circuit for adding 3 bits to the upper side of the 12-bit image data transmitted from the timing adjustment circuit 704 of the correction unit 124. As a result, the data level becomes 1/8 with respect to the full scale. Reference numeral 708 denotes an upper bit shift circuit that adds 3 bits to the upper side of the 12-bit image data transmitted from the multiplication circuit 705 of the correction unit 124 and shifts the data to the upper bit side by 3 bits. As a result, the data level is maintained with respect to the full scale. A selection circuit 709 switches the image data from the upper bit addition circuit 707 and the image data from the upper bit shift circuit 708 in accordance with a flag signal from the timing adjustment circuit 706. Reference numeral 710 denotes a 16-bit register for temporarily storing the selected image data 15 bits and the flag 1 bit together. The flag distinguishes between the first pixel signal component and the second pixel signal component. As a result of the determination, the selection circuit 709 selects the output on the higher bit addition circuit 707 side for the digital signal component resulting from the first pixel signal, and the digital signal component resulting from the second pixel signal. For the above, the output of the upper bit shift circuit 708 is selected. As a result, the component resulting from the second pixel signal amplified by the q-times (1 times) amplification factor among the combined signals is the first amplified by the p-times (8 times) amplification factor. Conversion is performed so that the component resulting from the pixel signal is p / q times (8 times) relatively.

  In the output unit 126, a format 711 transmits 16-bit data (15-bit image data + flag 1 bit) DATA 2 [15: 0] from the bit conversion unit 125 to the external system of the solid-state imaging device 1 as output DATAOUT. This is an output format conversion circuit for converting to. For example, the output format conversion circuit 711 is a circuit that uses a low-voltage differential output to reduce external radiation noise, or multiplexes to transmit with a small number of lines and serializes the number of signal pair lines less than the number of bits. is there. In the output format conversion circuit 711, the output data is 16 bits. However, if the flag signal from the timing adjustment circuit 706 is unnecessary after the solid-state imaging device 1, it may be output as 15-bit data including only image data. Absent.

  A driving method of the solid-state imaging device 1 from the column AD conversion unit 121 to the output unit 126 will be described with reference to FIGS. 7 and 8 together with FIGS. 7 and 8 show the difference in operation between the case where the flag FLAG in the second pixel signal period is at the high level and the case in which the flag FLAG is at the low level based on the determination performed by the replacement unit 122 according to the level of the image signal ASIG. Yes. 7 and 8, one horizontal scanning (1H) period is shown as a period between the start pulses φHSTART of the horizontal scanning circuit 104. Here, a signal between the nth Vn line and the (n + 1) th Vn + 1 line of the vertical scanning circuit 103 is shown. ΦHCLK is a scanning clock of the horizontal scanning circuit 104. The signal φCOLSEL2 indicates a read period from the noise removal unit 120 of the first pixel signal at an amplification factor of 8 times, and the signal φCOLSEL1 reads out the second pixel signal from the noise removal unit 120 at an amplification factor of 1 Indicates the period.

  The ASIG signal indicates an analog signal input to the column AD conversion unit 121, and the RAMP signal indicates a comparison signal generated by the reference signal generation unit 128 for AD conversion. COMPOUT is a comparison result between the two by the comparator 129. φADCLK is a clock used by the reference signal generator 128, the counter 130, and the like to perform AD conversion. Further, φFLAGCHK is a trigger signal that gives a timing for performing replacement determination, and the FLAG signal is a flag as a result output of the determination unit 127. CNTRST is a reset signal for the counter 130 and the comparator 129, and DATA 0 [11: 0] is the lower 12 bits of the output of the replacement unit 122. φHCLK is a clock of the horizontal scanning circuit 104, and DATA1 [12: 0] is an image signal and a flag signal sequentially read from each column input to the correction unit 124. DATA2 [15: 0] is the output of the bit conversion unit 125, and DATAOUT indicates the output of the output unit 126.

  Of one horizontal scanning period, a period before each column is sequentially selected and horizontal scanning is performed is referred to as a blanking period. During the blanking period, the signal is read twice from the pixel unit 10 to the noise removing unit 120 while changing the amplification factor in the column amplification unit 102 as described above. Further, in the same blanking period, first, a signal corresponding to the first pixel signal amplified by an amplification factor of 8 is read from the noise removing unit 120 during the period of the signal φCOLSEL2, and the ASIG signal is input to the comparator 129. . At this time, the ASIG signal is compared with the RAMP signal generated by the reference signal generation unit 128 using φADCLK as a clock. The comparison result output COMPOUT changes to the low level while the level of the RAMP signal is lower than the ASIG signal, and changes to the high level when it exceeds.

  In FIG. 7, the level of the RAMP signal is lower than the ASIG signal until the count number of φADCLK reaches the maximum value 4095 (decimal number) of 12 bits. Therefore, COMPOUT is not inverted until this timing, and the 12-bit counter 130 outputs the maximum value 4095 as the count value. In this embodiment, the 12-bit decoder 131 is set to output a high level when reaching 4095 or more, and transitions to a high level output at this point. Therefore, the flag signal FLAG transitions to a high level when φFLAGCHK is input. Further, the CNTRST signal resets the comparator 129 and the counter 130. As a result, the count value DATA0 [11: 0] once becomes 4095 in the decimal number, but again returns to the initial value and is counted up.

  Next, during the period of the signal φCOLSEL1, a signal corresponding to the second pixel signal amplified by the amplification factor of 1 is read from the noise removing unit 120, and the ASIG signal is input to the comparator 129 and compared with the RAMP signal again. Is done. In the second reading, when the φADCLK count reaches 2047, the level of the RAMP signal exceeds the ASIG signal, and COMPOUT is inverted. As a result, the 12-bit counter 130 outputs 2047 as the count value. As a result, the output of this column in the illustrated vertical row Vn line is determined as DATA0 [11: 0] = 2047 and FLAG = DATA0 [12] = 1.

  In accordance with the clock φHCLK of the horizontal scanning circuit 104, the output value of each column determined in this way is sent to the correction unit 124 and the subsequent and subjected to pipeline processing. In DATA1 [12: 0] input to the correction unit 124, as described above, the error caused by the column amplification unit 102 or the like is corrected for the signal of the corresponding flag. The bit conversion unit 125 converts the 13-bit signal into the 16-bit output DATA2 [15: 0], and then the output unit 126 converts the signal into a differential output, which is output from the solid-state imaging device 1 as the output DATAOUT. .

  Here, processing performed in the correction unit 124 and the bit conversion unit 125 will be described with reference to the schematic diagram of FIG. 9. FIG. 9A schematically shows a signal read from the pixel 101 with an amplification factor of 8 times, the horizontal axis indicates the position in one row, and a, b, and c are the respective columns. Indicates the position. Here, the signal read from the pixel increases from 0 to 4095 which is the maximum value of 12 bits as it progresses from the 0th column to the ath column. It decreases from 4095 toward 0 until column c. FIGS. 9B and 9C schematically show signals read from the pixels 101 at a single amplification factor, and a, b, and c are the positions of the columns as in FIG. 9A. Is shown. Originally, because the same pixel signals have different amplification factors by 8 times, the values in columns a and b in FIGS. 9B and 9C are ((4095 + 1) / 8) −1 as indicated by dotted lines. = 511. However, in actuality, due to an amplification factor error of the column amplification unit 102, the values in the a column and the b column have errors as indicated by solid lines. FIG. 9B shows a case where the value is obtained larger and FIG. 9C shows a smaller value. For this reason, the correction unit 124 multiplies the correction coefficient so that the values of the a column and the b column become 511 in the situation as shown in FIG. 9B or FIG. Is corrected so as to coincide with FIG. Also, the bit conversion unit 125 performs a process that does not change the value of the signal of FIG. 9A by simply adding 3 higher bits, and converts the signal to the signal of FIG. 9B or 9C. On the other hand, 3 bits are added and 3 bits are shifted to the upper side. As a result of the bit shift, the signal in FIG. 9B or FIG. 9C is converted to a value of 8 times. Actually, at the stage of the replacement unit 122 before correction, 4095 is set as a threshold value, and the signals in FIG. Until this time, the signals shown in FIG. 9B or 9C are synthesized in such a manner that they are identified by flags. The data after correction and bit conversion is shown in FIG. 9D in the case of the combination of FIGS. 9A and 9B, and in the case of the combination of FIGS. 9A and 9C, the data in FIG. Become. In FIG. 9D, the maximum value is saturated, but no gradation level difference occurs in the a row and b row of the joint where the images of FIGS. 9A and 9B are combined, and image quality deterioration is suppressed. It is done.

  Here, the case where a signal having an amplification factor of 1 is read first will be discussed with reference to FIG. FIG. 10A schematically shows a signal read from the pixel 101 with a gain of 1 ×, the horizontal axis indicates the position in one row, and a, b, and c are each column. Indicates the position. Here, the signal read from the pixel 101 increases from 0 to 4095 which is the maximum value of 12 bits as it progresses from the 0th column, and becomes 511 in the ath column. In addition, from 4095 to c column, the value decreases from 4095 to 0, and b column becomes 511. FIGS. 10B and 10C schematically show signals read from the pixels with an amplification factor of 8 times, and a, b, and c indicate the positions of the columns as in FIG. Show. Originally, because the same pixel signals differ in amplification factor by 1/8, the values in columns a and b in FIGS. 10B and 10C are indicated by dotted lines ((511 + 1) / 8). -1 = 4095. However, in actuality, due to an amplification factor error of the column amplification unit 102, the values in the a column and the b column have errors as indicated by solid lines. FIG. 10B shows a case where the value is obtained smaller and FIG. 10C shows a larger value. For this reason, the correction unit 124 multiplies the correction coefficient so that the values in the a column and the b column become 511 in the case of the situation shown in FIG. Is corrected so as to coincide with FIG. Further, the bit conversion unit 125 adds 3 bits to the signal shown in FIG. For the signal of FIG. 10B or FIG. 10C, processing is performed in which the value does not change by simply adding 3 higher bits. As a result of the bit shift, the signal in FIG. 10A is converted to an eightfold value. The data after correction and bit conversion is as shown in FIG. 10D for the combination of FIGS. 10A and 10B, and as shown in FIG. 10E for the combination of FIGS. 10A and 10C. However, in FIG. 10B, since the data in the 0th to 0th columns does not exceed 4095, it is possible to correct the solid line data as shown by the dotted line. However, in FIG. 10C, the data from the 0th column to the ath column exceeds 4095. Therefore, even if the solid line data is corrected like the dotted line, some data saturated at 4095 is , Can not be corrected. For this reason, in the vicinity of the a column and the b column in FIG. 10 (e), image quality deterioration that causes unnatural joints of images occurs. For this reason, in the present embodiment, the first pixel signal and the second pixel signal are read out, column AD conversion is performed, determination is performed using the first pixel signal, and synthesis is performed. In this case, the present embodiment can reduce the error with a small configuration by using a signal read with a high amplification factor as an image to be determined.

  As illustrated in FIG. 6, the correction unit 124 is configured so that the first pixel signal and the second pixel signal selected by the horizontal scanning circuit 104 are relative to each other between the first pixel signal and the second pixel signal. The error is corrected and output to the bit converter 125. The bit conversion unit 125 selects the first pixel signal or the second pixel signal selected by the horizontal scanning circuit 104 and corrected by the correction unit 124 with respect to the first pixel signal at a first magnification (for example, 1). The pixel signal multiplied by (times) and having an increased number of bits. Then, the bit conversion unit 125 outputs a pixel signal in which the second pixel signal is multiplied by a second magnification (p / q times) different from the first magnification and the number of bits is increased. Here, p> q, for example, p = 8 and q = 1. The replacement unit 122 outputs a flag signal FLAG indicating which one of the first pixel signal and the second pixel signal is selected to the bit conversion unit 125. When the flag signal FLAG indicates selection of the first pixel signal, the bit conversion unit 125 outputs a pixel signal in which the first pixel signal is multiplied by the first magnification and the number of bits is increased. Then, when the flag signal FLAG indicates selection of the second pixel signal, the bit conversion unit 125 outputs a pixel signal in which the second pixel signal is multiplied by the second magnification and the number of bits is increased.

  In FIG. 8, since the level of the RAMP signal exceeds the ASIG signal when the count number of φADCLK reaches 1999 (decimal number) of 12 bits, COMPOUT is also inverted at this timing, and the 12-bit counter 130 is “1999”. Is output as a count value. In this embodiment, the 12-bit decoder 131 is set to output a high level when reaching 4095 or more, and therefore the output of the decoder 131 remains at a low level. For this reason, the flag signal FLAG maintains a low level even when φFLAGCHK is input. Therefore, the comparator 129 and the counter 130 are not reset at this stage, and no replacement is performed. During the high level period of the signal φCOLSEL1, a signal corresponding to the second pixel signal amplified by the amplification factor of 1 is read from the noise removing unit 120. Then, the ASIG signal is input to the comparator 129 and the RAMP signal is also input, but the comparator 129 does not compare the two. In the second reading, the level of the RAMP signal exceeds the ASIG signal when the count of φADCLK reaches 249, but COMPOUT remains at a low level.

  As a result, the output of this column in the illustrated vertical row Vn line is determined by DATA0 [11: 0] = 1999 and FLAG = DATA0 [12] = 0. Also in this case, in accordance with the clock φHCLK of the horizontal scanning circuit 104, the determined output value of each column is sequentially output as DATA1 [12: 0] to the correction unit 124 and subjected to pipeline processing, whereby the bit conversion unit 125 has 16 bits. Output DATA2 [15: 0]. Thereafter, the output unit 126 converts the output into a differential output and outputs the output DATAOUT from the solid-state imaging device 1.

  The point of this embodiment is to read out a plurality of pixel signals whose amplification factors are switched and read out the signals for each column while reading out the image signal of one horizontal scanning period from the solid-state imaging device 1. That is, the column amplification unit 102, the column AD conversion unit 121, and the replacement unit 122 are configured so that the first pixel signal and the second pixel are output during a period in which the horizontal scanning circuit 104 selects and outputs pixel signals for one row. Perform signal processing. In addition, the column AD conversion unit 121 and the replacement unit 122 provided in each column are used as composition for each column. As a result, it is possible to obtain an output with an accuracy equivalent to a high number of bits that would otherwise take a longer time for AD conversion in the time required to perform column AD conversion with a smaller number of bits twice. In column AD conversion, it is generally known that the conversion time increases as the bit precision of data increases. For example, in the case of a system that performs AD conversion in comparison with a simple ramp-type reference signal, a conversion time that is eight times that of 12 bits is required to obtain 15-bit accuracy. According to the present embodiment, by changing the amplification factor twice and reading the signal twice and performing the 12-bit AD conversion twice, the AD conversion time can be reduced to ¼ while obtaining the accuracy equivalent to 15 bits. . In addition, since the same signal is simply read out at two amplification factors determined in advance in units of rows, it is not necessary to feed back the signal of the previous frame and reflect the result, and it is not necessary to perform accumulation twice, and the frame rate I can do it quickly. Although it is necessary to read out the pixel signal twice and perform AD conversion, it is determined that the rate of speed reduction is small. In addition, since the first pixel signal and the second pixel signal are read out by horizontal scanning after synthesis in each column, it is not necessary to prepare a memory for frame synthesis outside the solid-state imaging device 1, thereby reducing the circuit scale. it can. Further, it is not necessary to individually feedback control the amplification factor of each column, and the column amplification unit 102 of each column performs a common operation, so that the structure can be simplified. In this way, with a small circuit scale and a small decrease in operation speed, the S / N ratio of the signal output from the solid-state image sensor 1 can be improved and the solid-state image sensor 1 with an expanded dynamic range can be realized.

(Second Embodiment)
In the first embodiment, the column AD conversion unit 121 performs AD conversion on the signal read out twice by changing the amplification factor from the same column amplification unit 102 in one horizontal scanning period, and the replacement provided in each column The synthesis was performed in part 122. In the second embodiment of the present invention, pixel signals having different amplification factors are simultaneously read out from two column amplification units in one horizontal scanning period, and the two signals are subjected to AD conversion and synthesis by one column AD conversion unit. An example is shown.

  FIG. 11 is an equivalent circuit diagram of the solid-state imaging device 1 according to the second embodiment of the present invention. The configuration of the column amplification units 102A and 102B and the noise removal unit 120 for one pixel 101 is shown in more detail. The present embodiment is characterized in that two systems of column amplification units 102A and 102B and noise removal unit 120 are prepared for each column. The pixel 101 is the same as that in the first embodiment (FIG. 3). Also, in FIG. 11, those given the same numbers are the same parts as in FIG. 3 of the first embodiment. The column amplification units 102A and 102B are amplification units having different amplification factors provided in the same pixel column, and are provided in place of the column amplification unit 102 of the first embodiment. Here, the capacitance values of the feedback capacitors C1 and C2 are set to be 1 and 1/8 times the capacitance value of the input capacitor C0, respectively. That is, in this embodiment, two column amplification units 102A and 102B having different amplification factors are provided. The signal amplified by the column amplification unit 102A is selectively transmitted to and held in the storage capacitor CTS1 or CTN1 in the noise removal unit 120. Further, the signal amplified by the column amplifier 102B is selectively transmitted to and held in the holding capacitor CTS2 or CTN2 in the noise removing unit 120. The holding capacitors CTS1 and CTS2 hold a signal based on charges obtained by photoelectric conversion by the photodiode PD, and the holding capacitors CTN1 and CTN2 hold a signal based on resetting the pixel output unit SF. The Thereafter, as in the first embodiment, the signals held in the holding capacitors CTS1 and CTN1 are transferred to the differential amplifier D.D via a switch that is turned on by the signal φCOLSEL1. The signal is input to an input terminal having a different Amp. The signals held in the holding capacitors CTS2 and CTN2 are supplied to the differential amplifier D.D via a switch that is turned on by the signal φCOLSEL2. The signal is input to an input terminal having a different Amp. Differential amplifier Amp1 outputs the difference between the signals held in the holding capacitors CTS1 and CTN1 and the difference between the signals held in the holding capacitors CTS2 and CTN2 in time series.

  First, operations in one horizontal scanning period related to the pixel 101, the column amplification units 102A and 102B, and the noise removal unit 120 illustrated in FIG. 11 will be described with reference to FIG. The capacitance values of the feedback capacitors C1 and C2 are assumed to be 1 and 1/8 times the capacitance value of the input capacitor C0. That is, a case where one signal is amplified with an amplification factor of 1 and 8 will be described. First, at time t0, signals other than the signals φTX and φHn transition to a high level. Since the pixel selection unit SEL becomes conductive when the signal φSEL becomes high level, the source terminal of the pixel output unit SF and the constant current source Icnt are electrically connected to form a source follower circuit. Accordingly, a level corresponding to the potential of the gate terminal of the pixel output unit SF appears on the vertical signal line VL as a signal. Since the signal φRES is at the high level at this timing, the reset unit RES is turned on, and a level corresponding to the state in which the gate terminal of the pixel output unit SF is reset appears on the vertical signal line VL. Further, when the signals φC, φC1, and φC2 become high level, the inverting input terminal and the output terminal of the operational amplifier Amp are short-circuited, and the feedback capacitors C1 and C2 are reset. Due to the virtual grounding of the operational amplifier Amp, the potentials of both terminals of the feedback capacitors C1 and C2 can be regarded as the same potential as the power supply Vref. Since the signals φCTN1, φCTS1, φCTN2, and φCTS2 are at a high level, the holding capacitors CTN1, CTS1, CTN2, and CTS2 are reset by the output of the operational amplifier Amp.

  The operation from time t1 to t3 is the same as in the first embodiment. At time t7, when the signals φCTN1 and φCTN2 become a high level in a pulse shape and the signals φCTN1 and φCTN2 become a low level, signals including offset components caused by the column amplification units 102A and 102B are held in the holding capacitors CTN1 and CTN2. . When the signal φTX transits to a high level at time t8, the charge accumulated in the photodiode PD is transferred to the gate terminal of the pixel output unit SF. The signals φCTS1 and φCTS2 are at a high level in a pulse shape from time t8, and the signal amplified by the column amplifier 102A is held by the storage capacitor CTS1 when the signal φCTS1 transitions to a low level. Further, the signal amplified eight times by the column amplifier 102B is held in the holding capacitor CTS2 when the signal φCTS2 transitions to a low level.

  At time t9, the signals φC1 and φC2 transition to the low level. Thereafter, when the signal φSEL becomes low level, the pixel selection unit SEL is turned off and the selection state of the pixel 101 is released. When the signal φCOLSEL2 becomes high level at time t11, the signals held in the holding capacitors CTS2 and CTN2 are changed to the differential amplifier D.D. Output to Amp. Differential amplifier Amp outputs a difference signal between the signals of the storage capacitors CTS2 and CTN2 to the column AD conversion unit 121 as a first pixel signal. Subsequently, when the signal φCOLSEL1 becomes high level at time t13, the signals held in the holding capacitors CTS1 and CTN1 are changed to the differential amplifier D.D. Output to Amp. Differential amplifier Amp outputs a difference signal between the signals of the storage capacitors CTS1 and CTN1 to the column AD conversion unit 121 as a second pixel signal. The column AD converter 121 and the subsequent steps are the same as those shown in FIGS. 5 and 6 of the first embodiment. The first pixel signal and the second pixel signal are AD-converted by the column AD conversion unit 121, and then one of the first pixel signal and the second pixel signal is selected as an output signal for each column by the replacement unit 122. Thereafter, at time t14, the replacement data of each column is sequentially read out to the subsequent correction unit 124 by the drive pulse φHCLK of the horizontal scanning circuit 104.

  As described above, the first column amplifying unit 102B outputs the first pixel signal that has been amplified with an amplification factor of p times (for example, 8 times). The second column amplification unit 102A outputs a second pixel signal amplified with an amplification factor of q times (for example, 1 time). As a result, it is possible to obtain an output with an accuracy equivalent to a high number of bits that would otherwise take a longer time for AD conversion in the time required to perform column AD conversion with a smaller number of bits twice. According to the present embodiment, by changing the amplification factor twice and reading the signal twice and performing the 12-bit AD conversion twice, the AD conversion time can be reduced to ¼ while obtaining the accuracy equivalent to 15 bits. . In addition, since only the signal of the same pixel 101 is read at two amplification factors determined in advance in units of rows, there is no need to feed back the signal of the previous frame and reflect the result, or to perform accumulation twice. The frame rate can also be increased. In addition, since the first pixel signal and the second pixel signal are read out by horizontal scanning after synthesis in each column, it is not necessary to prepare a memory for frame synthesis outside the solid-state imaging device 1, thereby reducing the circuit scale. it can. In addition, it is not necessary to individually feedback control the amplification factor of each column, and the column amplification units 102A and 102B of each column perform a common operation, so that the structure can be simplified.

  According to the first and second embodiments, a time delay for one frame does not occur, the circuit scale does not increase in the memory unit, a reduction in operation speed is prevented, and a signal output from the solid-state imaging device 1 The solid-state imaging device 1 having an improved S / N ratio and an expanded dynamic range can be realized.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor, 101 pixels, 102 column amplification part, 103 vertical scanning circuit, 104 horizontal scanning circuit, 121 column AD (analog-digital) conversion part, 122 substitution part, 124 correction | amendment part, 125 bit conversion part

Claims (7)

A plurality of pixels arranged in a two-dimensional matrix and generating signals using photoelectric conversion elements;
A first pixel signal that is provided in each column of the plurality of pixels and that is amplified with a gain of p times with respect to the signal of the same pixel, and a second pixel that is amplified with a gain of q times different from the p times A column amplifier for outputting a signal;
A holding unit that is provided corresponding to each of the plurality of column amplification units and holds an output of the corresponding column amplification unit;
A column AD conversion unit that is provided in each column of the plurality of pixels and that is held in the holding unit and that converts the first pixel signal and the second pixel signal amplified by the column amplification unit from analog to digital; ,
When the first pixel signal provided in each column of the plurality of pixels and converted by the column AD conversion unit is less than a threshold, the first pixel signal converted by the column AD conversion unit is selected, and the column A replacement unit that selects the second pixel signal converted by the column AD conversion unit when the first pixel signal converted by the AD conversion unit is larger than a threshold;
Have a horizontal scanning circuit for sequentially selecting the first pixel signal or the second pixel signals of each column selected by said replacement unit,
The column amplifying unit includes an operational amplifier, an input capacitor, and a plurality of feedback capacitors capable of switching connection states.
The pixel is reset, and at least two of the feedback capacitors are connected, and the input / output terminal of the operational amplifier is short-circuited,
Thereafter, one of the feedback capacitors is electrically disconnected from the feedback path, and the holding unit holds the output of the column amplification unit with the gain of the column amplification unit multiplied by q.
Thereafter, the other feedback capacitor is electrically disconnected from the feedback path, and the one feedback capacitor is electrically connected to the feedback path, so that the column amplification unit has a gain of p times in the state where the gain is increased. The holding unit holds the output of the amplification unit,
Thereafter, a signal based on photoelectric conversion of the photoelectric conversion element in a state where the gain of the column amplification unit is p times is output from the pixel, and further, the output of the column amplification unit is held by the holding unit,
Thereafter, the one feedback capacitor is electrically disconnected from the feedback path, and the other feedback capacitor is electrically connected to the feedback path, so that the gain of the column amplifier is increased by q times. An imaging apparatus , wherein the holding unit holds the output of the amplification unit .   The column amplification unit, the column AD conversion unit, and the replacement unit may be configured such that the first pixel signal and the second pixel are output during a period in which the horizontal scanning circuit selects and outputs pixel signals for one row. 2. The image pickup apparatus according to claim 1, wherein the image pickup apparatus performs signal processing. p> q,
3. The imaging apparatus according to claim 1, further comprising a bit conversion unit that outputs a pixel signal obtained by multiplying the second pixel signal selected by the horizontal scanning circuit by p / q times. .   The imaging apparatus according to claim 1, wherein the column amplification unit outputs the first pixel signal and the second pixel signal in time series. The column amplification unit includes:
A first column amplifier for outputting a first pixel signal amplified at the amplification factor of p,
The imaging apparatus according to claim 1, further comprising: a second column amplification unit that outputs a second pixel signal amplified by the amplification factor of q.   Further, a signal amplified by the column amplifier in the reset state of the pixel and a signal amplified by the column amplifier in the reset release state of the pixel are provided in each column of the plurality of pixels in the subsequent stage of the column amplifier. The imaging apparatus according to claim 1, further comprising a noise removal unit that outputs a difference signal from the amplified signal to the column AD conversion unit. Driving an imaging apparatus having a plurality of pixels arranged in a two-dimensional matrix and generating a signal using a photoelectric conversion element, and a column amplification unit including an operational amplifier, an input capacitor, and a plurality of feedback capacitors whose connection state can be switched. A method,
For each column of the plurality of pixels, a first pixel signal amplified at a p-fold amplification rate with respect to the signal of the same pixel and a second pixel signal amplified at a q-fold amplification rate different from the p-fold are obtained. An output column amplification step;
A column AD conversion step for converting the first pixel signal and the second pixel signal amplified by the column amplification step from analog to digital for each column of the plurality of pixels;
For each column of the plurality of pixels, when the first pixel signal converted by the column AD conversion step is less than a threshold, the first pixel signal converted by the column AD conversion step is selected, and the column AD conversion is performed. A replacement step of selecting the second pixel signal converted by the column AD conversion step when the first pixel signal converted by the step is larger than a threshold;
Have a horizontal scanning step of sequentially selecting the first pixel signal or the second pixel signals of each column selected by said replacement step,
In the column amplification step,
The pixel is reset, and at least two of the feedback capacitors are connected, and the input / output terminal of the operational amplifier is short-circuited,
Thereafter, one of the feedback capacitors is electrically disconnected from the feedback path, and the output of the column amplification unit is held in a state where the gain of the column amplification unit is multiplied by q.
Thereafter, the other feedback capacitor is electrically disconnected from the feedback path, and the one feedback capacitor is electrically connected to the feedback path, so that the column amplification unit has a gain of p times in the state where the gain is increased. Hold the output of the amplifier,
Thereafter, a signal based on photoelectric conversion of the photoelectric conversion element in a state where the gain of the column amplification unit is p times is output from the pixel, and further holds the output of the column amplification unit,
Thereafter, the one feedback capacitor is electrically disconnected from the feedback path, and the other feedback capacitor is electrically connected to the feedback path, so that the gain of the column amplifier is increased by q times. A driving method of an imaging apparatus, characterized by holding an output of an amplification unit .

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