JP5417939B2 - High frequency signal output test method and semiconductor device - Google Patents

Description

  The present invention relates to a high-frequency signal output test method and a semiconductor device for testing a semiconductor device that outputs a high-frequency signal with a tester, and more particularly to impedance matching of a high-frequency signal output for testing.

  Currently, semiconductor devices (LSIs) that handle high-frequency signals such as digitally modulated RF signals, such as TV tuners and portable terminals, output high-frequency signals and evaluate the characteristics of high-frequency output signals with a tester to assure quality. . The evaluation is generally performed by evaluating characteristics such as EVM constellation, spectrum flatness, and spectrum mask.

  A test of a semiconductor device that handles high-frequency signals is performed by setting a test target semiconductor device (DUT) on a test board and connecting a tester to the test board. In testing high frequency signals that are output, it is very important to match the impedance. The signal path between the DUT and the tester needs a certain length, and the output impedance of the high-frequency signal is greatly influenced by the length of the signal path. The test is performed by connecting an impedance matching circuit to the output of the high frequency signal and inputting the high frequency signal output from the impedance matching circuit to the tester.

  Since the characteristics of the semiconductor device also vary and the characteristics of the tester also vary, if the connection is made as it is, the variation in the impedance of the signal path is large and a normal test cannot be performed. Therefore, a plurality of impedance matching circuits that provide different impedance values are prepared. For each DUT, a plurality of impedance matching circuits are connected, the impedance matching circuit with the best measurement result by the tester is selected, and the selected impedance matching circuit is connected to perform measurement for characteristic evaluation. The impedance matching circuit is created by determining the impedance. However, since the capacitance and the inductor forming the impedance matching circuit have manufacturing variations, the impedance value varies from circuit to circuit.

  FIG. 1 is a diagram showing a general test environment of a semiconductor device that handles high-frequency signals.

  As shown in FIG. 1, a test target semiconductor device (DUT) 10 that outputs a high-frequency signal (RF Out) is mounted on a test board. The DUT 10 can be attached to and detached from the test board 10, and the DUTs 10 are mounted one after another for testing. The test board 10 is provided with an impedance matching circuit 21. The impedance matching circuit 21 is also detachable from the test board 10. As shown in FIG. 1, the impedance matching circuit 21 is a circuit in which a capacitor C and inductors L1 and L2 are connected. Depending on the capacitance value of the capacitor C and the inductance values of the inductors L1 and L2, the impedance matching circuit 21 Give different impedance values. A tester 30 is connected to the output of the impedance matching circuit 21 of the test board 20.

  As shown in FIG. 1, the tester 30 includes an amplifier 31 that amplifies an input signal, a down converter 32 that extracts a carrier band from a high-frequency signal, and an AD converter (ADC) 33 that converts the extracted signal into a digital signal. The digital demodulator 34 that demodulates the digital signal from the output of the ADC 33, the calibrator 35 that normalizes the frequency characteristics using the signal of the digital demodulator 34, and adjusts the characteristics of the measurement system to the ideal values, and displays the digital signal. It has a waveform display unit 36 and an arithmetic circuit 37 that digitizes the measured digital signal and evaluates it. In the mass production process, the arithmetic circuit 37 determines the quality of the product based on the evaluation result.

  An EVM constellation can be used for signal quantification and evaluation. As shown in FIG. 2, in the EVM constellation, it is digitized as an error vector that is a vector difference of a measured value with respect to an ideal value on IQ coordinates. Note that the above-described spectrum flatness, spectrum mask, and the like may be used for signal quantification and evaluation.

  As described above, since the impedance of the high-frequency signal is affected by the length of the signal path, the impedance matching circuit 21 is required to be disposed in the immediate vicinity of the semiconductor device 10.

  Further, although there is a method of using a Smith chart for adjusting the impedance, optimization by this method is difficult because of variations in impedance of the semiconductor device (DUT) itself to be measured and the impedance matching circuit.

JP 2004-097588 A Japanese Patent Laid-Open No. 2007-218779

  As described above, since the characteristics of the semiconductor device 10 and the tester 30 vary, the optimal capacitance value and inductance value of the impedance matching circuit in the measurement environment cannot be obtained by simulation. This is because there is a difference between the actual measurement environment and the simulation, and the above variation causes an error.

  Therefore, multiple impedance matching circuits that give different impedance values as described above are prepared, and the optimum impedance circuit is determined by repeating the replacement of the impedance matching circuit manually. There was a problem of requiring a lot of man-hours.

  Therefore, it has been desired that the impedance can be easily optimized when the output signal of the semiconductor device that outputs a high-frequency signal is tested with a tester.

  The high-frequency signal output test method according to the embodiment is a high-frequency signal output test method in which a semiconductor device that outputs a high-frequency signal from an output terminal is tested with a tester. In the method of the embodiment, an impedance matching circuit having a plurality of impedance adjustment units that give different impedance adjustment amounts and a selection circuit that selects any one of the impedance adjustment units according to a selection signal is connected to the output terminal. Then, while changing the selection of multiple impedance adjustment units, measure the high-frequency signal output from the impedance matching circuit with a tester, select the optimum impedance adjustment unit based on the measurement results, and select the optimum impedance matching circuit. The adjustment unit is set to the selected state, and the high-frequency signal output from the impedance matching circuit is tested with a tester.

  According to the embodiment, the optimization of impedance when the output signal of a semiconductor device that outputs a high-frequency signal is tested with a tester is automated, and a plurality of impedance adjustment units can be tried in a short time compared with manual operation. Can do.

FIG. 1 is a diagram showing a general test environment of a semiconductor device that handles high-frequency signals. FIG. 2 is a diagram for explaining quantification and evaluation of a high-frequency signal by the EVM constellation. FIG. 3 is a diagram illustrating a test environment according to the embodiment. FIG. 4 is a diagram illustrating a configuration of the impedance matching circuit according to the embodiment. FIG. 5 is a diagram illustrating a configuration of another impedance matching circuit according to the embodiment. FIG. 6 is a flowchart showing the measurement operation in the embodiment. FIG. 7 is a flowchart showing another measurement operation in the embodiment. FIG. 8 is a diagram illustrating a modification of the test environment. FIG. 9 is a diagram illustrating a modification of the test environment.

  FIG. 3 is a diagram illustrating a measurement environment of a semiconductor device that handles high-frequency signals in the embodiment.

  As shown in FIG. 3, a test target semiconductor device (DUT) 10 that outputs a high-frequency signal (RF Out) is mounted on a test board. The DUT 10 can be attached to and detached from the test board 10, and the DUTs 10 are mounted one after another for testing. The test board 10 is provided with an impedance matching circuit 40. The impedance matching circuit 40 is fixed to the test board 10. A tester 30 is connected to the output of the impedance matching circuit 40 of the test board 20.

  The impedance matching circuit 40 includes a selection circuit having an input-side selector 41, an output-side selector 42, and a decoder circuit 43, and a plurality (16 in this case) of impedance adjustment units Z11-Zmn. The input side selector 41 forms a signal path for transmitting a high frequency signal from the input terminal to the impedance adjustment unit indicated by the output of the decoder circuit 43. The output side selector 42 forms a signal path for transmitting the high frequency signal that has passed through the impedance adjustment unit designated by the output of the decoder circuit 43 to the output terminal. In response to the selection signal input from the tester 30, the decoder circuit 43 outputs a decode signal indicating the impedance adjustment unit to be selected.

  Each impedance adjustment unit is a circuit in which a capacitor C and inductors L1 and L2 as shown in FIG. 1 are connected. When the plurality of impedance adjustment units Z11-Zmn are arranged in an m × n matrix, the inductance values of the inductors L1 and L2 sequentially change in the column direction, and the capacitance value of the capacitor C sequentially changes in the row direction. Is set. Therefore, the inductance values of the inductors L1 and L2 from Zj1 to Zjn (j = 1 to m) are the same, and the capacitance values of the capacitors C from Z1k to Zmk (k = 1 to n) are the same. Each impedance adjustment unit gives an impedance value determined by the set inductance value and capacitance value to the high-frequency output signal. Therefore, the impedance adjustment unit having a combination of different inductance values and capacitance values may give a similar impedance value, but the high-frequency signal passed through the impedance adjustment unit having a different inductance value and capacitance value even though the impedance values are similar. Are not necessarily identical in characteristics.

  The impedance matching circuit 40 is an IC, and the path length from the input terminal to the output terminal can be shortened regardless of which impedance adjustment unit is selected.

  As in the case of FIG. 1, the tester 30 includes an amplifier 31, a down converter 32, an ADC 33, a digital demodulation circuit 34, a calibrator 35, a waveform table 36, and an arithmetic circuit 37. The tester 30 further includes a storage circuit 38 that stores the evaluation result of the arithmetic circuit 37, and a control circuit 39.

  The control circuit 39 outputs to the decoder circuit 43 a selection signal that indicates an impedance adjustment unit to be selected in the impedance matching circuit 40. Further, the control circuit 39 compares the evaluation results stored in the storage circuit 38 to determine an impedance adjustment unit that provides an optimal evaluation result, and selects such that a signal path including the determined optimal impedance adjustment unit is established. Output a signal.

  FIG. 4 is a diagram illustrating a configuration example of the impedance matching circuit 40. The example shown in FIG. 4 is the case where m and n of each of the plurality of impedance adjustment units Z11-Zmn is 4, and Z11-Z44 of a 4 × 4 matrix is changed to Z11,..., Z14, Z21,. , Z31,..., Z34, Z41,.

  Since the output-side selector 42 has a symmetric configuration with the input-side selector 41, only the block is shown here, and the internal configuration is not shown. The input-side selector 41 includes a plurality of switches arranged in a hierarchy in a tree form of a binary tree, and P-channel transistors and N-channel transistors that function as switches are provided at each branch point. The decoder circuit 43 outputs a 4-bit decode signal of j0, j1, k0, and k1. The decode signals j0, j1, k0, and k1 take one of two states “L” and “H”. The decode signals j0, j1, k0, and k1 are applied to the gates of the P-channel transistor and the N-channel transistor in the first to fourth stages, respectively. The P-channel transistor is turned on when the decode signal is “L”, and is turned off when the decode signal is “H”. The N-channel transistor is turned on when the decode signal is “H”, and is turned off when the decode signal is “L”. Therefore, one of the 16 signal paths connected to the 16 impedance adjustment units Z11 to Z44 is selected to be conducted by the decode signal. In the other signal paths, at least one switch (transistor) is in a cut-off state, and no signal path is formed.

  Since the output side selector 42 has a symmetric configuration with the input side selector 41, a signal path is established in which only the selected impedance adjustment unit is connected to the output terminal, and the other signal paths are partially cut off. .

  If variable J is represented by 2 bits of decoded signals j0 and j1, variable K is represented by 2 bits of decoded signals k0 and k1, and each takes a value of 1-4, impedance adjustment unit ZJK is determined by decoded signals J and K. The signal path that passes is selected. Hereinafter, this is expressed as the impedance adjustment unit ZJK being selected. If j0 is the most significant bit and k1 is the least significant bit, JK takes 16 values of 11, 12, ..., 14, 21, ..., 24, ..., 41, ..., 44.

  As described above, when the plurality of impedance adjustment units Z11-Zmn (here, m, n = 4) are arranged in an m × n matrix, the inductance values of the inductors L1 and L2 change in order in the column direction. In addition, the capacitance value of the capacitor C is set so as to sequentially change in the row direction. By changing the impedance value according to the value of JK, the corresponding impedance adjustment unit can be selected.

  For example, if j0, j1, k0, and k1 are 1, 0, 0, and 1, respectively, J is 3 and K is 2, and the impedance adjustment unit Z32 is selected.

  FIG. 5 is a diagram illustrating another configuration example of the impedance matching circuit 40. The example shown in FIG. 5 is a case where m and n of each of the plurality of impedance adjustment units Z11-Zmn is 3, and Z11-Z33 of a 3 × 3 matrix is changed to Z11,..., Z14, Z21,. , Z31,..., Z34, Z41,.

  Also in this case, the output-side selector 42 has a symmetric configuration with the input-side selector 41 and will not be described. The input side selector 41 includes a plurality of sets of switches arranged in a hierarchy (two layers) in a tree form of a ternary tree. A plurality of sets of P-channel transistors and / or N-channel transistors connected in series functioning as switches are provided at each branch point. In the first branch path, two N-channel transistors are connected in series. In the second branch path, an N-channel transistor and a P-channel transistor are connected in series. In the third branch path, a P-channel transistor and an N-channel transistor are connected in series.

  The decoder circuit 43 outputs decoded signals of j0 and j1 constituting the variable J and k0 and k1 constituting the variable K. The decode signal j0 is at the gate of the first-stage front transistor, the decode signal j1 is at the gate of the first-stage rear transistor, the decode signal k0 is at the gate of the second-stage front transistor, and the decode signal k1 is The voltage is applied to the gates of the rear transistors in the second stage. Variable J takes a value of 1 to 3, variable K takes a value of 1 to 3, and is selected so that one of nine signal paths connected to nine impedance adjustment units Z11 to Z33 is conducted. Is done.

  Again, when the plurality of impedance adjustment units Z11-Zmn (here, m, n = 3) are arranged in an m × n matrix, the inductance values of the inductors L1 and L2 change in order in the column direction, The capacitance values of the capacitors C are set so as to change in the row direction. By changing the impedance value according to the value of JK, the corresponding impedance adjustment unit can be selected.

  For example, if j0, j1, k0, and k1 are 1, 0, 0, and 1, respectively, J is 3 and K is 2, and the impedance adjustment unit Z32 is selected.

  The selection circuit of the impedance matching circuit 40 shown in FIGS. 4 and 5 has a tree structure in which both P-channel transistors and N-channel transistors are used as switches, but the selection circuit includes only one of the P-channel transistor and the N-channel transistor. May be formed. In this case, each switch includes two transistors arranged in parallel, and supplies a positive / negative signal of each decoder signal to the gates of the two transistors, which complicates the selection circuit.

  FIG. 6 is a flowchart showing a test operation in the embodiment. Here, the case where the impedance matching circuit 40 of FIG. 4 is used will be described as an example, but the basic operation is the same when the impedance matching circuit of FIG. 5 is used.

  In step 101, 1 is set to J.

  In step 102, K is set to 1.

  In step 103, the control circuit 39 outputs a control signal for selecting ZJK to the decoder circuit, and the decoder circuit 43 decodes the control signal and outputs a decoded signal. Thereby, the impedance adjustment unit ZJK, here, Z11 is selected. In this state, EVM constellation measurement is performed.

  In step 104, the value of the EVM constellation measurement is stored in the storage circuit 38.

  In step 105, K is incremented by one.

  In step 106, it is determined whether K is n, here, 4. If not 4, the process returns to step 103, and if it is 4, the process proceeds to step 107. Therefore, steps 103 to 106 are repeated until K becomes 4. Thereby, the EVM constellation measurement from the impedance adjustment units Z11 to Z14 is performed, and the measured value is stored. In other words, the EVM constellation measurement is performed by the impedance adjustment unit in which the capacitance value of the capacitor C is constant and the inductance values of the inductors L1 and L2 are sequentially changed.

  In step 107, K is incremented by one.

In step 108, it is determined whether J is m, here, 4. If not 4, the process returns to step 103. Therefore, steps 103 to 108 are repeated until J becomes 4. Thereby, EVM constellation measurement is further performed from the impedance adjustment units Z21 to Z24, Z31 to Z34, and Z41 to 44, and the measured values are stored.
In other words, the EVM constellation measurement by the impedance adjustment unit in which the inductance values of the inductors L1 and L2 are sequentially changed is performed for all the capacitance values while the capacitance value of the capacitor C is sequentially changed.

  In step 109, the EVM constellation measurement values corresponding to the impedance adjustment units Z11 to Z44 are compared, and the best impedance adjustment unit Zab corresponding to the best measurement result is determined. Specifically, the best condition is determined when the error vector from the ideal value in FIG. 2 to the actually measured value is the smallest.

  In step 110, a control signal for selecting the best impedance adjustment unit Zab determined by the control circuit 39 is output. Accordingly, a signal path passing through the best impedance adjustment unit Zab is set in the impedance matching circuit.

  In step 111, a predetermined measurement operation is performed and the process ends.

  In the above measurement operation, instead of the EVM constellation, characteristics such as spectrum flatness and spectrum mask may be measured and evaluated. Further, the evaluation may be performed by combining a plurality of characteristics such as EVM constellation, spectrum flatness, and spectrum mask.

  FIG. 7 is a flowchart showing an operation in a modified example of determining the best EVM constellation measurement value within the narrowed range after narrowing down to a certain range in the spectrum flatness evaluation.

Steps 201 to 209 measure the spectrum flatness instead of measuring the EVM constellation, and determine the range in which the spectrum flatness is good, i.e., determine jmax, jmin, kmax, kmin. To 109.
The range in which the spectrum flatness is good can be obtained, for example, by determining the range in which the spectrum flatness evaluation value is equal to or greater than a predetermined threshold. As the predetermined threshold value, a test standard at the time of product shipment or a value stricter than that is used.

  In addition, since the impedance range in which the spectrum flatness is good is only for narrowing down, it is not necessary to measure and store the measured values for all of the plurality of impedance adjustment units, and the values of J and K are appropriate. For example, in FIG. 7, J is changed by f and K is changed by g. In the process of FIG. 7, it is desirable to make measurement under the conditions of j = 1 and j = n for J and k = 1 and k = m for K.

  Further, when the impedance range in which the spectrum flatness is good is only one impedance adjustment unit, the change range before and after the impedance adjustment unit is set as a narrowing range. Specifically, jmin = jmax−f and jmax = jmax + f are set when jmax = jmin, and kmin = kmax−g and kmax = kmax + g are set when kmax = kmin.

  In steps 210 to 218, the EVM constellation determines the best impedance adjustment unit with the best range within the range determined in step 209. This operation is performed in the same manner as in FIG. 6 except that the impedance adjustment unit to be selected and measured is within the range determined in step 209.

  In step 220, the measurement operation is performed with setting to select the best impedance adjustment unit, and the process ends.

  In FIG. 7, the range is narrowed down to the impedance range where the spectrum flatness is good, but the range may be narrowed down by the characteristic value of the spectrum mask or the like, or the range may be narrowed down by the characteristic value of both the spectrum flatness and the spectrum mask.

  In the above embodiment, as shown in FIG. 3, the impedance matching circuit 40 is provided in the test board 20, and the memory circuit 38 and the control circuit 39 are provided in the tester 30. There may be various modifications for the locations where these are provided.

  FIG. 8A shows a modification of the test environment in which the impedance matching circuit 40 is provided in the tester 30. The DUT 10 is detachably provided on the test board 20. The tester 30 is connected to a terminal of the test board 20 that is connected to the output terminal of the DUT 10. In this environment, it is important that the tester 30 be connected as close as possible to the terminals of the test board 20, in other words, with a short signal path.

  FIG. 8B shows an example in which the memory circuit 38 and the control circuit 39 are provided on the test board 20. The tester 30 outputs the measurement values (EVM constellation, spectrum flatness, spectrum mask evaluation value, pass / fail judgment result, etc.) calculated by the calculation circuit 37 to the control circuit 39. The control circuit 39 stores the measurement values in the storage circuit. 38. Other configurations are the same as those of the embodiment.

  FIG. 9A shows a test environment in the case of a modification in which the impedance matching circuit 40 is provided in the semiconductor device (DUT) 10. The DUT 10 outputs the generated high frequency signal via the impedance matching circuit 40. The DUT 10 needs to have an input terminal for inputting the selection signal of the impedance matching circuit 40. When the number of bits of the selection signal is large, the number of terminals of the DUT 10 is greatly increased, which is not preferable. Therefore, it is desirable to use a terminal that is not used during the test as an input terminal for the selection signal only during the test.

  Further, as shown in FIG. 9B, a counter 50 that counts the counter clock from the tester 30 is provided in the DUT 10. The counter 50 starts the counter operation when the / Reset signal becomes valid, stops the counter operation when the / Reset signal becomes invalid, and the output becomes a default value, for example, the initial value of the counter. The count value of the counter 50 is input to the decoder 43 as a selection signal. Further, a default state of only wiring is provided as the impedance adjustment unit, and the decoder 43 is configured to output a decode signal for selecting the default state to the selection circuit when the counter value is the initial value.

  At the time of the test, the / Reset signal is validated and the counter 50 is in a state where the counting operation can be performed. When the control circuit 39 outputs one counter clock, the count value of the counter 50 changes by 1, and the count value is input to the decoder 43 as a selection signal. The decoder 43 decodes the selection signal and selects the first impedance adjustment unit. In this state, the tester 30 performs measurement and stores the measured value. After the measurement value is stored, when the control circuit 39 outputs one counter clock, the count value of the counter 50 is changed by 1, and the next impedance adjustment unit is selected, so that the measurement and the measurement result are stored. Do. Hereinafter, this operation is repeated, and the measurement values in all the states in which the plurality of impedance adjustment units are connected are stored. Therefore, the best impedance adjustment unit is determined. If necessary, the control circuit once invalidates the / Reset signal and then enables it again, and outputs the number of counter clocks necessary for selecting the best impedance adjustment unit. As a result, the impedance matching circuit 40 is in a state in which the best impedance adjustment unit is selected, and the measurement operation is performed in this state.

  When the / Reset signal terminal is open, the shipped semiconductor device 10 is in a default state in which a high-frequency signal is output via a signal path only with wiring because the / Reset signal is invalid. Note that the user of the semiconductor device 10 can set the impedance state to a predetermined impedance state using the impedance matching circuit 40 for impedance adjustment.

  All examples and conditions described herein are set forth for the purpose of assisting understanding of the inventive concept applied to the invention and technology, and the examples and conditions specifically described are intended to limit the scope of the invention. Rather, the configuration of such examples in the specification is not indicative of the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
A high frequency signal output test method for testing a semiconductor device that outputs a high frequency signal from an output terminal with a tester,
An impedance matching circuit having a plurality of impedance adjustment units that give different impedance adjustment amounts and a selection circuit that selects any one of the impedance adjustment units according to a selection signal is connected to the output terminal,
While changing the selection of the plurality of impedance adjustment units, the high-frequency signal output from the impedance matching circuit is measured by the tester, and the optimum impedance adjustment unit is selected based on the measurement result, and the impedance matching circuit is selected. Set the optimum impedance adjustment unit to the selected state,
A high-frequency signal output test method, wherein the high-frequency signal output from the impedance matching circuit is tested by the tester. (1) (FIGS. 3 and 6)
(Appendix 2)
The semiconductor device is set on a detachable test board,
The impedance matching circuit is provided on the test board,
The high-frequency signal output test method according to claim 1, wherein the tester is connected to the test board. (2) (Figure 3)
(Appendix 3)
The high frequency signal output test method according to appendix 2, wherein the impedance matching circuit is provided in an IC chip. (3)
(Appendix 4)
The semiconductor device is set on a detachable test board,
The impedance matching circuit is provided in the tester,
The high-frequency signal output test method according to claim 1, wherein the tester is connected to the test board. (Fig. 8 (A)
(Appendix 5)
The high-frequency signal output test method according to any one of appendices 1 to 4, wherein the selection circuit includes a plurality of switches arranged in a hierarchy in a tree shape and a decoding circuit. (Figs. 4 and 5)
(Appendix 6)
The selection of the optimum impedance adjustment unit is performed by sequentially storing the measurement results obtained by measuring the high-frequency signal output by the impedance matching circuit with the tester while sequentially selecting the plurality of impedance adjustment units. 6. The high-frequency signal output test method according to any one of appendices 1 to 5, wherein an optimum one is selected from the above. (Fig. 6)
(Appendix 7)
The optimum impedance adjustment unit is selected by determining the range of the plurality of impedance adjustment units to be evaluated by evaluating the measurement result of the high-frequency signal by the tester using a sub-evaluation method. 7. The high-frequency signal output test method according to any one of appendices 1 to 6, wherein a measurement result is evaluated by a main evaluation method and an optimum one is selected. (Fig. 7)
(Appendix 8)
When testing a semiconductor device that outputs a high-frequency signal from an output terminal with a tester, the semiconductor device is a test board that is set to be detachable,
A test board comprising: an impedance matching circuit having a plurality of impedance adjustment units that give different impedance adjustment amounts; and a selection circuit that selects any one of the impedance adjustment units according to a selection signal. (Figure 3)
(Appendix 9)
A semiconductor device that outputs a high-frequency signal,
A semiconductor device comprising: an impedance matching circuit having a plurality of impedance adjustment units that give different impedance adjustment amounts to the high-frequency signal; and a selection circuit that selects any one of the impedance adjustment units according to a selection signal. (4) (FIG. 9A)
(Appendix 10)
The selection circuit includes:
A counter that counts external clock signals;
A decoder for decoding the count value of the counter;
The semiconductor device according to appendix 9, further comprising a plurality of switches arranged in a tree-like hierarchy and selected by the output of the decoder. (Fig. 9 (B))
(Appendix 11)
The counter performs a counting operation at the time of setting, and outputs a predetermined value at the time of resetting,
The impedance matching circuit switches the plurality of switches so as to give an impedance adjustment amount of a predetermined default value to the high-frequency signal based on a decoding result of the predetermined value of the decoder at the time of reset. The semiconductor device according to appendix 10.
(Appendix 12)
A high-frequency signal output test method for testing a high-frequency signal output from an output terminal of the semiconductor device according to appendix 9, using a tester,
The high-frequency signal output from the impedance matching circuit is measured by the tester while changing the selection of the plurality of impedance adjustment units according to the selection signal from the tester, and the optimum impedance adjustment based on the measurement result Select a unit, set the impedance matching circuit to the state of selecting the optimum impedance adjustment unit,
A high-frequency signal output test method, wherein the high-frequency signal output from the impedance matching circuit is tested by the tester. (5) (FIG. 9A)

10 Semiconductor device (DUT)
20 Test board 30 Tester 38 Memory circuit 39 Control circuit 40 Impedance matching circuit 41, 42 Selector 43 Decoder circuit

Claims (3)

A high frequency signal output test method for testing a semiconductor device that outputs a high frequency signal from an output terminal with a tester,
An impedance matching circuit having a plurality of impedance adjustment units that give different impedance adjustment amounts and a selection circuit that selects any one of the impedance adjustment units according to a selection signal is connected to the output terminal,
While changing the selection of the plurality of impedance adjustment units, the high frequency signal output from the impedance matching circuit is measured by the tester,
The difference between the output value of the high-frequency signal and a predetermined value is stored in a storage circuit in all cases of the selection,
Determining the impedance adjustment unit with the smallest difference, and setting the impedance matching circuit in a selected state of the determined impedance adjustment unit;
A high-frequency signal output test method, wherein the high-frequency signal output from the impedance matching circuit is tested by the tester. The semiconductor device is set on a detachable test board,
The impedance matching circuit is provided on the test board,
The high-frequency signal output test method according to claim 1, wherein the tester is connected to the test board. The high-frequency signal output test method according to claim 2, wherein the impedance matching circuit is provided in the semiconductor device .

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