JP5417699B2 - MOS type semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a MOS semiconductor device and a manufacturing method thereof, and more particularly to a MOS semiconductor device such as a MOSFET having a trench structure and a manufacturing method thereof.

In a power semiconductor element, a MOSFET element having a channel density increased by using a trench structure in order to reduce the on-resistance of the element. Such a trench MOSFET is manufactured as follows, for example.
A silicon epitaxial layer (drift layer) of the same conductivity type is grown on a low conductivity silicon substrate of one conductivity type. This is hereinafter referred to as a silicon substrate or a substrate. A dopant of another conductivity type is ion-implanted and diffused in the silicon epitaxial layer to form a p-well. Simultaneously with the formation of the p-well, an oxide film formed on the substrate is patterned by photolithography, and trench etching is performed using the oxide film as a mask to form a trench reaching the silicon epitaxial layer below the p-well. Thereafter, the silicon oxide film polymer residue and the mask oxide film remaining in the trench are removed by HF etching. Next, soft etching and sacrificial oxidation are performed to remove the damaged layer on the inner surface of the trench by the trench etching. After removing the sacrificial oxide film and the mask oxide film, a gate oxide film is formed. Further, in order to form a gate electrode, a conductive polysilicon layer is deposited on the substrate surface and buried in the trench, and the polysilicon layer on the substrate surface is removed by etching.
There are mainly two known methods for forming the n ⁺ source region on the silicon substrate on which the trench, the trench gate oxide film and the gate electrode are formed, in order to reduce the number of mask alignments. 2A is a schematic view of the main part of a trench MOSFET formed by the first method, FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line XY in FIG. . Further, the interlayer insulating film 12 and the source electrode 16 in FIG. 2A are removed except for a part so that the underlying structure can be seen. In the first method, as described above, the trench 10 and the trench 10 are formed on the silicon substrate in which the n-type silicon epitaxial layer 1 and the p-well 2 are formed on the n ⁺ -type silicon substrate (not shown). A gate oxide film 10-1 and a gate electrode 10-2 are formed on the inner surface. Thereafter, in order to form the n ⁺ source region 11 in the surface layer of the mesa portion between the trenches 10, As (arsenic) is ion-implanted as an impurity and heat treatment is performed to form the n ⁺ source region 11. Thereafter, an interlayer insulating film 12 is deposited on the surface, and the interlayer insulating film 12 is patterned in order to form a stripe-shaped planar pattern contact trench 15 in parallel between the stripe-shaped planar parallel patterns of the trench 10. A contact trench opening 14 is formed. Then, the contact trench 15 is formed by etching deeper than the pn junction between the n ⁺ source region 11 and the p well 2. High-concentration boron ions are implanted and activated in the p-well 2 exposed at the bottom of the contact trench 15 to form a p ⁺ contact 13. The contact trench 15 has a configuration in which the contact surface of the n ⁺ source 11 is exposed at the side wall portion and the p ⁺ contact 13 is formed at the bottom portion. As a result, the source electrode 16 embedded in the contact trench 15 is in ohmic contact with the n ⁺ source 11 and the p well in common.

In the second method, as shown in the plan view of the main part of the conventional trench MOSFET in FIG. 7, the surface layer of the mesa portion between the plane parallel patterns of the stripe-shaped trench MOS gate 10 is arranged in the longitudinal direction of the trench 10. N ⁺ source regions 11 and p ⁺ contacts 13 alternately arranged in a vertical shape are formed by ion implantation and heat treatment. Thereafter, an interlayer insulating film (not shown) is deposited and patterned to form a metal contact opening, and metal is deposited and patterned to form a source electrode. Further, as shown in the perspective view of FIG. 8, the pattern of the trench contact 20 (the trench reaching the p-well through the source region) is perpendicular to the pattern of the trench MOS gate 10. There is also known a method (Patent Document 1) for reducing the element structure by reducing the interval between parallel trench MOS gates.
JP 2001-15743 A

However, the method described in Patent Document 1 is advantageous for miniaturization of the cell pitch because it is not necessary to consider the lateral diffusion of the p ⁺ contact region (not shown) as compared with the first method. However, there is a drawback that a channel is not formed in the p ⁺ contact region.
The present invention has been made in view of the above-described points, and an object of the present invention is to provide a MOS semiconductor capable of increasing channel density per unit area and having low on-resistance with the same design rule. An apparatus and a method for manufacturing the same are provided.

According to the invention of claim 1, the one conductivity type drift layer, the other conductivity type well formed in the surface layer of the drift layer, and the one layer formed in the surface layer of the well. A plurality of first trenches having a conductive source region and a plurality of first MOS gate trenches having a depth reaching the drift layer from the surface of the source region, and having a substantially rectangular surface shape having a length longer than a width. Are arranged in a periodic matrix pattern, a gate insulating film is formed in the first trench and on the source region, and a gate electrode embedded through the gate insulating film is formed in the first trench. The gate electrode extends between the first trenches in a direction perpendicular to the width of the first trench along the direction of the trench rows arranged in parallel at a predetermined interval in the width direction of the first trench. Source territory The trench row is electrically connected in a direction perpendicular to the width of the first trench by the gate electrode drawn on the gate insulating film on the region, and is connected to the gate pad, and the trench row is electrically conductive. The gate electrode connected to the first trench is disposed with a width that is separated from a longitudinal end of the trench and is narrower than a longitudinal length of the trench, and the source of the one conductivity type is provided between the trenches in the longitudinal direction of the first trench. A contact second trench having a depth penetrating from the surface to reach the other conductivity type well, contacting the one conductivity type source region at a side wall portion of the second trench and contacting the well at the bottom portion The object of the present invention is achieved by using a MOS semiconductor device having electrodes.
According to the second aspect of the present invention, in the method of manufacturing the MOS type semiconductor device according to the first aspect, the other conductivity type well is formed on the surface layer of the one conductivity type drift layer. Forming a plurality of first trenches after forming a source region of one conductivity type on the surface layer of the well, forming a gate insulating film in the trench and on the source region , a step of silicon was formed on the gate insulating film on write Mutotomoni the source region embedded in the trench is patterned so as to connect between the first trench, after depositing an interlayer insulating film, said first trench A step of forming a contact hole in the interlayer insulating film, an etching step of forming a second trench in the contact hole, and a contact region of another conductivity type at the bottom of the second trench A step, a method of manufacturing a MOS type semiconductor device having a step of embedding a metal electrode on the second trench.

According to the invention of claim 3, the one conductivity type drift layer, the other conductivity type well formed in the surface layer of the drift layer, and the one layer formed in the surface layer of the well. A conductive type source region and a plurality of third trenches for MOS gates having a depth reaching the drift layer from the surface of the source region, the third trench being perpendicular to the stripe-shaped trench and the stripe-shaped trench A plurality of combination trenches, in which a plurality of trenches having a short transverse length are arranged at intervals longer than the width of the stripe-shaped trench, are arranged in parallel, and the source region includes the stripe-shaped trench and the length contact with the short trenches, wherein the third trench and a gate electrode that is embedded through a gate insulating film, the gate electrode, the end portion of the striped trench The fourth contact for contact having a depth reaching the well of the other conductivity type through the source region of the one conductivity type between the combination trenches arranged in parallel in the third trench. The MOS semiconductor device includes a trench and has a metal electrode in contact with the one conductivity type source region at the side wall portion of the fourth trench and in contact with the well at the bottom portion.
According to a fourth aspect of the present invention, there is provided a method for forming the MOS type semiconductor device according to the third aspect, wherein a well of another conductivity type is formed on a surface layer of a drift layer of one conductivity type. A step of forming a plurality of third trenches, a step of forming a gate insulating film in the trenches, patterning so as to embed doped polysilicon in the trenches and connect the third trenches, Forming a source region of one conductivity type in a surface layer of the other conductivity type well between third trenches, and depositing an interlayer insulating film and forming a contact hole in the interlayer insulating film between the third trenches And forming a fourth trench by etching the contact hole, forming a contact region of another conductivity type at the bottom of the fourth trench, A method of manufacturing a MOS type semiconductor device having a step of embedding a metal electrode to the four trenches.

  In short, in the present invention, the trench MOS structure forming the channel is not formed in a stripe shape, but short linear trenches are periodically arranged. A contact region is formed between the longitudinal trenches of the short linear trench, the gate electrode is wired in a direction perpendicular to the width of the short linear trench, and the gate electrode in the short linear trench is conductive. It is set as a structure to connect. In the contact region, a trench penetrating the source region is formed perpendicular to the trench MOS structure, and a source contact is formed at the side wall and a p-well contact is formed at the bottom. In the MOS type semiconductor device having such a structure, the cell pitch can be easily reduced with respect to the vertical direction of the trench of the MOS portion, and the channel density can be increased. Alternatively, the trench may be formed so as to cross the width of the short linear trench in the vertical direction.

  According to the present invention, it is possible to provide a MOS semiconductor device and a method for manufacturing the same that can increase channel density per unit area and have low on-resistance with the same design rule.

Hereinafter, a MOS type semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 shows a plan view (a) of a main part of a trench MOSFET fabricated according to Example 1 and a cross-sectional view (b) taken along the line AA in FIG. FIG. 3 is a plan view illustrating a part of the planar pattern of the trench gate after the gate oxidation of the trench MOSFET according to the first embodiment. FIG. 4 is a plan view (a) and sectional views (b) and (c) after patterning of doped polysilicon for conductively connecting a plurality of trench gates of the trench MOSFET according to the first embodiment. 4 (a) is a cross-sectional view taken along line B-B, and FIG. 4 (c) is a cross-sectional view taken along line CC of FIG. FIG. 5A is a plan view after forming the p ⁺ contact region of the trench MOSFET according to the first embodiment, and FIG. 5B is a cross-sectional view taken along the line DD of FIG. 6A and 6B are a plan view (a) of a part of different trench gates according to the second embodiment, a cross-sectional view taken along line EE of (a), and a plan view (c) of a chip. FIG. 9 is a diagram referred to for explaining that the channel density can be increased according to the trench MOSFET according to the present invention. From FIG. 1A, the polysilicon gate electrode 10-2, the interlayer insulating film 12, and the source are shown. FIG. 7 is a view excluding the electrode 16, (a) is a plan view of the main part of the trench MOSFET according to the present invention, and (b) is a plan view of the main part of the conventional trench MOSFET shown in FIG. It is.

In Example 1, boron is ion-implanted from the surface of the epitaxial silicon layer 1 into a substrate in which an epitaxial silicon layer 1 (n-type drift layer) doped with phosphorus on an n-type silicon substrate is grown to a thickness of about 10 μm. Then, p-well 2 is formed by diffusion. As (arsenic) is ion-implanted and heat-treated in the entire area corresponding to the active portion located inside the breakdown voltage structure portion of each MOSFET chip pattern on the substrate surface after the formation of the p-well 2 to form the n ⁺ source region 11. . After an oxide film is formed on the entire surface of this substrate, a rectangular pattern of oxide film openings having a width of 0.35 μm and a length of 2 μm are arranged in a parallel direction (vertical direction on the paper surface) by photolithography as shown in FIG. A plurality of patterns are formed in a pattern that repeats periodically at a pitch of 1 μm and a pitch of 4 μm in the column direction (the horizontal direction of the paper). Using this patterned oxide film as a mask, a trench 10 (first trench) having a depth of 2 μm is formed in the opening by anisotropic etching such as RIE (Reactive Ion Etching). In order to remove the damage layer on the inner surface of the trench 10 formed when the trench 10 is formed by the RIE etching, isotropic etching and sacrificial oxidation using CDE (Chemical Dry Etching) is performed (not shown). ).
Next, a CVD oxide film 10-1 serving as a gate oxide film is formed with a film thickness of 100 nm (FIG. 3). Next, a conductive polysilicon layer to be a gate electrode is deposited to 500 nm. Furthermore, as shown in FIG. 4A, the plan view of FIG. 4B, the cross-sectional view taken along the line BB of FIG. 4A, and the cross-sectional view taken along the line CC of FIG. The trench 10 is filled with the conductive polysilicon layer 10-2 via the gate oxide film 10-1, and the conductive polysilicon layer 10-2 is narrower than the length of the trench 10 in the length direction. On the other hand, in order to form a shape that crosses vertically and covers the gate, a gate electrode is formed by etching other portions. The gate oxide film 10-1 left on the substrate surface is removed.

As shown in FIG. 5, a CVD oxide film having a thickness of 200 nm and a BPSG (borophosphosilicate glass) of 400 nm are deposited and re-followed as an interlayer insulating film, and then re-followed. Stripe patterning (openings) is performed on the interlayer insulating film 12 in order to form ap ⁺ high concentration region (p ⁺ contact region) 13 for good contact. The interlayer insulating film 12 shown in FIG. 5A is removed except for a part so that the underlying pattern structure can be seen. After forming an opening (contact hole) 14 in the interlayer insulating film 12 by this patterning, a contact trench 15 (through the n ⁺ source region 11 on the surface of the Si substrate exposed in the opening 14 and reaching the lower p-well 2 ( A second trench) is formed by etching. Then, after depositing a screen oxide film (not shown), boron is ion-implanted and activated at the bottom of the contact trench 15 to form the p ⁺ contact region 13.
Thereafter, as shown in FIG. 1, an electrode material having aluminum or the like as a main metal is deposited and patterned so as to form a source electrode 16 and a gate pad metal portion (not shown) to form an electrode portion. FIG. 1 shows a plan view and a sectional view taken along line AA of the MOS gate side surface of the MOSFET formed in this way. The interlayer insulating film 12 and the source electrode 16 in FIG. 1A have been removed in order to make the pattern structure of the lower layer visible, except for a part.

The fact that the trench MOSFET of the present invention described above can have a higher channel density than the conventional trench MOSFET will be described with reference to FIG. In order to clarify the effect of the invention, FIG. 9A according to the present invention has a limit in the distance between the trenches 10 (the distance in the horizontal direction in the figure) rather than the arrangement of the trenches 10 and the contact trenches 15 shown in FIG. It is shrunk to. Moreover, the linear broken line marked in the vertical direction of FIG. 9 is a ruler for making the standard of a dimension. The actual arrangement of the trench is close to that shown in FIG. In the MOSFET according to the present invention, the pitch of the parallel trenches 10 is LA, the pitch of the contact trenches 15 is LB, the width of the trenches 10 is WA, the length of the trenches 10 is WT, and the width of the p ⁺ contact region 13 is WB. The channel density per unit area is represented by 2 (WA + WT) / (LA × LB). On the other hand, the conventional channel density per unit area is represented by 2 (LB−WB) / (LA × LB). The channel density when the trench pitch and the trench length are changed between the present invention and the conventional trench MOSFET is calculated, and the channel density of the trench MOSFET of the present invention is shown in Table 1 below, respectively. Are summarized in Table 2 below.

表１、２から、トレンチピッチとトレンチ長さを表１、２のように変えた場合でも、チャネル密度は本発明のトレンチＭＯＳＦＥＴが優れていることが分かる。

From Tables 1 and 2, it can be seen that the trench MOSFET of the present invention is superior in channel density even when the trench pitch and the trench length are changed as shown in Tables 1 and 2.

A second embodiment will be described with reference to FIG. 6A is a plan view of a part of the trench 30 on the MOS gate side surface of the MOSFET, and FIG. 6B is a cross-sectional view taken along the line E-E of FIG. Consists of FIG. Example 2 differs from the trench 10 (first trench) of Example 1 in the planar pattern shape of the trench 30 (third trench). The shape of the trench 10 in the first embodiment has a structure in which the substantially rectangular trenches 10 separated from each other are connected to each other by a conductive polysilicon gate electrode that covers the top of the trench 10. In addition to the plurality of trenches 10a separated in parallel corresponding to the trenches 10 of the first embodiment, a stripe-like trench 10b extending in a direction transversely intersecting the width of the parallel trenches 10a is newly added. This is a trench 30 formed and combined.
In this trench 30, the trenches 10a corresponding to the trenches 10 are connected to each other by the intersecting trenches 10b and the polysilicon gate electrodes 10-2 filling the trenches 10a and 10b. A planar pattern of the trench 30 is shown in FIG. In FIG. 6A, only the trench 10b extending in the direction crossing the center of the two parallel trenches 10a in the vertical direction is shown, but actually, more parallel trenches 10a are arranged in the center. Thus, the stripe-shaped trench 10b is crossed. The left and right trenches in FIG. 6 (a) are conductively connected by gate lead-out wiring 10-3 (see FIG. 6 (c)) provided at the periphery of the active part, which is the terminal part of the stripe-shaped trench 10b. Are connected to the gate pad 10-4. The surfaces of the gate lead-out line 10-3 and the gate pad 10-4 are covered with an aluminum film.

  Boron is ion-implanted and diffused from the surface of the phosphorus-doped epitaxial silicon layer on a substrate obtained by growing a phosphorus-doped epitaxial silicon layer (drift layer) on an n-type silicon substrate to a thickness of about 10 μm to form a p-well. To do. After an oxide film is formed on the entire surface of this substrate, as shown in FIG. 6, a direction in which the oxide film openings 10a having a rectangular pattern with a width of 0.35 μm and a length of 2 μm are arranged in parallel by photolithography (shown in the drawing). (Vertical direction) is formed at a pitch of 1.4 μm, and a pattern that is periodically repeated at a pitch of 4 μm is formed in the longitudinal direction (horizontal direction of the drawing) of the opening shape, and further arranged in parallel in the vertical direction in the drawing A stripe-shaped opening 10b is formed which intersects the central part of the oxide film opening 10a having the quadrangular pattern perpendicularly. Using the opened oxide film as a mask, a trench having a depth of 2 μm is formed in the opening by anisotropic etching such as RIE. In order to remove the damaged layer on the inner surface of the trench formed when the trench 30 is formed by the RIE etching, isotropic etching and sacrificial oxidation are performed using CDE (Chemical Dry Etching). The reason why the interval of 1.4 μm between the parallel trenches 10a in Example 2 is larger than the interval of 1.0 μm in Example 1 is that the unit area formed on the side wall of the trench in Examples 1 and 2 is as follows. This is because the density of the hit channels is approximately the same.

Next, a gate oxide film 10-1 is formed to a thickness of 100 nm by a CVD method, a conductive polysilicon layer as a gate electrode 10-2 is deposited to a thickness of 500 nm to fill the trench 30, and FIG. Patterning is performed so as to leave a gate lead-out wiring 10-3 in the outer peripheral portion and a polysilicon wiring (not shown) connecting the lead-out wiring 10-3 and the gate electrode 10-2 as shown in FIG. Etch back the conductive polysilicon layer. After removing the gate oxide film remaining on the substrate surface, a screen oxide film (not shown) is formed, and As (arsenic) is ion-implanted into a region without the polysilicon layer using the polysilicon layer remaining in the active portion as a mask. And heat treatment to form an n ⁺ source region 11 similar to that shown in FIG.
Next, as in FIG. 1B, a CVD oxide film of 200 nm and BPSG (borophosphosilicate glass) of 400 nm are deposited and re-followed as the interlayer insulating film 12, and then on the n ⁺ source region 11 between the trenches 30. In order to form a high concentration region (p ⁺ contact region) for good contact with the metal electrode in the interlayer insulating film 12, stripe patterning (opening) is performed on the interlayer insulating film. After forming an opening in the interlayer insulating film 12 by this patterning, etching is performed to a depth that reaches the lower p-well 2 through the n ⁺ source region 11 of the Si substrate exposed in the opening. 4th trench) is formed. Then, after depositing the screen oxide film, boron is ion-implanted and activated at the bottom of the trench 15 to form the p ⁺ contact region 13.

Thereafter, an electrode material mainly composed of aluminum or the like is deposited and patterned to form the source electrode 16, the gate lead-out wiring 10-3, and the gate pad 10-4, thereby forming an electrode portion. Even in the case of Example 2, the channel density of the same level as in Example 1 becomes high.
According to the trench MOSFETs described in the first and second embodiments described above, the channel density per unit area is 5% to 50% as compared with the conventional trench MOSFET having the stripe-shaped trench gate manufactured by the same design rule. As a result, the on-resistance can be reduced by 20%.

It is sectional drawing (b) in the AA line of the principal part top view (a) and (a) of trench MOSFET of Example 1 concerning this invention. It is sectional drawing (a) and the top view (b) of the conventional trench MOSFET. It is a top view which shows a part of plane pattern of the trench gate after gate oxidation of the trench MOSFET concerning Example 1 of this invention. The top view after the etch-back of the doped polysilicon of the trench MOSFET concerning Example 1 of this invention, and sectional drawing (b), (c), (b) is the BB line of (a). Sectional drawing and (c) are CC sectional view taken on the line of the figure. 2A is a plan view after forming a p ⁺ contact region of a trench MOSFET according to Example 1 of the present invention, and FIG. FIG. 10 is a plan view (a) of a part of a different trench gate according to Example 2 of the present invention, a cross-sectional view taken along line EE of (a), and a plan view (c) of a chip. It is a principal part top view of the conventional trench MOSFET. It is a principal part perspective view of conventional trench MOSFET (according to patent documents 1). (A) is a principal part top view of trench MOSFET concerning this invention, (b) is a principal part top view of the conventional trench MOSFET (it describes in patent document 1) shown by FIG.

Explanation of symbols

1 n-type epitaxial silicon layer, n-type drift layer 2 p-well 10, 30 trench 10-1 gate oxide film 10-2 conductive polysilicon gate electrode 10-3 gate lead-out wiring 10-4 gate pad 11 n ⁺ source region 12 Interlayer insulating film 13 p ⁺ contact region 14 contact trench opening 15 contact trench 16 source electrode.

Claims (4)

One conductivity type drift layer, another conductivity type well formed in the surface layer of the drift layer, one conductivity type source region formed in the surface layer of the well, and the drift layer from the surface of the source region A plurality of first trenches having a substantially rectangular surface shape whose length is longer than the width, and wherein the first trenches are arranged in a periodic matrix pattern, A gate insulating film is formed in the trench and on the source region , and the first trench has a gate electrode embedded through the gate insulating film , and the gate electrode has a width direction of the first trench. along the direction of the trench columns arranged in parallel at predetermined intervals in the which, drawn on said gate insulating film on the source region between the said perpendicular direction to the width of the first trench first trench While connecting the trench row in a direction perpendicular to the width of the first trench conductively by chromatography gate electrode, it is wired to the gate pad, the gate electrode for connecting the trench column conductively the longitudinal direction of the trench Between the trenches in the longitudinal direction of the first trench, penetrate the source region of one conductivity type from the surface to the well of the other conductivity type. A MOS type semiconductor device comprising: a second trench for contact reaching a depth, and having a metal electrode in contact with the one conductivity type source region at a side wall portion of the second trench and in contact with the well at a bottom portion . 2. The method of manufacturing a MOS type semiconductor device according to claim 1, wherein a step of forming another conductivity type well in the surface layer of the one conductivity type drift layer, and a source region of one conductivity type in the surface layer of the well are formed. after formation and forming a plurality of first trenches, said trench and forming a gate insulating film on the source region, doped polysilicon said on write Mutotomoni the source region embedded in the trench Forming on the gate insulating film and patterning so as to connect the first trenches; depositing an interlayer insulating film; and forming a contact hole in the interlayer insulating film between the first trenches; An etching process for forming a second trench in the contact hole, a process for forming a contact region of another conductivity type at the bottom of the second trench, and a metal electrode embedded in the second trench Method of manufacturing a MOS type semiconductor device characterized by having a step. One conductivity type drift layer, another conductivity type well formed in the surface layer of the drift layer, one conductivity type source region formed in the surface layer of the well, and the drift layer from the surface of the source region A plurality of third trenches for MOS gates, each having a depth that reaches a width of the stripe-shaped trench, and a trench whose surface is perpendicular to the stripe-shaped trench, A plurality of combination trenches arranged in parallel at a long interval, the source region is in contact with the stripe-shaped trench and the short-length trench, and gate insulation is provided in the third trench. A gate electrode embedded through the film, and the gate electrode is wired from the end of the stripe-shaped trench to the gate pad portion, and the third train A fourth trench for contact having a depth reaching the well of the other conductivity type through the source region of the one conductivity type is provided between the plurality of combination trenches arranged in parallel, and at the side wall portion of the fourth trench, A MOS type semiconductor device comprising a metal electrode in contact with the one conductivity type source region and in contact with the well at the bottom. A method for forming a MOS type semiconductor device according to claim 3, wherein a step of forming a well of another conductivity type on the surface layer of the drift layer of one conductivity type, a step of forming a plurality of third trenches, Forming a gate insulating film in the trench, patterning the buried polysilicon in the trench to connect the third trenches, and forming a surface layer of the other conductivity type well between the third trenches; Forming a source region of one conductivity type; depositing an interlayer insulating film; forming a contact hole in the interlayer insulating film between the third trenches; and etching the contact hole to form a fourth trench. Forming a contact trench, forming a contact region of another conductivity type at the bottom of the fourth trench, and embedding a metal electrode in the fourth trench. Method of manufacturing a MOS type semiconductor device according to claim and.

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