JP5415018B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a Schottky junction.

  A semiconductor device using silicon carbide as a semiconductor material has excellent characteristics such as high breakdown voltage, low loss, low leakage current, high temperature operation, and high speed operation. Conventionally, a semiconductor device having a Schottky junction is known as such a semiconductor device (see, for example, Patent Document 1). FIG. 9 is a diagram for explaining a conventional semiconductor device 901. FIG. 9A is a plan view of the semiconductor device 901, and FIG. 9B is a cross-sectional view taken along line AA in FIG. 9A.

Conventional semiconductor device 901, as shown in FIG. 9, n ^- -type silicon carbide epitaxial layer 904, n ^- is formed on a part of the surface of the -type silicon carbide epitaxial layer 904, n ^- -type silicon carbide epitaxial layer 904 A p-type impurity region 908 is formed on the surface of the n ⁻ -type silicon carbide epitaxial layer 904 so as to be in contact with the end of the barrier metal layer 906, and a barrier metal layer 906 that forms a Schottky junction at the interface with A p ⁺⁺ type impurity region 910 is formed on the surface of the p type impurity region 908. N ⁻ type silicon carbide epitaxial layer 904 is formed on n ⁺ type silicon carbide single crystal substrate 902 containing n-type impurities at a higher concentration than n ⁻ type silicon carbide epitaxial layer 904. Further, a back electrode 920 is formed on the back surface of n ⁺ type silicon carbide single crystal substrate 902.

Therefore, according to the conventional semiconductor device 901, the p-type impurity region 908 is depleted at the time of reverse bias, and the electric field at the end of the p ⁺⁺ type impurity region 910 can be relaxed to obtain a high breakdown voltage.

Japanese Patent Laying-Open No. 2003-101039 (FIG. 10)

  By the way, since such a semiconductor device is normally used for an application that requires a high breakdown voltage, in such a semiconductor device, it is required to make the reverse surge breakdown withstand higher than before. Of course, it goes without saying that even in such a case, the static characteristics of the semiconductor device must not be impaired.

  Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the reverse surge breakdown resistance compared with the conventional one without impairing the static characteristics. .

  The semiconductor device of the present invention includes a first conductivity type silicon carbide layer and a barrier metal layer formed on a part of the surface of the silicon carbide layer and forming a Schottky junction at an interface with the silicon carbide layer. A first second conductivity type impurity region is formed on the surface of the silicon carbide layer or in the vicinity of the surface so as to include all or a part of the end portion of the barrier metal layer in plan view, The second conductivity region having a higher concentration than the first second conductivity type impurity region so as to include a part of the barrier metal layer in plan view on the surface of the first second conductivity type impurity region or in the vicinity of the surface. A second second conductivity type region containing a conductivity type impurity is formed, and inside and / or outside of the second second conductivity type impurity region on the surface of the first second conductivity type impurity region, The second second is in contact with the second second conductivity type impurity region. A third second conductivity type impurity region containing a second conductivity type impurity having a lower concentration than the first impurity region and a higher concentration than the first second conductivity type impurity region is formed. To do.

By the way, in the conventional semiconductor device 901, most of the reverse surge current flows through the end of the second second-conductivity type impurity region, so that a large amount of heat is generated in the narrow region, and the temperature is likely to rise. As a result, it is not easy to increase the reverse surge breakdown resistance.
On the other hand, according to the semiconductor device of the present invention, the first second conductivity type impurity region has a first inner side and / or an outer side of the second second conductivity type impurity region as viewed in plan. The second conductive impurity containing the second conductive impurity having a lower concentration than the second second conductive impurity region and a higher concentration than the first second conductive impurity region so as to be in contact with the second second conductive impurity region. Since the third second conductivity type impurity region is formed, the reverse surge current flows over the entire second second conductivity type impurity region. For this reason, since the area where the reverse surge current flows can be made wider than before, the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

  In addition, according to the semiconductor device of the present invention, the Schottky junction portion that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device, so that the static characteristics are not impaired.

  Therefore, the semiconductor device of the present invention is a semiconductor device capable of increasing the reverse surge breakdown resistance compared to the conventional one without impairing the static characteristics.

  In the semiconductor device of the present invention, the third second-conductivity type impurity region is present both inside and outside the second second-conductivity type impurity region on the surface of the first second-conductivity type impurity region. Preferably it is formed.

  With this configuration, the reverse surge current flows more evenly over the entire second second conductivity type impurity region, so that the reverse surge breakdown resistance can be further increased.

  In the semiconductor device of the present invention, an end portion of the barrier metal layer may be located on the second second conductivity type impurity region, or may be located outside the second second conductivity type impurity region. 3 on the second second conductivity type impurity region, or on the first second conductivity type impurity region outside the second second conductivity type impurity region.

  With such a configuration, the reverse surge current surely flows into the second second conductivity type impurity region, and the effect of the present invention can be obtained with certainty.

  In the semiconductor device of the present invention, the width of the second second conductivity type impurity region is preferably wider than the width of the third second conductivity type impurity region.

  By adopting such a configuration, it is possible to further increase the reverse surge breakdown resistance by further increasing the area through which the reverse surge current flows.

  In the semiconductor device of the present invention, the silicon carbide layer is located on a surface opposite to the surface on which the barrier metal layer is formed, and contains a first conductivity type impurity having a higher concentration than the silicon carbide layer. A second silicon carbide layer of one conductivity type may be further provided, or a back electrode formed on the back surface of the second silicon carbide layer may be further provided.

  Hereinafter, a semiconductor device of the present invention will be described based on an embodiment shown in the drawings.

[Embodiment]
[Embodiment 1]
1. Configuration of Semiconductor Device 1 According to First Embodiment FIG. 1 is a diagram for explaining the semiconductor device 1 according to the first embodiment. FIG. 1A is a plan view of the semiconductor device 1, and FIG. 1B is a cross-sectional view taken along the line AA in FIG.

As shown in FIG. 1, semiconductor device 1 according to Embodiment 1 includes silicon carbide semiconductor substrate 100 having n ⁻ -type silicon carbide epitaxial layer (silicon carbide layer) 104, as in the case of conventional semiconductor device 901, n ^- it is formed on a part of the surface of the -type silicon carbide epitaxial layer 104, n ^- and a barrier metal layer 106 to form an interface Schottky junction between the -type silicon carbide epitaxial layer 104, n ^- -type silicon carbide epitaxial A semiconductor device (Schottky barrier diode) in which a p-type impurity region (first second conductivity type impurity region) 108 is formed on the surface of the layer 104 so as to include the end portion of the barrier metal layer 106 in plan view. It is.

N ⁻ type silicon carbide epitaxial layer 104 is formed on n ⁺ type silicon carbide single crystal substrate (second silicon carbide layer) 102 containing n-type impurities at a higher concentration than n ⁻ type silicon carbide epitaxial layer 104. Yes. Further, on the surface of the p-type impurity region 108, a p-type impurity (second conductivity type impurity) having a concentration higher than that of the p-type impurity region 108 is included so as to include a part of the barrier metal layer 108 in plan view. A p ⁺⁺ type impurity region (second second conductivity type impurity region) 110 to be contained is formed. Further, p-type on the inner and outer ^{p ++} -type impurity regions 110 in the surface of the impurity region ^108, so as to be in contact with the ^{p ++} -type impurity regions ^{110, p ++} type low concentration and p-type impurity region 108 than the the impurity region 110 A p ⁺ -type impurity region (third second conductivity type impurity region) 112 containing a higher concentration of p-type impurities is formed. A back electrode 120 is formed on the back surface of n ⁺ -type silicon carbide single crystal substrate 102.

As the n ⁺ -type silicon carbide single crystal substrate 102, a substrate having an n-type impurity concentration of, for example, about 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and a thickness of, for example, about 30 μm to 400 μm can be used. . Further, as the crystal polymorph of the n ⁺ -type silicon carbide single crystal substrate 102, for example, 4H can be used.

As n ⁻ type silicon carbide epitaxial layer 104, an n type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of about ³ μm to 20 μm can be used, for example.

As barrier metal layer 106, a barrier metal layer made of a metal (eg, titanium) that forms a Schottky junction with n ⁻ type silicon carbide epitaxial layer 104 can be used. The barrier metal layer 106 may be used as an anode electrode as it is, or a metal film (for example, a laminated film or a nickel film in which titanium and aluminum are laminated) that can be ohmic-connected to the barrier metal layer 106 may be used as an anode electrode. Good.

  As the back electrode 120, for example, an electrode made of a laminated film in which titanium, nickel, and silver are laminated can be used. The back electrode 120 serves as a cathode electrode.

The p-type impurity region 108 has a depth of about 0.2 μm to 1.0 μm, for example, and a p-type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example. P type impurity region 108 is formed in a ring shape on the surface of n ⁻ type silicon carbide epitaxial layer 104 (see FIG. 1A).

The p ⁺⁺ type impurity region 110 has a depth of, for example, about 0.1 μm to 0.5 μm, and a p type impurity concentration of, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The width of the p ⁺⁺ type impurity region 110 is about 8 μm, for example.

The p ⁺ type impurity region 112 has a depth of, for example, about 0.1 μm to 0.5 μm, and a p type impurity concentration of, for example, about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The width of the p ⁺ -type impurity region 112 is about 1 μm, for example, inside and outside the p ⁺ -type impurity region 110.

2. Method for Manufacturing Semiconductor Device 1 According to Embodiment 1 FIGS. 2 and 3 are views for explaining a method for manufacturing the semiconductor device 1 according to Embodiment 1. FIG. 2 (a) to 2 (c) and FIGS. 3 (a) to 3 (d) are process diagrams.

  The semiconductor device 1 according to the first embodiment can be manufactured by performing the following steps (S1) to (S6) as shown in FIGS.

(S1) the semiconductor substrate preparation step n ⁺ -type silicon carbide single-crystal substrate 102 (thickness: 400 [mu] m, the impurity ^{concentration: 1 × 10 19 cm -3)} n on the upper surface of the ^- type silicon carbide epitaxial layer 104 (thickness: 10 [mu] m, A silicon carbide semiconductor substrate 100 having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ ) is prepared (see FIG. 2A).

(S2) First p-type impurity introduction step First, the surface of silicon carbide semiconductor substrate 100 is cleaned. Thereafter, a mask M1 having an opening in a portion corresponding to p type impurity region 108 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, a relatively small amount of boron ions as a p-type impurity is implanted into a predetermined portion 107 of the n ⁻ -type silicon carbide epitaxial layer 104 through the mask M1 (see FIG. 2B). In the first p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M1.

(S3) Second p-type impurity introduction step First, the mask M1 is removed. Thereafter, a mask M 2 having an opening in a portion corresponding to p ⁺ type impurity region 112 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, boron ions as a p-type impurity are introduced into the predetermined portion 111 of the n ⁻ -type silicon carbide epitaxial layer 104 via the mask M2 at a lower energy amount than in the first p-type impurity introduction step and the first p-type. A larger amount is implanted than in the impurity introduction step (see FIG. 2C). In the second p-type impurity introduction step, boron ions may be implanted under conditions where a thin silicon oxide film or the like exists in the opening of the mask M2.

(S4) Third p-type impurity introduction step First, the mask M2 is removed. Thereafter, a mask M3 having an opening in a portion corresponding to p ⁺⁺ type impurity region 110 is formed on the surface of silicon carbide semiconductor substrate 100. Thereafter, boron ions as a p-type impurity are injected into the predetermined portion 109 of the n ⁻ -type silicon carbide epitaxial layer 104 via the mask M3 with a lower energy amount than in the first p-type impurity introduction step and the second p-type. A larger amount is implanted than in the impurity introduction step (see FIG. 3A). In the third p-type impurity introduction step, boron ions may be implanted under the condition that a thin silicon oxide film or the like is present in the opening of the mask M3.

(S5) Impurity activation step First, the mask M3 is removed. Thereafter, after forming a protective resist layer (not shown) on the front and back surfaces of the silicon carbide semiconductor substrate 100, the protective resist layer is carbonized to form graphite masks M4 and M5 (see FIG. 3B). ). Thereafter, p-type impurities are activated by heating silicon carbide semiconductor substrate 100 to a temperature of 1600 ° C. or higher, and p-type impurity regions 108 (depth: 0.5 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁷ cm ⁻³ ), p ⁺ -type impurity region 112 (depth: 0.2 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁸ cm ⁻³ ) and p ^{+ +} -type impurity region 110 (depth: ^0.10 cm). 2 μm, surface p-type impurity concentration: 1.0 × 10 ¹⁹ cm ⁻³ ) (see FIG. 3B).

(S6) Barrier metal layer forming step First, the graphite masks M4 and M5 are removed. Thereafter, a barrier metal layer 106 made of titanium is formed on a part of the surface of silicon carbide semiconductor substrate 100 (see FIG. 3C).

(S7) Back Electrode Formation Step A back electrode 120 made of a laminated film in which titanium, nickel, and silver are laminated on the back surface of the silicon carbide semiconductor substrate 100 is formed (see FIG. 3D).

  By performing the above steps, the semiconductor device 1 according to the first embodiment can be manufactured.

3. Effect of Semiconductor Device 1 According to First Embodiment FIG. 4 is a diagram for explaining the effect of the semiconductor device 1 according to the first embodiment. FIG. 4A is a diagram schematically showing a current path of a reverse surge current in the semiconductor device 1 according to the first embodiment, and FIG. 4B is a semiconductor device 901 according to the comparative example 1 (conventional semiconductor device). It is a figure which shows typically the electric current path | route of a reverse direction surge current of 901.).

According to the semiconductor device 1 according to the first embodiment, the inner and outer ^{p ++} -type impurity regions 110 in the surface of the p-type impurity region ^108, so as to be in contact with the ^{p ++} -type impurity regions ^{110, p ++} -type impurity regions 110 since the p ⁺ -type impurity regions 112 containing a high concentration p-type impurity than the low-concentration and p-type impurity regions 108 are formed than, as shown in FIG. 4, the reverse surge current, p ⁺⁺ type It flows over the entire impurity region 110. For this reason, since the area where the reverse surge current flows can be made wider than before, the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

  In addition, according to the semiconductor device 1 according to the first embodiment, the portion of the Schottky junction that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device 901, so that the static characteristics are not impaired.

  Therefore, the semiconductor device 1 according to the first embodiment is a semiconductor device that can increase the reverse surge breakdown resistance compared to the conventional one without impairing the static characteristics.

In the semiconductor device 1 according to the first embodiment, the p ⁺ -type impurity region 112 is formed on both the inner side and the outer side of the p ⁺ -type impurity region 110 on the surface of the p-type impurity region 108, and thus in the reverse direction. The surge current flows more evenly throughout the p ⁺⁺ type impurity region 110. As a result, the reverse surge breakdown resistance can be further increased.

Further, in the semiconductor device 1 according to the first embodiment, since the end portion of the barrier metal layer 106 is located on the p ⁺⁺ type impurity region 110, the reverse surge current is reliably generated in the p ⁺⁺ type impurity region 110. As a result, the effects of the present invention can be obtained with certainty.

In the semiconductor device 1 according to the first embodiment, since the width of the p ⁺⁺ type impurity region 110 is wider than the width of the p ⁺ type impurity region 112, the area where the reverse surge current flows is further increased. The directional surge breakdown resistance can be further increased.

[Embodiment 2]
FIG. 5 is a partial cross-sectional view of the semiconductor device 2 according to the second embodiment.
The semiconductor device 2 according to the second embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the position of the end of the barrier metal layer 106 is the case of the semiconductor device 1 according to the first embodiment. Is different. That is, in the semiconductor device 2 according to the second embodiment, as shown in FIG. 5, the position of the end portion of the barrier metal layer 106 is located on the p ⁺ -type impurity regions 112 outside the p ⁺⁺ -type impurity regions 110 .

As described above, the semiconductor device 2 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment in the position of the end of the barrier metal layer 106, but the semiconductor device 2 according to the first embodiment. Similarly, the inner and outer ^{p ++} -type impurity regions 110 in the surface of the p-type impurity region ^108, so as to be in contact with the ^{p ++} -type impurity regions ^110, a low concentration and the p-type impurity region than ^{p ++} -type impurity regions 110 Since the p ⁺ -type impurity region 112 containing the p-type impurity having a higher concentration than 108 is formed, the reverse surge current flows through the entire p ^{+ +} -type impurity region 110. For this reason, since the area where the reverse surge current flows can be made wider than before, the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

  In addition, according to the semiconductor device 2 according to the second embodiment, the portion of the Schottky junction that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device 901, and thus the static characteristics are not impaired.

  Therefore, the semiconductor device 2 according to the second embodiment is a semiconductor device that can increase the reverse surge breakdown resistance compared to the conventional one without impairing the static characteristics.

  The semiconductor device 2 according to the second embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except for the position of the end of the barrier metal layer 106, and thus the semiconductor device according to the first embodiment. 1 has the corresponding effect.

[Embodiment 3]
FIG. 6 is a partial cross-sectional view of the semiconductor device 3 according to the third embodiment.
The semiconductor device 3 according to the third embodiment basically has the same configuration as that of the semiconductor device 1 according to the first embodiment, but the end portion of the barrier metal layer 106 is located in the semiconductor device 1 according to the first embodiment. Is different. In other words, in the semiconductor device 3 according to the third embodiment, as shown in FIG. 6, the end portion of the barrier metal layer 106 is located on the p-type impurity region 108 outside the p ^++- type impurity region 110.

As described above, the semiconductor device 3 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in the position of the end of the barrier metal layer 106, but is different from the case of the semiconductor device 1 according to the first embodiment. Similarly, the inner and outer ^{p ++} -type impurity regions 110 in the surface of the p-type impurity region ^108, so as to be in contact with the ^{p ++} -type impurity regions ^110, a low concentration and the p-type impurity region than ^{p ++} -type impurity regions 110 Since the p ⁺ -type impurity region 112 containing the p-type impurity having a higher concentration than 108 is formed, the reverse surge current flows through the entire p ^{+ +} -type impurity region 110. For this reason, since the area where the reverse surge current flows can be made wider than before, the temperature is less likely to rise than before, and as a result, the reverse surge breakdown resistance can be increased.

  Further, according to the semiconductor device 3 according to the third embodiment, the Schottky junction portion that determines the static characteristics of the semiconductor device has the same structure as that of the conventional semiconductor device 901, and thus the static characteristics are not impaired.

  Therefore, the semiconductor device 3 according to the third embodiment is a semiconductor device that can increase the reverse surge breakdown withstand capability without impairing the static characteristics.

  The semiconductor device 3 according to the third embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment except for the position of the end portion of the barrier metal layer 106, and thus the semiconductor device according to the first embodiment. 1 has the corresponding effect.

  Although the semiconductor device of the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(1) In each of the embodiments described above, the depth of the p ⁺ -type impurity region 112 is the same as the depth of the p ⁺ -type impurity region 110, but the present invention is not limited to this. For example, the p ⁺ -type impurity region 112 may be deeper or shallower than the p ⁺ -type impurity region 110.

(2) In each of the above embodiments, the semiconductor device of the present invention has been described with the first conductivity type as n-type and the second conductivity type as p-type. However, the present invention is not limited to this. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

(3) In the above embodiments, the semiconductor device of the present invention as an example of a semiconductor device in which the p ⁺ -type impurity regions 112 inside and outside the p ⁺⁺ -type impurity regions 110 in the surface of the p-type impurity regions 108 are formed However, the present invention is not limited to this. FIG. 7 is a partial cross-sectional view of the semiconductor device 4 according to the first modification. FIG. 8 is a partial cross-sectional view of a semiconductor device 5 according to Modification 2. As shown in FIGS. 7 and 8, be p ⁺ -type p ⁺ -type impurity regions 114 and spaced apart from the p ⁺ -type impurity regions 112 outside of the impurity region 112 is further formed on the surface of the p-type impurity regions 108 A p-type impurity region 116 may be further formed outside the p-type impurity region 108 on the surface of the n ⁻ -type silicon carbide epitaxial layer 104 so as to be separated from the p-type impurity region 108.

(4) In each of the above embodiments, the n ⁺ type silicon carbide single crystal substrate having a crystal polymorph of 4H is used, but the present invention is not limited to this. For example, an n ⁺ type silicon carbide single crystal substrate having a crystal polymorphism of 6H or 3C can be used.

1 is a diagram for explaining a semiconductor device 1 according to a first embodiment. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. FIG. 4 is a diagram for explaining the effect of the semiconductor device 1 according to the first embodiment. FIG. 6 is a partial cross-sectional view of a semiconductor device 2 according to a second embodiment. FIG. 6 is a partial cross-sectional view of a semiconductor device 3 according to a third embodiment. 7 is a partial cross-sectional view of a semiconductor device 4 according to Modification 1. FIG. 11 is a partial cross-sectional view of a semiconductor device 5 according to Modification 2. FIG. It is a figure shown in order to demonstrate the conventional semiconductor device 901.

Explanation of symbols

1, 2, 3, 4, 5, 901 ... semiconductor device, 100 ... silicon carbide semiconductor substrate, 102, 902 ... n ⁺ type silicon carbide single crystal substrate, 104, 904 ... n ^- type silicon carbide epitaxial layer, 106, 906 ... barrier metal layer, 107, 109, 111 ... predetermined portion, 108, 116, 908 ... p-type impurity region, 110 ... p ⁺⁺ type impurity region, 112, 114 ... p ⁺ type impurity region, 120, 920 ... back electrode, M1, M2, M3 ... Mask, M4, M5 ... Graphite mask

Claims (9)

A silicon carbide layer of a first conductivity type;
A barrier metal layer formed on a part of the surface of the silicon carbide layer and forming a Schottky junction at an interface with the silicon carbide layer;
On the surface of the silicon carbide layer or in the vicinity of the surface, a first second conductivity type impurity region is formed so as to include all or a part of the end portion of the barrier metal layer in plan view,
The surface of the first second conductivity type impurity region or the vicinity thereof has a higher concentration than the first second conductivity type impurity region so as to include a part of the barrier metal layer in plan view. A second second conductivity type region containing a second conductivity type impurity is formed;
The second second conductivity type impurity region is in contact with the second second conductivity type impurity region on the inside and / or outside of the second second conductivity type impurity region on the surface of the first second conductivity type impurity region. semiconductors third second-conductive type impurity region containing a low concentration and the first high concentration than the second conductive type impurity regions a second conductivity type impurity than the second conductivity type impurity region is formed A device,
The first second-conductivity type impurity region, the second second-conductivity type impurity region, and the third second-conductivity type impurity region are formed into the first second-conductivity type impurity region by an ion implantation method. “First second conductivity type impurity introduction step for introducing second conductivity type impurity into corresponding region”, “the second conductivity type impurity is introduced into the region corresponding to the second second conductivity type impurity region by ion implantation method”. "Second Second Conductive Impurity Introduction Step" and "Third Second Conductive Impurity Introducing Second Conductive Impurity into Region Corresponding to Third Third Conductive Impurity Region by Ion Implantation Method" A semiconductor device formed by using an “introducing step” . The semiconductor device according to claim 1 ,
The impurity concentration of the first second conductivity type impurity region is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ , and the second second conductivity type impurity region is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm. ⁻³ , and the third second conductivity type impurity region is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . The semiconductor device according to claim 1 or 2,
The third second conductivity type impurity region is formed both inside and outside the second second conductivity type impurity region on the surface of the first second conductivity type impurity region. Semiconductor device. The semiconductor device according to claim 1,
An end portion of the barrier metal layer is located on the second second conductivity type impurity region. The semiconductor device according to claim 1,
An end portion of the barrier metal layer is located on a third second conductivity type impurity region outside the second second conductivity type impurity region. The semiconductor device according to claim 1,
An end portion of the barrier metal layer is located on the first second conductivity type impurity region outside the second second conductivity type impurity region. In the semiconductor device according to claim 1,
The width of the second second conductivity type impurity region is wider than the width of the third second conductivity type impurity region. In the semiconductor device according to claim 1,
A first conductivity type second silicon carbide that is located on the opposite side of the silicon carbide layer from the surface on which the barrier metal layer is formed and contains a higher concentration of the first conductivity type impurities than the silicon carbide layer. A semiconductor device further comprising a layer. The semiconductor device according to claim 8,
The semiconductor device further comprising a back electrode formed on the back surface of the second silicon carbide layer.

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