JP5402094B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device.

  Conventionally, a technique related to a power conversion device that efficiently drives a load by using a power source has been disclosed. For example, Patent Document 1 discloses a power converter that can use and distribute a plurality of power sources without using a DC / DC converter to reduce the overall volume and loss. Specifically, this power conversion device has a plurality of switch means, and generates a voltage pulse from the output voltage of each power supply in accordance with the conduction state of each switch means.

JP 2006-296040 A

  However, there is a possibility that the conversion loss increases according to the difference in the configuration of the switch means and the solid variation. Therefore, although it is necessary to reduce the conversion loss, even in this case, the power conversion device needs to generate an output voltage corresponding to the output voltage command value set according to the load request.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce conversion loss while satisfying an output voltage corresponding to an output voltage command value.

  In order to solve such a problem, the present invention provides a switch means having an output voltage corresponding to an output voltage command value corresponding to a load request based on the configuration of each switch means and the position of the common bus. The respective conduction times of the switch means are determined from the control patterns relating to the respective conduction times.

  According to the present invention, the conduction time of each switch means can be determined so as to reduce the conduction ratio of the switch means with high loss and increase the conduction ratio of the switch means with low loss. Thereby, the loss of a power converter can be reduced, seeing the output voltage according to an output voltage command value.

Explanatory drawing which shows typically the whole structure of the control system containing the power converter device concerning 1st Embodiment. Explanatory drawing which shows typically the system configuration centering on the power converter 10 concerning 1st Embodiment. The block diagram which shows the structure of the electric power control part 43 Explanatory drawing of the on-off state of each switch 1-9 of the power converter 10 by the PWM pulse generation part 45 Explanatory drawing which shows the relationship between each initial modulation rate command value mu_a * and mu_b * and each final modulation rate command value mu_ac * and mu_bc * focusing on the U phase only Illustration of current path Explanatory drawing which shows typically the system configuration centering on the power converter 10 concerning 2nd Embodiment. Explanatory drawing which shows the relationship between each initial modulation rate command value mu_a * and mu_b * and each final modulation rate command value mu_ac * and mu_bc * focusing on the U phase only Explanatory drawing which shows typically the system configuration centering on the power converter 10 concerning 3rd Embodiment. Explanatory drawing which shows typically the structure of the electric power control part 43 concerning 3rd Embodiment. Explanatory drawing showing the relationship between each final modulation factor command value mu_ac *, mu_bc * focusing on the U phase only Explanatory drawing of the on-off state of each switch 61-69 of the power converter 10 by the PWM pulse generation part 45 Illustration of current path Explanatory drawing which shows typically the whole structure of the control system containing the power converter device concerning the 4th Embodiment of this invention. Explanatory drawing which shows typically the system configuration centering on the power converter 10 concerning 4th Embodiment. Explanatory drawing showing the modulation factor command value mu_ac * according to the total loss of the upper and lower arms focusing on the U phase Explanatory drawing which shows typically the whole structure of the control system concerning 5th Embodiment The flowchart which shows the calculation process of the voltage offset command value Voffs_a concerning 5th Embodiment. Explanatory drawing which shows the output voltage command value of each phase after offset processing Explanatory drawing which shows the output voltage command value of each phase after offset processing

(First embodiment)
FIG. 1 is an explanatory diagram schematically showing an overall configuration of a control system including a power conversion device according to the first embodiment of the present invention. In the present embodiment, a control system applied to a drive motor for an electric vehicle will be described. This control system is mainly configured by a power converter 10, a motor 30, and a control unit 40. The power converter 10 as a power converter and the control unit 40 as a controller are the power converter according to the present embodiment. Is configured.

  FIG. 2 is an explanatory diagram schematically showing a system configuration centering on the power converter 10 according to the first embodiment. The power converter 10 is connected to a plurality of power sources (first and second power sources 20 and 21 in the present embodiment) connected in parallel to each other, and is controlled by the control unit 40 so that each power source 20, An output voltage pulse is generated from the 21 output voltages. And the power converter 10 produces | generates the drive voltage of the 3-phase alternating current synchronous motor 30 which is a load with the output voltage pulse produced | generated for every phase.

  Here, the first and second power sources 20 and 21 are independent DC power sources. As each power supply 20, 21, for example, a battery such as a nickel metal hydride battery or a lithium ion battery can be used. A negative electrode bus (common bus) 11 is connected to each of the negative electrodes of the first and second power supplies 20 and 21. The positive electrode of the first power supply 20 is connected to the first positive electrode bus 12a, and the positive electrode of the second power supply 21 is connected to the second positive electrode bus 12b. A smoothing capacitor 14 is provided between the negative electrode bus 11 and the first positive electrode bus 12a, and a smoothing capacitor 15 is provided between the negative electrode bus 11 and the second positive electrode bus 12b.

  In the power converter 10, bidirectional switches (switch means) 1 to 3 capable of controlling bidirectional conduction are connected between the first positive electrode bus 12a and output terminals corresponding to the three phases, respectively. ing. Similarly, bidirectional switches (switch means) 4 to 6 are respectively connected between the second positive electrode bus 12b and the output terminals corresponding to the three phases. The individual bidirectional switches 1 to 6 are connected in series with a pair of unidirectional switches 1a / 1b to 6a / 6b, each of which can control conduction in one direction, with their conduction directions being opposite to each other. It is configured. Each of the unidirectional switches 1a / 1b to 6a / 6b is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT), and each semiconductor switch has a diode (see FIG. (Not shown) are connected in series so as to be connected in parallel to the other semiconductor switch in the pair. In addition, when using a switch with a high withstand pressure | voltage as each switch 1a / 1b-6a / 6b, the diode connected in series is unnecessary.

  Unidirectional switches (switch means) 7 to 9 capable of controlling unidirectional conduction between the negative electrode bus 11 and the output terminals corresponding to the three phases, like the lower arm of a general three-phase inverter. Are connected to each other. Each of the unidirectional switches 7 to 9 is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT), and each of the semiconductor switches is connected in reverse parallel with a reflux diode.

  The on / off state of these switches 1 to 9, that is, switching between conduction and interruption (switching operation) is controlled through a switch drive signal output from the control unit 40. Each switch is turned on by the control unit 40, and turned off and turned off (cut off).

  The motor 30 includes, for example, a plurality of phase windings star-connected around a neutral point (in this embodiment, three phase windings including a U-phase winding, a V-phase winding, and a W-phase winding) Is a three-phase AC synchronous motor. The motor 30 is driven by an interaction between a magnetic field generated by supplying three-phase AC power converted in the power converter 10 to each phase winding and a magnetic field generated by a permanent magnet of the rotor. The rotor of the motor 30 is connected to the input shaft of the automatic transmission.

  Referring again to FIG. 1, the control unit 40 is a control unit that controls the power converter 10, and controls the output torque of the motor 30 that is a load via the power converter 10. As the control unit 40, a microcomputer mainly composed of CPU, ROM, RAM, and I / O interface can be used. The control unit 40 performs a calculation for controlling the power converter 10 in accordance with a control program stored in the ROM. Then, the control unit 40 outputs the control signal calculated by this calculation to the power converter 10.

  The control unit 40 has a torque control unit 41, a current control unit 42, a power control unit 43, a three-phase / dq conversion unit 44, and a PWM pulse generation unit 45 when this is functionally grasped. ing.

  The torque control unit 41 calculates the d-axis and q-axis current command values id * and iq corresponding to the torque request of the motor 30 based on the torque command T * given from the outside and the motor rotation speed ω, respectively. The torque control unit 41 holds a map that defines the relationship between the torque command value T * and the motor rotational speed ω and the d-axis and q-axis current command values id * and iq *. The torque control unit 41 calculates the d-axis and q-axis current command values id * and iq * with reference to the map.

  Based on the d-axis and q-axis current command values id * and iq * and the d-axis and q-axis current values id and iq, the current control unit 42 is configured to match the command value with the actual value. q-axis voltage command values vd * and vq * are respectively calculated. Here, the d-axis and q-axis current values id and iq are obtained by detecting the current of each phase of the motor 30 by a current sensor, and the three-phase / dq conversion unit 44 converts the current of the three phases into the rotor position of the motor 30. It is calculated by converting based on the expressed electrical phase (electrical angle) θ. Since the sum of the currents of the respective phases of the motor 30 is zero, the currents of the respective phases of the motor 30 can be specified by detecting at least the two-phase currents iu and iv. The current control unit 42 converts the d-axis and q-axis voltage command values vd * and vq * into three-phase output voltage command values vu *, vv *, and vw *. The generated output voltage command values vu *, vv *, vw *, that is, the output voltage command values vu *, vv *, vw * corresponding to the load request of the motor 30 are sent to the power control unit 43. Is output.

  FIG. 3 is a block diagram illustrating a configuration of the power control unit 43. The power control unit 43 calculates a modulation factor command value corresponding to each of the power supplies 20 and 21. This modulation factor command value is a modulation factor command for comparison with a carrier in a PWM pulse generation unit 45, which will be described later, when generating a switch drive signal for controlling the conduction state of each of the switches 1 to 9 of the power converter 10. Value. The power control unit 43 includes a voltage distribution unit 43a, a modulation factor calculation unit 43b, a voltage offset calculation unit 43c, a modulation factor offset calculation unit 43d, and an offset processing unit 43e.

  The voltage distribution unit 43a distributes the output voltage command values vu * to vw * of each phase according to the power distribution ratio rto_pa given from the outside. As a result, the first voltage command values vu_a *, vv_a *, vw_a *, which are three-phase output voltage command values related to the first power supply 20, and the three-phase output voltage command values related to the second power supply 21 are displayed. 2 voltage command values vu_b *, vv_b *, and vw_b * are calculated.

  Here, the power distribution ratio rto_pa is a parameter indicating the output ratio of the first power supply 20. When power is output only from the first power supply 20, “1” is input as the power distribution ratio rto_pa, and when power is output only from the second power supply 21, “0” is input as the power distribution ratio rto_pa. . Further, when power is evenly distributed between the first power supply 20 and the second power supply 21, “0.5” is input as the power distribution ratio rto_pa.

The voltage distribution unit 43a calculates each of the voltage command values vu_a * to vw_b * based on the three-phase output voltage command values vu * to vw * and the power distribution ratio rto_pa, as shown in the following equation.

  The calculated voltage command values vu_a * to vw_b * are output to the modulation factor calculation unit 43b.

The modulation factor calculation unit 43b normalizes the voltage command values vu_a * to vw_b * with the power supply voltages Vdc_a and Vdc_b of the power sources 20 and 21, respectively, so that the initial modulation factor command values mu_a * corresponding to the power sources 20 and 21 are obtained. Calculate ~ mw_b *. Specifically, each of the first voltage command values vu_a * to vw_a * is normalized by the output voltage (hereinafter referred to as “first power supply voltage”) Vdc_a of the first power supply 20, thereby Initial modulation rate command values mu_a *, mv_a *, mw_a * are generated. Each of the second voltage command values vu_b * to vw_b * is normalized by the output voltage (hereinafter referred to as “second power supply voltage”) Vdc_b of the second power supply 21, whereby the second initial modulation factor command value is obtained. mu_b *, mv_b *, and mw_b * are generated. Here, the relationship represented by the following equation is established between each voltage command value vu_a * to vw_b * and each initial modulation factor command value mu_a * to mw_b *.

  The calculated initial modulation rate command values mu_a * to mw_b * are output to the offset processing unit 43e.

  The voltage offset calculation unit 43c has a function of calculating an offset amount (modulation rate offset command described later) for offsetting each initial modulation rate command value mu_a * to mw_b * by a predetermined amount. In the voltage offset calculation unit 43c, an offset amount based on the output voltage command values vu_a * to vw_b * is generated as a premise for generating a modulation factor offset command. Specifically, the first voltage offset command value Voffs_a is generated as a value that defines the offset amount with respect to the first initial modulation factor command values mu_a * to mw_a *. Similarly, the second voltage offset command value Voffs_b is generated as a value that defines the offset amount for the second initial modulation factor command values mu_b * to mw_b *.

The voltage offset calculation unit 43c calculates the amplitude Vpk of the three-phase output voltage command values vu * to vw * as a premise for performing such calculation. The amplitude Vpk is calculated based on the d-axis and q-axis voltage command values vd * and vq * by performing the calculation shown in the following equation.

The amplitude Vpk can be calculated based on the output voltage command values vu * to vw * of each phase in addition to the calculation shown in Formula 3 (see Formula 4). Also, in order to increase the voltage utilization factor, when superimposing third-order harmonics on the output voltage command values vu_a * to vw_b * of each phase, or when performing a control method widely used in motor control such as dead time compensation Therefore, the amplitude Vpk may be calculated in consideration of the compensation voltage amplitude.

  In addition, the voltage offset calculation unit 43c holds loss information regarding the loss (ON loss) of each switch 1 to 9 according to the circuit configuration of the switches 1 to 9 constituting the power converter 10. In the present embodiment, the power converter 10 includes bidirectional switches 1 to 3 corresponding to the upper arm between the first positive electrode bus 12a and the output terminals of the respective phases. Bidirectional switches 4 to 6 corresponding to the upper arm are provided between the phase output terminals. These bidirectional switches 1 to 6 have large on-loss compared to the lower arm connecting the negative electrode bus 11 and the output terminals of the respective phases, that is, the unidirectional switches 7 to 9. This is because each bidirectional switch 1 to 6 includes a diode connected in series, and the on-loss includes both the on-loss of the diode and the on-loss of the switch (transistor). On the other hand, the on loss of the switches 7 to 9 includes one of the on loss of the diode and the on loss of the switch (transistor). Therefore, the loss information includes an upper arm corresponding to each of the power supplies 20 and 21 as an arm with a large on loss, that is, the bidirectional switches 1 to 3 on the first positive bus 12a side and the second positive bus 12b side. Bidirectional switches 4 to 6 are defined, and switches 7 to 9 on the side of the negative bus 11 that is a common bus are defined as lower arms, that is, arms with small on-loss. As described above, the magnitude of the loss related to the switches 1 to 9 depends on the configuration of each of the switches 1 to 9 and a common bus connected to a plurality of DC power sources having a common potential among the plurality of buses (in this embodiment, the negative bus 11 ) Will be determined according to the position.

  By referring to the loss information, the voltage offset calculation unit 43c determines that the on-loss of the bidirectional switches 1 to 6 is relatively large and generates more heat in each of the switches 1 to 9 constituting the power converter 10. Can do. That is, the voltage offset calculation unit 43c can determine that the switches with small on-loss are the switches 7 to 9 on the negative electrode bus 11 side.

The voltage offset calculation unit 43c calculates the first and second voltage offset command values Voffs_a and Voffs_b based on the amplitude Vpk of the output voltage command values vu * to vw * and the loss information (see Formula 5).

  The voltage offset command values Voffs_a and Voffs_b obtained by this calculation are the lower limit (minimum peak) of the voltage command values vu_a * to vw_a * and vu_b * to vw_b * corresponding to the power sources 20 and 21, respectively. It corresponds to the amount of offset to correspond respectively. In other words, the offset amount corresponding to each of the power supplies 20 and 21 is the minimum peak of the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * of each phase related to the power supplies 20 and 21 and the potential of the negative electrode bus 11. Corresponds to the difference. The calculated voltage offset command values Voffs_a and Voffs_b are output to the modulation factor offset calculation unit 43d.

The modulation factor offset calculation unit 43d normalizes the voltage offset command values Voffs_a and Voffs_b with the power supply voltages Vdc_a and Vdc_b of the power supplies 20 and 21, respectively. Specifically, the first voltage offset command value Voffs_a is normalized by the first power supply voltage Vdc_a, so that the modulation factor offset command value corresponding to the first power source 20 (hereinafter referred to as “first modulation factor offset”). Moffs_a ”(referred to as“ command value ”) is generated. Further, the second voltage offset command value Voffs_b is standardized by the second power supply voltage Vdc_b, whereby a modulation factor offset command value corresponding to the second power source 21 (hereinafter referred to as “second modulation factor offset command value”). Moffs_b is generated. Here, the relationship shown in the following equation is established between the voltage offset command values Voffs_a and Voffs_b and the modulation factor offset command values moffs_a and moffs_b.

  The calculated modulation factor offset command values moffs_a and moffs_b are output to the offset processing unit 43e.

  The offset processing unit 43e performs offset processing on each initial modulation rate command value mu_a * to mw_b * using each modulation rate offset command value moffs_a and moffs_b, and thereby obtains the final modulation rate command value mu_ac * to mw_bc *. Calculate. Specifically, by adding the first modulation factor command value Voffs_a to each of the first initial modulation factor command values mu_a * to mw_a *, the final modulation factor command value mu_ac of each phase related to the first power supply 20 is obtained. *, Mv_ac *, mw_ac * are calculated. Further, by adding the second modulation factor command value Voffs_b to each of the second initial modulation factor command values mu_b * to mw_b *, the final modulation factor command values mu_bc * to mw_bc of the respective phases relating to the second power source 21. * Is calculated. The calculated final modulation factor command values mu_ac * to mw_bc * are output to the PWM pulse generator 45.

  Referring again to FIG. 1, the PWM pulse generator 45 determines each of the power converters 10 based on the final modulation rate commands mu_ac * to mw_bc * and the carriers Ca and Cb corresponding to the power sources 20 and 21. A switch drive signal for setting on / off states of the switches 1 to 9 is generated. And the PWM pulse generation part 45 controls the conduction | electrical_connection state, ie, conduction | electrical_connection period (on period), of each switch 1-9 of the power converter 10 through the produced | generated switch drive signal. As a result, output voltage pulses are generated from the output voltages of the power supplies 20 and 21. In the present embodiment, the carriers Ca and Cb are triangular waves having a lower limit “−1” and an upper limit “1”, and the carrier Ca corresponding to the first power source 20 and the carrier corresponding to the second power source 20. The phase is offset by 180 degrees from Cb.

  FIG. 4 is an explanatory diagram of the on / off states of the switches 1 to 9 of the power converter 10 by the PWM pulse generation unit 45. The PWM pulse generation unit 45 compares the final modulation factor commands mu_ac * to mw_bc * with the carriers Ca and Cb for each of the power supplies 20 and 21 to generate a switch drive signal. Hereinafter, the description will be given focusing on the U phase, but the same applies to the other phases. In FIG. 4, when the switch drive signals S1a, S1b, S4a, S4b, and S7 related to the switches 1a, 1b, 4a, 4b, and 7a are at a high level, the switches 1a, 1b, 4a, 4b, and 7a are turned on. Become.

  Here, the switch drive signals S1a, S1b, S4a, S4b, and S7 will be described.

S1a: drive signal S1b of the switch 1a conducting from the positive electrode of the first power supply 20 to the output terminal S1b: drive signal S4a of the switch 1b conducting from the output terminal to the first power supply 20 S2a of the second power supply 21 Drive signal S4b of the switch 4a conducting from the positive electrode to the output terminal: Drive signal S7 of the switch 4b conducting from the output terminal to the second power source 21: Drive signal of the switch 7 conducting from the output terminal to the negative electrode The PWM pulse generator 45 is driven so that the switch 1a is turned on when the U-phase final modulation factor command value mu_ac * of the first power supply 20 is larger than the carrier Ca of the first power supply 20 (Ca <mu_ac *). The signal S1a is output. The PWM pulse generator 45 turns off the switch 1a when the U-phase final modulation factor command value mu_ac * of the first power supply 20 is smaller than the carrier Ca of the first power supply 20 (Ca> mu_ac *). The drive signal S1a is output to On the other hand, the PWM pulse generator 45 inverts and outputs the drive signal S1a of the switch 1a as the drive signal S4b of the switch 4b.

  On the other hand, when the U-phase final modulation factor command value mu_bc * of the second power source 21 is larger than the carrier Cb of the second power source 21 (Cb <mu_bc *), the PWM pulse generator 45 sets the switch 4a. The drive signal S4a is output so as to be turned on. The PWM pulse generator 45 turns off the switch 4a when the U-phase final modulation factor command value mu_bc * of the second power supply 21 is smaller than the carrier Cb of the second power supply 21 (Cb> mu_bc *). Drive signal S4a. On the other hand, the PWM pulse generator 45 inverts and outputs the drive signal S4a of the switch 4a as the drive signal S1b of the switch 1b.

  The PWM pulse generator 45 outputs a logical product of the drive signal S1b of the switch 1b and the drive signal S4b of the switch 4b as the drive signal S7 of the switch 7.

  In a case where there is a potential difference between the first power supply 20 and the second power supply 21, a short circuit may occur when the switch 1a and the switch 4b are turned on at the same time. A short-circuit prevention period (dead time) is added so that the switches 1a and 4b are not simultaneously turned on. Similarly, a dead time is added between the switch 4a and the switch 1b.

  As described above, in the present embodiment, the control unit 40 includes the common bus (negative electrode bus 11) to which the configurations of the switches 1 to 9 and a plurality of DC power sources having a common potential among the plurality of buses 11, 12a, and 12b are connected. The conduction time of each switch 1-9 is determined from the control pattern regarding the conduction time of each switch 1-9 which comprises the output voltage according to output voltage command value vu * -vw * based on this position.

  According to such a configuration, the on-loss of each of the switches 1 to 9 can be estimated. For this reason, from the control pattern regarding the conduction time of each switch 1-9 which comprises the output voltage according to output voltage command value vu * -vw *, the conduction | electrical_connection ratio of the switches 1-9 with high ON loss is reduced, On the other hand, the conduction time of each switch 1-9 can be determined so as to increase the conduction ratio of the switches 1-9 with low on-loss. Thereby, the ON loss of the power converter 10 can be reduced while observing the output voltage corresponding to the output voltage command values vu * to vw *.

  In the present embodiment, one of the unidirectional switch and the bidirectional switch is selected for each of the switches 1 to 9 according to the position of the common bus. Then, the control unit 40 determines the conduction time of each of the switches 1 to 9 so that the conduction time of the bidirectional switch is short and the conduction time of the unidirectional switch is long. The bidirectional switch has higher ON loss than the unidirectional switch. For this reason, the conduction ratio of the bidirectional switch with high loss is suppressed, and the conduction ratio of the unidirectional switch with low loss is increased. Thereby, the ON loss of the power converter 10 can be reduced.

  FIG. 5 is an explanatory diagram showing the relationship between each initial modulation rate command value mu_a *, mu_b * and each final modulation rate command value mu_ac *, mu_bc *, focusing on only the U phase. In the present embodiment, the negative electrode bus 11 is a common bus, and the switches 1 to 3 and 4 to 6 corresponding to the upper arms of the power supplies 20 and 21 are constituted by bidirectional switches. In this case, the offset process is performed based on the determination that the on-loss of the bidirectional switches 1 to 3 and 4 to 6 corresponding to the upper arms is larger than the on-loss of the unidirectional switches 7 to 9. That is, the first final modulation factor command value mu_ac * is offset downward (lower limit direction of the carrier) compared to the first initial modulation factor command value mu_a *. In particular, in the present embodiment, the lower limit (minimum peak) of the first final modulation factor command values mu_ac * to mw_ac * is offset so as to coincide with the lower limit of the carrier. When the first output voltage command values vu_a * to vw_a * are taken as a base, the output voltage command values vu_a * to vw_a * of each phase are converted into the first output voltage command values vu_a * to The difference between the minimum peak of vw_a * and the potential of the negative electrode bus 11 can be reduced as an offset amount.

  Further, the second final modulation factor command values mu_bc * to mw_bc * are offset downward (in the lower limit direction of the carrier) as compared with the second initial modulation factor commands mu_b * to mw_b *. In particular, in the present embodiment, the upper limit (minimum peak) of the second final modulation factor command values mu_bc * to mw_bc * is offset so as to coincide with the lower limit of the carrier. When the second output voltage command values vu_b * to vw_b * are taken as a base, the output voltage command values vu_b * to vw_b * of each phase are converted into the second output voltage command values vu_b * to The difference between the minimum peak of vw_b * and the potential of the negative electrode bus 11 can be reduced as an offset amount.

  When the final modulation rate command values mu_ac * to mw_bc * are offset to the lower side compared to the initial modulation rate command values mu_a * to mw_b *, the upper arm off time is compared with that before the offset is set. Lengthens and lowers the on-time of the lower arm. Therefore, it is possible to increase the ratio of conduction of the lower arm having a small on loss. Further, in the power converter 10 that outputs the multiphase AC voltage, when the voltage command values of the respective phases are offset corresponding to each other, the output voltage does not change before and after the offset. This can be realized without changing the output voltage of the load by controlling the offset voltage command value. Thereby, the loss of the power converter 10 can be reduced while distributing a plurality of power supply powers and securing a desired output voltage.

  FIG. 6 is an explanatory diagram of current paths. In the case of a path through which a current flows by short-circuiting between the U phase and the V phase by the switches 1 to 9, a path through which a current flows using the bidirectional switches 1 and 2, and switches 7 and 8 which are lower arms There are two possible paths: a current flow path. According to the present embodiment, the conduction time of the switches 7 and 8 on the lower arm is increased and the conduction time of the bidirectional switches 1 and 2 is decreased. Thereby, since the conduction ratio of the switches 7 and 8 having a small on-loss is increased, the on-loss can be reduced.

  In the above-described embodiment, the difference between the minimum peak of the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * and the potential of the negative electrode bus 11 is set as an offset amount for each power supply. The effect can be obtained by offsetting in the direction.

  Further, when the circuit configuration of the power converter 10 is changed, the loss information is held according to the circuit configuration as necessary, and the switches 1 to 9 are changed by changing the loss information according to the current circuit configuration. It is preferable to appropriately define the loss in accordance with the circuit configuration.

(Second Embodiment)
Hereinafter, a control system according to the second embodiment of the present invention will be described. The control system according to the second embodiment is different from that of the first embodiment in the configuration of the power converter 10. The description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 7 is an explanatory diagram schematically showing a system configuration centering on the power converter 10 according to the second embodiment. In the power converter 10, unidirectional conduction can be controlled between the positive bus (common bus) 12 and the output terminals corresponding to the three phases, similarly to the upper arm of a general three-phase inverter. Unidirectional switches 51 to 53 are connected to each other. Each of the switches 51 to 53 is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT), and each of the semiconductor switches has a reflux diode connected in reverse parallel.

  Bidirectional switches 54 to 56 capable of controlling bidirectional conduction are respectively provided between the first negative electrode bus 11a connected to the negative electrode of the first power supply 20 and the output terminals corresponding to the three phases. It is connected. Bidirectional switches 57 to 59 are also connected between the second positive electrode bus 12 b connected to the negative electrode of the second power supply 21 and the output terminals corresponding to the three phases. The individual bidirectional switches 54 to 59 are connected in series with a pair of unidirectional switches 54a / 54b to 59a / 59b, each of which can control conduction in one direction, with their conduction directions being opposite to each other. It is configured. The individual switches 54a / 54b to 59a / 59b constituting the both switches 54 to 59 are mainly composed of semiconductor switches (for example, switching elements such as transistors such as IGBTs), and each semiconductor switch has a withstand voltage. The diodes are connected in series.

  Due to such a configuration of the power converter 10, the voltage offset calculation unit 43c of the control unit 40 generates the first and second voltage offset command values Voffs_a and Voffs_b. Here, the loss information held by the voltage offset calculation unit 43c includes lower arms corresponding to the power supplies 20 and 21, that is, bidirectional switches 54 to 56 on the first negative electrode bus 11a side, as an arm having a large on loss. In addition, bidirectional switches 57 to 59 on the second negative electrode bus 11b side are defined, and switches 51 to 53 on the positive bus 12 side, which is a common bus, are defined as upper arms, that is, small arms with low on-loss.

  By referring to the loss information, the voltage offset calculation unit 43c determines that the on-loss of the bidirectional switches 54 to 59 is relatively large and generates more heat in each of the switches 51 to 59 constituting the power converter 10. Can do. That is, the voltage offset calculation unit 43c can determine that the arm with small on-loss is the upper arm on the positive electrode bus side.

The voltage offset calculator 43c calculates the first and second voltage offset command values Voffs_a and Voffs_b based on the amplitude Vpk of the output voltage command values vu * to vw * and the loss information (see Formula 7).

  The voltage offset command values Voffs_a and Voffs_b obtained by this calculation are such that the upper limit (maximum peak) of the voltage command values vu_a * to vw_a * and vu_b * to vw_b * corresponding to the power sources 20 and 21 is the positive potential of the power sources 20 and 21. This is equivalent to the amount of offset.

In other words, the offset amount corresponding to each of the power supplies 20 and 21 is the maximum peak of the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * of each phase related to the power supplies 20 and 21 and the potential of the positive bus 12. Corresponds to the difference. The calculated voltage offset command values Voffs_a and Voffs_b are output to the modulation factor offset calculation unit 43d.

  FIG. 8 is an explanatory diagram showing the relationship between each initial modulation rate command value mu_a *, mu_b * and each final modulation rate command value mu_ac *, mu_bc *, focusing only on the U phase. In the present embodiment, the positive bus 12 is a common bus, and the switches 54 to 56 and 57 to 59 corresponding to the lower arms of the power supplies 20 and 21 are constituted by bidirectional switches. In this case, the offset processing is performed based on the determination that the on-loss of the bidirectional switches 54 to 56 and 57 to 59 corresponding to the lower arms is larger than the on-loss of the unidirectional switches 51 to 53. That is, the first final modulation factor command values mu_ac * to mw_ac * are offset upward (upper limit direction of the carrier) compared to the first initial modulation factor command values mu_a * to mw_a *. In particular, in the present embodiment, the upper limit (maximum peak) of the first final modulation factor command values mu_ac * to mw_ac * is offset so as to coincide with the upper limit of the carrier. When the first output voltage command values vu_a * to vw_a * are taken as a base, the output voltage command values vu_a * to vw_a * of each phase are converted into the first output voltage command values vu_a * to The difference between the maximum peak of vw_a * and the potential of the positive electrode bus 12 can be increased as an offset amount.

  Further, the second final modulation factor command values mu_bc * to mw_bc * are offset upward (in the upper limit direction of the carrier) compared to the second initial modulation factor commands mu_b * to mw_b *. In particular, in the present embodiment, the second final modulation factor command values mu_bc * to mw_bc * are offset so that the upper limit (maximum peak) matches the upper limit of the carrier. When the second output voltage command values vu_b * to vw_b * are taken as a base, the output voltage command values vu_b * to vw_b * of each phase are converted into the second output voltage command values vu_b * to The difference between the maximum peak of vw_b * and the potential of the positive electrode bus 12 can be increased as an offset amount.

  When the final modulation rate command values mu_ac * to mw_bc * are offset upward compared to the initial modulation rate command values mu_a * to mw_b *, the lower arm off time is compared to before the offset is performed. Longer, longer on time of upper arm. Therefore, it is possible to increase the ratio at which the upper arm with a small ON loss is conducted. Thereby, the loss of the power converter 10 can be reduced while distributing a plurality of power supply powers and securing a desired output voltage.

(Third embodiment)
Hereinafter, a control system according to a third embodiment of the present invention will be described. The control system according to the third embodiment is different from that of the first embodiment in the configuration of the power converter 10. The description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 9 is an explanatory diagram schematically showing a system configuration centering on the power converter 10 according to the third embodiment. The power converter 10 is connected to a plurality of power supplies (first and second power supplies 20 and 21 in the present embodiment) connected in series with each other, and is controlled by the control unit 40 so that each power supply 20, An output voltage pulse is generated from the 21 output voltages. Here, each of the first and second power sources 20 and 21 is an independent DC power source, and a positive electrode of the first power source 20 positioned at the upper level and a negative electrode of the second power source 21 positioned at the lower level are provided. It is connected in series by being connected.

  In the power converter 10, bidirectional conduction is controlled between the common bus 13 connected to the positive electrode of the first power supply 20 and the negative electrode of the second power supply 21 and the output terminals corresponding to the three phases. Possible bidirectional switches 61 to 63 are respectively connected. The individual bidirectional switches 61 to 63 are connected in series with a pair of unidirectional switches 61a / 61b to 63a / 63b, each of which can control conduction in one direction, with their conduction directions being opposite to each other. It is configured. Each of the switches 61a / 61b to 63a / 63b is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT), and each semiconductor switch has a diode (not shown) to have a withstand voltage. ) Are connected in series so as to be connected in parallel to the other semiconductor switch in the pair.

  One-way conduction can be controlled between the positive bus 12 connected to the positive electrode of the second power supply 21 and the output terminals corresponding to the three phases, like the upper arm of a general three-phase inverter. Unidirectional switches 64 to 66 are connected to each other. Further, between the negative electrode bus 11 connected to the negative electrode of the first power supply 20 and the output terminals corresponding to the three phases, the unidirectional switches 67 to 69 are connected to each other. Each of the unidirectional switches 64 to 69 is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT), and each of the semiconductor switches has a reflux diode connected in reverse parallel.

  Here, in the power converter 10 of the present embodiment, the potential of the positive bus 12 is not reversed, and the potential of the positive bus 12 is larger than the potential of the common bus 13. For this reason, it is not a bidirectional switch between the positive electrode bus line 12 and the output terminal of each phase, but it can be set as the same structure as the upper arm of a normal inverter by the unidirectional switches 64-66.

  FIG. 10 is an explanatory diagram schematically showing the configuration of the power control unit 43 according to the third embodiment. Based on the power distribution ratio rto_pa, the power control unit 43 calculates the modulation rate command values (final modulation rate command values) mu_ac * to mw_bc corresponding to the power supplies 20 and 21 from the output voltage command values vu * to vw * of each phase. Calculate each *. The power controller 43 includes an offset processor 43f, a voltage offset calculator 43g, and a modulation factor calculator 43h.

  The offset processing unit 43f performs an offset process on the output voltage command values vu * to vw * using the voltage offset command values Voffs_a and Voffs_a calculated by a voltage offset calculation unit 43g described later based on the power distribution ratio rto_pa. . As a result, the voltage command values vu_a * to vw_a * and vu_b * to vw_a * of the respective phases related to the power supplies 20 and 21 are calculated. The calculated voltage command values vu_a * to vw_b * are output to the modulation factor calculation unit 43h.

  The modulation factor calculation unit 43h normalizes the voltage command values vu_a * to vw_b * with the power supply voltages Vdc_a and Vdc_b of the power sources 20 and 21, thereby allowing the modulation factor command values mu_ac * to correspond to the power sources 20 and 21, respectively. Calculate mw_cb *. Specifically, the first voltage command values vu_a * to vw_a * are normalized by the first power supply voltage Vdc_a, thereby generating the first modulation factor command values mu_ac *, mv_ac *, and mw_ac *. The By normalizing each of the second voltage command values vu_b * to vw_b * with the second power supply voltage Vdc_b, second initial modulation factor command values mu_bc *, mv_bc *, and mw_bc * are generated.

  Hereinafter, details of processing by the offset processing unit 43f and the voltage offset calculation unit 43g according to the present embodiment will be described. Here, in the loss information held by the voltage offset calculation unit 43g, bidirectional switches 61 to 63 connected to the common bus 13 are defined as arms having a large on loss, and the positive bus 12 side is defined as an arm having a small on loss. Switches 64 to 66 and switches 67 to 69 on the negative electrode bus 11 side are defined.

  First, the voltage offset calculation unit 43g calculates the amplitude Vpk of the three-phase output voltage command values vu * to vw *. The method of calculating the amplitude Vpk is the same as the method shown in the first embodiment. Next, based on the power distribution ratio rto_pa, the voltage offset calculation unit 43g determines whether power is supplied from only one power source 20, 21 or whether power is supplied from both power sources 20, 21. Based on the determination result, the voltage offset calculation unit 43g has a first voltage offset command value Voffs_a which is an offset command value corresponding to the first power supply 20 and an offset command value corresponding to the second power supply 21. One or both of the two voltage offset command values Voffs_b are generated.

(Case where power is supplied only from the first power supply 20 (rto_pa = 1))
In order to reduce the conduction frequency of the bidirectional switches 61 to 63 corresponding to the upper arm in this case, the voltage offset calculation unit 43g and the negative potential of the first power source 21 and the amplitude Vpk of the output voltage command values vu * to vw *. Based on the above, the second voltage offset command value Voffs_b is calculated so as to be offset in the positive direction (downward) (see Formula 8). In the case where power is supplied only from the first power source 20, the second voltage offset command value Voffs_b is not calculated.

The offset processing unit 43f adds the first voltage offset command value Voffs_a to each of the output voltage command values vu * to vw *, so that the voltage command values vu_a *, vv_a *, vw_a * is calculated (see Equation 9). In this case, the voltage command values vu_b *, vv_b *, and vw_b * for each phase related to the second power supply 21 are not calculated.

  FIG. 11A shows the concept of offset processing in this case. In this case, the offset processing is performed by the first voltage offset command value Voffs_a so that the lower limit (minimum peak) of the output voltage command values vu * to vw * corresponds to the negative potential of the first power supply 20. . In other words, the offset amount (first voltage offset command value Voffs_a) corresponding to the first power supply 20 is the difference between the minimum peak of the output voltage command values vu * to vw * of each phase and the potential of the negative electrode bus 11. Corresponds to the difference. In this case, as shown in the figure, the first modulation factor command values mu_ac * to mw_ac * output from the modulation factor calculator 43h are offset so that the lower limit (minimum peak) matches the lower limit of the carrier. ing. In the figure, only the U phase is illustrated, but the same applies to the other phases (hereinafter the same in FIG. 11).

(Case where power is supplied only from the second power source 21 (rto_pa = 0))
In order to reduce the conduction frequency of the bidirectional switches 61 to 63 corresponding to the lower arm in this case, the voltage offset calculation unit 43g and the positive potential of the second power supply 21 and the amplitude Vpk of the output voltage command values vu * to vw *. Based on the above, the second voltage offset command value Voffs_b is calculated so as to be offset in the negative direction (upward) (see Expression 10). In the case where power is supplied only from the second power supply 21, the first voltage offset command value Voffs_a is not calculated.

The offset processing unit 43f adds the second voltage offset command value Voffs_b to each of the output voltage command values vu * to vw *, so that the voltage command values vu_b *, vv_b *, vv_b *, vw_b * is calculated (see Equation 11). In this case, the voltage command values vu_a *, vv_a *, vw_a * for each phase relating to the first power supply 20 are not calculated.

  FIG. 11B shows the concept of offset processing in this case. In this case, the offset process is performed by the second voltage offset command value Voffs_b so that the upper limit of the second voltage command values vu_b * to vw_b * corresponds to the positive potential of the second power supply 21. In other words, the offset amount (second voltage offset command value Voffs_b) corresponding to the second power supply 20 is the difference between the maximum peak of the output voltage command values vu * to vw * of each phase and the potential of the positive bus 12. Corresponds to the difference. In this case, as shown in the figure, the upper limit (upper peak (maximum value)) of the second modulation factor command values mu_bc * to mw_bc * output from the modulation factor calculator 43h matches the upper limit of the carrier. So that it is offset.

(Case where power is supplied from each power source 20, 21 (0 <rto_pa <1))
The voltage offset calculation unit 43g calculates the first and second voltage offset command values Voffs_a and Voffs_b by the calculation shown in the following equation in order to reduce the conduction frequency of the bidirectional switches 61 to 63.

The offset processing unit 43f adds the first voltage offset command value Voffs_a to each of the output voltage command values vu * to vw *, so that the voltage command values vu_a *, vv_a *, vw_a * is calculated. Further, the offset processing unit 43f adds the second voltage offset command value Voffs_b to each of the output voltage command values vu * to vw *, thereby allowing the voltage command values vu_b * and vv_b of each phase related to the second power supply 20 to be added. * And vw_b * are calculated (see Equation 13).

  FIG. 11C shows the concept of offset processing in this case. As shown in the figure, the first modulation rate commands mu_ac * to mw_ac * output from the modulation rate calculation unit 43h are offset upward, and the second modulation rate commands mu_bc * to mw_bc * are offset downward. The In this case, the first modulation rate command mu_ac * and the second modulation rate command mu_bc * have a relationship in which values that are the upper and lower limits of the carrier appear alternately. When the first modulation rate command mu_ac * and the second modulation rate command mu_bc * exceed the upper and lower limits of the carrier, the values are limited with the upper and lower limits of the carrier as the limits.

  In the present embodiment, the PWM pulse generation unit 45 sets the on / off state of each switch of the power converter 10 based on each final modulation rate command mu_ac * to mw_bc * and a single carrier C. Generate a signal. Then, the PWM pulse generation unit 45 controls the on / off states of the switches 61 to 69 of the power converter 10 through the generated switch drive signal. As a result, output voltage pulses are generated from the output voltages of the power supplies 20 and 21. In the present embodiment, the carrier C is a triangular wave whose lower limit is “−1” and whose upper limit is “1”.

  FIG. 12 is an explanatory diagram of the on / off states of the switches 61 to 69 of the power converter 10 by the PWM pulse generation unit 45. The PWM pulse generation unit 45 generates a switch drive signal as a result of comparison between each final modulation factor command mu_ac * to mw_ac and the carrier C, and controls the on / off state of each switch through the switch drive signal. Hereinafter, only the U phase will be described, but the same applies to the other phases. In FIG. 12, when the switch drive signals S61a, S67, S61b, and S64 related to the switches 61a, 67, 61b, and 64 are at a high level, the switches 61a, 67, 61b, and 64 are turned on.

  Here, the switch drive signals S61a, S67, S61b, and S64 will be described.

S61a: Drive signal of switch 61a conducting from common bus 13 to output terminal S67: Drive signal of switch 67 conducting from output terminal to negative electrode of first power supply 20 S61b: Direction of common bus 13 from output terminal The drive signal S64 of the switch 61b that conducts to the drive signal of the switch 64 that conducts in the direction from the second power supply 21 to the output terminal. The PWM pulse generation unit 45 uses the U-phase modulation factor command of the first power supply 20 rather than the carrier C. When the value mu_ac * is large, the drive signal S61a is output so that the switch 61a is turned on. Further, when the U-phase final modulation factor command value mu_ac * of the first power supply 20 is smaller than the carrier C, the PWM pulse generation unit 45 outputs the drive signal S61a so as to turn off the switch 61a. On the other hand, the PWM pulse generation unit 45 inverts and outputs the drive signal S61a of the switch 61a as the drive signal S67 of the switch 67.

  On the other hand, when the U-phase final modulation factor command value mu_bc * of the second power source 21 is larger than the carrier C, the PWM pulse generator 45 outputs the drive signal S64 so as to turn on the switch 64. In addition, when the U-phase final modulation factor command value mu_bc * of the second power supply 21 is smaller than the carrier C, the PWM pulse generation unit 45 outputs the drive signal S64 so as to turn off the switch 64. On the other hand, the PWM pulse generator 45 inverts and outputs the drive signal S64 of the switch 64 as the drive signal S61b of the switch 61b.

  Since a short circuit may occur when the switch 61a and the switch 67 are simultaneously turned on, a short-circuit prevention period (dead time) is added so that both the switches 61a and 67 are not simultaneously turned on. Yes. Similarly, a dead time is added between the switch 64 and the switch 61b.

  As described above, in the present embodiment, the control unit 40 performs the offset processing for each of the power supplies 20 and 21 based on the power distribution ratio rto_pa, based on the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * for each phase. Are offset respectively. According to such a configuration, when driven by one of the power supplies 20, 21, the time for conducting the bidirectional switches 61-63 can be reduced, and the time for conducting the unidirectional switches 64-69 can be increased. On-loss can be reduced. Even when driving with both power supplies 20 and 21, the time for conducting the bidirectional switches 61 to 63 can be reduced, the time for conducting the unidirectional switches 64 to 69 can be increased, and the ON loss can be reduced. Can be reduced. Thereby, the loss of the power converter 10 can be reduced while distributing a plurality of power supply powers and securing a desired output voltage.

  FIG. 13 is an explanatory diagram of current paths. In the case of a path through which a current flows by short-circuiting between the U phase and the V phase by the switches 61 to 69, a path through which a current flows using the bidirectional switches 61 and 62 and a switch 67 and 68 which are lower arms are used. There are two possible paths: a current flow path. According to this embodiment, the conduction time of the switches 67 and 68 of the lower arm is increased, and the conduction time of the bidirectional switches 1 and 2 is decreased. Thereby, since the conduction ratio of the switches 61 and 62 having a small on-loss is increased, the on-loss can be reduced.

  If an error occurs between the power distribution ratio rto_pa and the actual power distribution, the relationship between the errors is measured in advance, and the value converted into the power distribution ratio rto_pa corresponding to the actual power distribution is calculated. It is preferable to use it.

(Fourth embodiment)
Hereinafter, a control system according to a fourth embodiment of the present invention will be described. The control system according to the fourth embodiment is different from that of the first embodiment in the configuration of the power converter 10. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 14 is an explanatory diagram schematically showing the overall configuration of a control system including a power conversion device according to the fourth embodiment of the present invention. The control system is mainly composed of the power converter 10, the motor 30, and the control unit 40.

  FIG. 15 is an explanatory diagram schematically illustrating a system configuration centering on the power converter 10 according to the fourth embodiment. The power converter 10 is connected to a single power source 20 and is controlled by the control unit 40 to generate an output voltage pulse from the output voltage of the power source 20. And the power converter 10 produces | generates the drive voltage of the 3-phase alternating current synchronous motor 30 which is a load with the output voltage pulse produced | generated for every phase. The power source 20 is a DC power source, and for example, a battery such as a nickel metal hydride battery or a lithium ion battery can be used.

  In the power converter 10, switches 71 to 73, which are upper arms, are connected between the positive bus connected to the positive electrode of the power source 20 and the output terminals of the respective phases. Further, switches 74 to 76 as lower arms are respectively connected between the negative electrode bus connected to the negative electrode of the power supply 20 and the output terminal of each phase. Each of the switches 71 to 76 is mainly composed of a semiconductor switch (for example, a switching element such as a transistor such as an IGBT) that can control conduction in one direction, and each semiconductor switch has a reverse diode connected in reverse parallel. Has been.

  Referring again to FIG. 1, the control unit 40 is a control unit that controls the power converter 10, and controls the output torque of the motor 30 that is a load via the power converter 10. When the control unit 40 grasps this functionally, the torque control unit 41, the current control unit 42, the power control unit 47, the three-phase / dq conversion unit 44, the PWM pulse generation unit 45, and the voltage offset A calculation unit 46 is included.

  The torque control unit 41 calculates the d-axis and q-axis current command values id * and iq of the motor 30 based on the torque command T * given from the outside and the motor rotational speed ω, respectively. In the present embodiment, the relationship between the torque command T * and the motor rotational speed ω and the on loss Sloss in each of the switches 71 to 76 is maintained. The torque control unit 41 calculates the on loss Sloss of each of the switches 71 to 76 with reference to the map. This on-loss Sloss is a basic on-loss generated in each of the switches 71 to 76 when the power converter 10 is operated in accordance with the operating state of the motor 30 defined by the torque command T * and the motor rotational speed ω. Is shown. Note that the on-loss Sloss may be calculated online using an arithmetic expression, in addition to a method using a map. The calculated on-loss Sloss of each of the switches 71 to 76 is output to the voltage offset calculation unit 46.

  The voltage offset calculator 46 calculates a voltage offset command value Voff_a based on the on-loss Sloss of each of the switches 71 to 76 and the voltage offset command value Voffs_a calculated in the previous processing cycle. First, the voltage offset calculation unit 46 calculates the total loss of the upper arm and the total loss of the lower arm based on the on-loss Sloss of each of the switches 71 to 76. When calculating the total loss of each arm, the previous voltage offset command value Voffs_a is fed back to determine which arm has a higher conduction frequency and reflected in each total loss.

  Specifically, when the voltage offset command value Voffs_a has an effect of offsetting in the positive direction (downward), the lower arm is frequently conducted. Conversely, when the voltage offset command value Voffs_a has an effect of offsetting in the negative direction (upward), the upper arm is frequently conducted. In this way, in the arm having a high conduction frequency, the ON loss increases as heat is generated. Therefore, when calculating the total loss of each arm, the loss corresponding to the previous voltage offset command value Voffs_a is corrected. The correction values for the individual switches 71 to 76 can be uniquely determined according to the previous voltage offset command value Voffs_a using, for example, a map.

  The voltage offset calculation unit 46 compares the total loss of the upper arm and the total loss of the lower arm, and determines which arm has the larger total loss depending on whether the loss difference exceeds a predetermined threshold. To do. The voltage offset calculator 46 calculates the voltage offset command value Voffs_a according to the determination result. Note that the voltage offset calculation unit 46 calculates the amplitude Vpk of the output voltage command values vu * to vw *, similarly to the voltage offset unit 43c shown in the first embodiment and 43c.

(Case where the total loss of the upper arm is large)
In order to lower the conduction frequency of the upper arm in this case, the voltage offset calculation unit 46 is set in a positive direction so that the lower limit (minimum peak) of the output voltage command values vu * to vw * corresponds to the negative potential of the power supply 20 ( The voltage offset command value Voffs_a is calculated as an offset amount to the lower side (see Equation 13).

(Case where the total loss of the lower arm is large)
In order to reduce the conduction frequency of the lower arm in this case, the voltage offset calculation unit 46 has a negative direction so that the upper limit (maximum peak) of the output voltage command values vu * to vw * corresponds to the positive potential of the power supply 20 ( A voltage offset command value Voffs_a is calculated as an offset amount to the lower side (see Equation 14).

(Case where there is no difference in the total loss of the upper and lower arms)
The voltage offset calculator 46 calculates the voltage offset command value Voffs_a as “0” so that no substantial offset is performed. The voltage offset command value Voffs_a calculated in this case and each case described above is output to the power control unit 47.

  The power control unit 47 adds the voltage offset command value Voff_a to each of the voltage command values vu * to vw * of each phase output from the current control unit 42 (offset processing), thereby obtaining the final voltage command of each phase. Calculate the value. Then, the power control unit 47 normalizes each final voltage command value of each phase with the output voltage Vdc_a of the power supply 20, thereby allowing each phase modulation rate command value (final modulation rate command value) mu_ac *, mv_ac *. , Mw_ac * is calculated. The calculated modulation factor command values mu_ac * to mw_ac * are output to the PWM pulse generator 45 to generate a switch drive signal in comparison with the carrier.

  FIG. 16 is an explanatory diagram showing the modulation factor command value mu_ac * corresponding to the total loss of the upper and lower arms, focusing on the U phase. In the figure, (a) shows a case where there is no difference in the total loss of the upper and lower arms, (b) shows a case where the total loss of the upper arm is large, and (c) shows a case where the total loss of the lower arm is large. As shown in FIG. 6A, the offset process is not performed in the case where there is no difference in the total loss between the upper and lower arms. Also, as shown in FIG. 5B, in the case where the total loss of the upper arm is large, the modulation factor command values mu_ac * to mw_ac * are offset so that the lower limit (minimum peak) matches the lower limit of the carrier. ing. Also, as shown in FIG. 6C, in the case where the total loss of the lower arm is large, the modulation factor command values mu_ac * to mw_ac * are offset so that the upper limit (maximum peak) matches the upper limit of the carrier. ing.

  Thus, in the present embodiment, the control unit 40 has a function as loss determination means for determining the loss state of each of the switches 71 to 76. Then, the control unit 40 has a control pattern relating to the conduction time of the switches 71 to 76 having the output voltages corresponding to the output voltage command values vu * to vw * based on the respective loss states of the switches 71. To determine the conduction time of each of the switches 71-76.

  According to this configuration, the conduction ratio of the switches 71 to 76 having a high on-loss is determined from the control pattern regarding the conduction time of the switches 71 to 76 having the output voltage corresponding to the output voltage command values vu * to vw *. On the other hand, the conduction time of each of the switches 71 to 76 can be determined so as to increase the conduction ratio of the switches 71 to 76 with low on-loss. Thereby, the ON loss of the power converter 10 can be reduced while observing the output voltage corresponding to the output voltage command values vu * to vw *.

  Further, according to the present embodiment, the temperature rise of the switches 71 to 76 can be appropriately controlled by operating the arm where the on loss occurs. This makes it possible to lengthen the driving time at a higher output.

(Fifth embodiment)
A control system according to a fifth embodiment of the present invention will be described. The control system according to the fifth embodiment is different from that of the fourth embodiment in the calculation method of the voltage offset command value Voffs_a. The overlapping description of the configuration common to the fourth embodiment will be omitted, and the description below will focus on the differences.

  FIG. 17 is an explanatory diagram schematically showing the overall configuration of a control system according to the fifth embodiment of the present invention. The control system is mainly composed of the power converter 10, the motor 30, and the control unit 40. As in the fourth embodiment, the control unit 40 includes a torque control unit 41, a current control unit 42, a power control unit 47, a three-phase / dq conversion unit 44, a PWM pulse generation unit 45, and a voltage offset. A calculation unit 46 is included.

  As one of the features of this embodiment, the voltage offset calculation unit 46 includes temperatures T1 to T7 of the switches 71 to 76 detected by temperature sensors (not shown) provided to the switches 71 to 76, respectively. Have been entered. Note that the input of the on-loss Sloss of each of the switches 71 to 76 and the feedback of the voltage offset command value Voffs_a shown in the fourth embodiment are not performed.

  FIG. 18 is a flowchart showing a calculation process of the voltage offset command value Voffs_a according to the fifth embodiment. First, in step 1 (S1), the voltage offset calculator 46 reads the temperatures T1 to T6 of the switches 71 to 76 from each temperature sensor.

  In step 2 (S2), the voltage offset calculator 46 selects the maximum temperature Tmax among the temperatures T1 to T6. In step 3 (S3), the voltage offset calculation unit 46 determines whether or not the maximum temperature Tmax is larger than the set temperature condition Tth. This temperature condition Tth is preset in advance through experiments and simulations in order to determine whether or not the on-loss of each of the switches 71 to 76 has increased to generate heat and reach a certain temperature. ing.

  If an affirmative determination is made in step 3, that is, if the maximum temperature Tmax is equal to or higher than the temperature condition Tth, the process proceeds to step 4 (S4). On the other hand, if a negative determination is made in step 3, that is, if the maximum temperature Tmax is smaller than the temperature condition, the process proceeds to step 7 (S7).

  In step 4, the voltage offset calculation unit 46 determines whether or not the switch corresponding to the maximum temperature Tmax is an upper arm switch. If an affirmative determination is made in step 4, that is, if the switch having the maximum temperature Tmax is an upper arm switch, the process proceeds to step 5 (S5). On the other hand, if a negative determination is made in step 4, that is, if the switch of the maximum temperature Tmax is a switch of the lower arm, the process proceeds to step 6 (S6).

  In step 5, the voltage offset calculation unit 46 calculates the voltage offset command value Voffs_a as shown in Expression 13 in the fourth embodiment in order to reduce the conduction frequency of the upper arm. In step 6, the voltage offset calculation unit 46 calculates the voltage offset command value Voffs_a as shown in Expression 14 in the fourth embodiment in order to reduce the conduction frequency of the lower arm. Further, in step 7, the voltage offset calculator 46 calculates the voltage offset command value Voffs_a as “0”.

  When the voltage offset command value Voffs_a is calculated in this way, the power control unit 47 adds the voltage offset command value Voffs_a to the output voltage command values vu * to vw * of each phase (offset processing). The final voltage command value is calculated. Then, the power control unit 47 normalizes each final voltage command value of each phase with the output voltage Vdc_a of the power supply 20, thereby allowing each phase modulation rate command value (final modulation rate command value) mu_ac *, mv_ac *. , Mw_ac * is calculated. The calculated modulation factor command values mu_ac * to mw_ac * are output to the PWM pulse generator 45 to generate a switch drive signal in comparison with the carrier.

  Thus, in the present embodiment, the control unit 40 determines that the loss of the switches 71 to 76 having the high temperature is large based on the detection results of the temperatures T1 to T6 of the switches 71 to 76. In this case, the control unit 40 identifies the switch means with a large loss based on the temperature condition Tth for determining that the loss is in a large state and the temperatures T1 to T6 of the switches 71 to 76.

  According to such a configuration, it is possible to reduce the on-loss of the power converter 10 while observing the output voltage corresponding to the output voltage command values vu * to vw *. Moreover, the temperature rise of the switches 71-76 can be appropriately controlled by operating the arm in which the on loss occurs according to the temperature of each of the switches 71-76. This makes it possible to lengthen the driving time at a higher output.

(Sixth embodiment)
Hereinafter, a control system according to a sixth embodiment of the present invention will be described. The control system according to the sixth embodiment is different from that of the first embodiment in that the power control unit 43 (specifically, the voltage offset calculation unit 43c) of the control unit 40 performs the first and second operations. This is a calculation method of the voltage offset command values Voffs_a and Voffs_b. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

The voltage offset calculation unit 43c selects the minimum voltage command value as the first minimum voltage command value Vmin_a among the first voltage command values vu_a * to vw_a *. Further, the voltage offset calculation unit 43c selects the minimum voltage command value as the second minimum voltage command value Vmin_b from the second voltage command values vu_b * to vw_b *. And the voltage offset calculating part 43c calculates voltage offset command value Voffs_a, Voffs_b based on the following Formula.

  As described above, according to the present embodiment, as shown in FIG. 19, the output voltage command value that is the smallest of the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * for each phase related to the power sources 20 and 21 The output voltage command values vu_a * to vw_a * and vu_b * to vw_b * for each phase are decreased using the difference from the potential of the negative electrode bus 11 as the maximum offset amount. According to such a configuration, it is possible to shorten the time during which the bidirectional switches 1 to 6 are conducted, and to reduce the number of times of switching. Thereby, the loss of the power converter 10 can be reduced more.

Note that the method shown in the present embodiment can be applied to the control system shown in the second embodiment. Specifically, the voltage offset calculation unit 43c selects the maximum voltage command value as the first maximum voltage command value Vmax_a among the first voltage command values vu_a * to vw_a *. Further, the voltage offset calculation unit 43c selects the maximum voltage command value as the second maximum voltage command value Vmin_b among the second voltage command values vu_b * to vw_b *. And the voltage offset calculating part 43c calculates voltage offset command value Voffs_a, Voffs_b based on the following Formula.

  As described above, according to the present embodiment, as shown in FIG. 20, the maximum output voltage command value among the output voltage command values vu_a * to vw_a * and vu_b * to vw_b * of each phase related to the power sources 20 and 21 The output voltage command values vu_a * to vw_a * and vu_b * to vw_b * for each phase are increased by using the difference from the potential of the positive electrode bus 12 as the maximum offset amount. According to such a configuration, it is possible to shorten the time during which the bidirectional switches 1 to 6 are conducted, and to reduce the number of times of switching. Thereby, the loss of the power converter 10 can be reduced more.

DESCRIPTION OF SYMBOLS 10 ... Power converter 11 ... Negative electrode bus | bath 12 ... Positive electrode bus | bath 13 ... Common bus | bath 20 ... 1st power supply 21 ... 2nd power supply 30 ... Motor 40 ... Control unit 41 ... Torque control part 42 ... Current control part 43 ... Power control Unit 44 ... 3-phase / dq conversion unit 45 ... PWM pulse generation unit 46 ... Voltage offset calculation unit 47 ... Power control unit

Claims (8)

A power converter that generates a drive voltage of a load by outputting an output voltage pulse generated and synthesized from a plurality of DC power sources,
A common bus connected in common to a first electrode of said plurality of direct current power source, and a plurality of busbars which are individually connected to the second electrode of said plurality of direct current power supply, the individual output terminals connected to said load First switch means for connecting between a plurality of connected bus lines, and second switch means for connecting between an output terminal connected to the load and the common bus line and having different on-loss from the first switch means a power conversion means for bets equipped with, generates an output voltage pulse in response to each of the conductive state of the first and second switch means from said plurality of direct current power source,
Control means for controlling respective conduction times of the first and second switch means based on an output voltage command value corresponding to the load request;
Said control means, based on the ON loss of the first and second switch means, the control pattern for each of the conduction time of the first and second switch means and an output voltage corresponding to the output voltage command value A power converter according to claim 1 , wherein a conduction time of each of the first and second switch means is determined within a range. Each of the first and second switch means is selected by one of the unidirectional switch means capable of controlling unidirectional conduction and the bidirectional switch means capable of controlling bidirectional conduction according to the position of the common bus. Has been
The control means determines the conduction time of each of the first and second switch means so that the conduction time of the bidirectional switch is short and the conduction time of the unidirectional switch is long. The described power converter. The power conversion means includes a plurality of output terminals corresponding to a plurality of phases,
The control means performs an offset process for offsetting the output voltage command value corresponding to each phase based on the configuration of each of the first and second switch means and the position of the common bus , and 3. The conduction time of each of the first and second switch means is controlled based on a comparison between the output voltage command value of each phase after offset processing and a carrier. Power converter. The plurality of DC power sources are constituted by a first DC power source and a second DC power source in which the negative electrodes of the individual DC power sources are connected to a common negative electrode bus, and the positive electrodes of the individual DC power sources are each connected to a single bus. Has been
The control means includes
By allocating the output voltage command value of each phase according to the power distribution ratio between the first DC power source and the second DC power source, the output voltage command of each phase relating to the first DC power source. A value and a voltage command for each phase related to the second DC power source,
As the offset process, for each DC power supply, the maximum offset amount is defined as a difference between the minimum output voltage command value of each phase related to the DC power supply and the potential of the common negative electrode bus. 4. The power converter according to claim 3, wherein the output voltage command value of each phase is decreased within a range of the quantity.   The control means, as the offset processing, for each DC power supply, the difference between the minimum peak of the output voltage command value of each phase related to the DC power supply and the potential of the common negative electrode bus is used as an offset amount, and the output voltage of each phase The power conversion device according to claim 4, wherein each of the command values is decreased. The plurality of DC power supplies are constituted by a first DC power supply and a second DC power supply in which the positive poles of the individual DC power supplies are connected to a common positive bus, and the negative poles of the individual DC power supplies are respectively connected to a single bus. Has been
The control means includes
By allocating the output voltage command value of each phase according to the power distribution ratio between the first DC power source and the second DC power source, the output voltage command of each phase relating to the first DC power source. A value and an output voltage command for each phase relating to the second DC power source,
As the offset processing, for each DC power supply, the maximum offset voltage is set to the difference between the maximum output voltage command value of each phase related to the DC power supply and the potential of the common positive electrode bus. 4. The power converter according to claim 3, wherein the output voltage command value of each phase is increased within a range of the quantity.   The control means, as the offset processing, for each DC power supply, the difference between the maximum peak of the output voltage command value of each phase related to the DC power supply and the potential of the common positive electrode bus is used as an offset amount, and the output voltage of each phase The power converter according to claim 6, wherein each of the command values is decreased. In the plurality of DC power supplies, the negative electrode of the upper DC power supply and the positive electrode of the lower DC power supply are connected to a common bus, and the positive electrode of the upper DC power supply and the negative electrode of the lower DC power supply are each connected to a single bus. 1 DC power supply and 2nd DC power supply,
The control means includes
By distributing the output voltage command value of each phase according to the power distribution ratio between the first DC power supply and the second DC power supply and the voltage of each DC power supply, the first DC power supply is distributed. Calculating an output voltage command value of each phase related to the power supply and an output voltage command of each phase related to the second DC power supply,
4. The power conversion device according to claim 3, wherein, as the offset processing, the output voltage command value of each phase is offset for each DC power source based on the power distribution ratio. 5.

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