JP5396689B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an IGBT (insulated gate bipolar transistor) having not only high speed and low loss but also soft switching characteristics and a manufacturing method thereof.

  As a power semiconductor device, there are a diode, IGBT, and the like of a withstand voltage class such as 600V, 1200V, or 1700V. Recently, the characteristics of these devices have been improved. Power semiconductor devices are used in power conversion devices such as highly efficient and power-saving converter-inverters, and are indispensable for control of rotary motors and servo motors.

Such power control devices are required to have characteristics such as low loss and power saving, high speed and high efficiency, and environmental friendliness, that is, no adverse effects on the surroundings. In response to such a demand, a broad buffer structure has been proposed in the diode. The broad buffer structure, N ^- average concentration distribution of the drift layer has a peak (maximum value) substantially near the middle of the same layer, and towards the emitter and collector direction, so as to decrease with an inclination structure (For example, see Patent Document 1 below).

  In the diode of the broad buffer structure, high-speed operation (for example, carrier frequency: 20 kHz or more) that is difficult with the conventional technique for reducing the emitter injection efficiency and controlling the lifetime distribution (for example, see Patent Document 2 below). Soft recovery characteristics and oscillation suppression effect can be realized. Patent Document 1 discloses the following two methods for manufacturing such a broad buffer diode.

The first method is a method in which a region having a phosphorus concentration higher than the initial phosphorus concentration of the semiconductor substrate is formed by an epitaxial growth method in a deep region in the bulk, that is, in a region 30 to 60 μm or deeper than the surface of the semiconductor chip. It is. The second method is a method in which proton ions (H ⁺ ) are irradiated to a FZ (floating zone) bulk wafer and heat treatment is performed, whereby protons are converted to donors in the vicinity of the range Rp inside the bulk. Since the bulk wafer is less expensive than the epitaxial wafer, the second method is less expensive than the first method.

In addition to Patent Document 1, various methods for forming a high-concentration N ⁺ layer using a proton donor phenomenon caused by proton irradiation and heat treatment have been proposed (for example, Patent Document 3 and Patent below). Reference 4). In addition, Patent Document 4 discloses a method of forming an N ⁺ layer using a thermal donor using oxygen. In addition, when it is necessary to avoid proton donor formation, there is a proposal to use helium instead of proton (see, for example, Patent Document 5 below).

  Further, as a method for realizing a broad buffer structure at a low cost, a method for obtaining a high concentration region inside a bulk as a net doping concentration by compensating a donor (phosphorus) concentration of a semiconductor substrate with an acceptor element has been proposed (for example, , See Patent Document 6 below). Further, a method is known in which defects are formed in a silicon substrate by proton irradiation and the residual defects are adjusted by heat treatment to locally reduce the lifetime (see, for example, Patent Document 5 below).

  Further, as a method of manufacturing an IGBT with low cost and low electrical loss, a conventional semiconductor substrate (for example, a silicon wafer) is thinned by grinding or the like, and then an element is ion-implanted from the ground surface side at a predetermined concentration to perform heat treatment. The method of performing is known (for example, refer to Patent Document 7 below). In recent years, the development and manufacture of devices by such low-cost methods are becoming mainstream.

  In addition to the field stop IGBT disclosed in Patent Document 7 described above, the soft punch-through IGBT disclosed in Patent Document 8 below, as an IGBT having improved both low loss characteristics and soft recovery characteristics, The intermediate high concentration layer insertion type IGBT disclosed in the following Patent Document 9 and Patent Document 10 is known.

JP 2003-318812 A JP-A-8-148699 Japanese Patent Laid-Open No. 9-260639 JP 2001-156299 A Japanese Patent Laid-Open No. 2003-249662 JP-A-2005-64429 Japanese translation of PCT publication No. 2002-52085 JP 2000-195870 A JP-A-3-44969 JP 2004-193212 A

  However, as in Patent Documents 1 to 7 described above, although a technique related to a diode having a broad buffer structure is disclosed, a technique related to an IGBT having a broad buffer structure is hardly disclosed.

In the IGBTs disclosed in Patent Documents 8 to 10, the specific resistance in the N ⁻ drift layer on the side where the MOS gate is formed on the device surface is the highest, that is, the donor concentration is low. For this reason, although the element breakdown voltage is sufficiently ensured, the depletion layer spreads to more than half of the N ⁻ drift layer in the operation with the normal DC bus voltage that is a voltage of about half of the element breakdown voltage to less than the element breakdown voltage.

  For this reason, the internal excess carriers are depleted during switching, and the rate of change in the voltage across the device (dV / dt) and the rate of decrease in the device current (−dI / dt) become steep. As a result, there is a problem that the surge voltage exceeds the device withstand voltage and the device is destroyed or oscillates at a frequency of several MHz or more. The mechanism by which such waveform oscillation occurs is the same mechanism as the diode oscillation phenomenon disclosed in Patent Document 1 above.

Further, in the IGBT having the conventional structure, by reducing the thickness of the N ⁻ drift layer, it is possible to obtain an element having high-speed and low-loss switching characteristics (turn-off / turn-on loss) and low conduction loss (saturation voltage). However, in this case, there is a problem that the above-mentioned element is easily broken or oscillated because excess carriers in the inside are reduced.

Here, the result of the experiment conducted by the present inventor will be described. In this experiment, the FZ-N type silicon wafer was irradiated with protons and subjected to heat treatment, and then the concentration profile was directly evaluated by the spread resistance measurement method. The specific resistance of the wafer was 330 Ωcm, and the phosphorus concentration was 1.4 × 10 ¹³ / cm ³ . The proton irradiation energy was 7.9 MeV, and the dose was 1.0 × 10 12 / cm ² . An aluminum absorber was used to adjust the proton range to a depth of about 50 μm from the silicon surface, that is, the proton irradiation surface. A thermal oxide film having a thickness of 10,000 angstroms was formed on the proton irradiation surface.

  The heat treatment condition was 350 ° C. for 60 minutes. Also, annealing was performed in a nitrogen and hydrogen atmosphere. The sample thus prepared was affixed to a mount having an angle of 5 ° 44 ′ and polished using a 1/20 diamond compound so that the cross section of the wafer was exposed.

  Further, the spreading resistance of the sample was measured using SSM2000 manufactured by solid state measurement. The result of converting the resistance value obtained by the measurement into the carrier concentration is shown in FIG. In FIG. 26, the vertical axis represents the carrier concentration, and the horizontal axis represents the distance from the wafer surface (proton irradiation surface), that is, the depth.

  From FIG. 26, when annealed at 350 ° C., the average concentration of the wafer irradiated with protons (after proton irradiation in FIG. 26) in the vicinity of a depth of 50 μm from the surface is the wafer not irradiated with protons (FIG. 26). It can be seen that it is an order of magnitude lower than the concentration before proton irradiation. This is because there are many defects before and after the range of protons, which results in high resistance in this depth region. Therefore, it is clear that the broad buffer structure as disclosed in Patent Document 1 is not provided. As described above, it is difficult to form a desired broad buffer structure by known proton irradiation and heat treatment methods.

Further, in Patent Document 1 described above, application of a broad buffer structure to a MOSFET or reverse blocking IGBT is shown as an application example of the broad buffer structure to a device other than a diode. However, the application of the broad buffer structure to the punch-through IGBT is not shown. The first reason why the broad buffer structure cannot be applied to the punch-through IGBT is because the punch-through IGBT does not have a diode operation due to a parasitic diode of the MOSFET or a back surface PN junction of the reverse blocking IGBT. Secondly, since the depletion layer spreads not only from the front surface but also from the back surface, the reverse blocking IGBT has to form a high concentration N ⁺ buffer layer on the surface. For this reason, it is impossible to form the reverse blocking IGBT in a punch-through type in terms of device operation.

In a conventional punch-through IGBT, in a high-speed operation type device having a carrier frequency of 10 kHz or more (typically 20 kHz), the N ⁻ drift layer is made thin and the transport efficiency is lowered by electron beam irradiation or the like. Yes. For this reason, internal carriers are depleted at the time of turn-off, and a rapid change in the voltage across the element (dV / dt) and a rapid decrease in the element current (-dI / dt) occur. As a result, there are problems that the surge voltage exceeds the element withstand capability at the time of turn-off and the device is damaged, or a waveform having a frequency of several MHz or more oscillates.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which has high speed and low loss and has soft switching characteristics in order to solve the above-described problems caused by the prior art. In addition, the present invention provides a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device having high speed, low loss, and soft switching characteristics at low cost and with good controllability using an FZ bulk wafer. For the purpose.

To solve the above problems and achieve an object, a semiconductor device according to this invention includes a first conductive type drift layer, it is selectively formed on the first main surface of the first conductivity type drift layer A second conductivity type base layer; a first conductivity type source region selectively formed on a surface of the second conductivity type base layer; the first conductivity type drift layer of the second conductivity type base layer; A MOS gate structure comprising a gate insulating film in contact with a portion sandwiched between the first conductive type source region and a gate electrode in contact with the gate insulating film; and the first conductive type source region and the second conductive type base layer. A semiconductor device comprising: an emitter electrode in contact; a second conductivity type collector layer formed on the second main surface side of the first conductivity type drift layer; and a collector electrode in contact with the second conductivity type collector layer. The first conductivity type There is at least one location in the lift layer where the impurity concentration of the first conductivity type drift layer is a maximum, and the second conductivity type from the location where the impurity concentration of the first conductivity type drift layer is the maximum. In both the base layer and the second conductivity type collector layer, oxygen atoms and oxygen atoms are present at locations where the impurity concentration of at least the first conductivity type drift layer in the first conductivity type drift layer is at a maximum. Hydrogen atoms are included, and at least a portion of the first conductivity type drift layer in which the impurity concentration of the first conductivity type drift layer is maximized is defined as the first conductivity type impurity at the location, It has a composite donor derived from a hydrogen atom .

According to the above invention, the desired broad buffer structure is formed by the presence of the composite donor due to the oxygen atom and the hydrogen atom at the position where the impurity concentration of the first conductivity type drift layer is maximized.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a first conductivity type buffer layer provided between the first conductivity type drift layer and the second conductivity type collector layer is provided.

The semiconductor device according to this invention, in the above invention, the first conductivity type buffer layer, a first conductivity type impurity, and having a composite donor due to the hydrogen atom and the oxygen atom .

The semiconductor device according to this invention, in the above invention, the impurity concentration of said first conductivity type buffer layer, and greater than 5 times the average impurity concentration of said first conductivity type drift layer.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: introducing oxygen into a first conductivity type semiconductor substrate serving as the first conductivity type drift layer when manufacturing the semiconductor device described above; Irradiating the first principal surface or the second principal surface of the semiconductor substrate with ionized charged particles to introduce crystal defects into the first conductivity type drift layer in the semiconductor substrate; By recovering crystal defects introduced into the one conductivity type drift layer to form a composite donor resulting from the oxygen atom and the hydrogen atom, the net doping concentration of a part of the first conductivity type drift layer is reduced to the semiconductor And a step of making the concentration higher than the initial net doping concentration of the substrate.

A method of manufacturing a semiconductor device according to this invention, in the above invention, the ionized charged particles, characterized in that a proton.

In the method of manufacturing a semiconductor device according to the present invention, in the above invention, the range of the charged particles from the first main surface or the second main surface of the semiconductor substrate that irradiates the charged particles is the first conductivity. It is characterized in that at least the first conductivity type drift layer in the type drift layer has a maximum impurity concentration equal to the distance from the main surface to be irradiated.

The semiconductor device manufacturing method according to the present invention is characterized in that, in the above invention, the heat treatment is performed in a hydrogen atmosphere.

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the method further includes a step of grinding the second main surface of the semiconductor substrate.

The semiconductor device according to the present invention includes a first conductivity type drift layer, a second conductivity type base layer selectively formed on the first main surface side of the first conductivity type drift layer, and the second conductivity type. A first conductivity type source region selectively formed on the surface of the mold base layer, and a portion of the second conductivity type base layer sandwiched between the first conductivity type drift layer and the first conductivity type source region A MOS gate structure comprising a gate insulating film in contact with the gate insulating film and a gate electrode in contact with the gate insulating film, an emitter electrode in contact with the first conductive type source region and the second conductive type base layer, and the first conductive type drift A second conductivity type collector layer formed on the second main surface side of the layer; a first conductivity type buffer layer provided between the first conductivity type drift layer and the second conductivity type collector layer; The contact with the second conductivity type collector layer A first conductivity type drift layer formed by epitaxial growth is provided on the first main surface side of the second conductivity type collector layer formed by epitaxial growth, and the first conductivity type is provided. The impurity concentration of the type buffer layer is larger than five times the average impurity concentration of the first conductivity type drift layer, and the thickness of the second conductivity type collector layer is the first conductivity type drift layer in the first conductivity type drift layer. There is at least one location where the impurity concentration of the first conductivity type drift layer is maximum in the first conductivity type drift layer, which is thicker than the thickness of the region where the impurity concentration is higher than the average impurity concentration of the type drift layer. In addition, the impurity concentration of the first conductivity type drift layer is directed from the local maximum to both the second conductivity type base layer and the second conductivity type collector layer. Wherein the lower Te.

In the semiconductor device according to the present invention, the thickness of the region including the portion where the impurity concentration of the first conductivity type drift layer is maximum is five times the thickness of the first conductivity type buffer layer. It is characterized by being larger than.

  According to the semiconductor device of the present invention, a semiconductor device having high speed and low loss and soft switching characteristics can be obtained. In addition, according to the method for manufacturing a semiconductor device according to the present invention, a semiconductor device having high speed, low loss, and soft switching characteristics can be manufactured inexpensively and with good controllability using an FZ bulk wafer. it can.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in the layers and regions with N or P, respectively. Further, + and − attached to N and P mean that the impurity concentration is relatively high or low, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a diagram illustrating the configuration, net doping concentration, and proton distribution of the semiconductor device according to the first embodiment. In FIG. 1, a P base layer 2 is formed on one main surface side of an N ⁻ drift layer 1 as shown in a sectional view 100 of the semiconductor device. Also, N ^- on the other main surface side of the drift layer 1, N ^- impurity concentration than the drift layer 1 is higher N-type collector buffer layer 3 is formed. A P collector layer 4 is formed on the surface of the collector buffer layer 3.

An emitter electrode 5 is formed on the surface of the P base layer 2. In addition, a MOS gate structure including gate insulating film 6 and gate electrode 7 is formed so as to be in contact with N ⁻ drift layer 1 and P base layer 2. Further, an N ⁺ source region 8 is formed in a portion of the P base layer 2 in contact with the emitter electrode 5 and the gate insulating film 6. A collector electrode 9 is formed on the surface of the P collector layer 4.

In Figure 1, the distance from the emitter electrode 5 - as shown in the characteristic diagram 110 of net doping concentration (log), N ^- net doping concentration of the drift layer 1, N ^- have a peak substantially near the middle of the drift layer 1 However, it decreases toward the P base layer 2 and the collector buffer layer 3 with an inclination. That is, the semiconductor device of the first embodiment has a broad buffer structure. The net doping concentrations of P base layer 2, collector buffer layer 3 and P collector layer 4 are all higher than the net doping concentration of N ⁻ drift layer 1.

  As an example, the net doping concentration and dimensions of each part when the semiconductor device of the first embodiment is manufactured with a chip size of 10 mm × 10 mm so that the withstand voltage is 1200 V class and the rated current is 150 A are illustrated. The dimension is represented by the distance from this interface, unless otherwise specified, with reference to the interface between the P base layer 2 and the emitter electrode 5.

The distance to the interface between the P base layer 2 and the N ⁻ drift layer 1 is 3 μm. The distance to the interface between the P collector layer 4 and the collector electrode 9 is 140 μm. The distance from the interface between the collector buffer layer 3 and the P collector layer 4 to the interface between the P collector layer 4 and the collector electrode 9, that is, the thickness of the P collector layer 4 is 0.5 μm.

Net doping concentration of the P base layer 2 is 5 × 10 ¹⁶ atoms / cm ³ at the interface with the emitter electrode 5, N ^- becomes lower toward the drift layer 1, N ^- at the interface between the drift layer 1, 5 × 10 ¹³ atoms / cm ³ lower. N ^- net doping concentration of the drift layer 1, at the interface between the P base layer 2, 5 is lower than ^{× 10 13 atoms / cm 3,} P base layer 2 in the vicinity of the interface 5 × 10 ¹³ atoms / cm ³ and It becomes.

The net doping concentration at the peak in the vicinity of the middle of the N ⁻ drift layer 1 is 1.5 × 10 ¹⁴ atoms / cm ³ . The net doping concentration of the N ⁻ drift layer 1 at the interface with the collector buffer layer 3 and in the vicinity thereof is 5 × 10 ¹³ atoms / cm ³ .

The net doping concentration of the collector buffer layer 3 is 5 × 10 ¹³ atoms / cm ³ at the interface with the N ⁻ drift layer 1 and increases toward the P collector layer 4. The net doping concentration of the collector buffer layer 3 is higher than 1.5 × 10 ¹⁴ atoms / cm ^3, which is the peak net doping concentration of the N ⁻ drift layer 1 in the vicinity of the interface with the P collector layer 4. At the interface with the layer 4, it is lower than 5 × 10 ¹³ atoms / cm ³ .

The net doping concentration of the P collector layer 4 is lower than 5 × 10 ¹³ atoms / cm ^{3 at} the interface with the collector buffer layer 3, but increases toward the collector electrode 9, and 1 × 10 at the interface with the collector electrode 9. ¹⁸ atoms / cm ³ .

In FIG. 1, as shown in the distance-proton distribution characteristic diagram 120 from the emitter electrode, the distance to the portion where the net doping concentration of the N ⁻ drift layer 1 reaches a peak is 60 μm. This distance is equal to the proton range Rp when the surface of the P base layer 2 is irradiated with protons in the manufacturing stage. The proton concentration is high before and after the proton range Rp. Oxygen atoms are introduced into the N ⁻ drift layer 1, and a desired broad buffer structure is formed by a composite donor composed of oxygen atoms and protons.

Next, a manufacturing process of the semiconductor device according to the first embodiment will be described. Here, as an example, a case where a semiconductor device having the dimensions and net doping concentration illustrated in FIG. 1 (withstand voltage: 1200 V class, rated current: 150 A) will be described. 2 and 3 are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. First, as shown in a sectional view 200 of FIG. 2, an FZ wafer 10 having a specific resistance of 40 to 120 Ωcm, for example, 90 Ωcm (phosphorus concentration 5.0 × 10 ¹³ atoms / cm ³ ) is prepared as a semiconductor substrate.

Then, as shown in a cross-sectional view 210 of FIG. 2, phosphorus glass 11 is applied to both surfaces of the FZ wafer 10, and heat treatment is performed, for example, at 1250 ° C. for 100 hours in a nitrogen and oxygen atmosphere. To diffuse. By this heat treatment, a large amount of oxygen (O) is introduced into the wafer from both sides of the FZ wafer 10, and the oxygen concentration in the FZ wafer 10 becomes a solid solution limit concentration (about 1 × 10 ¹⁸ atoms / cm ³ ).

Next, as shown by the alternate long and short dash line in the cross-sectional view 210, the FZ wafer 10 is ground to remove the high-concentration phosphorus diffusion layer 211 on the wafer surface. As a result, as shown in the cross-sectional view 220 of FIG. 2, a thin wafer 213 having an N ⁺ layer 214 made of a high concentration phosphorus diffusion layer 211 is obtained. One surface of the thin wafer 213 is polished to a mirror finish. On the mirror finished surface of the FZ wafer 10, a MOS gate structure including the P base layer 2, the emitter electrode 5, the gate insulating film 6 and the gate electrode 7 and an N ⁺ source region 8 are formed in a later MOS device forming process. Is done. The thickness of the FZ wafer 10 is selected in advance so as to be, for example, 500 μm after the grinding and polishing.

The specific resistance at the mirror finished surface of the FZ wafer 10 is, for example, 90 Ωcm. The other surface of the FZ wafer 10 is in a state where the phosphorus glass 11 is removed. The surface concentration of this surface is, for example, about 1 × 10 ²⁰ atoms / cm ³ , and high-concentration phosphorus is diffused to a depth of, for example, about 80 μm.

Next, as shown in a cross-sectional view 230 of FIG. 2, a MOS gate structure including a P base layer 2, an emitter electrode 5, a gate insulating film 6, and a gate electrode 7 serving as a P base layer by a standard MOS device process step. N ⁺ source region 8 is formed. The concentration of the P base layer 2 is, for example, 5 × 10 ¹⁶ atoms / cm ³ , and the depth thereof is, for example, 3 μm.

Next, as shown in a sectional view 240 of FIG. 2, the FZ wafer 10 is irradiated with protons accelerated by a cyclotron from the emitter electrode 5 side. At that time, the acceleration voltage of the cyclotron is, for example, 7.9 MeV, and the dose amount of protons is, for example, 1.0 × 10 ¹² atoms / cm ² . In addition, an aluminum absorber is used and the thickness thereof is adjusted so that the proton range is 60 μm from the interface between the semiconductor of the FZ wafer 10 and the emitter electrode 5. In the cross-sectional view 240, the x mark represents the crystal defect 12 generated in the FZ wafer 10 by proton irradiation.

  Next, as shown in a cross-sectional view 300 of FIG. 3, for example, heat treatment is performed at 350 ° C. for 1 hour in a hydrogen atmosphere to recover the crystal defects 12. As a result, a high concentration region 13 is formed around a depth of 60 μm from the interface between the semiconductor of the FZ wafer 10 and the emitter electrode 5. A desired broad buffer structure is formed by the high concentration region 13.

  Next, as shown in a cross-sectional view 310 of FIG. 3, the surface of the FZ wafer 10 with the phosphor glass 11 removed is ground or wet etched to make the FZ wafer 10 have a predetermined thickness. . In the case of the 1200V class, the thickness of the FZ wafer 10 at this stage is typically 100 to 160 μm. In the first embodiment, the thickness of the FZ wafer 10 at this stage is, for example, 120 μm.

Next, as shown in a cross-sectional view 320 of FIG. 3, an N-type impurity such as phosphorus is ion-implanted into the surface of the FZ wafer 10 on which grinding or wet etching has been performed. The acceleration voltage at that time is, for example, 200 keV, and the dose amount is, for example, 5 × 10 ¹² atoms / cm ² . Next, the ion-implanted surface is irradiated with a laser beam such as a YAG second harmonic laser by a double pulse method.

  Here, the double pulse method is a method of continuously irradiating a plurality of pulse lasers by shifting the irradiation timing by a predetermined delay time from a plurality of laser irradiation apparatuses for each laser light irradiation area. The double pulse method is described in detail in Japanese Patent Application Laid-Open No. 2005-223301.

The energy density at the time of laser beam irradiation by the double pulse method is, for example, 3 J / cm ² in total for each laser beam irradiation area. The delay time of the double pulse is, for example, 300 nsec. By this laser irradiation, an N-type impurity such as phosphorus ion-implanted before that is electrically activated, and a collector buffer layer 3 serving as a field stop layer for stopping the depletion layer is formed. Note that ions to be implanted when forming the collector buffer layer 3 are N-type elements (for example, selenium) having a diffusion coefficient larger than that of phosphorus, and a buffer layer having a deeper diffusion depth than that of phosphorus is formed. Also good.

Subsequently, a P-type impurity such as boron is ion-implanted into the surface on which the collector buffer layer 3 is formed. The acceleration voltage at that time is, for example, 45 keV, and the dose amount is, for example, 1 × 10 ¹⁴ atoms / cm ² . Next, the ion-implanted surface is heat-treated at 350 ° C. for 1 hour, for example, to form the P collector layer 4.

Finally, a metal film is formed on the surface of the P collector layer 4 in the order of aluminum, titanium, nickel, and gold to form the collector electrode 9, thereby completing the semiconductor device (IGBT). The portion of the FZ wafer 10 between the P base layer 2 and the collector buffer layer 3 becomes the N ⁻ drift layer 1. A characteristic diagram 330 in FIG. 3 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 320.

The ratio of the peak doping concentration Np in the broad buffer layer portion to the average doping concentration Ndm in the N ⁻ drift layer 1 is preferably Np / Ndm <5. The reason is that if Np / Ndm <5, the rate of change (dV / dt) in the voltage across the element is reduced. The effective integration density of the broad buffer layer is 1 cm ² per 8 × 10 ¹¹ / cm ² or less, N ^- effective integration density of the entire drift layer is to a 1 cm ² per 1.2 × 10 ¹¹ / cm ² desirable.

Here, the result of the experiment conducted by the present inventor will be described. In this experiment, oxygen was introduced into the FZ-N type silicon wafer under the same conditions as in the manufacturing process of FIGS. 2 and 3, a thermal oxide film having a thickness of 10,000 angstroms was formed on the surface of the wafer, and protons were formed on the surface. Irradiated. The specific resistance of the wafer was 330 Ωcm, and the phosphorus concentration was 1.4 × 10 ¹³ / cm ³ . The proton irradiation energy was 7.9 MeV, and the dose was 1.0 × 10 ¹² / cm ² .

  Thereafter, heat treatment was performed in a hydrogen atmosphere. The heat treatment condition was 350 ° C. for 60 minutes. The obtained sample was affixed to a mount having an angle of 5 ° 44 ′, polished with a 1/20 diamond compound so that the cross section of the wafer was exposed, and the exposed surface was subjected to SSM2000 manufactured by solid state measurement. Was used to measure the spreading resistance.

  FIG. 4 (heat treatment temperature: 350 ° C.) shows the result of converting the resistance value obtained by the measurement into the carrier concentration. In FIG. 4, the vertical axis represents the carrier concentration, and the horizontal axis represents the distance from the wafer surface (proton irradiation surface).

  As shown in FIG. 4, when annealing is performed at 350 ° C., in the vicinity of a depth of 50 μm from the surface, the average concentration of the wafer irradiated with protons (after proton irradiation in FIG. 4) is the wafer not irradiated with protons (FIG. 4). It can be seen that the desired broad buffer structure is formed. In FIG. 4, the high concentration region (low resistance region) from the wafer surface to a depth of about 15 μm is due to the diffusion of oxygen from the oxide film.

From the above description and a comparison between FIG. 4 and FIG. 26 , in order to form a broad buffer structure, not only hydrogen atoms are introduced into the substrate by proton irradiation but also oxygen is contained in the substrate. It is clear that it is extremely important. In order to become a composite donor by the interaction with oxygen by heat treatment, it is necessary to irradiate an element lighter than oxygen. Accordingly, the charged particles to be irradiated are preferably H or He lighter than Li among H, He, Li, Be and B, and particularly preferably H (proton).

FIG. 5 is a diagram illustrating a turn-off waveform of the semiconductor device and the conventional IGBT according to the first embodiment. In FIG. 5, the collector current Ic and the collector-emitter voltage Vc of the semiconductor device (N ⁻ drift layer thickness: 120 μm) according to the first embodiment are indicated by bold solid lines. Further, the collector current Ic and the collector-emitter voltage Vc of the conventional IGBT having an N ⁻ drift layer thickness of 120 μm are indicated by a thin solid line. Further, the collector current Ic and the collector-emitter voltage Vc of the conventional IGBT having an N ⁻ drift layer thickness of 140 μm are indicated by a one-dot broken line.

  All the turn-off waveforms shown in FIG. 5 are waveform diagrams in the snubberless circuit 60 shown in FIG. The load inductance Lm of the main circuit of the snubberless circuit 60 is 1 mH, and the circuit floating inductance Ls of the main circuit is 200 nH. Further, the gate resistance of the snubberless circuit 60 is 10Ω, and the gate drive voltage is ± 15V. Further, the bonding temperature at the time of measurement was 125 ° C.

In the case of a conventional IGBT having an N ⁻ drift layer thickness of 120 μm, the surge voltage increases by 50 V and oscillates. In the case of a conventional IGBT having an N ⁻ drift layer thickness of 140 μm, no oscillation occurs as in the case of a conventional IGBT having an N ⁻ drift layer thickness of 120 μm. Thus, in order to suppress oscillation in the conventional IGBT, it is necessary to increase the N ⁻ drift layer thickness to, for example, about 140 μm. On the other hand, the semiconductor device according to the first embodiment does not oscillate even when the N ⁻ drift layer thickness is 120 μm, and exhibits a smooth switching waveform.

In addition, the semiconductor device according to the first embodiment has improved loss characteristics as compared with the conventional IGBT. The saturation voltage of the conventional IGBT having an N ⁻ drift layer thickness of 140 μm is 1.9 V, whereas the saturation voltage of the semiconductor device according to the first embodiment is 1.7 V, and the saturation voltage is about 0.2 V. Reduced. Further, the turn-off loss of the conventional IGBT having an N ⁻ drift layer thickness of 140 μm is 14.5 mJ / cm ² , whereas the turn-off loss of the semiconductor device according to the first embodiment is 13.5 mJ / cm ² . The turn-off loss is reduced by about 7%. Thus, in the semiconductor device according to the first embodiment, the trade-off characteristics can be remarkably improved as compared with the conventional IGBT.

FIG. 7 is an explanatory diagram of a change in the internal state of the semiconductor device according to the first embodiment at the time of turn-off due to device simulation. FIG. 8 is an explanatory diagram showing a change in internal state at the time of turn-off of a conventional IGBT (N ⁻ drift layer thickness: 120 μm) by device simulation. 7 and 8 show the relationship between the distance from the emitter electrode-impurity concentration (donor concentration), the relationship from the emitter electrode at each time (μs) -the relationship between the electric field strength and each time (μs) from the start of measurement. The relationship between the distance from the emitter electrode and the electron concentration is shown.

  As shown in FIG. 7, in the semiconductor device according to the first embodiment, the exhaustion of surplus carriers is not observed between time 0.3 and 0.4 μs. In the semiconductor device according to the first embodiment, the depletion layer stops spreading around 100 μm from the emitter electrode. On the other hand, as shown in FIG. 8, in the conventional IGBT, depletion of surplus carriers is observed after time 0.375 μs from the start of measurement. In the conventional IGBT, the depletion layer extends from the emitter electrode to around 120 μm, and the depletion layer extends almost to the field stop layer. That is, in the conventional IGBT, carriers are scavenged by the expansion of the depletion layer, and excess carriers are depleted. This is the same phenomenon as the so-called pinning effect of the space charge region disclosed in Patent Document 1 described above.

(Embodiment 2)
Subsequently, a manufacturing process of the semiconductor device according to the second embodiment will be described. The configuration of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment, but the manufacturing process is different. Specifically, in the first embodiment, the collector buffer layer 3 is formed by ion implantation and pulse irradiation. In the second embodiment, the collector buffer layer 3 is formed by a proton shadow donor.

  FIG. 9 is a diagram illustrating the configuration, net doping concentration, and proton distribution of the semiconductor device according to the second embodiment. In FIG. 9, the cross-sectional view 900 of the semiconductor device and the distance-net doping concentration (log) characteristic diagram 910 of the semiconductor device 5, the configuration of the semiconductor device according to the second embodiment and the net doping concentration are shown in FIG. The semiconductor device according to the first embodiment shown in FIG.

On the other hand, as shown in the distance-proton distribution characteristic diagram 920 from the emitter electrode 5, the distance to the location where the net doping concentration of the N ⁻ drift layer 1 peaks is 50 μm, and the proton concentration before and after this is high. In addition, in the region where the depth is 110 to 140 μm, the proton concentration is high. The reason why the proton concentration is high in the vicinity of a depth of 50 μm is that a broad buffer structure is formed. The reason why the proton concentration is high in the region having a depth of 110 to 140 μm is that the collector buffer layer 3 is formed.

  In addition, although the distance to the interface between the P collector layer 4 and the collector electrode 9 is 120 μm, the proton concentration is high in the region where the depth is 110 to 140 μm. This is because the wafer before grinding, which is thicker than 120 μm, is irradiated with protons so that the range is 110 to 140 μm.

10 and 11 are diagrams illustrating a manufacturing process of the semiconductor device according to the second embodiment. Here, as an example, a case will be described in which a semiconductor device (withstand voltage: 1200 V class, rated current: 150 A) having the same dimensions and net doping concentration as the semiconductor device according to the first embodiment is manufactured. First, as shown in the cross-sectional view 1000, the cross-sectional view 1010, the cross-sectional view 1020, and the cross-sectional view 1030 in FIG. 10, oxygen is introduced to phosphorus (P) and the solid solution limit concentration in the same manner as the process described in FIG. On the mirror finished surface of the FZ wafer 10, a MOS gate structure comprising the P base layer 2, the emitter electrode 5, the gate insulating film 6 and the gate electrode 7 and an N ⁺ source region 8 are formed by standard MOS device process steps. To do.

  Next, as shown in a sectional view 1040 of FIG. 10, the FZ wafer 10 is irradiated with protons from the emitter electrode 5 side under the same conditions as described in FIG. However, the thickness of the aluminum absorber is adjusted so that the proton range is 50 μm from the interface between the semiconductor of the FZ wafer 10 and the emitter electrode 5 (see Rp1 in FIG. 9 and the characteristic diagram 920). In the cross-sectional view 1040, the X mark on the side close to the P base layer 2 represents the crystal defect 12 generated in the FZ wafer 10 due to proton irradiation when the range Rp1 is 50 μm.

  Subsequently, the thickness of the aluminum absorber is adjusted so that the proton range is 110 to 140 μm from the interface between the semiconductor of the FZ wafer 10 and the emitter electrode 5 (see Rp2 in FIG. 9 and the characteristic diagram 920). The FZ wafer 10 is irradiated with protons from the electrode 5 side under the same conditions as described in FIG. In the cross-sectional view 1040, the X mark on the side far from the P base layer 2 represents a crystal defect 14 generated in the FZ wafer 10 by proton irradiation when the range Rp2 is 110 to 140 μm.

The second proton irradiation may be performed from the opposite side of the emitter electrode 5. Opposite the emitter electrode 5, if an emitter electrode 5 are formed on the front surface of the FZ wafer 10 is that the back side of the F Z wafer 10. The proton distribution when the second proton irradiation is performed from the back side is shown by a broken line in a characteristic diagram 920 of FIG.

  Next, as shown in a cross-sectional view 1100 of FIG. 11, heat treatment is performed under the same conditions as described in FIG. As a result, a first high concentration region 13 is obtained by recovery of the crystal defects 12 formed by the first proton irradiation, and a second high concentration region 15 is formed by recovery of the crystal defects 14 formed by the second proton irradiation. A desired broad buffer structure is formed by the first high concentration region 13. Further, the collector buffer layer 3 is formed by the second high concentration region 15.

Next, as shown in the sectional view 1110 of FIG. 11, the FZ wafer 10 is made to have a thickness of 120 μm, for example, in the same manner as in the description of FIG. Then, as shown in the sectional view 1120 of FIG. 11, the P collector layer 4 and the collector electrode 9 are formed in the same manner as in the description of FIG. 3, and the semiconductor device is completed. The portion of the FZ wafer 10 between the P base layer 2 and the collector buffer layer 3 becomes the N ⁻ drift layer 1. A characteristic diagram 1130 in FIG. 11 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 1120.

(Embodiment 3)
FIG. 12 is a diagram illustrating the configuration and net doping concentration of the semiconductor device according to the third embodiment. In the third embodiment, the broad buffer structure of the N ⁻ drift layer 1 is formed by acceptor compensation. As shown in a sectional view 1200 of the semiconductor device in FIG. 12, the semiconductor device of the third embodiment has a configuration in which the collector buffer layer 3 of the semiconductor device of the first embodiment shown in FIG. Since other configurations are the same as those of the first embodiment, the same reference numerals are given and description thereof is omitted.

  As an example, the net doping concentration and dimensions of each part of the semiconductor device of the third embodiment are illustrated. However, only values different from the values exemplified in the first embodiment will be described. In FIG. 12, the distance from the emitter electrode 5 vs. the net doping concentration (log) characteristic diagram 1210 shows that the distance to the interface between the P collector layer 4 and the collector electrode 9 is 120 μm.

The donor concentration of the entire substrate of the semiconductor device is 1.5 × 10 ¹⁴ atoms / cm ³ . Aluminum (Al) or gallium (Ga) is diffused as an acceptor from the interface between the emitter electrode 5 and the P base layer 2 to almost the center of the N ⁻ drift layer 1 (near the peak of the net doping concentration). Further, zinc (Zn) or platinum (Pt) is diffused as an acceptor from the interface between the collector electrode 9 and the P collector layer 4 to almost the center of the N ⁻ drift layer 1. This acceptor concentration is lower than the donor concentration of the entire substrate at each position.

  Next, a manufacturing process of the semiconductor device according to the third embodiment will be described. Here, as an example, a case will be described in which a semiconductor device (withstand voltage: 1200 V class) having the dimensions and net doping concentration illustrated in FIG. 12 is manufactured. 13 and 14 are diagrams illustrating a manufacturing process of the semiconductor device according to the third embodiment. First, as shown in a sectional view 1300 of FIG. 13, an FZ wafer 10 similar to that of the first embodiment is prepared as a semiconductor substrate.

Next, as shown in a cross-sectional view 1310 of FIG. 13, aluminum (or gallium; hereinafter omitted) is ion-implanted from one surface of the FZ wafer 10. The acceleration voltage at that time is, for example, 60 keV, and the dose amount is, for example, 3 × 10 ¹¹ atoms / cm ² . Then, for example, heat treatment is performed at 1150 ° C. for 80 minutes to diffuse aluminum and form an aluminum diffusion layer 1311 (gallium diffusion layer when gallium is implanted). As disclosed in Patent Document 1, since aluminum has a property of diffusing outwardly, when aluminum is injected, a nitride film is used to prevent outward diffusion. By this diffusion, the aluminum diffusion layer 1311 reaches a depth of about 20 μm from the surface of the FZ wafer 10.

Next, as shown in a sectional view 1320 of FIG. 13, a MOS gate structure including the P base layer 2, the gate insulating film 6, and the gate electrode 7, an N ⁺ source region 8 and the like are formed by standard MOS device process steps. To do. At this time, since aluminum is also diffused during diffusion of the shallow P layer of 4 to 8 μm, the aluminum diffusion layer 1311 reaches about 40 μm from the surface.

Next, as shown in a cross-sectional view 1330 of FIG. 13, the FZ wafer 10 is ground from the back surface to a thickness of 140 μm. Further, wet etching with hydrofluoric acid is performed on the FZ wafer 10 to a thickness of 120 μm. Thereafter, as shown in a sectional view 1400 of FIG. 14, zinc or platinum is ion-implanted from the back surface of the FZ wafer 10. The acceleration voltage at that time is, for example, 300 keV, and the dose amount is, for example, 3 × 10 ¹¹ / cm ² . Then, for example, heat treatment is performed at 1000 ° C. for 2 hours to diffuse zinc or platinum from the back surface of the FZ wafer 10 to a depth of about 30 μm.

Subsequently, as shown in a cross-sectional view 1410 of FIG. 14, phosphorus (P) is ion-implanted from the back surface of the FZ wafer 10 at, for example, an acceleration voltage of 200 keV and a dose of 1 × 10 ¹³ / cm ^2. Boron (B) is ion-implanted from the back surface of the substrate at an acceleration voltage of 200 keV and a dose of 1 × 10 ¹⁴ / cm ² , for example. Alternatively, instead of phosphorus, selenium (Se) or sulfur (S) having a diffusion coefficient larger than that of phosphorus is ion-implanted, for example, at an acceleration voltage of 200 keV and a dose of 1 × 10 ¹³ / cm ² . Boron (B) may be ion-implanted from the back surface, for example, at an acceleration voltage of 200 keV and a dose of 1 × 10 ¹⁴ / cm ² .

  Then, for example, heat treatment is performed at 1000 ° C. for 30 minutes to form the collector buffer layer 3 for stopping the depletion layer. Further, Al-1% Si is formed by sputtering with 5 μm, and patterning etching is performed to form the emitter electrode 5.

  Next, as shown in cross-sectional views 1420 and 1440 of FIG. 14, Al—Si sintering is performed at 400 ° C. for 80 minutes to form a passivation polyimide film in a peripheral withstand voltage structure. Cross-sectional view 1420 is a cross-sectional view when phosphorus having a small diffusion coefficient is ion-implanted in the step shown in cross-sectional view 1410, and the diffusion depth is about 0.5 μm. Cross-sectional view 1440 is a cross-sectional view when selenium or sulfur having a large diffusion coefficient is ion-implanted in the step shown in cross-sectional view 1410, and the diffusion depth is about 30 μm.

Thereafter, boron is ion-implanted from the back surface of the FZ wafer 10. The acceleration voltage at that time is 45 keV, for example, and the dose is 1 × 10 ¹⁴ / cm ² , for example. Then, for example, heat treatment is performed at 380 ° C. for 1 hour to form the P collector layer 4. Finally, titanium, nickel and gold are vapor-deposited on the back surface of the FZ wafer 10 to form the collector electrode 9. A characteristic diagram 1430 in FIG. 14 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 1420. A characteristic diagram 1450 in FIG. 14 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 1440.

In the above description of the first to third embodiments, only the IGBT using the FZ wafer has been described. However, the present invention can also be applied to the IGBT using the epitaxial wafer. FIG. 15 is a diagram showing the configuration and net doping concentration of a semiconductor device in which the present invention is applied to an epitaxial wafer. As shown in a cross-sectional view 1500 of the IGBT in FIG. 15, an N ⁺ buffer layer (collector buffer layer) 1502 is formed by epitaxial growth on one main surface of a 10 μm-thick P-type substrate 1501 serving as a P collector layer.

An N ⁻ drift layer 1503 is formed on the surface of the N ⁺ buffer layer 1502 by epitaxial growth. Further, surface structures such as a P base layer 1504, an emitter electrode 1505, a gate insulating film 1506, a gate electrode 1507, and an N ⁺ source region 1508 are formed on the surface of the N ⁻ drift layer 1503. A collector electrode 1509 is formed on the other main surface of the P-type substrate 1501.

As shown in FIG. 1510, the distance from the emitter electrode to the net doping concentration (log) in FIG. 15 shows that the net doping concentration of the N ⁻ drift layer 1503 has a peak near the middle of the N ⁻ drift layer. It decreases with an inclination toward the base layer 1504 and the N ⁺ buffer layer 1502, and the IGBT shown in FIG. 15 has a broad buffer structure. A characteristic diagram 1510 in FIG. 15 is a profile of net doping concentration corresponding to the IGBT in the cross-sectional view 1500.

Such a broad buffer structure can be formed by adjusting the flow rate of a gas serving as a donor when the N ⁻ drift layer 1503 is epitaxially grown, as shown in Patent Document 1 above. Thereby, characteristics can be improved also in a punch-through type IGBT using an epitaxial wafer.

  The present invention can also be applied to a non-punch through type IGBT. FIG. 16 is a diagram showing the configuration and net doping concentration of a non-punch through IGBT to which the present invention is applied. In FIG. 16, a cross-sectional view 1600 shows a configuration of a non-punch through type IGBT to which the present invention is applied. A characteristic diagram 1610 is a net doping concentration profile corresponding to the IGBT shown in the cross-sectional view 1600.

In FIG. 16, a P base layer 1602, an emitter electrode 1603, a gate insulating film 1604, a gate electrode 1605, and an N ⁺ source region 1606 are formed on one main surface of the N ⁻ drift layer 1601, as shown in an IGBT cross-sectional view 1600. Has been. Further, a P collector layer 1607 and a collector electrode 1608 are formed on the other main surface of the N ⁻ drift layer 1601.

  As described above, since it is possible to form a broad buffer layer without using a field stop layer, the present invention can be applied to a non-punch through type IGBT. In the non-punch through type IGBT, even if a voltage equal to the element breakdown voltage is applied, the depletion layer does not reach the P collector layer on the back surface, so that a leakage current as seen in the field stop type IGBT does not occur.

  The present invention can also be applied to reverse blocking IGBTs and reverse conducting IGBTs as disclosed in Japanese Patent Application Laid-Open No. 2004-363328. FIG. 17 is a diagram showing the configuration and net doping concentration of a reverse conducting IGBT to which the present invention is applied. In FIG. 17, a cross-sectional view 1700 is a cross-sectional view of a reverse conducting IGBT to which the present invention is applied, and a characteristic view 1710 is a net doping concentration profile corresponding to the IGBT of the cross-sectional view 1700.

  The IGBT to which the present invention is applied can realize turn-off with low loss and suppressed oscillation. In particular, the reverse conducting IGBT to which the present invention is applied has an IGBT section 1720 and a freewheeling diode section 1730 as shown in FIG. 17, so that the reverse recovery characteristic can be improved at the same time.

  Furthermore, the application example of IGBT concerning this invention is shown in FIGS. A converter-inverter circuit 1800 shown in FIG. 18 can efficiently control an induction motor, a servo motor, and the like, and is widely used in industries, electric railways, and the like. A power factor correction circuit (PFC circuit) 1900 shown in FIG. 19 is a circuit that improves the waveform by controlling the input current of AC-AC conversion in a sine wave shape, and is used for a switching power supply. A circuit diagram 2000 of FIG. 20 is an overall diagram of the matrix converter circuit 2001, and a circuit diagram 2010 is a diagram showing a configuration of the switching unit 2002 of the matrix converter circuit 2001.

(Embodiment 4)
FIG. 21 is a diagram illustrating the configuration and net doping concentration of the semiconductor device according to the fourth embodiment. In FIG. 21, a P emitter layer 2102 is formed on a part of one main surface of the N ⁻ drift layer 2101 as shown in a sectional view 2100 of the semiconductor device. A collector buffer layer 2103 is formed on the other main surface side of the N ⁻ drift layer 2101. A P ⁺ collector layer 2104 is formed on the surface of the collector buffer layer 2103. A collector electrode 2109 is formed on the surface of the P ⁺ collector layer 2104.

An N ⁺ source region 2108 is formed in the P emitter layer 2102. A MOS gate structure including a gate insulating film 2106 and a gate electrode 2107 is formed so as to be in contact with the N ⁻ drift layer 2101, the P emitter layer 2102, and the N ⁺ source region 2108. An emitter electrode 2105 is formed so as to be in contact with a part of the P emitter layer 2102 and the N ⁺ source region 2108 and to cover the MOSFET gate structure.

In Figure 21, the distance from the emitter electrode 2105 - as shown in the characteristic diagram 2110 of the net doping concentration (log), N ^- net doping concentration of the drift layer 2101, N ^- have a peak substantially near the middle of the drift layer 2101 However, it decreases with an inclination toward the P emitter layer 2102 and the collector buffer layer 2103. That is, the semiconductor device of the fourth embodiment has a broad buffer structure. The net doping concentration of P emitter layer 2102, collector buffer layer 2103 and P ⁺ collector layer 2104 are all higher than the net doping concentration of N ⁻ drift layer 2101.

Net doping concentration of the P emitter layer 2102 is 5 × 10 ¹⁶ atoms / cm ³ at the interface with the emitter electrode 2105, N ^- becomes lower toward the drift layer 2101, N ^- at the interface between the drift layer 2101, 5 × 10 ¹³ atoms / cm ³ lower. N ^- net doping concentration of the drift layer 2101 at the interface between the P emitter layer 2102, 5 × but 10 ¹³ less than atoms / cm ^3, near the interface 5 × 10 ¹³ atoms / cm ³ of the P emitter layer 2102 It becomes.

The average net doping concentration N _dm of the N ⁻ drift layer 2101 is 9 × 10 ¹³ atoms / cm ³ . The net doping concentration of the N ⁻ drift layer 2101 at the interface with the collector buffer layer 2103 and in the vicinity thereof is 5 × 10 ¹³ atoms / cm ³ . Moreover, the net doping concentration of the collector buffer layer 2103 (peak concentration) N _B is ^{1 × 10 15 atoms / cm 3} . The net doping concentration (peak concentration) of the P ⁺ collector layer 2104 is 1 × 10 ¹⁸ atoms / cm ³ .

Further, the thickness of each layer of the semiconductor device is 120 μm for the N ⁻ drift layer 2101, 15 μm for the collector buffer layer 2103, and 215 μm for the P ⁺ collector layer 2104.

Here, the thickness and net doping concentration of each layer are determined as follows. First, the net doping concentration N _B of the collector buffer layer 2103, N ^- 5 times of the average net doping concentration N _dm drift layer 2101, i.e., so that the following equation (1) holds.
5N _dm <N _b (1)

This is due to the following reason. In a state where the voltage is blocked at the time of OFF, a depletion layer spreads in the N ⁻ drift layer 2101 from the front surface (emitter) side to the back surface (collector) side. In the punch-through type IGBT, this depletion layer is stopped by the collector buffer layer 2103 (punched through) so as not to reach the P ⁺ collector layer 2104.

N ^- extension of the depletion layer in the drift layer 2101, from the equation of Poisson, N ^- immediately before the collector buffer layer 2103 of phosphorus concentration in the drift layer 2101 ^- average broad buffer layer is a drift layer 2101 net doping concentration (N N _dm , which is integrated in the depth direction and divided by the thickness of the N ⁻ drift layer 2101. In order to stop the depletion layer in the collector buffer layer 2103, the net doping concentration N _B of the collector buffer layer 2103 must be higher than the average net doping concentration N _{dm of the} N ⁻ drift layer 2101 (broad buffer layer).

When the net doping concentration N _B of the collector buffer layer 2103 and the average net doping concentration N _dm of the N ⁻ drift layer 2101 are approximately the same, in order to stop the depletion layer in the collector buffer layer 2103, the thickness of the collector buffer layer 2103 And the thickness of the N ⁻ drift layer 2101 should be approximately the same. In that case, a region where carriers are accumulated in the ON state becomes thick, leading to an increase in conduction loss and turn-off loss. The depletion layer is preferably stopped at about 1/5 of the thickness of the N ⁻ drift layer 2101. Therefore, the average net doping concentration NB of the N ⁻ drift layer 2101 is about five times the net doping concentration N _dm of the collector buffer layer 2103, that is, the above formula (1) is satisfied. In the example of FIG. 21, an ^{_{N dm = 9 × 10 13 atoms}} / cm 3, NB = 1 × 10 15 atmos / cm 3, the above formula (1) is satisfied.

Next, the thickness of the P ⁺ collector layer 2104 is preferably thicker than the thickness of the N ⁻ drift layer 2101. More specifically, the thickness of the P ⁺ collector layer 2104 (W _A) is N ^- among N drift layer 2101 ^- net doping concentration than the average net doping concentration of the drift layer 2101 is a region of high thickness (W _M ) Is desirable.

This is due to the following reason. The net doping concentration of the P ⁺ collector layer 2104 is approximated as a rectangular distribution, placing the integral net doping concentration of the P ⁺ collector layer 2104 and the N _A W _A. Similarly, place the integral net doping concentration of the collector buffer layer 2103 and the N _B W _B. Here, N _A and N _B are the concentrations of the P ⁺ collector layer 2104 and the collector buffer layer 2103, respectively. W _A and W _B are the thicknesses of the P ⁺ collector layer 2104 and the collector buffer layer 2103, respectively.

In this case, the injection efficiency of the transport efficiency only collector buffer layer 2103 from alpha _t, P ⁺ collector layer 2104 into the collector buffer layer 2103 gamma _e, the diffusion length of the bipolar carrier and L _a, the collector buffer layer 2103 The common base gain α ₀ is expressed by the following equation (2).

The implantation from the high concentration P-type substrate (P ⁺ collector layer 2104) is a high implantation. For this reason, it is desirable that the injection efficiency γ _e is about 1 as a low injection condition from the high concentration P-type substrate. Further, since N _A > N _B , the following formula (3) is established.
W _A >> W _B (3)

On the other hand, the field strength of the depletion layer is attenuated in the broad buffer layer (N ⁻ drift layer 2101) in the region where the net doping concentration is equal to or higher than the average net doping concentration, that is, the net doping concentration becomes the average net doping concentration 2. A region M (thickness W _M ) sandwiched between the points. In the example of FIG. 21, the thickness W _M = 80 μm. Since 5N _dm <N _{b as} shown in the above formula (1), the thickness W _M of the region M needs to be at least 5 times W _B. That is, the following formula (4) is satisfied.
W _M / 5> W _B (4)

From the following formulas (3) and (4), the thickness W _M in the broad buffer layer must satisfy the following formula (5). In addition, since the hole injection efficiency from the P ⁺ collector layer 2104 must be kept high, the thickness W _A of the P ⁺ collector layer 2104 should preferably satisfy the following formula (6). That is, the thickness of the P ⁺ collector layer 2104 (W _A) is, N ^- among the drift layer 2101 N ^- average net doping concentration net doping concentration than the thickness of the high region of the drift layer 2101 (W _M) than Thick is desirable.
W _A >> W _M / 5 >> W _B (5)
W _A > W _M (6)

Next, a manufacturing process of the semiconductor device according to the fourth embodiment will be described. 22 to 24 are diagrams illustrating a manufacturing process of the semiconductor device according to the fourth embodiment. First, as shown in a cross-sectional view 2200 of FIG. 22, a high-concentration P-type CZ wafer serving as a P ⁺ collector layer 2104 is prepared as a semiconductor substrate.

Next, a high-concentration N-type epitaxial layer (collector buffer layer 2103) having a phosphorus concentration of 1 × 10 ¹⁵ atoms / cm ³ and a thickness of 15 μm is epitaxially grown on the surface (mirror-finished surface) of the CZ wafer 2201. Subsequently, as shown in a sectional view 2300 of FIG. 23, an N ⁻ drift layer 2101 (broad buffer layer) having a total thickness of 120 μm is epitaxially grown on the surface of the N-type epitaxial layer 2103.

The broad buffer structure of the N ⁻ drift layer 2101 is formed by adjusting the flow rate of phosphine gas containing phosphorus. Specifically, the flow rate of the phosphine gas is reduced so that the portion of the N ⁻ drift layer 2101 in contact with the collector buffer layer 2103 has a doping concentration of 6 × 10 ¹³ atoms / cm ³ . In the subsequent growth process, the flow rate of the phosphine gas is continuously increased so that the peak of the doping concentration becomes 2 × 10 ¹⁴ atoms / cm ³ . Thereafter, the flow rate of the phosphine gas is continuously decreased so that the doping concentration becomes 6 × 10 ¹³ atoms / cm ³ . It should be noted that the growth rate and gas flow rate are controlled so that the portion where the doping concentration reaches a peak is 50 μm deep from the surface of the N ⁻ drift layer 2101.

Next, a thermal oxide film having a thickness of 8000 mm is formed on the surface of the N ⁻ drift layer 2101. The thermal oxide film is patterned, and the edge termination portion is opened by wet etching. Next, boron ions are implanted into the edge termination portion at a dose of 1 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 100 keV. Then, heat treatment is performed at 1150 ° C. for 200 minutes to drive in to form a guard ring structure. Thereafter, the active portion is opened by wet etching while leaving the thermal oxide film at the edge termination portion, and a gate insulating film 2106 having a thickness of 605 mm is grown.

Next, a polysilicon film having a thickness of 10 μm is formed and patterned. Subsequently, an Al-1% Si film is formed by 5 μm sputtering, and patterning etching is performed to form an emitter electrode 2105. Subsequently, after irradiating an electron beam with an acceleration voltage of 4.6 MeV and an irradiation energy of 300 kGy, heat treatment is performed at 350 ° C. for 1 hour. Finally, a metal film is formed on the surface of the P ⁺ collector layer 2104 in the order of aluminum, titanium, nickel, and gold to form a collector electrode 2109, thereby completing the semiconductor device shown in the sectional view 2400 of FIG. A characteristic diagram 2410 in FIG. 24 is a net doping concentration profile corresponding to the semiconductor device in the cross-sectional view 2400.

  FIG. 25 is a diagram illustrating a turn-off waveform of the semiconductor device and the conventional IGBT according to the fourth embodiment. In FIG. 25, the collector current Ic and the collector-emitter voltage Vc of the semiconductor device according to the fourth embodiment are indicated by solid lines. Further, the collector current Ic and the collector-emitter voltage Vc of the conventional IGBT are shown by a one-dot chain line. The thickness of the drift layer of the semiconductor device according to the fourth embodiment is equal to the thickness of the drift layer of the conventional IGBT. In the semiconductor device according to the fourth embodiment, the oscillation phenomenon is suppressed as compared with the conventional IGBT.

As described above, the semiconductor device according to the fourth embodiment can suppress the oscillation phenomenon at the turn-off that is likely to occur due to the thin N ⁻ drift layer as compared with the conventional IGBT. For this reason, in the semiconductor device according to the fourth embodiment, the broad buffer layer can be made thinner as compared with the conventional IGBT, and the turn-off loss and the conduction loss can be reduced.

  As described above, according to the IGBT according to the present invention, the broad buffer structure has the effect that the reverse recovery loss can be reduced and the soft recovery characteristic can be obtained most efficiently. In addition, when an FZ wafer is used, and since there is no epitaxial growth process, there is an effect that it is significantly cheaper than the conventional one. Further, in the first and second embodiments, proton irradiation and heat treatment for forming a broad buffer structure are performed before the wafer is ground and thinned, so that the wafer is cracked during these processes. Can be prevented.

  Further, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, various values such as dimensions, concentrations, voltage values, current values, processing conditions such as temperature and time described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is N-type and the second conductivity type is P-type. However, in the present invention, the first conductivity type is P-type and the second conductivity type is N-type. It holds.

  The present invention is not limited to the 1200 V class, and can be similarly applied to a withstand voltage class of 600 V, 1700 V, or higher. For example, in the 600V class, the specific resistance of the wafer is 20 to 90 Ωcm, and the final thickness is 50 to 70 μm. In the case of the 1700 V class, the specific resistance of the wafer is 80 to 200 Ωcm, and the final thickness is 120 to 200 μm. Further, the present invention is not limited to the trench gate structure but can be similarly applied to a planar gate structure.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for power semiconductor devices, and in particular, IGBT modules and IPMs (intelligent power) that take into consideration environmental problems with low electrical loss and radiated electromagnetic noise. Module).

FIG. 3 is a diagram illustrating a configuration, net doping concentration, and proton distribution of the semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment; FIG. 3 is a diagram showing a wafer concentration profile by proton irradiation and heat treatment at 350 ° C. in the first embodiment. FIG. 3 is a diagram illustrating a turn-off waveform of the semiconductor device according to the first embodiment and a conventional IGBT. It is a figure which shows the structure of a snubberless circuit. It is explanatory drawing which shows the change of the internal state at the time of turn-off of the semiconductor device concerning Embodiment 1 by device simulation. It is explanatory drawing which shows the change of the internal state at the time of turn-off of conventional IGBT by device simulation. FIG. 6 is a diagram showing a configuration, net doping concentration, and proton distribution of a semiconductor device according to a second embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment; FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment; FIG. 6 is a diagram illustrating a configuration and net doping concentration of a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment; FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment; It is a figure which shows the structure and net doping concentration of the semiconductor device which applied this invention to the epitaxial wafer. It is a figure which shows the structure and net doping density | concentration of the non punch through type IGBT to which this invention is applied. It is a figure which shows the structure and net doping density | concentration of reverse conducting IGBT which applied this invention. It is a figure which shows the example of application of IGBT concerning this invention. It is a figure which shows the example of application of IGBT concerning this invention. It is a figure which shows the example of application of IGBT concerning this invention. FIG. 6 is a diagram illustrating a configuration of a semiconductor device according to a fourth embodiment and a net doping concentration. FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment; FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment; FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment; It is a figure which shows the turn-off waveform of the semiconductor device concerning Embodiment 4, and conventional IGBT. It is a figure which shows the density | concentration profile of the wafer by the conventional proton irradiation and the heat processing at 350 degreeC.

Explanation of symbols

1 N ⁻ drift layer 2 P base layer 3 collector buffer layer 4 P collector layer 5 emitter electrode 6 gate insulating film 7 gate electrode 8 N ⁺ source region 9 collector electrode

Claims (11)

A first conductivity type drift layer, a second conductivity type base layer selectively formed on the first main surface side of the first conductivity type drift layer, and selectively formed on the surface of the second conductivity type base layer A first insulating type source region, a gate insulating film in contact with a portion of the second conductive type base layer sandwiched between the first conductive type drift layer and the first conductive type source region, and the gate insulating film; Formed on the second main surface side of the first conductivity type drift layer; a MOS gate structure comprising a gate electrode in contact; an emitter electrode in contact with the first conductivity type source region and the second conductivity type base layer; A semiconductor device comprising: a second conductivity type collector layer; and a collector electrode in contact with the second conductivity type collector layer,
In the first conductivity type drift layer, there is at least one place where the impurity concentration of the first conductivity type drift layer becomes maximum, and from the place where the impurity concentration of the first conductivity type drift layer becomes maximum. Lower toward both the second conductivity type base layer and the second conductivity type collector layer;
Furthermore, oxygen atoms and hydrogen atoms are included in the first conductivity type drift layer at least where the impurity concentration of the first conductivity type drift layer is maximized,
In the first conductivity type drift layer, at least a portion where the impurity concentration of the first conductivity type drift layer becomes a maximum, a composite donor derived from the oxygen atom and the hydrogen atom is used as the first conductivity type impurity at the location. A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a first conductivity type buffer layer provided between the first conductivity type drift layer and the second conductivity type collector layer.   The semiconductor device according to claim 2, wherein the first conductivity type buffer layer has a composite donor derived from the oxygen atom and the hydrogen atom as the first conductivity type impurity.   3. The semiconductor device according to claim 2, wherein an impurity concentration of the first conductivity type buffer layer is greater than five times an average impurity concentration of the first conductivity type drift layer. In manufacturing the semiconductor device according to any one of claims 1 to 4,
Introducing oxygen into a first conductivity type semiconductor substrate to be the first conductivity type drift layer;
A step in which the irradiated on the first major surface or second major surface of the semiconductor substrate charged particles ionized, introducing crystal defects on the first conductive type drift layer in the semiconductor substrate,
A part of the first conductivity type drift layer is formed by performing a heat treatment to recover a crystal defect introduced into the first conductivity type drift layer and forming a composite donor resulting from the oxygen atom and the hydrogen atom. A step of making the net doping concentration of the semiconductor substrate higher than the initial net doping concentration of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the ionized charged particles are protons.   The range of the charged particles from the first main surface or the second main surface of the semiconductor substrate that irradiates the charged particles is such that the impurity concentration of at least the first conductivity type drift layer in the first conductivity type drift layer is the same. The method for manufacturing a semiconductor device according to claim 5, wherein the maximum local area is equal to a distance from the main surface to be irradiated.   The method for manufacturing a semiconductor device according to claim 5, wherein the heat treatment is performed in a hydrogen atmosphere. The method for manufacturing a semiconductor device according to claim 5 , further comprising a step of grinding the second main surface of the semiconductor substrate. A first conductivity type drift layer, a second conductivity type base layer selectively formed on the first main surface side of the first conductivity type drift layer, and selectively formed on the surface of the second conductivity type base layer A first insulating type source region, a gate insulating film in contact with a portion of the second conductive type base layer sandwiched between the first conductive type drift layer and the first conductive type source region, and the gate insulating film; Formed on the second main surface side of the first conductivity type drift layer; a MOS gate structure comprising a gate electrode in contact; an emitter electrode in contact with the first conductivity type source region and the second conductivity type base layer; A second conductivity type collector layer, a first conductivity type buffer layer provided between the first conductivity type drift layer and the second conductivity type collector layer, and a collector in contact with the second conductivity type collector layer And a semiconductor device comprising: Te,
The first conductivity type drift layer formed by epitaxial growth is provided on the first main surface side of the second conductivity type collector layer formed by epitaxial growth,
The impurity concentration of the first conductivity type buffer layer is greater than five times the average impurity concentration of the first conductivity type drift layer, and the thickness of the second conductivity type collector layer is the same as that of the first conductivity type drift layer. Thicker than the thickness of the region where the impurity concentration is higher than the average impurity concentration of the first conductivity type drift layer,
In the first conductivity type drift layer, there is at least one place where the impurity concentration of the first conductivity type drift layer becomes maximum, and from the place where the impurity concentration of the first conductivity type drift layer becomes maximum. A semiconductor device characterized by being lowered toward both the second conductivity type base layer and the second conductivity type collector layer. The thickness of the region containing the portion where the impurity concentration of the first conductivity type drift layer becomes maximum is according to claim 10, wherein greater than 5 times the thickness of the first conductivity type buffer layer Semiconductor device.

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