JP5395568B2 - Digitally controlled oscillator - Google Patents

Description

  The present invention relates to a digitally controlled oscillator (DCO) and a TDC (Time to Digital Converter) used in an All-digital type PLL (ADPLL).

  Usually, the ADPLL includes a TDC that converts the phase difference between the oscillation signal output from the DCO and the reference signal into a digital value. A conventional TDC includes, for example, a delay stage composed of cascaded inverters as shown in Patent Document 1 (see particularly FIG. 5). The TDC quantizes the phase difference between the oscillation signal and the reference signal with a unit delay amount provided by each of the inverters that constitute these delay stages. Therefore, the conventional TDC requires the number of delay stages corresponding to the minimum value of the variable frequency of the DCO (that is, the maximum value of the variable period). In addition, since ADPLL standardizes and uses decimal phase information, it is necessary to quantize the period of an oscillation signal with a unit delay amount every time frequency control is executed. Further, the conventional ADPLL differentiates both pieces of information with a differentiator in order to avoid spurious due to the time difference between the detection timing of the integer phase information from the counter and the detection timing of the fractional phase information from the TDC. Then compare the phases.

JP 2002-76886 A

  In order to use the conventional TDC in ADPLL, a delay stage, a differentiator, a circuit for quantizing the period of the oscillation signal with a unit delay amount, and the like are required. If such a redundant configuration can be reduced, a reduction in circuit area and power consumption can be expected.

  Therefore, an object of the present invention is to provide a DCO that can reduce a redundant configuration related to TDC.

  A DCO according to one embodiment of the present invention includes a ring oscillator in which an odd number of three or more single-phase inverters whose delay amount is controlled by a digital control signal are connected in a ring shape, and an output signal of the odd number of single-phase inverters A counter that counts one rising edge or falling edge and outputs a count value; a first flip-flop that holds the count value at the rising edge or falling edge of the reference signal and outputs it as integer phase information; Buffer each output signal of the single-phase inverter and output each as a first differential signal, and the value of the first differential signal at the rising or falling edge of the reference signal And an odd number of second flip-flops that respectively output the second differential signals as the second differential signals, Continuous high-level values when odd sets of second differential signals output from several second flip-flops are input and the odd sets of second differential signals are arranged in order of phase progression Alternatively, an edge detector that outputs binary data indicating the end of successive low-level values, and the binary data is divided by the number of phases of the second differential signal of the odd set to output normalized decimal phase information And a normalizer.

  A DCO according to another aspect of the present invention includes a ring oscillator in which a plurality of differential amplifiers whose delay amounts are controlled by digital control signals are connected in a ring shape, and one rising edge of output signals of the plurality of differential amplifiers. Or a counter that counts falling edges and outputs a count value; a first flip-flop that holds the count value at the rising edge or falling edge of a reference signal and outputs it as integer phase information; and the plurality of differences Buffering each output signal of the dynamic amplifier, and holding a plurality of buffers each outputting as a first differential signal, and holding the value of the first differential signal at the rising edge or falling edge of the reference signal A plurality of second flip-flops each outputting a second differential signal, and the plurality of second flip-flops When a plurality of sets of second differential signals output from the drop are input and the plurality of sets of second differential signals are arranged in order of phase advance, a continuous high level value or a continuous low level value An edge detector that outputs binary data indicating the end; and a normalizer that divides the binary data by the number of phases of the second differential signal to obtain normalized fractional phase information.

  ADVANTAGE OF THE INVENTION According to this invention, DCO which can reduce the redundant structure regarding TDC can be provided.

1 is a block diagram showing a DCO according to a first embodiment. The timing chart of each signal in DCO of FIG. The timing chart of each signal in DCO of FIG. The timing chart of each signal in DCO of FIG. The timing chart of each signal in DCO of FIG. The timing chart of each signal in DCO of FIG. The block diagram which shows DCO which concerns on 2nd Embodiment. 6 is a timing chart of each signal in the DCO in FIG. 5. 6 is a timing chart of each signal in the DCO in FIG. 5. The block diagram which shows DCO which concerns on 3rd Embodiment. The timing chart of each signal in DCO of FIG. The block diagram which shows DCO which concerns on 4th Embodiment. The block diagram which shows the PLL circuit which concerns on 5th Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the DCO according to the first embodiment of the present invention includes single-phase inverters 101 to 105, buffers 111 to 115, D flip-flops 121 to 125, an edge detector 130, a counter 140, and a D flip-flop. 150, a normalizer 160, a subtractor 170, and a phase comparator 180.

  The single-phase inverters 101 to 105 are connected in a ring shape. These single-phase inverters 101 to 105 correspond to so-called ring oscillators. The ring oscillator is configured by annularly connecting an odd number (three or more) of single-phase inverters. Therefore, the single-phase inverters 101 to 105 may be replaced with three-stage or seven-stage or more single-phase inverters. Single-phase inverters 101-105 oscillate at a frequency determined by a digital control signal (not shown). In other words, the delay amount of each of the single-phase inverters 101 to 105 as the delay stage is controlled by the digital control signal. Single-phase inverters 101-105 output oscillation signals 11-15, respectively. The oscillation signals 11 to 15 have the same frequency although the phases are different from each other by 2π / 5. At least one of the oscillation signals 11 to 15 (for example, the oscillation signal 11) is output to the outside (for example, the outside of the ADPLL) as an output signal of the ring oscillator. The output signal (oscillation signal 11) of this ring oscillator is also input to the counter 140.

  Buffers 111 to 115 buffer oscillation signals 11 to 15 from single-phase inverters 101 to 105, respectively. One of the technical significances of buffering the oscillation signals 11 to 15 is to suppress waveform rounding caused by wiring capacitance between the ring oscillator and D flip-flops 121 to 125 described later. This technical significance is particularly significant with respect to a layout in which the wiring between the two becomes long. Further, the buffers 111 to 115 convert the oscillation signals 11 to 15 into differential signals. That is, the buffers 111 to 115 not only serve as normal buffers but also serve as single-phase / differential converters.

  Note that the buffers 111 to 115 input an input signal to a one-stage inverter, branch the output signal, and supply one to the one-stage inverter and the other to the two-stage inverter. However, this configuration is exemplary, and the configurations that can be used as the buffers 111 to 115 are not limited thereto.

  More specifically, the buffer 111 outputs an oscillation signal 21 having the same phase and frequency as the oscillation signal 11 and an oscillation signal 26 that is a reverse phase signal of the oscillation signal 21. The buffer 112 outputs an oscillation signal 28 having the same phase and frequency as the oscillation signal 12 and an oscillation signal 22 that is a reverse phase signal of the oscillation signal 28. The buffer 113 outputs an oscillation signal 23 having the same phase and frequency as the oscillation signal 13 and an oscillation signal 28 that is a reverse phase signal of the oscillation signal 23. The buffer 114 outputs an oscillation signal 29 having the same phase and frequency as the oscillation signal 14 and an oscillation signal 24 that is a reverse phase signal of the oscillation signal 29. The buffer 115 outputs an oscillation signal 25 having the same phase and frequency as the oscillation signal 15 and an oscillation signal 30 that is a reverse phase signal of the oscillation signal.

  The D flip-flops 121 to 125 receive the differential signals from the preceding buffers 111 to 115 as input signals, and receive the reference signal 10 as a clock signal. That is, if the D flip-flops 121 to 125 are positive edge trigger flip-flops, they hold and output the differential signal value at the rising edge of the reference signal 10, and if they are negative edge trigger flip-flops, the falling edge of the reference signal 10 Holds and outputs the value of the differential signal at the edge. The D flip-flops 121 to 125 input differential signals to be output to the edge detector 130, respectively.

  More specifically, the D flip-flop 121 holds the value of the oscillation signal 21 at the rising edge or the falling edge of the reference signal 10 and inputs the value to the Q1 terminal of the edge detector 130, and detects this reverse phase signal as an edge detection. To the Q1b terminal of the device 130. The D flip-flop 122 holds the value of the oscillation signal 27 at the rising edge or the falling edge of the reference signal 10 and inputs the value to the Q2 terminal of the edge detector 130, and this reverse phase signal is input to the Q2b terminal of the edge detector 130. input. The D flip-flop 123 holds the value of the oscillation signal 23 at the rising edge or the falling edge of the reference signal 10 and inputs the value to the Q3 terminal of the edge detector 130, and this reverse phase signal is input to the Q3b terminal of the edge detector 130. input. The D flip-flop 124 holds the value of the oscillation signal 29 at the rising edge or the falling edge of the reference signal 10 and inputs the value to the Q4 terminal of the edge detector 130, and this reverse phase signal is input to the Q4b terminal of the edge detector 130. input. The D flip-flop 125 holds the value of the oscillation signal 25 at the rising edge or the falling edge of the reference signal 10 and inputs the value to the Q5 terminal of the edge detector 130, and this reverse phase signal is input to the Q5b terminal of the edge detector 130. input.

  The edge detector 130 is, for example, a psuedo thermo-decoder. The edge detector 130 detects a phase error between the reference signal 10 and the oscillation signal 11. More specifically, the edge detector 130 includes 10 input terminals Q1, Q2b, Q3, Q4b, Q5, Q1b, Q2, Q3b, Q4, and Q5b, and this order corresponds to the phase of the input signal. It corresponds to the order of progression. That is, the phase of the input signal to the Q1 terminal is most advanced, and the phase of the input signal to the Q5b terminal is most delayed. Note that the number of input terminals of the edge detector 130 depends on the number of stages of the ring oscillator. The edge detector 130 inspects a high level value (for example, “1”) or a low level value (for example, “0”) successively from Q1, and inputs binary data indicating the end to the normalizer 160. For example, the edge detector 130 outputs “3 (= 0011)” if Q3 is the end, and outputs “8 (= 1000)” if Q3b is the end.

Hereinafter, an operation example of the edge detector 130 will be described with reference to FIG.
In FIG. 2, timing charts of the oscillation signals 11 to 15 and 21 to 30 and the reference signal 10 are drawn. In FIG. 2, the oscillation signals 21, 27, 23, 29, and 25 are depicted as being synchronized with the oscillation signals 11, 12, 13, 14, and 15. There is a delay associated with the passage. According to the example of FIG. 2, the rising edge of the reference signal 10 is later than the rising edge of the oscillation signal 26 and earlier than the rising edge of the oscillation signal 27. The value of each oscillation signal 21 to 30 at the rising edge of the reference signal 10 is input to the edge detector 130. That is, 10 sets of binary signals “0”, “1”, “1”, “1”, “1”, “1”, “0”, “0”, “0”, “0” are edges. It is given to the ten input terminals mentioned above of the detector. Then, the edge detector 130 outputs “6 = (0110)” which is the end of the continuous “1”. This binary data means that the phase of the reference signal 10 is delayed by 6 unit delay amounts compared to the oscillation signal 11. That is, this binary data represents a phase error between the reference signal 10 and the oscillation signal 11. The unit delay amount here is the minimum phase difference (π / 5) in the oscillation signals 21 to 30.

  The counter 140 counts the rising edge or the falling edge of the oscillation signal 11 and inputs the count value to the D flip-flop 150. The D flip-flop 150 is clocked by the reference signal 10 (operates at the same timing as the D flip-flops 121 to 125 described above). The D flip-flop 150 inputs the count value of the counter 140 at the rising edge or falling edge of the reference signal 10 to the subtractor 170 as integer phase information.

  The normalizer 160 performs an operation for normalizing the binary data from the edge detector 130. As described above, the binary data represents the phase error between the reference signal 10 and the oscillation signal 11, but usually the fractional phase information is used in a standardized state in the ADPLL. Therefore, the normalizer 160 divides the binary data by the number of phases of the input signal of the edge detector 130 (10 in this example). Furthermore, in this example, the counter 140 counts the rising edge or the falling edge of the oscillation signal 11 before the rising edge or the falling edge of the reference signal 10 by “1”, so the normalizer 160 Further performs an operation of subtracting the division result from this “1”. In the example of FIG. 2, the normalizer 160 divides the binary data (6) by the number of phases (10) of the input signal of the edge detector 130 and subtracts the division result (0.6) from “1”. Then, the normalized decimal phase information ε (0.4) is obtained. The normalizer 160 inputs the normalized decimal phase information ε to the subtractor 170.

  The subtractor 170 subtracts the decimal phase information ε from the integer phase information to obtain the phase information 32. The subtractor 170 inputs the phase information 32 to the phase comparator 180. The phase comparator 180 compares the integer part and decimal part of the desired phase information 33 with the integer part and decimal part of the phase information 32 and outputs a comparison result. The comparison result is processed by a component of ADPLL (not shown) and used to adjust the digital control signal.

  Next, spurious that may occur in the DCO according to the present embodiment will be described with reference to FIGS. 3A and 3B. This spurious is caused by a delay difference between the input signals (oscillation signals 21 to 30) to the D flip-flops 121 to 125 and the input signal (count value 31) to the D flip-flop 150.

  3A and 3B are examples of timing charts of the oscillation signal 11, the count value 31, the oscillation signal 21, the reference signal 10, the phase information 32, and the desired phase information 33. FIG. In FIGS. 3A and 3B, ΔTb represents a delay time generated in the buffers 111 to 115 (similar to the delay time between the oscillation signal 11 and the oscillation signal 21), and ΔTc represents a delay time generated in the counter 140. (It is the same as the delay time between the oscillation signal 11 and the count value 31). That is, ΔTb represents the delay time from the output of the single-phase inverter 101 to the input of the D flip-flop 121, and ΔTc represents the delay time from the output of the single-phase inverter 101 to the input of the D flip-flop 150. Yes. In this example, ΔTc is assumed to be smaller than ΔTb. In this example, the DCO operates for the purpose of outputting an oscillation signal 11 whose frequency is four times that of the reference signal 10 and whose phase is synchronized (locked) with the reference signal 10.

  In FIG. 3A, the frequency of the oscillation signal 11 is four times that of the reference signal 10, but the phase is not synchronized and a phase error (ε = 0.4) occurs. Therefore, the phase information 32 increases like “0.6”, “4.6”, “8.6”. At this time, the decimal part of the phase information 32 is “0.6”. On the other hand, the decimal part of the desired phase information 33 is “0.0”. Therefore, the digital control signal is adjusted to increase the oscillation frequency of the DCO.

  When the oscillation frequency of the DCO increases, the timing chart changes as shown in FIG. 3B. As shown in FIG. 3B, even if the phase of the oscillation signal 11 (more precisely, the oscillation signal 21) is synchronized with the reference signal 10 (ε = 0.0), the oscillation signal 11 and the oscillation signal 21 (and the reference signal) There is a delay time of ΔTb between 10) and 10). As described above, ΔTc is smaller than ΔTb. That is, before the edge of the reference signal 10 is input to the D flip-flop 150, the count value 31 in which one extra edge of the oscillation signal 11 is counted is input to the D flip-flop 150. Therefore, the phase information 32 increases like “2.0”, “6.0”, “10.0”, and becomes “1.0” larger than the original phase information. Then, the digital control signal is adjusted so as to lower the oscillation frequency of the DCO again. Repeated adjustment of the digital control signal as described above causes spurious.

  Considering the spurious generation principle as described above, it is desirable that ΔTb is smaller than ΔTc. 4A and 4B show timing charts corresponding to FIGS. 3A and 3B. 4A and 4B are the same as FIG. 3A and FIG. 3B except that ΔTb is smaller than ΔTc. As shown in FIG. 4B, when the phase of the oscillation signal 11 (more precisely, the oscillation signal 21) is synchronized with the reference signal 10 (ε = 0.0), the edge of the reference signal 10 is shifted to the reference signal 10 by Tb. The count value 31 is input to the D flip-flop 150 before the count value 31 is increased by the preceding edge of the oscillation signal 11. Therefore, the D flip-flop 150 can hold the count value 31 in which the edges of the oscillation signal 11 are correctly counted as shown in FIG. 3B. Therefore, the phase information 32 increases correctly like “1.0”, “5.0”, “10.0”. Since the phase information 32 matches the desired phase information 33, the digital control signal is not adjusted. The DCO outputs an oscillation signal 11 whose frequency is four times that of the reference signal 10 and whose phase is synchronized with the reference signal 10. Thus, by designing the DCO so that ΔTb is smaller than ΔTc, a mechanism (for example, a differentiator) for avoiding spurious becomes unnecessary.

  As described above, since the DCO according to the present embodiment can use the delay generated in the ring oscillator, the TDC can be used without separately providing a delay stage. In the DCO according to the present embodiment, since the period of the oscillation signal is a fixed value multiple of the unit delay amount (the number of stages of the ring oscillator × 2), a circuit for quantizing the period of the oscillation signal with the unit delay amount is provided. It is unnecessary. In addition, the DCO according to the present embodiment uses the fixed value as a divisor in the standardization of the fractional phase information output from the TDC. Therefore, the division process is simplified compared to the conventional method using the variable value as the divisor. it can. Therefore, according to the DCO according to the present embodiment, the redundant configuration related to TDC can be reduced.

(Second Embodiment)
As shown in FIG. 5, the DCO according to the second embodiment of the present invention has a configuration in which a buffer 290 is further provided between the single-phase inverter 101 and the counter 140 in the DCO according to the first embodiment described above. Equivalent to. In the following description, the same parts in FIG. 5 as those in FIG. 1 are denoted by the same reference numerals, and different parts will be mainly described.

  The buffer 290 buffers the oscillation signal 11 and inputs it to the counter 140. In the buffer 290, a delay similar to that of the buffers 111 to 115 described above occurs.

Hereinafter, the technical significance of providing the buffer 290 will be described with reference to FIGS. 6A and 6B.
As described in the first embodiment, from the viewpoint of avoiding spurious, the delay time between the oscillation signal 11 and the oscillation signal 21 is smaller than the delay time between the oscillation signal 11 and the count value 41. Is desirable. As shown in FIG. 6A, a delay time ΔTb similar to that of the buffers 111 to 115 occurs in the buffer 290. Therefore, the input timing of the oscillation signals 21 to 30 to the D flip-flops 121 to 122 and the input timing of the oscillation signal 11 to the counter 140 are approximately the same. The delay time ΔTc is further added until the oscillation signal 11 input to the counter 140 is reflected in the count value 41. Accordingly, the provision of the buffer 290 ensures that the delay time between the oscillation signal 11 and the oscillation signal 21 is smaller than the delay time between the oscillation signal 11 and the count value 41. Therefore, by providing the buffer 290, spurious can be avoided more reliably.

  As described above, the DCO according to the present embodiment is configured by further providing the buffer 290 before the counter 140 in the DCO according to the first embodiment described above. Therefore, according to the DCO according to the present embodiment, spurious can be avoided more reliably.

(Third embodiment)
As shown in FIG. 7, the DCO according to the third embodiment of the present invention includes differential amplifiers 301 to 304, buffers 311 to 314, D flip-flops 321 to 324, edge detector 330, counter 340, and D flip-flop. 350, a normalizer 360, a subtracter 370, and a phase comparator 380.

  The differential amplifiers 301 to 304 are annularly connected. These differential amplifiers 301 to 304 correspond to so-called ring oscillators. The ring oscillator can be configured by annularly connecting a plurality of differential amplifiers. Therefore, the differential amplifiers 301 to 304 may be replaced with a differential amplifier having three stages or less or five stages or more. The differential amplifiers 301 to 304 oscillate at a frequency determined by a digital control signal (not shown). In other words, the delay amount of each of the differential amplifiers 301 to 304 as the delay stage is controlled by the digital signal. The differential amplifiers 301 to 304 output normal phase oscillation signals 51p to 54p and negative phase oscillation signals 51n to 54n, respectively. The positive-phase oscillation signals 51p to 54p have the same frequency although the phases are different from each other by π / 4. The negative phase oscillation signals 51n to 54n are the negative phase signals of the normal phase oscillation signals 51p to 54p. At least one of the oscillation signals 51p to 54p and 51n to 54n (for example, the oscillation signal 51p) is output to the outside (for example, outside the ADPLL) as an output signal of the ring oscillator. The output signal (oscillation signal 51p) of this ring oscillator is also input to the counter 340.

  The buffers 311 to 315 buffer differential oscillation signals 51p, 51n to 54p, and 54n from the differential amplifiers 301 to 304, respectively, and output differential oscillation signals 61p, 61n to 64p, and 64n. One of the technical significance of buffering the oscillation signals 51p, 51n to 54p, 54n is to suppress waveform rounding caused by wiring capacitance between the ring oscillator and D flip-flops 321 to 324 described later. It is. This technical significance is particularly significant with respect to a layout in which the wiring between the two becomes long.

  The D flip-flops 321 to 324 receive the differential signal from the preceding buffers 311 to 314 as an input signal and the reference signal 60 as a clock signal. That is, if the D flip-flops 321 to 324 are positive edge trigger flip-flops, the differential signal value at the rising edge of the reference signal 60 is held and output, and if the D flip-flops 321 to 324 are negative edge trigger flip-flops, the reference signal 60 falls. Holds and outputs the value of the differential signal at the edge. The D flip-flops 321 to 324 input differential signals to be output to the edge detector 330, respectively.

  More specifically, the D flip-flop 321 holds the value of the oscillation signal 61p at the rising edge or the falling edge of the reference signal 60 and inputs the value to the Q1 terminal of the edge detector 330, and detects the reverse phase signal as an edge detection. To the Q1b terminal of the device 330. The D flip-flop 322 holds the value of the oscillation signal 62p at the rising edge or the falling edge of the reference signal 60 and inputs the value to the Q2 terminal of the edge detector 330, and this reverse phase signal is input to the Q2b terminal of the edge detector 330. input. The D flip-flop 323 holds the value of the oscillation signal 63p at the rising edge or the falling edge of the reference signal 60 and inputs the value to the Q3 terminal of the edge detector 330, and this reverse phase signal is input to the Q3b terminal of the edge detector 330. input. The D flip-flop 324 holds the value of the oscillation signal 64p at the rising edge or the falling edge of the reference signal 60 and inputs the value to the Q4 terminal of the edge detector 330, and this reverse phase signal is input to the Q4b terminal of the edge detector 330. input.

  The edge detector 330 detects a phase error between the reference signal 60 and the oscillation signal 51p. More specifically, the edge detector 330 has eight input terminals Q1, Q2, Q3, Q4, Q1b, Q2b, Q3b, and Q4b, and this order corresponds to the order of the phase of the input signal. ing. That is, the phase of the input signal to the Q1 terminal is most advanced, and the phase of the input signal to the Q4b terminal is most delayed. Note that the number of input terminals of the edge detector 330 depends on the number of stages of the ring oscillator. The edge detector 330 inspects a high level value (for example, “1”) or a low level value (for example, “0”) sequentially from Q1, and inputs binary data indicating the end to the normalizer 360. For example, the edge detector 330 outputs “3 (= 0011)” if Q3 is the end, and outputs “7 (= 0111)” if Q3b is the end.

Hereinafter, an operation example of the edge detector 330 will be described with reference to FIG.
In FIG. 8, timing charts of the oscillation signals 51p, 51n to 54p, 54n, 61p, 61n to 64p, 64n and the reference signal 60 are drawn. In FIG. 8, the oscillation signals 61p, 61n to 64p, and 64n are drawn so as to be synchronized with the oscillation signals 51p, 51n to 54p, and 54n. Has occurred. According to the example of FIG. 8, the rising edge of the reference signal 60 is later than the rising edge of the oscillation signal 61n and earlier than the rising edge of the oscillation signal 62n. The values of the oscillation signals 61p, 61n to 64p, 64n at the rising edge of the reference signal 60 are input to the edge detector 330. That is, eight sets of binary signals “0”, “1”, “1”, “1”, “1”, “0”, “0”, “0” are the above-described eight of the edge detector 330. To the input terminal. Then, the edge detector 330 outputs “5 = (0101)” which is the end of the continuous “1”. This binary data means that the phase of the reference signal 60 is delayed by 5 unit delay amounts compared to the oscillation signal 51p. That is, the binary data represents a phase error between the reference signal 60 and the oscillation signal 51p. Here, the unit delay amount is the minimum phase difference (π / 4) in the oscillation signals 61p, 61n to 64p, 64n.

  The counter 340 counts the rising edge or the falling edge of the oscillation signal 51 p and inputs the count value to the D flip-flop 350. The D flip-flop 350 is clocked by the reference signal 60 (operates at the same timing as the D flip-flops 321 to 324 described above). The D flip-flop 350 inputs the count value of the counter 340 at the rising edge or falling edge of the reference signal 60 to the subtractor 370 as integer phase information.

  The normalizer 360 performs an operation for normalizing the binary data from the edge detector 330. Specifically, like the normalizer 160 described above, the normalizer 360 divides the binary data by the number of phases of the input signal of the edge detector 330 (8 in this example). Further, the normalizer 360 further performs an operation of subtracting the division result from “1”. In the example of FIG. 8, the normalizer 360 divides the binary data (5) by the number of phases (8) of the input signal of the edge detector 330 and subtracts the division result (0.625) from “1”. Then, the normalized decimal phase information ε (0.375) is obtained. The normalizer 360 inputs the normalized decimal phase information ε to the subtractor 370.

Incidentally, if the number of stages of the ring oscillator is a power of 2 (for example, 2 ² ), the number of phases of the input signal of the edge detector 330 is also a power of 2 (for example, 2 ³ ). If this condition is satisfied, the normalizer 360 can realize the division by a bit shift operation. That is, the normalizer 360 may shift the binary data to the right by the power (for example, 3) corresponding to the number of phases of the input signal of the edge detector 330.

  The subtractor 370 subtracts the fractional phase information ε from the integer phase information to obtain phase information. The subtractor 370 inputs the phase information to the phase comparator 380. The phase comparator 380 compares the integer part and decimal part of the desired phase information with the integer part and decimal part of the phase information, and outputs the comparison result. The comparison result is processed by a component of ADPLL (not shown) and used to adjust the digital control signal.

  As described above, from the viewpoint of avoiding spurious, it is desirable that the delay time between the oscillation signal 51p and the oscillation signal 61p is smaller than the delay time between the oscillation signal 51p and the count value of the counter 340. That is, it is desirable that the delay time generated in the buffers 311 to 314 is smaller than the delay time generated in the counter 340. By designing the DCO to satisfy this condition, a mechanism (for example, a differentiator) for avoiding spurious becomes unnecessary.

  As described above, since the DCO according to the present embodiment can use the delay generated in the ring oscillator, the TDC can be used without separately providing a delay stage. In the DCO according to the present embodiment, since the period of the oscillation signal is a fixed value multiple of the unit delay amount (the number of stages of the ring oscillator × 2), a circuit for quantizing the period of the oscillation signal with the unit delay amount is provided. It is unnecessary. In addition, the DCO according to the present embodiment uses the fixed value as a divisor in the standardization of the fractional phase information output from the TDC. Therefore, the division process is simplified compared to the conventional method using the variable value as the divisor. it can. Further, if the number of stages of the ring oscillator is set to a power of 2 in the DCO according to the present embodiment, the division in the normalizer 360 can be easily realized by a bit shift operation. In addition, since the DCO according to the present embodiment has a ring oscillator formed by a differential amplifier, the symmetry of the waveform of the oscillation signal and the common-mode noise rejection ratio are higher than when the ring oscillator is formed by a single-phase inverter. Therefore, according to the DCO according to the present embodiment, the redundant configuration related to TDC can be reduced.

(Fourth embodiment)
As shown in FIG. 9, the DCO according to the fourth embodiment of the present invention includes a buffer 490 between the non-inverting output terminal of the differential amplifier 301 and the counter 340 in the DCO according to the third embodiment described above. Further, this corresponds to the provided configuration. In the following description, the same parts in FIG. 9 as those in FIG. 7 are denoted by the same reference numerals, and different parts will be mainly described.

  The buffer 490 buffers the oscillation signal 51p and inputs it to the counter 340. In the buffer 490, a delay similar to that of the buffers 311 to 315 described above occurs. Providing the buffer 490 ensures that the delay time between the oscillation signal 51p and the oscillation signal 61p is smaller than the delay time between the oscillation signal 51p and the count value of the counter 340. Therefore, by providing the buffer 490, spurious can be avoided more reliably.

  As described above, the DCO according to the present embodiment is configured by further providing the buffer 490 before the counter 340 in the DCO according to the third embodiment described above. Therefore, according to the DCO according to the present embodiment, spurious can be avoided more reliably.

(Fifth embodiment)
A PLL circuit can be configured using the DCO according to the first to fourth embodiments described above. FIG. 10 shows a PLL circuit using the DCO 500 according to the fourth embodiment. The PLL circuit of FIG. 10 includes a DCO 500, a digital low-pass filter (LPF) 510, and a loop gain control unit 520. The DCO 500 corresponds to the DCO in FIG. In the following description, the same parts in FIG. 10 as those in FIG. 9 are denoted by the same reference numerals, and different parts will be mainly described.

  The phase comparator 380 compares the integer part and decimal part of the desired phase information with the integer part and decimal part of the phase information, and inputs the phase difference information to the digital LPF 510.

  The digital LPF 510 receives the reference signal 60 as a clock signal and receives the phase difference information from the phase comparator 380 as an input signal. The digital LPF 10 performs filter processing on the phase difference information in the digital domain. By this filtering process, the noise component mixed in the phase difference information is suppressed.

  The loop gain control circuit 520 receives the reference signal 60 as a clock signal and receives phase difference information from the digital LPF 510 as an input signal. The loop gain control circuit 520 generates a digital control signal by performing bit shift processing, integration processing, and the like on the phase difference information. The loop gain control circuit 520 supplies digital control signals to the differential amplifiers 301 to 304, respectively. This digital control signal controls the delay amount (that is, the frequency of the ring oscillator) of each of the differential amplifiers 301 to 304, the loop band of the PLL circuit in FIG. 10, the loop order, and the like.

  In the negative feedback loop formed by the PLL circuit of FIG. 10, a digital control signal is generated based on the phase difference information output from the DCO 500, and the DCO 500 is controlled by this digital control signal. By repeating this negative feedback loop, the phase difference between the reference signal 60 and the oscillation signal 51p is reduced stepwise.

  As described above, the PLL circuit according to the present embodiment includes the DCO according to the first to fourth embodiments described above. Therefore, according to the PLL circuit according to the present embodiment, the same effects as those of the first to fourth embodiments described above can be obtained.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.

10 ... reference signal 11-15, 21-30 ... oscillation signal 31,41 ... count value 32,42 ... phase information 33 ... desired phase information 51p, 51n-54p, 54n, 61p , 61n to 64p, 64n ... oscillation signal 60 ... reference signal 101 to 105 ... single phase inverter 111 to 115, 290, 311 to 314, 490 ... buffer 121 to 125, 150, 321 to 324 , 350 ... D flip-flop 130, 330 ... Edge detector 140, 340 ... Counter 160, 360 ... Normalizer 170, 370 ... Subtractor 180, 380 ... Phase comparator 301-304 ... Differential amplifier 500 ... DCO
510: Digital low-pass filter 520: Loop gain control unit

Claims (5)

A ring oscillator in which an odd number of three or more single-phase inverters that oscillate at a frequency determined by a digital control signal are connected in a ring shape;
A counter that counts one rising edge or falling edge of the output signals of the odd number of single-phase inverters and outputs a count value;
A first flip-flop that holds the count value at the rising edge or the falling edge of the reference signal and outputs it as integer phase information;
An odd number of buffers for buffering the output signals of each of the single-phase inverters and outputting them as first differential signals;
An odd number of second flip-flops that hold the value of the first differential signal at the rising edge or the falling edge of the reference signal and respectively output as a second differential signal;
When the odd-numbered second differential signals output from the odd-numbered second flip-flops are input and the odd-numbered second differential signals are arranged in the order of phase advance, the continuous high level An edge detector that outputs information indicating the end of a value or successive low-level values;
A normalizer that divides the information by the number of phases of the odd-numbered second differential signal and outputs normalized fractional phase information ;
A digitally controlled oscillator comprising: a subtractor that obtains phase information by subtracting the decimal phase information from the integer phase information .   The amount of delay until each output signal of the odd number of single-phase inverters is input to the odd number of second flip-flops is such that one of the output signals of the odd number of single-phase inverters is the first value. 2. The digitally controlled oscillator according to claim 1, wherein the delay amount is smaller than a delay amount until the signal is input to the flip-flop. A ring oscillator that oscillates at a frequency determined by a digital control signal , and in which multiple differential amplifiers are connected in a ring,
A counter that counts one rising edge or falling edge among output signals of the plurality of differential amplifiers and outputs a count value;
A first flip-flop that holds the count value at the rising edge or the falling edge of the reference signal and outputs it as integer phase information;
A plurality of buffers for buffering each output signal of the plurality of differential amplifiers and outputting each as a first differential signal;
A plurality of second flip-flops which hold the value of the first differential signal at the rising edge or the falling edge of the reference signal and respectively output as a second differential signal;
When a plurality of sets of second differential signals output from the plurality of second flip-flops are input, and the plurality of sets of second differential signals are arranged in order of phase advance, a continuous high level value Or an edge detector that outputs information indicating the end of successive low level values;
A normalizer that divides the information by the number of phases of the second differential signal to obtain normalized fractional phase information ;
A digitally controlled oscillator comprising: a subtractor that obtains phase information by subtracting the decimal phase information from the integer phase information . The number of phases of the plurality of sets of second differential signals is a power of two;
The information is binary data;
The digitally controlled oscillator according to claim 3, wherein the normalizer performs bit division by shifting the binary data by a power corresponding to the number of phases of the plurality of sets of second differential signals.   The amount of delay until each output signal of the plurality of differential amplifiers is input to the plurality of second flip-flops is one of the output signals of the differential amplifier input to the first flip-flop. The digitally controlled oscillator according to claim 3, wherein the digitally controlled oscillator is smaller than an amount of delay until a predetermined time.

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