JP5382988B2 - Method for forming a metal wiring structure - Google Patents

Description

  The present invention relates to an integrated circuit (IC) manufacturing method, and more particularly, to an integrated circuit manufacturing method having a metal wiring layer therein.

  A conventional integrated circuit manufacturing method uses a metal damascene process to form a multilayer metal wiring layer on a semiconductor substrate. As shown in FIGS. 1A-1C, the conventional method may include forming a first insulating layer 14 on a semiconductor substrate 10 having a trench insulating region 12 therein. The first insulating layer 14 can be formed directly on the surface of the substrate 10 to provide a degree of passivation to the lower device structure (eg, the gate electrode 13). The first insulating layer 14 may be patterned using a photo etching process to define a plurality of contact holes 15 therein. As shown, the density of the contact holes 15 can vary depending on the position on the substrate 10. After forming the contact hole 15, a blanket layer 16 of a first conductive material (eg, tungsten (W)) can be conformally formed on the first insulating layer.

As shown in FIG. 1B, the blanket layer 16 is planarized for a sufficient time to expose the first insulating layer 14, and a plurality of first conductive vias such as reference numerals 16a, 16b, and 16c are formed. Can be limited. Such a planarization step is a conventional chemical mechanical polishing (hereinafter referred to as 'CMP') using a polishing apparatus with a slurry solution applied to the upper surface of the blanket layer 16 during polishing. Can be carried out by stage. In such a polishing process, excessive dishing of the first insulating layer 14 facing the portion of the substrate 10 having conductive vias having a relatively high density as shown by a reference numeral 16c may be caused by a dishing phenomenon. Thereafter, as shown in FIG. 1C, a second insulating layer 18 is formed on the structure of FIG. 1B and then patterned to define openings aligned with conductive vias such as 16a, 16b, 16c. it can. A blanket layer of a second conductive material (for example, copper (Cu) or tungsten (W)) can be conformally formed on the second insulating layer 18. Such a blanket layer can be planarized using CMP to define a plurality of second metal layers such as reference numerals 20a, 20b, 20c, and 20d. However, according to the prior art, due to excessive depression of the first insulating layer 14, the planarization of the second metal conductive material is a relatively wide metal line in which the adjacent conductive via 16c is electrically shorted. 20d formation may be invited. Such a relatively wide metal line 20d may exhibit metal defects (eg, metal line short circuit) that can seriously reduce the yield of the device after the back-end process steps are completed.
Korean Patent Publication No. 2005-0002426 Specification

  The technical problem to be solved by the present invention is to prevent a phenomenon in which adjacent conductive vias are electrically short-circuited due to planarization of a metal conductive material due to excessive depression of an insulating layer, and a back-end process step is performed. It is an object of the present invention to provide a method of forming a metal wiring structure that can reduce metal defects that can reduce the yield of the device after it has been completed.

  The technical problems of the present invention are not limited by the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

  One embodiment of the present invention for solving the technical problem includes a method of forming an integrated circuit device using stages of a metal damascene process. According to such an embodiment, the method comprises forming an insulating layer having a contact hole therein on a semiconductor substrate and forming a recess in the insulating layer located adjacent to the contact hole. . Next, the contact hole and the recess are filled with a first conductive material (for example, tungsten (W)). Then, at least one portion of the first conductive material in the contact hole is exposed. Such exposure is performed by etching back a portion of the insulating layer using the first conductive material in the contact hole and the recess as an etching mask. The first conductive material in the recess is removed to expose other portions of the insulating layer. Thereafter, the exposed portion of the first conductive material is covered with a second conductive material (eg, copper (Cu)), which is in direct contact with the exposed portion of the first conductive material. The wiring pattern including the first conductive material and the second conductive material is limited by the covering step. In particular, the covering step includes forming a metal layer directly on the exposed portion of the first conductive material, and planarizing the formed metal layer for a sufficient time to expose the insulating film. Can do.

  According to another embodiment of the present invention for solving the technical problem, the step of forming the recess in the insulating layer is performed using the layer formed with a pattern in the photolithography process as an etching mask. Etching a recess in the layer can be included. In this case, a step of forming a spin-on-glass (hereinafter referred to as “SOG”) layer inside the contact hole and above the insulating layer can be performed before the step of etching the recess portion. Following the step of forming the SOG layer, a step of forming an antireflection film on the SOG layer and a step of forming a photoresist (hereinafter referred to as 'PR') on the antireflection film are performed. Further, following the PR formation step, a step of patterning the PR layer and a step of etching the SOG layer using the PR layer on which the pattern is formed as an etching mask can be performed.

  According to yet another embodiment of the present invention for solving the technical problem, a method of forming an integrated circuit device using a metal damascene process step includes: an insulating layer having a contact hole in a semiconductor substrate; And forming a recess in the insulating layer located adjacent to the contact hole. The contact hole and the recess are filled with a first conductive material (for example, tungsten (W)). At least one portion of the first conductive material in the contact hole is exposed. Such exposure is performed by etching back one portion of the insulating layer using the first conductive material in the contact hole and the recess as an etching mask. Then, the first conductive material in the recess is removed to expose a further portion of the insulating layer. Thereafter, the exposed portion of the first conductive material and the first conductive material in the recess are covered with a second conductive material (for example, copper (Cu)), which is the first conductive material. Direct contact with exposed parts of the sex substance. The second conductive material is planarized for a sufficient time to remove the first conductive material in the recess, and the wiring pattern includes the first conductive material and the second conductive material. Limit. According to still another aspect of the present embodiment, the step of filling the contact hole and the recess portion using the first conductive material includes the step of filling the inside of the first contact hole and the first recess portion on the insulating layer. Forming a first conductive material extending inside the substrate, and planarizing the first conductive material for a sufficient period of time to expose the insulating layer, so that the conductive plug in the contact hole and the dummy in the recess are formed. Including defining a metal pattern.

  According to still another embodiment of the present invention for solving the technical problem, a method of forming an integrated circuit device includes a step of forming a first insulating layer on a semiconductor substrate and the first insulating layer. Forming a second insulating layer thereon. Next, a first contact hole is formed. Such a first contact hole extends through the first insulating layer and the second insulating layer. Next, a first recess is formed in the second insulating layer at a position adjacent to the first contact hole. Thereafter, the first contact hole and the first recess are filled with a first conductive material (for example, tungsten (W)). At least one portion of the first conductive material in the first contact hole is a portion of the second insulating layer using the first conductive material in the first contact hole and the first recess as an etching mask. It becomes exposed by etching back. The exposed portion of the first conductive material is covered with a second conductive material (for example, copper (Cu)), thereby limiting the wiring pattern. Such a wiring pattern includes a first conductive material and a second conductive material.

  According to still another embodiment of the present invention for solving the technical problem, the step of filling the first contact hole and the first recess portion with the first conductive material includes the second step. Forming a first conductive layer on the insulating layer extending to the inside of the first contact hole and the inside of the first recess. The first conductive layer is then planarized for a sufficient time to expose the second insulating layer. Such planarization includes planarizing the first conductive layer for a sufficient amount of time to limit the conductive plug in the first contact hole and the dummy metal pattern in the first recess. .

  In addition, before the covering step, the dummy metal pattern may be removed to expose another portion of the second insulating layer. In particular, the removing includes etching back a portion of the conductive plug in the first contact hole simultaneously with etching back the dummy metal pattern in the first recess. Alternatively, the covering step removes the dummy metal pattern by planarizing the metal layer for a sufficient time with the step of forming a metal layer (eg, copper metal layer) on the conductive plug and the dummy metal pattern, Exposing a further portion of the second insulating layer may be included.

  According to still another embodiment of the present invention for solving the technical problem, a method of forming an integrated circuit device includes forming a first insulating layer on a semiconductor substrate and on the first insulating layer. Forming an insulating dry etch stopper layer. Such an insulating dry etch stopper layer can have a relatively high dielectric constant compared to the first insulating layer. The second insulating layer is formed on the dry etch stopper layer, and the contact hole is formed to extend to the inside of the first insulating layer through the second insulating layer. The second insulating layer can have a relatively low dielectric constant compared to the dry etch stopper layer. Subsequently, a metal layer (for example, tungsten metal) is formed on the inner side of the contact hole and on the upper side of the second insulating layer. Such a metal layer is planarized for a sufficient time to expose the surface of the second insulating layer and to limit the metal plug within the contact hole. Next, the exposed surface of the second insulating layer is dry etched for a sufficient time to expose the surface of the dry etch stopper layer and the sidewalls of the metal plug extending from the dry etch stopper layer. The metal plug is then planarized using the dry etch stopper layer as a planarization stopper layer. Thereafter, the third insulating layer can be formed on the flattened metal plug and the dry etch stopper layer. Additionally, a second contact hole can be formed extending through the third insulating layer to expose the planarized metal plug.

  In this embodiment, the step of planarizing the metal layer may include CMP of the metal layer with a first polishing pad pressure. However, in order to reduce the possibility of 'dishing phenomenon' in the dry etch stopper layer, the step of planarizing the metal plug is a step of CMPing the metal plug with a second polishing pad pressure lower than the first polishing pad pressure. Can be included. Also, such a planarization process reduces the overall dielectric constant of the dry etch stopper layer and the third insulating layer, and reduces as much as possible the parasitic capacitance associated with the overlapping metal regions that can be electrically coupled to the metal plug. So that the dry etch stopper layer is made thin enough.

  According to still another embodiment of the present invention for solving the technical problem, the step of forming an insulating dry etch stopper layer on the first insulating layer includes about 200 to about 200 μm on the first insulating layer. Forming an insulating dry etch stopper layer having a thickness of 300 mm. In such a case, planarizing the metal plug can also include planarizing the dry etch stopper layer to a final thickness of about 100 to 200 inches. This dry etch stopper layer can be formed of silicon nitride, amorphous silicon carbide or SiCN, or a combination thereof.

  According to still another embodiment of the present invention for solving the technical problem, a step of forming a first insulating layer on a semiconductor substrate and forming a second insulating layer on the first insulating layer. Including a method of forming a metal wiring structure by steps. The second insulating layer and the first insulating layer are selectively etched sequentially to define a contact hole therein. Then, a first metal layer (for example, tungsten (W)) is formed. The first metal layer extends over the second insulating layer and inside the contact hole. Next, the first metal layer is patterned to expose the second insulating layer. The second insulating layer is selectively etched for a sufficient time to expose the first insulating layer and expose the metal plug in the contact hole. Such a selective etching step is performed using the patterned first metal layer as an etching mask. The seam in the exposed metal plug is then filled with a conductive filler material. A second metal layer is formed on the exposed metal plug containing a conductive filler material.

  According to still another embodiment of the present invention for solving the technical problem, the filling step includes filling a seam in the exposed metal plug using CoWP (Cobalt tungsten phosphor). The pattern forming step may include a step of forming an antireflection film on the first metal layer and a step of forming a PR layer on the antireflection film. The PR layer is then patterned. The antireflection film and the first metal layer are sequentially etched using the patterned PR layer as an etching mask.

  Yet another method of forming the metal wiring structure may include forming an insulating layer on the substrate and selectively etching the insulating layer to define contact holes therein. The first metal layer is formed inside the contact hole and defines a metal plug therein. The insulating layer is then etched back to expose the metal plug. The seam in the exposed metal plug is filled with a conductive filler material, and a second metal layer (eg, a copper layer) is formed on the exposed metal plug. Such a second metal layer can be flattened to limit the metal wiring including the metal plug. A step of forming a barrier metal layer on the exposed metal plug can be performed prior to the step of forming the second metal layer. Such a barrier metal layer can be made of tantalum (Ta) and / or tantalum nitride (TaN).

  As described above, the present invention can prevent a phenomenon in which adjacent conductive vias are electrically short-circuited due to planarization of a metal conductive material due to excessive depression of an insulating layer, and a back-end process step is completed. Metal defects (e.g., metal wire shorts) that can reduce the yield of subsequent devices can be reduced.

  Hereinafter, the present invention will be described in more detail with reference to the drawings showing preferred embodiments of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms. The present embodiment is intended to complete the disclosure of the present invention, and to those skilled in the art. The present invention is provided to fully inform the scope of the invention, and the present invention should be determined based on the description of the claims. In the drawings, the thickness and area of each layer are exaggerated for clarity. If a layer is to be on another layer or substrate, it may be directly on the other layer or substrate, with an intermediate layer in between. Note that the same reference numerals denote the same components throughout the specification.

  Referring to FIG. 2A, the method for forming a metal wiring layer according to an embodiment of the present invention includes forming a first insulating layer 114 on a semiconductor substrate 110. As shown, the semiconductor substrate 110 can be an integrated circuit substrate having a plurality of trench isolation regions 112 therein and a plurality of device structures 113 (eg, gate electrodes) thereon. The first insulating layer 114 may be made of silicon dioxide having a thickness of about 2,000 to 4,000 mm, but the insulating layer 114 may be less than 2,000 mm or 4,000 mm. It is also possible to have the above thickness. Next, the first insulating layer 114 is covered with the second insulating layer 118. Such a second insulating layer 118 may be an electrically insulating material having a relatively low dielectric constant, such as SiCOH or SiLK® which is an aromatic hydrocarbon polymer having a dielectric constant of about 2.65. It can be formed by depositing a material. The second insulating layer 118 can have a thickness of about 1,500 to 2,000 mm, but can also have other thicknesses. Next, the first insulating layer 114 and the second insulating layer 118 are each patterned to define a plurality of contact holes 117 therein. Such a contact hole 117 etched using a mask (not shown) made for a photoetching process extends completely through the first insulating layer 114, and / or the upper surface of the semiconductor substrate 110 and / or One or more device structures 113 can be exposed.

  Referring to FIG. 2B, a SOG layer 120 is conformally applied to fill the plurality of contact holes 117 and uniformly coat the upper surface of the second insulating layer 118. As can be appreciated by those skilled in the art, the SOG layer 120 can be used to obtain high surface flatness so that high-precision photoetching process steps can be performed sequentially. Such high-precision photolithography process steps may include sequentially forming a low temperature oxide (hereinafter referred to as 'LTO') layer 122 and an anti-reflective coating 124. Next, a PR (photoresist) layer can be formed and patterned to define a PR mask 126 of the opposite shape. Such a mask 126 can be formed to have an opening extending so as to face a part of the upper surface of the second insulating layer 118, but these are adjacent to each other so as to approach the contact hole 117.

  As shown in FIG. 2C, an anti-reflection film 124, an LTO layer 122, an SOG layer 120, and a second layer are formed by performing an etching step (for example, active ion etching (hereinafter referred to as 'RIE')). A plurality of recesses 128 can be defined in the upper surface of the second insulating layer 118 by selectively etching sequentially through the upper surface of the insulating layer 118. Such a recess 128 may have a depth of about 500 to 1,000 inches. 2D to 2E, the contact hole 117 and the recess 128 are filled with the first conductive material. In particular, the metal blanket layer 130 (eg, tungsten (W)) can be conformally formed on the upper side of the second insulating layer 118 and on the inner side of the contact hole 117. Such a metal blanket layer 130 may have a thickness of about 1,000 to 5,000 inches. The metal blanket layer 130 is then planarized by CMP of the metal blanket layer 130 for a sufficient amount of time to expose the top surface of the second insulating layer 118, and thus a plurality of conductive layers in the contact hole 117. The plurality of dummy metal patterns 132b and the plurality of dummy metal patterns 132b can be defined in the plurality of recesses 128, respectively.

  Referring to FIG. 2F, an active ion etching (RIE) step is performed to make the exposed portion of the second insulating layer 118 directional using the conductive plug 132a and the dummy metal pattern 132b as an etching mask. Etch back. As shown, such an RIE step can be performed for a sufficient amount of time to expose (and possibly etch back) the top surface of the first insulating layer 114. Thereafter, as shown in FIG. 2G, a second metal blanket layer (eg, copper (Cu)) is formed on the structure shown in FIG. 2F, followed by planarization (eg, using CMP) for a sufficient amount of time. The dummy metal pattern 132b is removed, and the portion of the second insulating layer 118 thereunder is exposed. The second metal blanket layer can have a thickness of about 4,000 to 9,000 inches. The portion of the second insulating layer 118 extending between the adjacent metal plugs 132a serves to electrically insulate adjacent metal wiring patterns. Each such wiring pattern includes a respective conductive plug 132a having a covering metal pattern 134 (eg, a copper cap) made from a second metal layer. Thereafter, a process and packaging step (not shown) may be performed to complete an integrated circuit device having one or more metallization layers formed from the process steps described herein.

  According to yet another embodiment of the invention, the steps shown and described with respect to FIGS. 2F-2G can be replaced with FIGS. 3A-3B. In particular, FIG. 3A illustrates performing an RIE step in which the exposed portion of the second insulating layer 118 is etched back in a directional manner using the conductive plug 132a and the dummy metal pattern 132b as an etching mask. Yes. Thereafter, an additional etching step (dry or wet etching) is performed to etch back (ie, shorten) the conductive plug 132a and remove the dummy metal pattern 132b. As shown in FIG. 3B, a second metal blanket layer (eg, copper (Cu)) is formed on the structure shown in FIG. 3A and then planarized (eg, using CMP) for a sufficient amount of time. Then, the portion of the second insulating layer 118 underneath is exposed. The portion of the second insulating layer 118 extending between the adjacent conductive plugs 132a serves to electrically insulate each adjacent metal wiring pattern. Each such wiring pattern includes a respective conductive plug 132a having a covering metal pattern 134 (eg, a copper cap) resulting from the second metal layer.

  Yet another embodiment of the present invention includes a method of forming a metal wiring structure on a semiconductor substrate. Such a metal wiring structure includes a metal plug shown by FIGS. 4A to 4E. In particular, FIG. 4A shows a step of forming an insulating dry etch stopper layer 216 on the first insulating layer after the first insulating layer 214 is formed. The second insulating layer 218 is formed on the dry etch stopper layer 216. The first insulating layer 214 and the second insulating layer 218, which may include the same material or other materials, may be formed of, for example, a USG (Undoped Silicate Glass) or BPSG (borophosphosilicate glass) layer. Such an insulating layer can be formed using a technique such as HDP (High Density Plasma), PECVD (Plasma Enhanced CVD), or SACVD (Semi-Atmospheric CVD). Further, the first insulating layer 214 can be formed on a semiconductor substrate such as the substrate 110 shown in FIGS. 2A to 2G. Then, a plurality of contact holes 217 are formed. Such a contact hole 217 extends to the inside of the first insulating layer 214 through the second insulating layer 218 as shown. Thereafter, a metallized blanket layer 220 (eg, tungsten metal) is conformally formed above the second insulating layer 218 and inside the contact hole 217.

  Referring to FIG. 4B, the metal layer 220 is planarized for a sufficient time to expose the upper surface of the second insulating layer 218, and a plurality of metal plugs 220a and 220b are formed inside the contact hole 217. limit. As shown, the planarization of the metal layer 220 can cause dishing (D) in the second insulating layer 218 if the density of the metal plugs is sufficiently high. Thereafter, as shown in FIG. 4C, the exposed surface of the second insulating layer 218 is dry etched for a sufficient time to extend the surface of the dry etch stopper layer 216 and the metal plugs 220a, 220b extending from the dry etch stopper layer 216. Expose the side wall.

  Next, as shown in FIG. 4D, the metal plugs 220a and 220b are planarized, and the dry etch stopper layer 216 is used as a planarization stopper layer. Thereafter, as shown in FIG. 4E, a third insulating layer 230 is formed on the planarized metal plugs 220a and 220b and the dry etch stopper layer 216. The third insulating layer 230 is patterned using a photolithography process to define a plurality of contact holes 232 exposing the corresponding lower metal plugs 220a and 220b.

According to yet another aspect of the embodiment shown in FIGS. 4A-4E, planarizing the metal layer 220 includes CMPing the metal layer 220 with a first polishing pad pressure, and the metal plugs 220a, 220b. The step of planarizing includes CMP of the metal plugs 220a and 220b with a second polishing pad pressure lower than the first polishing pad pressure. In particular, CMPing the metal layer 220 with a first polishing pad pressure comprises polishing the metal layer 220 with a polishing slurry containing SiO ₂ at a pad pressure of about 3 psi and a pad rotation speed of about 20 rpm to 100 rpm. Can be included. Additionally, CMPing the metal plug with a second polishing pad pressure comprises polishing the metal plug with a polishing slurry comprising SiO ₂ at a pad pressure of about 1 psi and a pad rotation speed of about 20 rpm to 100 rpm. Can be included.

  The soft planarization of the metal plug described later can also make the dry etch stopper layer 216 sufficiently thin (without substantial dishing), thereby reducing the overall dielectric constant of the dry etch stopper layer 216 and the third insulating layer 230. Accordingly, the parasitic capacitance related to the overlapped metal region that can be electrically coupled to the metal plugs 220a and 220b can be reduced.

  In addition, according to another embodiment of the present invention, the step of forming the insulating dry etch stopper layer 216 may include forming an insulating dry etch stopper layer having a thickness of about 200 to 300 on the first insulating layer 214. Forming 216. In this case, the step of planarizing the metal plugs 220a and 220b may include the step of planarizing the dry etch stopper layer 216 having a thickness of about 100 to 200 mm, thereby reducing the parasitic capacitance. it can. According to still another embodiment of the present invention, forming the insulating dry etch stopper layer 216 includes forming silicon nitride, amorphous silicon carbide or SiCN, or a combination thereof on the first insulating layer 214. including.

Referring to FIGS. 5A to 5J, another method of forming a metal wiring structure is to form a first insulating layer 310 and a second insulating layer 312 on a main surface of a substrate 300 shown as a semiconductor substrate. including. The first insulating layer 310 can be formed of silicon dioxide (SiO ₂ ) having an initial thickness of about 6,000 mm and can be polished to a thickness of about 3,500 mm to remove uneven surfaces. For example, the second insulating layer 312 may be formed of a carbon-doped silicon oxide (SiOC) layer having a thickness of about 1,350 mm. In still other embodiments, the first insulating layer 310 can be a USG or BPSG layer using techniques such as HDP, PECVD, or SACVD. The second insulating layer 312 can be formed of an FSG (Fluorine doped Silica Glass) layer. According to still another embodiment, the first insulating layer and the second insulating layer may be formed of the same material.

  As shown in FIG. 5B, the first insulating layer 310 and the second insulating layer 312 can be patterned using a photoetching process to define a contact hole 314 therein. In one embodiment of the present invention, the contact hole 314 may expose the main surface of the substrate 300. In still other embodiments, the contact hole may extend only partially through the first insulating layer 310. As shown in FIG. 5C, the first metal layer 316 is then disposed on the upper side of the second insulating layer 312 and inside the contact hole 314. Such a first metal layer 316 may comprise a tungsten (W) layer having a thickness of about 2500 mm. In some cases, the conformally formed first metal layer 316 may form a metal seam 317 extending vertically inside the contact hole 314.

  Referring to FIG. 5D, the first metal layer 316 defines the first metal layer 316a having a smooth and smooth main surface. Such planarization of the first metal layer 316 may include etching back the first metal layer 316 using, for example, RIE techniques, or CMPing the first metal layer 316. Thereafter, an antireflection film 318 can be formed on the metal layer 316a. The antireflection film 318 can be formed of a SiON layer having a thickness of about 1,000 mm. As shown in FIG. 5E, the selectively used anti-reflective coating 318 allows the PR layer 320 patterned with a photolithography process to be precisely made. As shown in FIG. 5F, the antireflection film 318a and the metal layer having the pattern are formed by selective etching of the antireflection film 318 and the metal layer 316a. The metal layer on which such a pattern is formed includes a metal region 316b and a metal plug 316c. Also, an expanded seam 317 is created by selective etching with respect to the metal layer 316a.

  Referring to FIG. 5G, the second insulating layer 312 (and the patterned antireflection film 318a) is selectively etched back for a sufficient time to expose the first insulating layer 310, and the pattern is The formed second insulating layer 312a is limited. During such an etching step, the patterned metal regions 316b together form a hard etch mask. As shown in FIG. 5H, the remaining metal hard mask 316b can be etched back to expose the second insulating layer 312a. The metal plug 316c can be a metal plug 316d having a seam 317 further etched away and exposed therein. Subsequently, such exposed seam 317 is filled with conductive filler material 322. Such filler material 322 can be added to the exposed seam 317 by selectively forming a CoWP layer. After filling the exposed seam 317 with conductive filler material 322, a blanket metal barrier layer (not shown) can be formed on the structure shown in FIG. 5H. Such a metal barrier layer can be formed of, for example, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, or a double layer containing tantalum and tantalum nitride. Referring to FIG. 5I, a second metal layer 324 is formed on the second insulating layer 312a patterned with the metal plug 316d. Such a second metal layer 324 may be formed of a copper (Cu) layer having a thickness of about 6,000 mm by electroplating. Referring to FIG. 5J, the second metal layer 324 is planarized for a sufficient time to expose the patterned second insulating layer 312a, thereby defining a plurality of wiring patterns 324a and 324b. The wiring pattern 324a is formed so as to be in direct contact with the metal plug 316d and the conductive filling material 322.

  In the drawings and specification, there have been described exemplary and preferred embodiments of the invention. Although specific terms have been used, they are intended to be used in a comprehensive and descriptive sense exclusively for the scope of the present invention as described in the claims and for limited purposes. is not.

It is sectional drawing of the intermediate structure which shows the conventional method of forming the metal wiring layer using a damascene process step. It is sectional drawing of the intermediate structure which shows the conventional method of forming the metal wiring layer using a damascene process step. It is sectional drawing of the intermediate structure which shows the conventional method of forming the metal wiring layer using a damascene process step. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an intermediate structure illustrating a method of forming a metal wiring layer according to an embodiment of the present invention. FIG. 2D is a cross-sectional view of an intermediate structure showing process steps alternative to those shown in FIGS. 2F-2G according to another embodiment of the present invention. FIG. 2D is a cross-sectional view of an intermediate structure showing process steps alternative to those shown in FIGS. 2F-2G according to another embodiment of the present invention. FIG. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention. FIG. 6 is a cross-sectional view of an intermediate structure showing a method of forming a metal wiring structure according to still another embodiment of the present invention.

Explanation of symbols

300 Substrate 310 First insulating layer 312, 312a Second insulating layer 314 Contact hole 316, 316a First metal layer 316b Metal region / metal hard mask 316c, 316d Metal plug 317 Seam 318, 318a Antireflection film 320 PR layer 322 conductive filling material 324 second metal layer 324a, 324b wiring pattern

Claims (16)

Forming a first insulating layer on a semiconductor substrate;
Forming a second insulating layer on the first insulating layer;
Selectively etching the second insulating layer and the first insulating layer sequentially to form a contact hole;
Etching the second insulating layer to form a plurality of recesses;
Forming a first metal layer extending on the second insulating layer and inside the contact hole and the recess ;
Patterning the first metal layer to expose the second insulating layer;
Using the first metal layer with the pattern formed as an etching mask, the second insulating layer is selectively etched to expose the first insulating layer so that a region corresponding to the recess remains. Forming an opening exposing the metal plug in the contact hole;
Filling a seam in the exposed metal plug with a conductive filler material; and forming a second metal layer filling the opening on the exposed metal plug filled with the conductive filler material. A method of forming a metal wiring structure comprising:   The method of claim 1, wherein filling the seam includes filling a seam in the exposed metal plug with CoWP. The patterning step comprises:
Forming an anti-reflective coating on the first metal layer;
Forming a PR layer on the antireflection film;
The method of claim 1, further comprising: patterning the PR layer; and sequentially etching the antireflection film and the first metal layer using the PR layer having the pattern as an etching mask. A method of forming the metal wiring structure described in 1. Metal wire according to claim 1, characterized in that it comprises the step of exposing the second insulating layer and planarizing the pre-Symbol second metal layer next to the step of forming the second metal layer A method of forming a structure.   The method of claim 1, wherein forming the second metal layer comprises electroplating a copper layer on the exposed metal plug. Forming an insulating layer on the substrate;
Selectively etching the insulating layer to form a contact hole;
Forming a metal plug having a seam to form a first metal layer on the inside said contact hole;
Etching back the insulating layer to expose the metal plug;
Etching back the metal plug to expand the area of the seam;
Filling a seam in the derived metal plug with a conductive filler material; and forming a second metal layer on the exposed metal plug. . 7. The metal wiring structure according to claim 6, further comprising the step of flattening the second metal layer to form a metal wiring structure including the metal plug after the step of forming the second metal layer. How to form. The first metal layer is tungsten;
The method of forming a metal wiring structure according to claim 6, wherein the second metal layer is copper.   The method of forming a metal wiring structure according to claim 6, wherein the conductive filling material includes CoWP.   7. The method of forming a metal wiring structure according to claim 6, wherein forming the second metal layer includes electroplating the second metal layer on the exposed metal plug. .   7. The method of claim 6, further comprising forming a barrier metal layer including tantalum and / or tantalum nitride on the exposed metal plug prior to forming the second metal layer. A method of forming a metal wiring structure. Forming a first insulating layer on a semiconductor substrate;
Forming a second insulating layer on the first insulating layer;
Selectively etching the first insulating layer and the second insulating layer sequentially to form a contact hole extending through the second insulating layer to the inside of the first insulating layer;
Forming a tungsten layer extending on the second insulating layer and inside the contact hole;
Forming a hard mask by patterning the tungsten layer;
Selectively etching the second insulating layer using the hard mask as an etching mask to expose a tungsten plug in the contact hole;
Filling the seam in the tungsten plug with CoWP; and forming a copper wiring pattern in contact with the tungsten plug. The step of forming the copper wiring pattern includes:
13. The method of forming a metal wiring structure according to claim 12, comprising: electroplating a copper layer on the tungsten plug; and CMPing the copper layer.   14. The method of forming a metal wiring structure according to claim 13, further comprising CMPing the tungsten layer before patterning the tungsten layer.   13. The method of forming a metal wiring structure according to claim 12, comprising CMP the tungsten layer before patterning the tungsten layer. Forming at least one insulating layer on the semiconductor substrate;
Selectively etching the at least one insulating layer to form a contact hole;
Forming a tungsten plug having a seam in the contact hole;
Selectively etching the at least one insulating layer to expose a portion of the tungsten plug in the contact hole;
Filling the seam in the tungsten plug with CoWP; and forming a copper wiring pattern on the tungsten plug including the seam to be filled.

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