JP5382048B2 - Differential signal failure detection apparatus and differential signal failure detection method - Google Patents

Description

  The present invention relates to capacitively coupled high-speed differential signal transmission, and more particularly to a differential signal failure detection device and the like for detecting a failure of the differential signal.

  Capacitive coupling is also called AC coupling. Known examples of capacitively coupled high-speed differential signal transmission include SAS and PCI-Express. SAS is a small computer system interface (SCSI) high-speed serial transmission standard. PCI-Express is a PCI (Peripheral Component Interconnect) high-speed serial transmission standard.

  FIG. 5 is a circuit diagram showing a high-speed differential signal transmission device in the related art. Hereinafter, description will be given based on this drawing.

  The high-speed differential signal transmission device 90 includes a transmission buffer 91, a reception buffer 92, transmission lines 93a and 93b, transmission-side AC coupling capacitors 94a and 94b, reception-side AC coupling capacitors 95a and 95b, a failure detection circuit 96, and the like. It is composed of Two signals A and B having opposite phases are transmitted to the transmission lines 93a and 93b, respectively. The transmission buffer 91 is provided at the transmission end of the transmission lines 93a and 93b, and transmits signals A and B. The reception buffer 92 is provided at the reception ends of the transmission lines 93a and 93b and receives the signals A and B. AC coupling capacitors 94a, 94b, 95a, and 95b are provided on the reception side and transmission side of transmission lines 93a and 93b, respectively, and block DC components included in signals A and B. The failure detection circuit 96 is provided on the output side of the reception buffer 92 and detects that a failure has occurred anywhere from the transmission buffer 91 to the reception buffer 92.

Japanese Patent Laid-Open No. 2003-167796 JP-A-8-43472

  However, in the related art, the failure is detected only by the failure detection circuit 96 ahead of the reception buffer 92. Therefore, even if a failure is detected, it has not been possible to determine whether the failure has occurred at the transmitting end or the receiving end.

  That is, in the related art high-speed differential signal transmission apparatus 90, the transmission end and the reception end are connected one-to-one, and a path failure (transmission error) can be detected only at the reception end. Therefore, it has not been possible to clearly determine whether the transmission end has caused a transmission error or the receiving end has caused a transmission error. As a result, the identification of the suspicion due to the transmission error, that is, the suspicion determination as to whether it is the transmitting end or the receiving end cannot be performed, and thus both are often exchanged.

  Further, Patent Documents 1 and 2 disclose a device for detecting a failure in a transmission line, but both have extremely complicated configurations.

  Accordingly, an object of the present invention is to provide a differential signal failure detection device and the like that can easily identify whether a failure location is a transmission end or a reception end.

The differential signal failure detection apparatus according to the present invention is
A differential signal failure detection device that detects a failure for the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
Waveform generating means for generating a waveform indicating the symmetry of the signal flowing through the first and second transmission lines;
An abnormality detecting means for detecting an abnormality of the waveform generated by the waveform generating means;
Failure determination means for determining a failure in the first and second transmission lines based on the abnormality detected by the abnormality detection means,
It is provided with.

The differential signal failure detection method according to the present invention includes:
A differential signal failure detection method for detecting a failure for the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
Generating a waveform indicative of symmetry of the signal flowing through the first and second transmission lines;
Detecting an abnormality in the generated waveform,
Determining a failure in the first and second transmission lines based on the detected abnormality;
It is characterized by that.

  According to the present invention, since the failure is detected in the middle of the transmission line by utilizing the breaking of the symmetry of the signal, it can be easily determined whether the failure point is the transmission end or the reception end.

1 is a circuit diagram showing a differential signal failure detection apparatus according to an embodiment of the present invention. 3 is a flowchart illustrating a differential signal failure detection method according to an embodiment of the present invention. It is a graph which shows the waveform at the time of normal of each signal in the differential signal failure detection apparatus of FIG. It is a graph which shows the waveform at the time of abnormality of each signal in the differential signal failure detection apparatus of FIG. It is a circuit diagram which shows the high-speed differential signal transmission apparatus in related technology.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the accompanying drawings.

  FIG. 1 is a circuit diagram showing a differential signal failure detection apparatus according to an embodiment of the present invention. Hereinafter, description will be given based on this drawing. In FIG. 1, the same reference numerals are used for the components shown in FIG.

  The differential signal failure detection apparatus 10 according to the present embodiment detects a failure in the first and second transmission lines 93a and 93b through which two signals A and B having opposite phases are transmitted. A generation unit 20, an abnormality detection unit 30, and a failure determination unit 40 are provided. The waveform generation means 20 generates a waveform (signal C) indicating the symmetry of the signals A and B flowing through the transmission lines 93a and 93b. The abnormality detection unit 30 detects an abnormality (signal E) in the waveform (signal C) generated by the waveform generation unit 20. The failure determination means 40 determines a failure in the transmission lines 93a and 93b based on the abnormality (signal E) detected by the abnormality detection means 30.

  Since the signals A and B at the normal time have opposite phases, they have a symmetrical waveform. If this symmetry is broken for some reason, the differential signal failure detection apparatus 10 determines that a failure has occurred in the transmission lines 93a and 93b. That is, it can be determined that the failure is not on the reception side but on the transmission side. If the failure detection circuit 96 outputs a signal indicating a failure (signal I) and the differential signal failure detection device 10 does not output a signal indicating a failure (signal H), it can be determined that the failure is on the receiving side. .

  For example, the waveform generation means 20 generates a superimposed waveform (signal C) of the signals A and B flowing through the transmission lines 93a and 93b as a waveform indicating symmetry. At this time, the abnormality detection unit 30 detects an abnormality of the superimposed waveform (signal C) by obtaining an integral value (signal E) of the superimposed waveform (signal C) generated by the waveform generation unit 20. The failure determination means 40 determines that a failure has occurred in the transmission lines 93a and 93b when the integrated value (signal E) obtained by the abnormality detection means 30 exceeds the threshold value Vth.

  Next, specific examples of each means will be described.

  The waveform generation means 20 includes a first resistor 21a that extracts a signal A that flows through the transmission line 93a, a second resistor 21b that extracts a signal B that flows through the transmission line 93b, and a signal A that is extracted from the resistor 21a. And an inductor 22 that generates a superimposed waveform (signal C) with the signal B extracted from the resistor 21b.

  The abnormality detection means 30 includes an operational amplifier 31 that outputs a difference voltage (signal D) corresponding to the difference between the voltage (signal C) corresponding to the superimposed waveform generated by the waveform generation means 20 and the reference voltage Vref, and the operational amplifier 31. It includes a diode 32 that outputs only the output differential voltage (signal D), and a capacitor 33 that is charged by the diode 32 and holds a voltage (signal E) corresponding to an integral value.

  The failure determination means 40 outputs a buffer 41 that outputs the magnitude relationship between the integral value (signal E) obtained by the abnormality detection means 30 and the threshold value Vth, and indicates that the integral value (signal E) has exceeded the threshold value Vth. Output a determination signal (signal H) indicating a failure and a discharge signal (signal G) for discharging the capacitor 33, and a discharge signal output from the determination unit 42. And a transistor 43 that discharges the capacitor 33 based on (signal G).

  Next, the connection relationship of each element will be described.

  The waveform generation means 20 includes resistors 21a and 21b, an inductor 22, a connection point 23, and a ground point 24. The resistor 21a has one end 211a connected to the transmission line 93a, and the resistor 21b has one end 211b connected to the transmission line 93b. The other end 212 a of the resistor 21 a and the other end 212 b of the resistor 21 b are connected to the connection point 23. The inductor 22 has one end 221 connected to the connection point 23 and the other end 222 connected to the ground point 24.

  The abnormality detection unit 30 includes an operational amplifier 31, a diode 32, a capacitor 33, and a ground point 34. The operational amplifier 31 has a voltage (corresponding to a difference between two input terminals 31+ and 31− that input a voltage at the connection point 23 (signal C) and a reference voltage Vref, and a voltage input from the input terminals 31+ and 31− ( An output terminal 312 for outputting a signal D). The diode 32 has an anode 321 connected to the output terminal 312. The capacitor 33 has one end 331 connected to the cathode 322 of the diode 32 and the other end 332 connected to the ground point 34.

  The failure determination unit 40 includes a buffer 41, a determination unit 42, a transistor 43, and a ground point 44. The buffer 41 has an input terminal 411 for inputting the integral value (signal E) obtained by the abnormality detection means 30, and an output terminal 412 for outputting a signal F indicating the magnitude relationship between the integral value (signal E) and the threshold value Vth. including. When the signal F is input from the output terminal 412 and the signal F indicates “signal E> threshold Vth”, the determination unit 42 outputs a determination signal (signal H) indicating a failure and discharges the capacitor 33. Discharge signal (signal G) is output. In the transistor 43, the gate 43 g receives a discharge signal (signal G), the drain 43 d is connected to one end 331 of the capacitor 33, and the source 43 s is connected to the ground point 44. The determination unit 42 can be realized by, for example, a buffer, a microcomputer, and its program.

  FIG. 2 is a flowchart showing a differential signal failure detection method according to an embodiment of the present invention. Hereinafter, the differential signal failure detection method of this embodiment will be described with reference to FIGS. 1 and 2.

  The differential signal failure detection method of the present embodiment captures the operation of the differential signal failure detection device 10 as a method invention, and has the same effects as the differential signal failure detection device 10. That is, the differential signal failure detection method of the present embodiment is a differential signal for detecting a failure in the first and second transmission lines 93a and 93b through which two signals A and B having opposite phases are transmitted. A fault detection method basically includes the following three steps. First, a waveform (signal C) indicating the symmetry of the signals A and B flowing through the transmission lines 93a and 93b is generated (step 51). Subsequently, an abnormality (signal E) in the generated waveform (signal C) is detected (step 52). Finally, a failure in the transmission lines 93a and 93b is determined based on the detected abnormality (signal E) (step 53).

  For example, in step 51, a superimposed waveform (signal C) of signals A and B flowing through the transmission lines 93a and 93b is generated as a waveform indicating symmetry. At this time, in step 52, an abnormality of the superimposed waveform (signal C) is detected by obtaining an integrated value (signal E) of the superimposed waveform (signal C) generated in step 51. In step 53, when the integrated value (signal E) obtained in step 52 exceeds the threshold value Vth, it is determined that a failure has occurred in the transmission lines 93a and 93b.

  Next, a specific example of each step will be described.

  In step 51, the signal A flowing through the transmission line 93a is taken out via the first resistor 21a, and the signal B flowing through the transmission line 93b is taken out via the second resistor 21b and taken out from the resistor 21a. A superimposed waveform (signal C) of the signal A and the signal B extracted from the resistor 21 b is generated via the inductor 22.

  In step 52, a differential voltage (signal D) corresponding to the difference between the voltage (signal C) corresponding to the superimposed waveform generated in step 51 and the reference voltage Vref is output via the operational amplifier 31 and output from the operational amplifier 31. Only the difference voltage (signal D) is output through the diode 32, the capacitor 33 is charged by the diode 32, and the voltage (signal E) corresponding to the integral value is held through the capacitor 33.

  In step 53, the magnitude relationship between the integral value (signal E) obtained in step 52 and the threshold value Vth is output via the buffer 41, and the buffer 41 outputs that the integral value (signal E) exceeds the threshold value Vth. In this case, a determination signal (signal H) indicating a failure is output via the determination unit 42, and a discharge signal (signal G) for discharging the capacitor 33 is output via the determination unit 42. The capacitor 33 is discharged through the transistor 43 on the basis of the discharge signal (signal G) output from.

  Hereinafter, the differential signal failure detection apparatus 10 of the present embodiment will be described in more detail.

  The differential signal failure detection apparatus 10 includes resistors 21a and 21b, an inductor 22, an operational amplifier 31, a diode 32, a capacitor 33, a buffer 41, a determination unit 42, a transistor 43, and the like.

  Resistors 21a and 21b have differential signal waveforms with respect to differential signal transmission lines 93a and 93b provided with transmission buffer 91, reception buffer 92, and AC coupling capacitors 94a, 94b, 95a, and 95b. It has a resistance value high enough not to affect it. The inductor 22 amplifies the superimposed waveform of the transmission lines 93a and 93b around the ground (ground) level. The operational amplifier 31 detects that the symmetry of the voltage amplitude of the differential signal is broken. The diode 32 and the capacitor 33 integrate the output of the operational amplifier 31. The buffer 41 converts the integrated potential into digital logic (1/0). The determination unit 42 determines from the output of the buffer 41 that a transmission error has occurred. The transistor 43 is a field effect transistor (FET), and discharges the electric charge accumulated in the capacitor 33 after the transmission error is determined by the determination unit 42.

  The differential signals (signals A and B) of the transmission lines 93a and 93b become a signal C through the resistors 21a and 21b and the inductor 22. The signal C is supplied to an inductor 22 as a low-pass filter that removes high-frequency components and a positive-side input terminal 31+ of the operational amplifier 31. The other of the inductors 22 is grounded. The negative input terminal 31- of the operational amplifier 31 is connected to a reference voltage Vref set to a level not affected by noise. The signal D output from the operational amplifier 31 is supplied to the anode 321 of the diode 32. A signal E output from the cathode 322 of the diode 32 is supplied to the capacitor 33, the input terminal 411 of the buffer 41, and the drain 43 d of the transistor 43. The other side of the capacitor 33 is grounded. The signal F output from the buffer 41 is supplied to the determination unit 42. The source 43s of the transistor 43 is grounded. A signal G is applied from the determination unit 42 to the gate 43 g of the transistor 43.

  FIG. 3 is a graph showing the normal waveforms of the signals A to F in the differential signal failure detection apparatus 10. FIG. 4 is a graph showing waveforms when signals A to F are abnormal in the differential signal failure detection apparatus 10. Hereinafter, the operation of the differential signal failure detection apparatus will be described in detail with reference to FIGS.

  FIG. 3 shows the waveforms of the signals A to F when operating normally, and FIG. 4 is a diagram showing the waveforms of the signals A to F when there is an abnormality (failure). The signals A to F are indicated with “1” as A1 to F1 when normal, and indicated with “2” as A2 to F2 when abnormal.

  First, the normal operation will be described with reference to FIG. The signals A1 and B1 output from the transmission buffer 91 have waveforms that are inverted from each other as illustrated. Since these signals A1 and B1 are wired through the resistors 21a and 21b, the signal C1 has a ground level waveform. The inductor 22 is a low-pass filter and has a role of removing a high-frequency component that is not required to be included in the signal C1. When the signal C1 is input to the positive side of the operational amplifier 31 and the reference voltage Vref set to a level not affected by noise is input to the negative side of the operational amplifier 31, the signal D1 output from the operational amplifier 31 is a waveform of the ground level. It becomes. Since the signal D1 is at the ground level, the signal E1 that is the charging voltage of the capacitor 33 is at the ground level, and the signal F1 output from the buffer 41 is at the low level.

  Next, the operation at the time of abnormality will be described with reference to FIG. Here, a case where the signal B2 is not output is taken as a failure example. At this time, since the signals A2 and B2 are wired through the resistors 21a and 21b, the signal C2 has a waveform like a sine wave. The inductor 22 is a low-pass filter and has a role of removing a high-frequency component that is not necessary for the signal C2. When the signal C2 is input to the positive side of the operational amplifier 31 and the voltage Vref that is not affected by noise is input to the negative side of the operational amplifier 31, the signal D2 output from the operational amplifier 31 has a waveform that is half-wave rectified. Become. The signal D <b> 2 flows from the anode 321 to the cathode 322 of the diode 32 and is charged in the capacitor 33. When the signal E reaches a threshold value Vth where the voltage is gradually increased, the buffer 41 outputs a high-level signal F. The determination unit 42 determines a transmission failure by detecting a high level signal F in the buffer 41. Further, since the electric charge charged in the capacitor 33 cannot be removed as it is, a discharging transistor 43 is provided. The determination unit 42 has a function of instructing a discharge to open the gate 43g of the transistor 43, thereby discharging the capacitor 33.

  According to the present embodiment, the failure is detected in the middle of the transmission lines 93a and 93b by using the symmetry breaking of the signals A and B, so it is easy to determine whether the failure location is the transmission end or the reception end. I can judge. In addition, since the suspected device can be specified, it is not necessary to replace both the transmitting end device and the receiving end device.

  Next, the present invention will be summarized. The present invention is a circuit for detecting a failure in the middle of a transmission line in a device using coupled high-speed balanced transmission. According to the present invention, in a device using capacitively coupled (AC coupled) high-speed differential signal transmission, a differential signal transmission line composed of an output buffer, an input buffer, and an AC coupling capacitor is provided in the middle. By providing a dynamic signal failure detection device, it is possible to detect when the balance is broken by utilizing the symmetry of the voltage amplitude of the differential signal. The differential signal failure detection apparatus of the present invention has means for detecting and determining when the balance is broken by utilizing the symmetry of the voltage amplitude of the differential signal. When a transmission error is detected by the differential signal failure detection device, it can be determined that there is a failure in the transmission line on the transmission end side.

  In other words, an object of the present invention is to provide a circuit that includes a failure detection circuit between a transmission end and a reception end and determines whether a failure location is a transmission end or a reception end. That is, the present invention is connected to a differential transmission line composed of an output buffer, an input buffer, and a coupling capacitor, a high-resistance resistor connecting the differential transmission lines, and a midpoint of the resistor, and the midpoint is grounded , An operational amplifier that detects a break in the symmetry of the voltage amplitude of the differential signal, a diode and an integrating capacitor that integrate the output of the operational amplifier, a determination unit that determines the integrated potential, and an FET that discharges after the determination It consists of. In the present invention, the middle point of the termination resistor is grounded via the inductor, and the abnormality is detected by amplifying and rectifying the voltage amplitude at the middle point in the hope that the signal obtained by combining the positive and negative signals will be at the ground level.

  The present invention has been described above with reference to the above embodiment, but the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. In addition, the present invention includes a combination of some or all of the configurations of the above embodiments as appropriate.

  Although a part or all of the above embodiments can be described as the following supplementary notes, the present invention is not limited to the following configurations.

[Appendix 1] A differential signal failure detection device for detecting a failure with respect to a first transmission line and a second transmission line through which two signals having opposite phases to each other are transmitted,
Waveform generating means for generating a waveform indicating the symmetry of the signal flowing through the first and second transmission lines;
An abnormality detecting means for detecting an abnormality of the waveform generated by the waveform generating means;
Failure determination means for determining a failure in the first and second transmission lines based on the abnormality detected by the abnormality detection means,
A differential signal failure detection apparatus comprising:

[Appendix 2] The differential signal failure detection apparatus according to Appendix 1,
The waveform generating means generates a superimposed waveform of the signal flowing through the first and second transmission lines as a waveform indicating the symmetry,
The abnormality detection means detects an abnormality of the superimposed waveform by obtaining an integral value of the superimposed waveform generated by the waveform generation means,
The failure determination means determines that a failure has occurred in the first and second transmission lines when the integral value obtained by the abnormality detection means exceeds a threshold value.
A differential signal failure detection apparatus.

[Appendix 3] The differential signal failure detection apparatus according to Appendix 2,
The waveform generating means includes
A first resistor for extracting a signal flowing in the first transmission line;
A second resistor for extracting a signal flowing in the second transmission line;
An inductor that generates a superimposed waveform of the signal extracted from the first resistor and the signal extracted from the second resistor;
Having
A differential signal failure detection apparatus.

[Appendix 4] The differential signal failure detection apparatus according to Appendix 2 or 3,
The abnormality detection means includes
An operational amplifier that outputs a difference voltage corresponding to a difference between a voltage corresponding to the superimposed waveform generated by the waveform generation means and a reference voltage;
A diode that outputs only the differential voltage output from this operational amplifier;
A capacitor charged by this diode and holding a voltage corresponding to the integral value;
Having
A differential signal failure detection apparatus.

[Appendix 5] The differential signal failure detection device according to any one of appendices 2 to 4,
The failure determination means includes
A buffer that outputs a magnitude relationship between the integral value and the threshold value obtained by the abnormality detection means;
When the buffer outputs that the integrated value exceeds the threshold value, the determination unit outputs a determination signal indicating a failure, and outputs a discharge signal for discharging the capacitor;
A transistor that discharges the capacitor based on the discharge signal output from the determination unit;
Having
A differential signal failure detection apparatus.

[Appendix 6] A differential signal failure detection method for detecting a failure with respect to first and second transmission lines through which two signals having opposite phases to each other are transmitted,
Generating a waveform indicative of symmetry of the signal flowing through the first and second transmission lines;
Detecting an abnormality in the generated waveform,
Determining a failure in the first and second transmission lines based on the detected abnormality;
And a differential signal failure detection method.

[Appendix 7] The differential signal failure detection method according to Appendix 6,
As a waveform indicating the symmetry, generating a superimposed waveform of the signal flowing through the first and second transmission lines,
When detecting an abnormality of the superimposed waveform, by detecting an integral value of the generated superimposed waveform, the abnormality of the superimposed waveform is detected,
When determining the failure in the first and second transmission lines, if the integral value obtained by the abnormality detection means exceeds a threshold value, a failure has occurred in the first and second transmission lines. To determine,
And a differential signal failure detection method.

[Appendix 8] A differential signal failure detection method according to appendix 7,
When generating the superimposed waveform,
While taking out the signal flowing through the first transmission line through the first resistor, taking out the signal flowing through the second transmission line through the second resistor,
A superimposed waveform of the signal extracted from the first resistor and the signal extracted from the second resistor is generated via an inductor.
And a differential signal failure detection method.

[Supplementary note 9] The differential signal failure detection method according to supplementary note 7 or 8,
When detecting the abnormality of the superimposed waveform,
A difference voltage corresponding to the difference between the voltage corresponding to the generated superimposed waveform and the reference voltage is output via an operational amplifier,
Only the differential voltage output from this operational amplifier is output via a diode,
A capacitor is charged by this diode, and a voltage corresponding to the integral value is held through the capacitor.
And a differential signal failure detection method.

[Supplementary note 10] The differential signal failure detection method according to any one of supplementary notes 7 to 9,
In determining a failure in the first and second transmission lines,
Output the magnitude relationship between the obtained integral value and the threshold value via a buffer,
When the buffer outputs that the integrated value has exceeded the threshold value, a determination signal indicating a failure is output via the determination unit, and a discharge signal for discharging the capacitor is output via the determination unit. Output,
Based on the discharge signal output from the determination unit, the capacitor is discharged through the transistor.
And a differential signal failure detection method.

[Appendix 11]
A first transmission line and a second transmission line through which two signals having opposite phases are transmitted;
A transmission buffer provided at a transmission end of each of the first and second transmission lines and transmitting the two signals;
A reception buffer provided at the receiving end of the first and second transmission lines, for receiving the two signals;
An AC coupling capacitor provided on the reception side and the transmission side of the first and second transmission lines, for blocking a DC component contained in the two signals;
A failure detection circuit that is provided on the output side of the reception buffer and detects that a failure has occurred somewhere from the transmission buffer to the reception buffer;
The differential signal failure detection device according to any one of supplementary notes 1 to 5 provided in the middle of the first and second transmission lines;
A high-speed differential signal transmission device comprising:

[Supplementary Note 12] A differential signal failure detection device for detecting a failure with respect to the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
When the symmetry of the voltage amplitude of the two signals is broken, it is determined that there is a failure in the first and second transmission lines.
A differential signal failure detection apparatus.

[Supplementary Note 13] A differential signal failure detection method for detecting a failure with respect to the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
When the symmetry of the voltage amplitude of the two signals is broken, it is determined that there is a failure in the first and second transmission lines.
And a differential signal failure detection method.

  The present invention can be used for high-speed differential signal transmission that transmits two signals having opposite phases to each other via two lines.

DESCRIPTION OF SYMBOLS 10 Differential signal failure detection apparatus 20 Waveform production | generation means 21a 1st resistor 21b 2nd resistor 22 Inductor 30 Abnormality detection means 31 Operational amplifier 32 Diode 33 Capacitor 40 Failure determination means 41 Buffer 42 Determination part 43 Transistor 90 High-speed differential Signal transmission device 91 Transmission buffer 92 Reception buffer 93a First transmission line 93b Second transmission line 94a, 94b, 95a, 95b AC coupling capacitor 96 Fault detection circuit

Claims (8)

A differential signal failure detection device that detects a failure for the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
Waveform generating means for generating a waveform indicating the symmetry of the signal flowing through the first and second transmission lines;
An abnormality detecting means for detecting an abnormality of the waveform generated by the waveform generating means;
Failure determination means for determining a failure in the first and second transmission lines based on the abnormality detected by the abnormality detection means,
Equipped with a,
The waveform generating means generates a superimposed waveform of the signal flowing through the first and second transmission lines as a waveform indicating the symmetry,
The abnormality detection means detects an abnormality of the superimposed waveform by obtaining an integral value of the superimposed waveform generated by the waveform generation means,
The failure determination means determines that a failure has occurred in the first and second transmission lines when the integral value obtained by the abnormality detection means exceeds a threshold value.
A differential signal failure detection apparatus. The differential signal failure detection device according to claim 1 ,
The waveform generating means includes
A first resistor for extracting a signal flowing in the first transmission line;
A second resistor for extracting a signal flowing in the second transmission line;
An inductor that generates a superimposed waveform of the signal extracted from the first resistor and the signal extracted from the second resistor;
Having
A differential signal failure detection apparatus. The differential signal failure detection device according to claim 1 or 2 ,
The abnormality detection means includes
An operational amplifier that outputs a difference voltage corresponding to a difference between a voltage corresponding to the superimposed waveform generated by the waveform generation means and a reference voltage;
A diode that outputs only the differential voltage output from this operational amplifier;
A capacitor charged by this diode and holding a voltage corresponding to the integral value;
Having
A differential signal failure detection apparatus. The differential signal failure detection device according to any one of claims 1 to 3 ,
The failure determination means includes
A buffer that outputs a magnitude relationship between the integral value and the threshold value obtained by the abnormality detection means;
When the buffer outputs that the integrated value exceeds the threshold, the determination unit outputs a determination signal indicating a failure, and outputs a discharge signal for discharging the capacitor;
A transistor that discharges the capacitor based on the discharge signal output from the determination unit;
Having
A differential signal failure detection apparatus. A differential signal failure detection method for detecting a failure for the first and second transmission lines through which two signals having opposite phases to each other are transmitted,
Generating a waveform indicative of symmetry of the signal flowing through the first and second transmission lines;
Detecting an abnormality in the generated waveform,
Determine a failure in the first and second transmission lines based on the detected abnormality,
As a waveform indicating the symmetry, generating a superimposed waveform of the signal flowing through the first and second transmission lines,
When detecting an abnormality of the superimposed waveform, by detecting an integral value of the generated superimposed waveform, the abnormality of the superimposed waveform is detected,
When determining the failure in the first and second transmission lines, if the integral value obtained by the abnormality detection means exceeds a threshold value, a failure has occurred in the first and second transmission lines. To determine,
And a differential signal failure detection method. The differential signal failure detection method according to claim 5 ,
When generating the superimposed waveform,
While taking out the signal flowing through the first transmission line through the first resistor, taking out the signal flowing through the second transmission line through the second resistor,
A superimposed waveform of the signal extracted from the first resistor and the signal extracted from the second resistor is generated via an inductor.
And a differential signal failure detection method. The differential signal failure detection method according to claim 5 or 6 ,
When detecting the abnormality of the superimposed waveform,
A difference voltage corresponding to the difference between the voltage corresponding to the generated superimposed waveform and the reference voltage is output via an operational amplifier,
Only the differential voltage output from this operational amplifier is output via a diode,
A capacitor is charged by this diode, and a voltage corresponding to the integral value is held through the capacitor.
And a differential signal failure detection method. A differential signal failure detection method according to any one of claims 5 to 7 ,
In determining a failure in the first and second transmission lines,
Output the magnitude relationship between the obtained integral value and the threshold value via a buffer,
When the buffer outputs that the integrated value has exceeded the threshold value, a determination signal indicating a failure is output via the determination unit, and a discharge signal for discharging the capacitor is output via the determination unit. Output,
Based on the discharge signal output from the determination unit, the capacitor is discharged through the transistor.
And a differential signal failure detection method.

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