JP5380984B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a multilayer wiring structure and its manufacture.

  In today's semiconductor integrated circuit devices, an enormous number of semiconductor elements are formed on a common substrate, and a multilayer wiring structure is used to interconnect them.

In a multilayer wiring structure, an interlayer insulating film in which a wiring pattern constituting a wiring layer is embedded is laminated.
In such a multilayer wiring structure, the lower wiring layer and the upper wiring layer are connected to each other by a via contact formed in the interlayer insulating film.

  Particularly in recent ultra-miniaturized and ultra-high-speed semiconductor devices, a low dielectric constant film (so-called low-k film) is used as an interlayer insulating film in order to alleviate the problem of signal delay (RC delay) in a multilayer wiring structure. At the same time, a low resistance copper (Cu) pattern is used as a wiring pattern.

  In such a multilayer wiring structure in which the Cu wiring pattern is embedded in the low dielectric constant interlayer insulating film, patterning by dry etching of the Cu layer is difficult, so that a wiring groove or a via hole is previously formed in the interlayer insulating film. The damascene method or dual damascene method is used. In the damascene method or the dual damascene method, the wiring trench or via hole formed in this way is filled with a Cu layer, and then an excessive Cu layer on the interlayer insulating film is removed by chemical mechanical polishing (CMP).

At that time, if the Cu wiring pattern is in direct contact with the interlayer insulating film, Cu atoms diffuse into the interlayer insulating film, causing problems such as short circuits. Therefore, the side wall surface of the wiring groove or via hole in which the Cu wiring pattern is formed In general, the bottom surface is covered with a conductive diffusion barrier, a so-called barrier metal film, and a Cu layer is deposited on the barrier metal film. As the barrier metal film, refractory metals such as tantalum (Ta), titanium (Ti), and tungsten (W), or conductive nitrides of these refractory metals are generally used.
JP 2004-289008 A JP 2003-257799 A

  1A to 1G show examples of forming a Cu wiring pattern by a typical damascene method.

  Referring to FIG. 1A, an interlayer insulating film 11 is formed on a substrate (not shown). A hard mask pattern 12 having an opening 12A is formed on the interlayer insulating film 11, and FIG. The structure shown is obtained.

  Next, the interlayer insulating film 11 is patterned using the hard mask pattern 12 as a mask. In the interlayer insulating film 11, a recess 11A serving as a wiring groove or a via hole is formed corresponding to the opening 12A. The structure shown in 1C is obtained.

  Next, the conductive diffusion barrier film 13 is continuously formed on the structure of FIG. 1C, typically by sputtering, so that the conductive diffusion barrier film 13 continues the hard mask pattern 12 and the side wall surface and bottom surface of the recess 11A. Then, the structure shown in FIG. 1D is obtained.

  Further, a Cu layer 14 is formed on the structure of FIG. 1D by sputtering and electrolytic plating, and the Cu layer 14 covers the conductive diffusion barrier film 13, the portion covering the hard mask pattern 12, and the side wall surface of the recess 11A. And the part which covers a bottom face is formed so that the said recessed part 11A may be filled and covered, and the structure of FIG. 1E is obtained.

  Next, the Cu layer 14 in the structure of FIG. 1D is removed by a chemical mechanical polishing (CMP) method until the hard mask pattern 12 is exposed, including the conductive diffusion barrier film 13 thereunder, and the openings. The structure shown in FIG. 1F in which 12A is filled with the Cu pattern 14A through the conductive diffusion barrier film 13 is obtained.

  Further, an insulating diffusion barrier film (cap film) 15 is formed on the structure of FIG. 1F so as to cover the Cu wiring pattern 14A and the hard mask pattern 12, and a next interlayer insulating film 16 is formed thereon. By doing so, the structure of FIG. 1G is obtained.

  In the wiring structure or multilayer wiring structure including the Cu wiring pattern 14A thus obtained, the diffusion of Cu atoms from the Cu wiring pattern 14A into the interlayer insulating film 11 is caused by the conductive diffusion barrier film 13 and the cap film 15. The problem of short circuit of wiring and generation of leakage current caused by diffusion of Cu atoms into the interlayer insulating film 11 or 16 is avoided.

  On the other hand, in such a structure, since the cap layer 15 is an insulating layer such as SiC or SiN, it is inevitable that defects occur at the interface with the Cu wiring pattern 14A that is a metal. When the wiring pattern 14A is energized, Cu atoms in the Cu wiring pattern 14A travel along such an interface, for example, as shown in FIG. 2, to the outside of the Cu wiring pattern by electromigration or stress migration. There is a risk of spreading. When such Cu atoms reach an adjacent similar Cu wiring pattern formed in the interlayer insulating film 11, a leakage current is generated.

  Further, when the resist pattern is used instead of the hard mask pattern 12 when forming the recess 11A, the hard mask pattern 12 does not exist, and the Cu atoms are directly connected to the interlayer insulating film 11 from the interface. It spreads inside.

According to one aspect, a semiconductor device includes a substrate, an insulating film formed on the substrate and having a recess defined by a sidewall surface and a bottom surface, and an upper end portion of the sidewall surface among the sidewall surfaces. A metal film that covers an upper first portion including the second insulating film so that the insulating film is exposed in a second portion below the first portion of the bottom surface of the concave portion and the side wall surface of the concave portion. A first diffusion barrier film that continuously covers the side wall surface and the bottom surface of the recess, and that covers the metal film in the first portion of the side wall surface; A copper wiring pattern filled via a diffusion barrier film, an insulating second diffusion barrier film covering the surface of the copper wiring pattern on the insulating film, the copper wiring pattern and the second diffusion barrier A concentrated region of metal elements formed at the interface with the film, and Enrichment region of the metal element, a metal element forming the metal film, seen containing a higher concentration than the copper wiring pattern in the metal element is selected from titanium, manganese, from the group consisting of zirconium and aluminum, The first diffusion barrier film is selected from the group consisting of a tantalum film, a manganese film, a tantalum nitride film, and a titanium nitride film, and the second diffusion barrier film is a carbide film or nitride film containing silicon .

The method of manufacturing a semiconductor device according to another aspect includes the steps of forming a recess in the insulation Enmaku, the metal film on the side wall surface of the concave portion, wherein the metal film is of said side wall, said side wall The upper first portion including the upper end portion is covered, and the insulating film is exposed in the second portion below the first portion of the bottom surface of the recess and the side wall surface of the recess. depositing, before Kize' edge film, forming a first diffusion barrier layer covering the sidewall surface and bottom surface of the concave portion continuously, a copper layer before Kize' edge film deposited, the concave portion, and the step of filling by the copper layer through the first diffusion barrier layer, before removing the copper layer on Kize' border membranes in the recess, by the copper layer a step of forming a copper pattern, before Kize' edge film, in contact with an upper surface of the copper pattern, to form a second diffusion barrier layer of insulating A step, heat treating the copper layer, the metal element forming the metal film, seen including and a step of rich fraction at the interface between the copper pattern and the second diffusion barrier layer, wherein the metal element The first diffusion barrier film is selected from the group consisting of a tantalum film, a manganese film, a tantalum nitride film, and a titanium nitride film, and the second diffusion barrier film is selected from the group consisting of titanium, manganese, zirconium, and aluminum. The film is a carbide film or nitride film containing silicon .

  According to the first and second aspects, the Cu wiring pattern filling the recess is formed on the upper side wall surface of the opening along the interface with the insulating diffusion barrier layer covering the Cu wiring pattern. A concentrated region is formed in which metal atoms diffused from the deposited metal film are concentrated. Such metal atoms are stably trapped by the defects present at the interface, and the Cu atoms in the Cu wiring pattern are prevented from diffusing outside the Cu wiring pattern through the defects. At this time, the metal film is formed so that the interlayer insulating film is exposed except for the upper portion including the upper end portion of the bottom surface and the side wall surface of the recess, thereby suppressing an increase in resistance of the Cu wiring pattern.

[First Embodiment]
The present inventor conducted a detailed analysis of elements distributed in the Cu wiring in the research which is the basis of the present invention. The following describes this study.

  FIG. 3 shows the configuration of the sample 20 of the Cu wiring pattern produced in the above research.

  Referring to FIG. 3, the sample 20 is formed on a silicon substrate 21 having a silicon oxide film 22 made of a thermal oxide film having a thickness of 100 nm, and a low dielectric constant film (on the silicon oxide film 22). A so-called low-K film), more specifically, an interlayer insulating film 23 made of SiOC is formed with a film thickness of about 500 nm. A hard mask layer 24 made of silicon carbide (SiC) having a thickness of, for example, 50 nm is formed on the interlayer insulating film 23 by, for example, a plasma CVD method, and the recess 23 is formed in the interlayer insulating film 23. It is formed with a width of 3000 nm and a depth of 800 nm by dry etching using the hard mask layer 24 as a mask.

  Further, in the sample 20 of FIG. 3, the metal film 25 made of titanium (Ti) continuously covering the side wall surface and the bottom surface of the recess 23T has a cross-sectional shape matched to the cross-sectional shape of the recess 23T and a film of about 20 nm. A first diffusion barrier film made of tantalum (Ta) or tantalum nitride (TaN) is formed on the metal film 25 so as to continuously cover the side wall surface and the bottom surface of the recess 23T. 26 is formed with a shape matching the cross-sectional shape of the metal film 25 and a film thickness of about 10 nm. The metal film 25 and the diffusion barrier film 26 are formed by sputtering.

  The recess 23T is filled with a Cu pattern 27 via the first diffusion barrier layer 26, and the upper surface of the Cu pattern 27 is formed to a thickness of, for example, 50 nm so as to cover the hard mask layer 24. And an insulating second diffusion barrier film 28 made of SiC. The Cu pattern 27 is formed by forming a Cu seed layer by sputtering, forming a Cu layer thereon by electrolytic plating, and then removing the Cu layer by CMP until the hard mask layer 24 is exposed. It is formed by the method.

  The second diffusion barrier film 28 is formed by a plasma CVD method at a temperature of 350 ° C. or more and 400 ° C. or less, and a second interlayer insulating film 29 is formed on the second diffusion barrier film 28 by a plasma CVD method or It is formed by a coating method. Note that when the diffusion barrier layer 28 is formed and also when the interlayer insulating film 29 is formed by plasma CVD, the Cu pattern 27 is subjected to heat treatment in a temperature range of 350 ° C. to 400 ° C. In the case of the sample 20 of FIG. 3, after the formation of the second diffusion barrier film 28, the Cu wiring pattern 27 is subjected to a heat treatment at a temperature of 400 ° C. for 60 minutes.

  The inventor of the present invention uses a high-precision Auger analyzer for the cross section surrounded by the broken line R in FIG. 4 in the structure of FIG. And analyzed. However, in FIG. 4, the same reference numerals are assigned to portions corresponding to the portions described above.

  As shown in FIG. 4, the cross section is obtained by obliquely cutting the Cu wiring pattern 27, a part of the Cu wiring pattern 27, a part of the first diffusion barrier film 26, and one part of the metal film 25. And a part of the second diffusion barrier film 28. The lower part of the Cu wiring pattern 27 is not included.

  FIG. 5 shows the measurement results obtained by the high-precision Auger analyzer. In FIG. 5, each point represents the detection of Ti atoms. In FIG. 5, lines A1-A2, A3, and A4 correspond to the auxiliary lines shown in FIG.

  5 shows that originally Ti was not introduced into the upper end portion of the Cu wiring pattern 27, that is, the interface between the Cu wiring pattern 27 and the second diffusion barrier film 28. It can be seen that Ti atoms are concentrated in the region along the auxiliary line A1-A2 and are deposited at a high concentration.

  On the other hand, in FIG. 5, the concentration of Ti atoms along the auxiliary lines A3 and A4 corresponds to the metal layer 25. When this portion is viewed in detail, the concentration of Ti atoms is indicated by a broken line. It can be seen that this is very remarkable in the enclosed portion, but decreases in the region D, which is close to the interface between the Cu wiring pattern 27 and the second diffusion barrier layer 28 and has a depth of up to about 260 nm. From these facts, the concentration of Ti atoms along the auxiliary line A1-A2 is caused by the fact that Ti atoms originally contained in the metal film 25 pass through the corners at the upper end of the Cu wiring pattern 27. It is considered that the diffusion has occurred along the interface between the Cu wiring pattern 27 and the second diffusion barrier film 28 as schematically shown in FIG. However, in FIG. 6, the part demonstrated previously is attached | subjected the same referential mark, and description is abbreviate | omitted.

  In FIG. 5, in a region surrounded by a broken line, a light-colored portion indicates that Ti atoms are present at a higher concentration than a dark-colored portion. In these portions, the concentration of Ti atoms has not changed significantly from before the heat treatment, indicating that the metal film 25 remains in a state close to the state before the heat treatment. On the other hand, in the region D up to the depth of 260 nm, the metal film 25 is a source of Ti atoms concentrated along the auxiliary line A1-A2, and accordingly, schematically shown in FIG. Thus, it is considered that the film thickness is reduced.

  By the way, from the study of electromigration so far, in the diffusion of Cu atoms in the Cu wiring pattern, it mainly consists of the Cu wiring pattern, SiN, SiCN, SiC, etc., and corresponds to the second diffusion barrier film 28. It is considered that diffusion at the interface with a so-called cap film is dominant. Hereinafter, the second diffusion barrier film 28 is referred to as a cap film. Since the insulating film and the metal film are in contact with each other at the interface, there are many defects or vacancies, and the adhesion is the weakest even in the wiring structure. On the other hand, on the other interface, that is, on the side surface and bottom surface of the Cu wiring pattern, the Cu wiring pattern is in contact with a so-called barrier metal containing a metal element such as the first diffusion barrier film 26, so there are few vacancies. The adhesion of is relatively strong. For this reason, when Cu atoms are transported by electromigration, the transport of Cu atoms easily proceeds along the diffusion path having the worst interface adhesion at the interface between the Cu wiring pattern and the cap film. Therefore, at such an interface, as a result of electromigration, vacancies gather and the probability that voids are formed is extremely high.

  On the other hand, as shown in FIG. 5, in the structure in which Ti atoms are deposited at the interface between the Cu wiring pattern 27 and the cap layer 28, Cu atoms are pinned by the Ti atoms, and diffusion of Cu atoms generated through the interface is performed. Can be suppressed. See, for example, US Pat.

  On the other hand, as can be seen from the distribution of Ti atoms in FIG. 5, Ti atoms are concentrated at the interface between the cap film 28 and the Cu wiring pattern 27 and are hardly detected in the Cu wiring pattern 27. . The concentration of Ti atoms in the Cu wiring pattern 27 is below the noise level. For this reason, in the wiring structures of FIGS. 3 to 5, the diffusion of Ti atoms from the metal film 25 does not increase the resistance of the Cu wiring pattern 27.

  The measurement results in FIG. 5 are the results for the sample 20 in FIG. 3, which was further cut as shown in FIG. 4 after forming a multilayer wiring structure thereon and finishing all the manufacturing steps. For this reason, the Cu wiring pattern 27 is subjected to various heat treatments at a total temperature of 400 ° C. for 1 hour.

  Further, in such an experiment, the metal film 25 is changed from a Ti film to a manganese (Mn) film, a zirconium (Zr) film, and an aluminum (Al) film, and the first diffusion barrier film 26 is changed for each. When repeated from the Ta film to a Mn film, further a nitrided Ta (TaN) film and a nitrided Ti (TiN) film, depending on the additive element, the temperature ranges from 300 ° C. to 500 ° C. for 1 minute. It has been confirmed that if heat treatment is performed for about 1 hour, the same phenomenon occurs, and the concentration of metal atoms in the metal layer 25 decreases in the region D where the depth is shallower than about 260 nm. When the metal film 25 is a Mn film and the diffusion barrier film 26 is also a Mn film, the upper end portion of the diffusion barrier film 26 also functions as a source of the metal element. Since the thickness is increased, the function of the diffusion barrier film 26 is not impaired even if Mn atoms diffuse in this way.

  As described above, in the wiring structure 20 of FIG. 6, the concentration of metal atoms such as Ti atoms occurs in the region 27D at the interface between the Cu wiring pattern 27 and the cap film 28 covering the surface thereof. The diffusion of Cu atoms is suppressed, and the wiring structure 20 exhibits excellent electromigration resistance and stress migration resistance.

  On the other hand, in the wiring structure 20 of FIG. 3 or FIG. 6, the metal film 25 serving as a source of metal atoms such as Ti is formed so as to continuously cover the side wall surface and the bottom surface of the recess 23T. Of 25, the portion that is actually the source of metal atoms is limited to the region D having a depth of 260 nm or less, as described above. The metal film 25 increases the resistance of the wiring pattern 27 in the other portions, that is, in the portion of the side wall surface of the recess 23T that covers the portion below the region D and the bottom surface of the recess 23T. It only contributes.

  7A to 7H show the multilayer wiring according to the first embodiment in which the above knowledge is applied to the formation of a multilayer wiring structure, and at this time, the formation of a metal film on an unnecessary portion is suppressed and the wiring resistance is reduced. A method of manufacturing the semiconductor device 40 having a structure is shown.

  Referring to FIG. 7A, the semiconductor device 40 is formed on a silicon substrate 41, and an element region 40A is defined on the silicon substrate 41 by an element isolation structure 41I.

  In the element region 40A, a polysilicon gate electrode 43 is formed on the silicon substrate 41 via a gate insulating film 42 made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In the silicon substrate 41, n-type or p-type LDD regions 41 a and 41 b are respectively formed on the first side and the second side of the gate electrode 43 in the element region 40.

  Side wall insulating films 43W1 and 43W2 are formed on the first and second side wall surfaces of the gate electrode 43, and the side wall insulating film 43W1 of the element region 40 in the silicon substrate 41 is formed. A p-type or n-type source diffusion region 41c is formed on the first side, and a p-type or n-type drain diffusion region 41d is formed on the second side of the sidewall insulating film 43W2.

  Further, the silicon substrate 41 is formed with a silicon oxide film 44 covering the gate electrode 43 including the side wall insulating films 43W1 and 43W2 as a base insulating film.

  Further, a so-called Low-K film 45 is formed as an interlayer insulating film on the base insulating film 44 by CVD or SOD (Spin On Deposition). In the illustrated example, a SiOC film is formed as the interlayer insulating film 45 to a thickness of 250 nm by a CVD method. Further, an SiC film 46 is formed as a hard mask film on the SiOC film 45 by a plasma CVD method to a thickness of, for example, 50 nm to obtain the structure of FIG. 7A.

  Next, in the structure of FIG. 7A, wiring grooves 45A, 45B, and 45C are formed by dry etching using the hard mask layer 45 as a mask in a portion of the interlayer insulating film 45 corresponding to the wiring pattern to be formed. 7B is obtained. In the example of FIG. 7B, the wiring patterns include those formed in the region A and having a wiring width of approximately 0.1 μm, and those formed in the region B and having a larger wiring width. Yes.

  Next, a metal film 47 corresponding to the metal film 25 is deposited on the structure of FIG. 7B by sputtering at room temperature to obtain the structure of FIG. 7C. In the example of FIG. 7C, here, a Ti film having a thickness of 5 nm corresponding to the field film thickness is used as the metal film 47. As described above, as the metal film 47, a Mn film, a Zr film, an Al film, or the like can be used.

  Further, the structure shown in FIG. 7C is re-sputtered while rotating the substrate 41 in an oblique direction, for example, by an angle θ of 5 to 75 ° with respect to the main surface of the interlayer insulating film 45, regardless of the wiring width. The metal film 47 deposited on a portion near the bottom surface of the bottom surface and the side wall surface of the wiring groove 45A to the wiring groove 45C is shaved, and the shoulder portion of the wiring groove 45A to the wiring groove 45C that is shaded, that is, the upper end portion of the wiring groove. The metal film 47 is left only in the region D including the depth of 260 nm. In the present embodiment, the resputtering can be performed under the conditions that the target bias is 510 W, the substrate bias is 380 W, and the high-frequency coil power is 1190 W. In this case, however, the resputtering conditions are not limited to those described above, and it is necessary to make fine adjustments according to the type and thickness of the barrier metal, the type of interlayer film, and the like.

  Next, a barrier metal film 48 for preventing diffusion of Ti atoms is formed on the structure shown in FIG. 7D by sputtering at room temperature corresponding to the first diffusion barrier film 26, and the structure shown in FIG. 7E. Get. In the example of FIG. 7E, as the barrier metal film 48, a Ta film is formed with a field film thickness equivalent to 5 nm, as in the wiring structure 20 of FIG. 3 or FIG.

  Next, a Cu film (not shown) serving as a seed layer is formed on the entire surface of the structure shown in FIG. 7E to a thickness of 20 nm by sputtering at room temperature. Thereafter, a Cu layer 49 is formed by electrolytic plating so that the Cu layer 49 fills the wiring grooves 45A to 45C, thereby obtaining the structure of FIG. 7F. Thereafter, the substrate 41 and the structure thereon are heat-treated at a temperature of 150 ° C. to grow crystal grains in the Cu film 49.

  Further, the Cu layer 49 is polished by CMP until the hard mask layer 46 is exposed to obtain the structure of FIG. 7G. In the structure of FIG. 7G, Cu wiring patterns 49A to 49C filling the wiring grooves 45A to 45C are formed from the Cu layer 49.

  Further, on the structure of FIG. 7G, an SiC film is formed as a cap film 49 corresponding to the second diffusion barrier film 28 by plasma CVD so as to cover the upper surfaces of the Cu wiring patterns 49A to 49C. Further, a silicon oxide film 50 having a thickness of 500 nm and a SiN film 51 having a thickness of 50 nm are formed thereon by a plasma CVD method executed at a temperature of 350 ° C. to 400 ° C. The structure of FIG. 7H is obtained.

  Further, in the structure of FIG. 7H obtained in this way, although not shown, the silicon oxide film 50 is removed by etching in the pad region at the end of the wiring, and an aluminum (Al) film is formed. By further patterning, terminal electrodes for resistance measurement of the Cu wiring patterns 49A to 49C were formed. This aluminum film forming process is a part of a general manufacturing process of a Cu wiring structure. In this process, the Cu wiring patterns 49A to 49C are subjected to a heat treatment at about 400 ° C. for about 30. Added for a minute.

  As a result of the heat treatment accompanying the step of forming the insulating film 45 or 46 or the step of forming the terminal electrode, as shown in FIG. 7H, in each of the Cu wiring patterns 49A to 49C, As a result of diffusion of metal atoms such as Ti atoms from the metal film 47 along the interface, a concentrated region 49D of metal atoms such as Ti atoms is formed corresponding to the region D. Along with this, the thickness of the metal film 47 decreases. However, the metal film 47 does not disappear.

  Thus, when the wiring resistance was investigated in the Cu wiring pattern where the wiring width in which the concentrated region 49D was formed was 0.1 μm, the results shown in Table 1 below were obtained. However, in Table 1, what is shown as “Example 1” is the resistance value for the Cu wiring pattern formed by the process described with reference to FIGS. 7A to 7H, while shown as “Comparative Example 1”. The reason is that the resistance value of the Cu wiring pattern having the same wiring width of 0.1 μm when the Ti film 47 forming process described in FIG. 7C and the resputtering process described in FIG. Example 2 ”shows the resistance value of the Cu wiring pattern having a wiring width of 0.1 μm when the resputtering step described with reference to FIG. 7D is omitted. In Table 1, the resistance values of “Example 1”, “Comparative Example 1”, and “Comparative Example 2” are normalized with respect to the resistance value of “Example 1”.

Referring to Table 1, when compared with a Cu wiring pattern having a wiring width of 0.1 μm, the wiring resistance of Conventional Example 1 is 98% of the wiring resistance of Example 1, and a Ti film 47 is slightly formed. Therefore, it is shown that the ratio of the Cu wiring pattern in the wiring groove is slightly decreased and the resistance value is slightly increased.

  On the other hand, in the conventional example 2, the wiring resistance is increased to 110% of that in the first embodiment. This is because the Ti film 47 continuously covers the entire side walls and bottom surfaces of the wiring grooves 45A to 45C. This reflects the effect that the ratio of the Cu wiring pattern in the wiring groove is smaller than that in the first embodiment.

Next, for the Cu wiring pattern thus formed having a wiring width of 0.1 μm, a reliability test was performed to evaluate the wiring life, and the results shown in Table 2 below were obtained. However, the reliability test is performed at a temperature of 300 ° C. and the current acceleration condition is set to ³ MA / cm ² . At that time, the wiring length is 1000 μm, which is much longer than the so-called Blech length. For this reason, it is considered that the effect of the wiring length is not affected in this reliability test. In Table 2, “Example 1”, “Comparative Example 1”, and “Comparative Example 2” are the same as those in Table 1. In Table 2, the wiring life of “Example 1” and “Comparative Example 2” is shown normalized to the wiring life of “Example 1”.

As shown in Table 2, it was shown that the wiring life of the Cu wiring pattern of Example 1 was about 5 times longer than that of the Cu wiring pattern of Conventional Example 1. Further, it was shown that the wiring life of the Cu wiring pattern of the conventional example 2 was almost the same as that of the example 1.

  Considering the results of Table 1 and Table 2 above, it is concluded that the Cu wiring pattern of Example 1 is advantageous in view of both wiring resistance and reliability.

[Second Embodiment]
8A to 8H show a method of manufacturing a semiconductor device according to the second embodiment including formation of a multilayer wiring structure by a dual damascene method. However, in the figure, the parts described above are denoted by corresponding reference numerals, and the description thereof is omitted.

  Referring to FIG. 8A, first, the lower layer wiring is manufactured by the same method as in the first embodiment described with reference to FIGS. 7A to 7G.

  Next, as described above with reference to FIG. 7H, the SiC film 51 is formed as a cap film by a plasma CVD method so as to cover the surfaces of the Cu wiring patterns 49A to 49C, for example, with a thickness of 50 nm. Then, a low-K film made of a SiOC film is formed to a thickness of about 550 nm as the interlayer insulating film 61 by plasma CVD. Further, a SiC film 62 having a thickness of 50 nm is formed as a hard mask layer on the interlayer insulating film 61, and the structure shown in FIG. 8B is obtained.

  Next, the hard mask layer 62 is patterned to form openings corresponding to via holes, and the interlayer insulating film 61 is etched by dry etching using the hard mask layer 62 as a mask until the cap layer 49 is exposed. A via hole 61V shown in FIG. 8C is formed in the interlayer insulating film 61.

  Further, the hard mask layer 62 is patterned to form openings corresponding to the wiring grooves formed in the interlayer insulating film 61, and the interlayer insulating film is etched by dry etching using the hard mask layer 62 as a mask. A wiring trench 61T shown in FIG. 8C is formed in the interlayer insulating film 61. The dry etching of the wiring trench 61T is terminated when the desired depth is reached by controlling the etching time, and as a result, the structure shown in FIG. 8C is obtained.

  Next, on the structure of FIG. 8C, the Ti film 63 is obliquely sputtered at an angle θ while rotating the substrate 41 around an axis perpendicular to the substrate, so that the thickness in the field region is 1 nm to 10 nm. It forms so that it becomes. In such oblique sputtering, the metal film 63 is hardly deposited on the bottom surface of the wiring groove 61T and the lower portion of the side wall surface following the wiring groove 61T, and further on the side wall surface and bottom surface of the via hole 61V.

  The angle θ when performing oblique sputtering is preferably optimized so that the metal film 62 covers only the depth D from the shoulder of the wiring groove 61T, that is, the upper end of the side wall surface to 260 nm. Actually, a large number of wiring grooves having different widths are formed in the multilayer wiring structure of the semiconductor device. However, the metal film 62 is a source of metal atoms such as Ti as described above with reference to FIG. It is sufficient that the wiring groove is slightly present at the shoulder in each wiring groove. Therefore, the angle θ is the width of the widest wiring groove in the multilayer wiring structure. It is preferable to optimize so as to cover a depth of 260 nm from the upper end of the substrate. In this case, in the narrower wiring trench, the metal film 63 covers a region shallower than 260 nm as measured from the upper end of the sidewall film. For example, when the width of the wiring groove 61T is 100 nm, the angle θ is preferably set to 69 °, and when the width of the wiring groove 61T is 1000 nm, the angle θ is preferably set to 14 °. . Sputtering of the metal film 62 can be performed at room temperature.

  Depending on the wiring layout, it may be unavoidable that deposition on the side surface or bottom near the bottom of the trench is unavoidable. In such a case, resputtering is performed in the same manner as described above with reference to FIG. 7D. It is useful to go and remove these extra films.

  As described above, the metal film 63 is not limited to a Ti film, and an Mn film, a Zr film, an Al film, or the like can be used.

  Thereafter, the same process as in the previous embodiment is performed.

  That is, a Ta film is formed as a diffusion barrier film 64 with a film thickness of, for example, 10 nm on the metal film 63 by sputtering at room temperature so as to continuously cover the sidewalls and bottom surfaces of the wiring trench 61T and the via hole 61V. Thus, the structure of FIG. 8E is obtained. The diffusion barrier film 64 is not limited to the Ta film, and may be another metal film such as a Mn film, or a conductive nitride film of a refractory metal such as a TaN film or a TiN film.

  Further, a Cu seed layer (not shown) is formed on the entire surface with a film thickness of 20 nm on the structure of FIG. 8E by sputtering at room temperature, and a Cu layer 65 is formed on the Cu seed layer by electrolytic plating. The wiring trench 61T and the via hole 61V are formed so as to be filled. Thereby, the structure shown in FIG. 8F is obtained.

  Further, the structure of FIG. 8F is subjected to a heat treatment at a temperature of 150 ° C. to grow grains of Cu crystals in the Cu layer 65, and then the hard mask film 62 is formed on the Cu layer 65 by CMP. As shown in FIG. 8G, the wiring groove 61T is filled with the Cu wiring pattern 65T, and the via hole 61V is filled with the Cu via plug 65V extending from the Cu wiring pattern 65T. The via plug 65V is in electrical contact with the underlying Cu wiring pattern 48 via the diffusion barrier film 64.

  Further, on the structure of FIG. 8G, a cap film 66 made of, for example, SiC and covering the Cu wiring pattern 65T is formed as a Cu diffusion preventing film with a thickness of, for example, 50 nm by plasma CVD, and further, A silicon oxide film 67 having a thickness of 500 nm and a silicon nitride film 68 having a thickness of 50 nm are formed as insulating films to obtain a multilayer wiring structure shown in FIG. 8H.

  Further, although not shown, the insulating films 67 and 68 corresponding to a predetermined pad region are removed by etching, an aluminum film is formed in the pad region, and this is further patterned to form a pad electrode. Form.

  The formation process of the films 66 to 68 and the formation process of the pad electrode are a part of the formation process of a general Cu wiring structure. When these processes are combined, a heat treatment at about 400 ° C. is applied for 45 minutes. Will be. As a result, a concentrated region 65D of metal atoms such as Ti atoms diffused from the metal film 63 is formed on the surface of the Cu wiring pattern 65T in the same manner as the active particle region 49D. The diffusion of Cu atoms along the interface with the film 66 is suppressed. Also in this embodiment, the metal film 63 is limited to a limited depth D range including the shoulder portion of the side wall surface of the wiring groove 61T, that is, the upper end portion, and therefore fills the wiring groove 61T. The decrease in the proportion of the Cu wiring pattern 65T is slight, and the increase in wiring resistance is minimized.

  For example, when the wiring resistance of the Cu wiring pattern 65T formed in this way is measured in this embodiment, it is confirmed that the wiring resistance is about 1% higher than that when the Ti oblique sputtering shown in FIG. 8D is not performed. . However, in the electromigration test performed under the same conditions as in Example 1 of the first embodiment, the wiring life of the Cu wiring pattern 65T of the present invention is about the wiring life of the metal film 63 that was not formed. It was confirmed to be 4.5 times longer.

  As described above, it has been found that the multilayer wiring structure according to the present embodiment can improve the reliability much after the increase of the wiring resistance.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A substrate,
An insulating film formed on the substrate and having a recess defined by a side wall surface and a bottom surface;
Among the side wall surfaces, an upper first portion including an upper end portion of the side wall surface is defined as a bottom surface of the recess and a second portion below the first portion among the side wall surfaces of the recess. A metal film covering the insulating film so as to be exposed;
A first diffusion barrier film that continuously covers the side wall surface and the bottom surface of the recess, and in the first part of the side wall surface, also covers the metal film;
A copper wiring pattern that fills the recess through the first diffusion barrier film;
An insulating second diffusion barrier film covering the surface of the copper wiring pattern on the insulating film;
A concentrated region of metal elements formed at the interface between the copper wiring pattern and the second diffusion barrier film;
With
The concentrated region of the metal element includes a metal element constituting the metal layer at a higher concentration than in the copper wiring pattern.
(Appendix 2)
The semiconductor device according to claim 1, wherein the metal element is selected from the group consisting of titanium, manganese, zirconium, and aluminum.
(Appendix 3)
3. The semiconductor device according to claim 2, wherein the metal film covers a range of 260 nm or less from the upper end portion toward the bottom surface of the side wall surface.
(Appendix 4)
The semiconductor device according to appendix 3, wherein the metal element is titanium.
(Appendix 5)
5. The semiconductor device according to claim 1, wherein the second diffusion barrier film is a carbide film or a nitride film containing silicon.
(Appendix 6)
6. The semiconductor device according to claim 1, wherein the first diffusion barrier film is made of a metal film containing tantalum or manganese.
(Appendix 7)
6. The semiconductor device according to claim 1, wherein the first diffusion barrier film is a nitride film of tantalum or titanium.
(Appendix 8)
Forming a recess in the interlayer insulating film;
A metal film is formed on a side wall surface of the opening, and the metal film covers an upper first portion of the side wall surface including an upper end portion of the side wall surface, a bottom surface of the concave portion, and a side wall surface of the concave portion. A step of depositing the insulating film so as to expose the second portion below the first portion; and
Forming a first diffusion barrier film on the interlayer insulating film so as to continuously cover the side wall surface and the bottom surface of the opening;
Depositing a copper layer on the interlayer insulating film, and filling the opening with the copper layer through the diffusion prevention film;
Removing the copper layer on the interlayer insulating film and forming a copper pattern with the copper layer in the opening;
Forming an insulating second diffusion barrier film on the interlayer insulating film in contact with the upper surface of the copper pattern;
Heat-treating the copper layer, and concentrating a metal element constituting the metal film at an interface between the copper pattern and the second diffusion barrier film;
A method for manufacturing a semiconductor device, comprising:
(Appendix 9)
9. The method of manufacturing a semiconductor device according to claim 8, wherein the metal film covers a range of 260 nm or less in the side wall surface from the upper end portion toward the bottom surface.
(Appendix 10)
The method of manufacturing a semiconductor device according to appendix 9, wherein the metal element is titanium.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to claim 8, wherein the heat treatment is performed at a temperature of 350 ° C. or higher and 400 ° C. or lower.
(Appendix 12)
The step of forming the metal film includes: forming the metal film continuously covering the side wall surface and the bottom surface of the opening; and forming the metal film from the bottom surface of the opening and the second portion. The method of manufacturing a semiconductor device according to any one of Supplementary Note 8 to Supplementary Note 11, including a step of removing.
(Appendix 13)
The step of forming the metal film is performed by a sputtering method, wherein the metal film is deposited on the first region of the side wall surface, and the upper end portion is formed on the second portion and the bottom surface. 12. The method of manufacturing a semiconductor device according to any one of appendices 8 to 11, wherein the method is performed in an oblique direction with respect to a main surface of the interlayer insulating film so as not to be deposited in the shade.

This is a method (No. 1) of forming a Cu wiring pattern by a conventional damascene method. This is a second method of forming a Cu wiring pattern by a conventional damascene method. This is a method (No. 3) of forming a Cu wiring pattern by a conventional damascene method. This is a method (part 4) of forming a Cu wiring pattern by a conventional damascene method. This is a method (No. 5) of forming a Cu wiring pattern by a conventional damascene method. This is a method (No. 6) of forming a Cu wiring pattern by a conventional damascene method. This is a method (part 7) of forming a Cu wiring pattern by a conventional damascene method. It is a figure explaining the subject of a prior art. It is a figure explaining the principle of 1st Embodiment. It is another figure explaining the principle of 1st Embodiment. It is another figure explaining the principle of 1st Embodiment. It is another figure explaining the principle of 1st Embodiment. FIG. 6 is a diagram (part 1) for explaining the method of manufacturing a semiconductor device according to the first embodiment; FIG. 8 is a diagram (part 2) for explaining the method of manufacturing a semiconductor device according to the first embodiment; FIG. 6 is a view (No. 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 4) for describing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 5) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 6) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 7 is a view (No. 7) for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 8 is a view (No. 8) for explaining the method for manufacturing the semiconductor device according to the first embodiment; It is FIG. (1) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. It is FIG. (2) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. FIG. 6 is a diagram (No. 3) for explaining the method for manufacturing a semiconductor device according to the second embodiment; It is FIG. (4) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. It is FIG. (5) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. It is FIG. (6) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. It is FIG. (7) explaining the manufacturing method of the semiconductor device by 2nd Embodiment. It is FIG. (8) explaining the manufacturing method of the semiconductor device by 2nd Embodiment.

Explanation of symbols

11, 16, 23, 29, 45, 61 Interlayer insulating film 11A, 23T Recess 12, 24, 46, 62 Hard mask pattern 12A Opening 13, 26, 48, 64 Conductive diffusion barrier film 14, 49, 65 Cu layer 15, 28, 49 Insulating diffusion barrier film 20 Semiconductor device 21, 41 Substrate 22, 44, 50, 51, 67, 68 Insulating film 25, 47, 63 Metal film 27D, 49D Metal atom concentration region 41A Element region 41a, 41b LDD diffusion region 41c, 41d source / drain diffusion region 41I element isolation region 42 gate insulating film 43 gate electrode 43W1, 43W2 gate sidewall insulating film 45A-45C, 61T wiring groove 49A-49C, 65T Cu wiring pattern 61V via hole 65V Cu via plug

Claims (4)

A substrate,
An insulating film formed on the substrate and having a recess defined by a side wall surface and a bottom surface;
Among the side wall surfaces, an upper first portion including an upper end portion of the side wall surface is defined as a bottom surface of the recess and a second portion below the first portion among the side wall surfaces of the recess. A metal film covering the insulating film so as to be exposed;
A first diffusion barrier film that continuously covers the side wall surface and the bottom surface of the recess, and in the first part of the side wall surface, also covers the metal film;
A copper wiring pattern that fills the recess through the first diffusion barrier film;
An insulating second diffusion barrier film covering the surface of the copper wiring pattern on the insulating film;
A concentrated region of metal elements formed at the interface between the copper wiring pattern and the second diffusion barrier film;
With
Enrichment region of the metal element, a metal element forming the metal film, seen containing a higher concentration than the copper wiring pattern in,
The metal element is selected from the group consisting of titanium, manganese, zirconium and aluminum,
The first diffusion barrier film is selected from the group consisting of a tantalum film, a manganese film, a tantalum nitride film, and a titanium nitride film,
The semiconductor device, wherein the second diffusion barrier film is a carbide film or a nitride film containing silicon . The metal film of the side wall, the bottom direction from the upper end, the semiconductor device according to claim 1, wherein the covering the range within 260 nm. The semiconductor device according to claim 2 , wherein the metal element is titanium. Forming a recess in the insulation Enmaku,
A metal film on the side wall surface of the concave portion, of the metal film of the side wall, covering a first portion of the upper including the upper portion of the side wall surface, a bottom surface of the recess, and the side wall surface of said recess A step of depositing the insulating film so as to expose the second portion below the first portion; and
Before Kize' edge film, forming a first diffusion barrier layer covering the sidewall surface and bottom surface of the concave portion continuously,
A step of a copper layer was deposited before Kize' edge film, the concave portion is filled with the copper layer through the first diffusion barrier layer,
Before removing the copper layer on Kize' border membranes in the recess, by the copper layer, and forming a copper pattern,
Before Kize' edge film, in contact with an upper surface of the copper pattern, and forming a second diffusion barrier layer of insulation,
Heat-treating the copper layer, and concentrating a metal element constituting the metal film at an interface between the copper pattern and the second diffusion barrier film;
Only including,
The metal element is selected from the group consisting of titanium, manganese, zirconium and aluminum,
The first diffusion barrier film is selected from the group consisting of a tantalum film, a manganese film, a tantalum nitride film, and a titanium nitride film,
The method of manufacturing a semiconductor device, wherein the second diffusion barrier film is a carbide film or a nitride film containing silicon .