JP5370308B2 - Semiconductor device, semiconductor device manufacturing method, and semiconductor device mounting method - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor element, and a manufacturing method and a mounting method thereof.

  A semiconductor chip such as a transistor or a diode and a chip for controlling driving thereof are mounted on a lead frame, and these chips and wires are connected between these chips and between the chip and the lead frame by wire bonding. A semiconductor device in which is sealed with resin is known. A technique for adjusting the flow of the resin by devising the shape of the lead frame, a technique for providing a heat dissipation member in the semiconductor device after sealing, and the like are also known.

JP 2000-138343 A

  In a semiconductor device using a lead frame as described above, the lead frame must be designed and processed for each type of semiconductor device to be formed, that is, for each type of semiconductor chip mounted on the lead frame. In a semiconductor device using such a lead frame, the semiconductor chip is mounted on the lead frame and then sealed with resin. Depending on the shape, number, arrangement, etc. of the semiconductor chip to be mounted, the lead frame may be Even if the shape is devised, it may be difficult to fill the resin with details.

  Further, the semiconductor device cannot be tested unless the semiconductor chip is mounted on the lead frame, connected by wire bonding, and further sealed with resin. In general, before resin sealing, the outer lead of the lead frame is connected by a tie bar, so the external lead-out terminals are not independent. Therefore, there is a problem that an electrical test cannot be performed unless the outer lead is separated from the tie bar after resin sealing.

  Even if a good semiconductor chip that has been inspected is mounted on a lead frame, if the chip is damaged during the mounting process, wire bonding process, resin sealing process, etc., the defect is revealed by a test after resin sealing. It will be.

  When a large number of semiconductor chips are encapsulated in one package as in Patent Document 1, if any one of the encapsulated chips is abnormal, the entire package including the non-defective chip becomes defective. There is a problem.

According to one aspect of the present invention, a heat dissipating member, a wiring layer formed on one main surface of the heat dissipating member and including a conductor layer and an insulating layer, an external lead terminal connected to the conductor layer, A semiconductor chip formed by resin-sealing a semiconductor chip having both a switching function for passing and blocking current and a function for reducing current capacity compared to the switching function and conducting in a direction opposite to the direction for blocking current . 1 semiconductor element and a second semiconductor element formed by resin-sealing a semiconductor chip in which a driving circuit for driving the first semiconductor element is integrated, and a conductor layer exposed from the insulating layer, A semiconductor device is provided in which the first semiconductor element and the second semiconductor element are mounted and connected to a compressor as an inverter device .

  According to the present invention, various high-quality semiconductor devices can be obtained efficiently.

1 is an explanatory diagram of a semiconductor device according to a first embodiment. It is a figure which shows the example of the semiconductor element containing a switching element. 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. It is explanatory drawing of an example of a wiring layer formation process. It is explanatory drawing of an example of a semiconductor element mounting process. It is explanatory drawing of another example of a semiconductor element mounting process. It is a figure which shows another example of the semiconductor device which concerns on 1st Embodiment. It is explanatory drawing of the semiconductor device which concerns on 2nd Embodiment. It is an example of the circuit diagram of the semiconductor device which concerns on 2nd Embodiment. It is explanatory drawing of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows an example of the mounting form to the circuit board of a semiconductor device.

First, the first embodiment will be described.
FIG. 1 is an explanatory diagram of the semiconductor device according to the first embodiment. Here, FIG. 1A is a schematic external view of the semiconductor device according to the first embodiment, and FIG. 1B is a schematic view corresponding to a cross section taken along a dashed line L1 in FIG.

A semiconductor device 1 illustrated in FIG. 1 includes a heat dissipation member 10, a wiring layer 20, and semiconductor elements 30 and 40.
For the heat radiating member 10, for example, a plate having a certain thermal conductivity is used. From the viewpoint of thermal conductivity, the heat radiating member 10 can be a metal plate such as aluminum, an aluminum alloy, copper, or a copper alloy. From another viewpoint, as described later, in order to form the wiring layer 20, at least one main surface can have a flat shape.

A wiring layer 20 is formed on one main surface of the heat radiating member 10. Here, the wiring layer 20 of the multilayer wiring is shown as an example.
As shown in FIG. 1A, semiconductor elements 30 and 40 are mounted at predetermined positions on the wiring layer 20. The wiring layer 20 is provided with input / output terminals for the semiconductor elements 30 and 40, but the illustration thereof is omitted in FIGS. 1 (A) and 1 (B).

  The wiring layer 20 includes a circuit pattern 21 (conductor layer) that constitutes a predetermined circuit by wiring and vias, and an insulating layer 22 provided around the circuit pattern 21. The circuit pattern 21 (wiring, via) can be formed using, for example, copper or a material containing copper. The insulating layer 22 can be formed using, for example, an epoxy resin, a polyimide resin, or a prepreg in which glass fiber or carbon fiber is impregnated with a resin such as an epoxy resin.

  On the wiring layer 20, here, as an example, there are two types of semiconductor elements: a semiconductor element 30 including a switching element and a semiconductor element 40 including a control element (control circuit) that controls driving of the semiconductor element 30. It is mounted and electrically connected to the circuit pattern 21.

  Here, FIG. 2 is a diagram illustrating an example of a semiconductor element including a switching element, in which (A) is a schematic diagram of a first example of the semiconductor element 30, and (B) is an L2-L2 cross section of (A). (C) is a schematic diagram of a second example of the semiconductor element 30, and (D) is a schematic diagram of the L3-L3 cross section of (C).

  The semiconductor element 30 includes, for example, an insulated gate bipolar transistor (IGBT) 31 that is a switching element, as shown in FIGS. The semiconductor element 30 is mounted on the lead frame 33 so that a free wheeling diode (FWD) 32 that is a rectifying element that allows current to flow in one direction is connected to the IGBT 31 in antiparallel with the IGBT 31. Has been.

  The IGBTs 31 and FWD 32 are mounted on the die pad 33 a of the lead frame 33 and are further electrically connected to the terminals 34 a and 34 b of the lead frame 33 by wires 37. The terminals 34a and 34b are electrically connected to the gate (G) and emitter (E) of the IGBT 31, for example. The collector (C) of the IGBT 31 is electrically connected to the die pad 33a. The IGBT 31 and FWD 32 are sealed with a sealing resin 35 (shown by dotted lines), and as shown in FIGS. 2A and 2B and FIG. 1B, terminals 34a, 34b and 34c (die pad 33a). Is partially exposed from the sealing resin 35.

  Thus, the switching element provided with FWD in antiparallel is not limited to the IGBT. For example, a power transistor or an element such as a MOSFET (Metal Oxide Field Field Effect Transistor) may be used. Alternatively, a SiC MOSFET (silicon carbide MOSFET) may be used as the MOSFET.

  Moreover, the semiconductor element 30 can also be comprised with one chip | tip provided with the conduction | electrical_connection function to a reverse direction as a switching element, as shown, for example in FIG.2 (C), (D). 2C and 2D, an RC-IGBT (Reverse Conducting IGBT) 36 is applied as a switching element having a conduction function in the reverse direction. In addition, as a switching element having a reverse conduction function, a parasitic diode of MOSFET or SiCMOSFET may be used.

  Here, as a conduction function in the reverse direction, whether to use a parasitic diode of MOSFET or SiCMOSFET or to connect the FWD in reverse parallel may be selected according to the duty required for the FWD depending on the load to be applied.

  2C and 2D, similarly to the above, the RC-IGBT 36 is sealed with a sealing resin 35, and the gate (G), emitter (E), and collector (C) of the RC-IGBT 36 are electrically connected. Connected terminals 34a, 34b, 34c (the back surface of die pad 33a) are partially exposed from sealing resin 35 as shown in FIGS. 2C and 2D and FIG. .

  Similarly, the semiconductor element 40 as a control IC in which a driving circuit for driving the semiconductor element 30 is integrated, as shown in FIG. 1B, is connected to a terminal 41a electrically connected to the control element. , 41b are sealed with a sealing resin so that they are partially exposed.

In FIG. 1A, the terminals 34a, 34b, 34c of the semiconductor element 30 and the terminals 41a, 41b of the semiconductor element 40 are not shown.
In this semiconductor device 1, as an example, an inverter that uses six semiconductor elements 30 and two semiconductor elements 40 having the above-described configuration and converts DC power to AC power and supplies it to a three-phase AC motor or the like. A circuit is configured.

FIG. 3 is an example of a circuit diagram of the semiconductor device according to the first embodiment.
The inverter circuit 100 shown in FIG. 3 uses six semiconductor elements 30 as switching elements and constitutes a three-phase bridge circuit as shown.

  The switching operation of the six switching elements (the IGBT 31 or the RC-IGBT 36 in the semiconductor element 30) is performed by the two semiconductor elements 40. Here, the switching operation of the three IGBTs on the high voltage side (P side) is controlled by one semiconductor element 40, and the switching operation of the three IGBTs on the low voltage side (N side) is controlled by the other semiconductor element 40. It is controlled by.

Here, if a driving circuit for driving all of the six switching elements (semiconductor elements 30) is integrated in one semiconductor element 40, one semiconductor element 40 is sufficient.
Alternatively, a drive IC (semiconductor element 40) in which drive circuits of switching elements (IGBT 31 or RC-IGBT 36 in the semiconductor element 30) are integrated is provided for each of the three semiconductor elements 30 on the high voltage side (P side). Also good.

The FWD connected to each IGBT plays a role of causing a load current to commutate to the IGBT or a surge current and a regenerative current to be circulated as the IGBT is switched.
In the semiconductor device 1, when the six semiconductor elements 30 and the two semiconductor elements 40 as described above are mounted on the wiring layer 20, the inverter circuit 100 as shown in FIG. A circuit pattern 21 of the wiring layer 20 is formed in advance.

  As shown in FIG. 1B, the semiconductor elements 30 and 40 are bonded onto the circuit pattern 21 of the wiring layer 20 via a bonding member 50 such as solder. The semiconductor element 30 has its terminals 34 a, 34 b and 34 c bonded to the circuit pattern 21 of the wiring layer 20 via the bonding member 50, and the semiconductor element 40 has its terminals 41 a and 41 b bonded to the circuit pattern 21 of the wiring layer 20. It is joined via the member 50. In addition, illustration of the joining member 50 is abbreviate | omitted in FIG. 1 (A).

  When the IGBT as described above is used for the semiconductor element 30, the amount of heat generated is relatively large. Therefore, it is preferable to form a relatively large volume via-shaped circuit portion 21A in the wiring layer 20 at a portion facing the semiconductor element 30 to be bonded, as shown in FIG. . For example, as shown in FIG. 1B, the circuit portion 21 </ b> A to which the terminal 34 c electrically connected to the collector (C) of the IGBT of the semiconductor element 30 is joined is formed in a region facing the semiconductor element 30. It is a relatively large area that spreads and is formed thicker toward the heat radiating member 10 side. As a result, the heat generated in the semiconductor element 30 can be quickly transferred over a wide area to the large-volume circuit unit 21A and released to the heat radiating member 10 side.

Next, a method for forming the semiconductor device 1 having the above configuration will be described.
First, the formation process of the wiring layer 20 will be described. FIG. 4 is an explanatory diagram of an example of a wiring layer forming process.

  First, as shown in FIG. 4A, a through hole is formed in an insulating layer 22a such as resin or prepreg, and a conductive material such as a conductive paste is filled therein to form a via 21a. The via 21a is formed not only in the region where the large-volume circuit portion 21A is formed, but also in a portion necessary for connection between wirings of different layers.

  Next, a foil such as copper is attached to the insulating layer 22a in which the via 21a is formed, and is patterned by etching or the like, thereby forming a wiring 21b as shown in FIG. The wiring 21b formed in FIG. 4B is formed on a region including the region where the circuit portion 21A is formed and in a predetermined region corresponding to the circuit pattern 21 of the wiring layer 20 to be formed.

  Next, as in FIG. 4A, an insulating layer 22b in which a via 21c is formed in a region where the circuit portion 21A is formed and other predetermined portions is prepared. Then, as shown in FIG. 4C, the insulating layer 22b in which the via 21c is formed is bonded to the wiring 21b side of the structure obtained in FIG. 4B by hot pressing or the like. Thereby, a structure as shown in FIG. 4D is obtained.

  Next, a foil such as copper is attached to the front and back surfaces of the structure obtained in FIG. 4D, and is patterned by etching or the like, so that each of the predetermined regions on the front and back surfaces is shown in FIG. 4E. Such wirings 21d and 21e are formed. The surface-side wiring 21d is formed in a region including a region where the circuit portion 21A is formed. The backside wiring 21e is formed in a predetermined region corresponding to the circuit pattern 21 of the wiring layer 20 to be formed. In addition, the foil affixed in order to form wiring 21d, 21e uses the thing thicker than the back surface side on the surface side, for example.

  Here, as the foil for forming the wiring layer, for example, copper foils having thicknesses of 18 μm, 35 μm, 70 μm, 105 μm, 175 μm, 300 μm, 400 μm, 500 μm, and 800 μm are easily available. In consideration of the above, a desired thickness may be used in combination.

  The basic structure of the wiring layer 20 is completed by the steps so far. That is, when the semiconductor elements 30 and 40 are mounted as will be described later, here, the circuit pattern 21 (wirings 21b, 21d, 21e and vias such that the inverter circuit 100 as shown in FIG. 21a, 21c) is obtained.

  Next, as shown in FIG. 4F, an insulating layer 22c such as a resin is formed on the heat radiating member 10, and the back side (wiring) of the structure obtained through the steps of FIGS. 21e side) is bonded to the insulating layer 22c. As a result, the circuit pattern 21 (wirings 21b, 21d, 21e and vias 21a, 21c) and the insulating layer 22 provided around the circuit pattern 21 are formed on the heat dissipation member 10 as shown in FIG. A wiring layer 20 having (insulating layers 22a, 22b, 22c) is formed.

Subsequently, a mounting process of the semiconductor elements 30 and 40 will be described. FIG. 5 is an explanatory diagram of an example of a semiconductor element mounting process.
After the wiring layer 20 is formed on the heat dissipation member 10 as described above, the semiconductor elements 30 and 40 are mounted on the surface side of the wiring layer 20. The semiconductor elements 30 and 40 are mounted on the wiring layer 20 using a bonding member 50 such as solder.

  For example, as shown in FIG. 5A, the bonding member 50 is disposed on the wiring 21d and the via 21c exposed on the surface side of the wiring layer 20, and the semiconductor elements 30 and 40 are further disposed. Then, the joining member 50 is melted, cooled, and solidified to join the semiconductor elements 30 and 40 to the wiring layer 20 as shown in FIG.

  At that time, the semiconductor element 30 joins the terminals 34a and 34b connected to the gate (G) and emitter (E) of the IGBT to the via 21c on the surface of the wiring layer 20 by using the joining member 50, and collects the collector ( The terminal 34 c connected to C) is joined to the wiring 21 d on the surface of the wiring layer 20 by using the joining member 50. At this time, since the semiconductor element 30 is disposed above the large volume circuit portion 21A, the heat generated in the semiconductor element 30 is efficiently transferred to the heat radiating member 10 side via the circuit portion 21A. Become heated. In the semiconductor element 40, the terminals 41 a and 41 b are bonded to the via 21 c on the surface of the wiring layer 20 using the bonding member 50.

  The semiconductor elements 30 and 40 can be collectively mounted on the wiring layer 20. It is also possible to mount one of the semiconductor elements 30 and 40 on the wiring layer 20 first and then mount the other on the wiring layer 20.

  Here, the method of joining the terminals 34a and 34b of the semiconductor element 30 and the terminals 41a and 41b of the semiconductor element 40 to the via 21c of the wiring layer 20 is exemplified, but in addition, as shown in FIG. Various methods can also be used.

FIG. 6 is an explanatory diagram of another example of the semiconductor element mounting process.
For example, as shown in FIG. 6A, a via 21c is formed in a region excluding the region where the circuit portion 21A is formed as shown in FIG. The insulating layer 22b which has not been bonded is bonded to obtain a structure as shown in FIG. Then, as shown in FIG. 6C, after the wiring 21d is formed, a via hole 23 that penetrates the insulating layer 22b and reaches the lower wiring 21b is formed. Thereafter, the wiring 21e is formed, and the resulting structure is bonded to the insulating layer 22c formed on the heat radiating member 10 as shown in FIG. 6D.

  When mounting the semiconductor elements 30 and 40, as shown in FIG. 6E, the terminals 34a and 34b of the semiconductor element 30 are bonded to the wiring 21b exposed from the via hole 23 using the bonding member 50, and the terminals 34 c is bonded to the wiring 21 d on the surface of the wiring layer 20 by using the bonding member 50. Further, the terminals 41 a and 41 b of the semiconductor element 40 are bonded to the wiring 21 b exposed from the via hole 23 using the bonding member 50.

It is also possible to form the semiconductor device 1 using a method as shown in FIG.
As described above, the wiring layer 20 having the predetermined circuit pattern 21 is formed in advance, and the semiconductor elements 30 and 40 are mounted thereon, so that a predetermined circuit, here shown in FIG. A semiconductor device 1 having such an inverter circuit 100 is obtained. The semiconductor device 1 uses semiconductor elements 30 and 40 that are individually packaged before being mounted on the wiring layer 20. Therefore, when the semiconductor elements 30 and 40 are mounted on the wiring layer 20, the semiconductor device 1 can be operated as an inverter circuit in the example of FIG.

  Since the semiconductor elements 30 and 40 are individually packaged before mounting, each can be tested. Based on this test, only good products of the semiconductor elements 30 and 40 can be mounted on the wiring layer 20.

Further, since there is no connection process such as wire bonding or a resin sealing process after the semiconductor elements 30 and 40 are mounted, no defects due to such processes occur.
Although the inverter circuit 100 has been described as an example here, a desired circuit configuration can be realized by changing the circuit pattern 21 formed in advance in the wiring layer 20 and the semiconductor elements 30 and 40 to be mounted. Various semiconductor devices 1 can be obtained. It is possible to flexibly cope with the change of the circuit pattern 21 and the change of the semiconductor elements 30 and 40. Compared with a method for forming a semiconductor device using a lead frame with sealing, the semiconductor device 1 of various forms can be formed efficiently and flexibly.

  In the above description, the semiconductor device 1 having an inverter circuit is taken as an example, and the case where an FWD is connected in reverse parallel to the switching element as a component of the inverter circuit has been described. In providing the FWD, a diode having characteristics corresponding to the degree of reflux that may occur in the semiconductor device 1 is selected and provided in the package of the semiconductor element 30.

  For example, when applied to an inverter device that drives an electric motor at a variable speed, a commutation of a main current at the time of switching and a regenerative current in a regenerative mode from the motor flow, so even if these currents flow through the FWD, the loss is low , Etc. are required.

  On the other hand, when applied to an inverter device having a compressor as a load, the current in the regenerative mode is hardly generated from the compressor load. Since only a small amount of current that commutates the main current flows at the time of switching, the duty of the FWD is light when applied to an inverter device having a compressor as a load. Therefore, a diode having a small chip size and current capacity can be used as compared with a case where the present invention is applied to an inverter device that performs variable speed driving of an electric motor. Applications of compressors include air conditioners (air conditioners), refrigerators, and the like. From the viewpoint of energy saving, there is an increasing need for fine control by inverters in these applications.

  As described above, in the inverter device applied to a load such as a compressor whose FWD duty is light, the mounting of the FWD 32 on the semiconductor element 30 as shown in FIG. 1A is omitted, and as shown in FIG. Alternatively, a semiconductor element 30 on which one chip of RC-IGBT or MOSFET is mounted may be used.

At this time, the reverse conduction diode of the RC-IGBT has a light duty as described above, and therefore, a diode with a small arrangement with respect to the chip area may be used.
By applying a one-chip device to the semiconductor element 30, the area of the die pad 33a can be effectively utilized as shown in FIGS. That is, the portion where the FWD 32 is mounted as shown in FIGS. 2A and 2B can also be used as a mounting region for switching elements such as IGBTs and MOSFETs. In other words, if the mounting area is the same, a large IGBT can be mounted to increase the current capacity. If the current capacity is small, the mounting area is decreased and the semiconductor element 30 is reduced in size. be able to.

  In the above description, a flat plate is used as the heat radiating member 10. This is because it is easier to form the wiring layer 20 and to mount the semiconductor elements 30 and 40 when at least one main surface is flat.

  Further, as the other main surface of the heat radiating member 10, it is possible to use one provided with a plurality of fins 11 as shown in FIG. 7. The fin 11 can be applied in various forms such as a plate shape, a corrugated plate shape, and a pin shape.

  These fins 11 may be formed by grinding or fitting the other main surface of the heat radiating member 10 (the main surface opposite to the surface on which the semiconductor elements 30 and 40 are mounted). Alternatively, it may be formed by extruding a solid material through a formwork in which one main surface is flat and the fin 11 is formed on the other main surface.

  In the above description, the wiring layer 20 having the circuit pattern 21 having the three-layer structure is illustrated, but the number of wiring layers 20 and the circuit pattern 21 are not limited to this example. A wiring layer 20 having a predetermined number of layers and a circuit pattern 21 may be formed in accordance with the circuit configuration formed in the semiconductor device 1.

  By using a multilayer circuit pattern, the degree of freedom of wiring increases, and semiconductor elements other than those shown in the figure can be arranged. In addition, the layout of the external lead-out terminals of the semiconductor device 1 (not shown in FIG. 1) is also free.

  At this time, it is advantageous in terms of heat dissipation that the portion immediately below the semiconductor element 30 is in contact with the heat radiating member 10 through an insulating layer that is as thin as possible within a range in which insulation can be maintained. It is preferable to arrange only the circuit pattern and the insulating layer to which the back surface of the die pad 33a is connected and not arrange other circuit patterns.

Next, a second embodiment will be described.
FIG. 8 is an explanatory diagram of the semiconductor device according to the second embodiment.
The semiconductor device 60 shown in FIG. 8 includes other semiconductor elements in addition to the six semiconductor elements 30 including the switching elements and the two semiconductor elements 40 that control them, which constitute the inverter circuit 100. It has an area (circuit area) AR that is mounted and constitutes a predetermined circuit. The semiconductor device 60 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment in that it has such a circuit region AR.

  Various circuits can be configured in the circuit region AR of the semiconductor device 60. For example, a rectifier circuit, a brake circuit, an inrush current suppression circuit, a sensor circuit, a control circuit, and the like can be configured in the circuit area AR.

FIG. 9 is an example of a circuit diagram of the semiconductor device according to the second embodiment.
FIG. 9 illustrates a circuit in which a rectifier circuit 110, a brake circuit 120, an inrush current suppression circuit 130, a sensor circuit 140, and a control circuit 150 are added to the inverter circuit 100. These various circuits may be incorporated according to the application of the semiconductor device 60.

As shown in FIG. 8, the inverter circuit 100 is formed by semiconductor elements 30 and 40 mounted on a predetermined circuit pattern 21 of the wiring layer 20.
Similarly, the rectifier circuit 110 is configured by mounting a plurality of rectifier elements (diodes) on a predetermined circuit pattern in the circuit area AR of FIG. Then, AC power supplied from an AC power source (not shown) is rectified and converted to DC power, and the DC power is supplied to the inverter circuit 100 side.

  Although not shown in FIG. 8, a diode that constitutes a rectifier circuit is a resin-encapsulated diode as shown in FIG. Alternatively, depending on the number of input phases (single phase, three phase, etc.), and depending on whether full-wave rectification or half-wave rectification, the number of diodes to be connected can be selected and individually sealed. Alternatively, a resin-sealed one that is bridge-connected may be used.

  If the semiconductor elements 30 and 40 and the diodes for the rectifier circuit 110 are formed in a surface mount type package, these are arranged in a predetermined circuit pattern of the wiring layer 20 and then collectively by reflow soldering. Can be joined and connected.

  The brake circuit 120 has a configuration in which a rectifying element (diode) and a switching element (transistor) are combined. For example, when the output side of the semiconductor device 60 is connected to a motor, the brake circuit 120 is generated during the regenerative operation of the motor. Suppresses the voltage rise due to energy.

  The inrush current suppression circuit 130 has a thyristor and suppresses the inrush current of the DC intermediate capacitor. The inrush current suppression circuit 130 may be a parallel circuit of a charging resistor and a mechanical relay instead of such a thyristor.

The sensor circuit 140 includes, for example, a temperature detection thermistor, and the detection signal is transmitted to the semiconductor element 40 or the control circuit 150, for example.
The control circuit 150 is a control circuit for controlling the driving of the semiconductor element 40 that controls the semiconductor element 30.

  In the circuit area AR of the semiconductor device 60, all or at least one of such rectifier circuit 110, brake circuit 120, inrush current suppression circuit 130, sensor circuit 140, and control circuit 150 are used depending on the application of the semiconductor device 60. ,It is formed.

  The rectifier circuit 110, the brake circuit 120, the inrush current suppression circuit 130, the sensor circuit 140, and the control circuit 150 are each realized by one or a plurality of semiconductor elements and a circuit pattern of the wiring layer 20 on which the semiconductor elements are mounted. be able to. A predetermined number of semiconductor elements such as diodes, transistors, and thermistors are selected so that a desired circuit is formed in the semiconductor device 60, and the wiring layer 20 having a circuit pattern on which the semiconductor elements are mounted is formed. The circuit pattern of the wiring layer 20 can be formed according to the example of FIG. 4 or FIG. 6 according to the circuit configuration of the semiconductor device 60.

  As described above, if the components constituting these various circuits are also formed in a surface mount type package, they are arranged in a predetermined circuit pattern of the wiring layer 20 and joined together by reflow soldering. -Connections can be made.

  When the semiconductor device 60 is formed, first, the circuit pattern 21 for the inverter circuit 100 and the circuit pattern of the circuit region AR corresponding to the circuit configuration of the semiconductor device 60 are formed on the heat dissipation member 10 with reference to FIG. Or it forms according to the example of FIG. Then, a semiconductor element for a circuit to be added is mounted on the wiring layer 20 together with the semiconductor elements 30 and 40 for the inverter circuit 100. The semiconductor element for a circuit to be added is mounted on the wiring layer 20 via a bonding member such as solder, like the semiconductor elements 30 and 40.

  In the case of such a semiconductor device 60 as well, as in the semiconductor device 1 according to the first embodiment, a desired circuit can be obtained by changing a circuit pattern formed in advance in the wiring layer 20 and a semiconductor element to be mounted. The configuration can be realized, and various semiconductor devices 60 can be obtained. In addition, since a packaged semiconductor element can be used, it is possible to efficiently and flexibly form various types of semiconductor devices 60 as compared with a method for forming a semiconductor device using a lead frame with sealing. Is possible.

Next, a third embodiment will be described.
FIG. 10 is an explanatory diagram of the semiconductor device according to the third embodiment.
As shown in FIG. 10A, the semiconductor device 70 includes three semiconductor elements 80. In this semiconductor device 70, the inverter circuit 100 as shown in FIG. 3 is configured using these three semiconductor elements 80. The semiconductor device 70 according to the third embodiment is different from the semiconductor device 1 according to the first embodiment in this respect.

  As shown in FIG. 10B, each semiconductor element 80 used in the semiconductor device 70 includes two switching elements such as IGBTs, rectifying elements such as FWDs connected in antiparallel to these two switching elements, and A control element (control circuit) that controls driving of the two switching elements is included.

  The semiconductor element 80 may include a switching element, a rectifying element, and a control element as separate chips, a chip in which the switching element and the rectifying element are integrated, and a control element chip, or You may have the chip | tip which integrated all the switching elements, the rectifier elements, and the control elements. Such a chip is sealed with a sealing resin to constitute a semiconductor element 80.

Each semiconductor element 80 may be configured not to include a rectifying element such as an FWD depending on the application of the semiconductor device 70 or the like.
The semiconductor device 70 having the inverter circuit 100 is obtained by using three semiconductor elements 80 as described above, forming a predetermined circuit pattern on the wiring layer 20 and mounting the three semiconductor elements 80.

  Although not shown here, each semiconductor element 80 is provided with a terminal exposed from the sealing resin that seals the chip, like the semiconductor elements 30 and 40 described in the first embodiment. Each semiconductor element 80 is mounted on the wiring layer 20 via its terminal and is electrically connected to the circuit pattern. At this time, each semiconductor element 80 is mounted on the wiring layer 20 via a bonding member such as solder, like the semiconductor elements 30 and 40 described in the first embodiment. The circuit pattern of the wiring layer 20 of the semiconductor device 70 can be formed according to the example of FIG. 4 or FIG. 6 so that the pattern arrangement is such that the inverter circuit 100 is configured when the semiconductor element 80 is mounted. .

  By using the semiconductor element 80 having the above-described configuration, the number of parts constituting the inverter circuit 100 can be reduced. As a result, a small semiconductor device 70 can be formed.

  Further, a rectifier circuit 110, a brake circuit 120, an inrush current suppression circuit 130, a sensor circuit 140, and a control circuit 150 as shown in FIG. 9 may be added to the semiconductor device 70 having such an inverter circuit 100. it can. In the semiconductor device 70, the inverter circuit 100 is configured by using the three semiconductor elements 80. Therefore, even when another circuit such as the rectifier circuit 110 is added, the increase in size can be suppressed.

Although the semiconductor devices 1, 60, and 70 have been described above, these semiconductor devices 1, 60, and 70 can be further provided with terminals and mounted on other circuit boards using the terminals.
FIG. 11 is a diagram illustrating an example of a mounting form of a semiconductor device on a circuit board.

Here, as an example, the case where the semiconductor device 1 according to the first embodiment is mounted on the circuit board 90 will be described.
First, as shown in FIG. 11A, the semiconductor device 1 is provided with a pin terminal 2 used for connection to the circuit board 90. Here, a plurality of pin terminals 2 are provided. Each pin terminal 2 is provided so as to be electrically connected to a predetermined portion of the circuit pattern 21 of the wiring layer 20.

  A predetermined circuit pattern (not shown) is provided on the circuit board 90 on which the semiconductor device 1 is mounted. Further, the circuit board 90 is penetrated through the pin terminal 2 as shown in FIG. 11A at a position corresponding to the circuit pattern at a position corresponding to the pin terminal 2 of the semiconductor device 1 to be mounted. A hole 91 is provided.

  When the semiconductor device 1 is mounted on the circuit board 90, the surface of the semiconductor device 1 where the pin terminals 2 are disposed is opposed to a predetermined surface of the circuit board 90, and the pin terminals 2 of the semiconductor device 1 are inserted into the through holes of the circuit board 90. 91 is inserted. Thereafter, the pin terminal 2 inserted into the through hole 91 is joined to the circuit board 90 by a method such as soldering, whereby the semiconductor device 1 is mounted on the circuit board 90 and the circuit of the circuit board 90 is connected via the pin terminal 2. A device electrically connected to the pattern can be obtained.

  Although the case where the semiconductor device 1 according to the first embodiment is mounted on the circuit board 90 is illustrated here, the semiconductor devices 60 and 70 according to the second and third embodiments are also shown in this example. It can be mounted on the circuit board 90 in the same manner. That is, a pin terminal connected to the circuit pattern of the wiring layer 20 of the semiconductor device 60 or the semiconductor device 70 is provided, and the pin terminal is inserted and joined to the through hole 91 of the circuit board 90, so that the semiconductor device 60 or the semiconductor A device in which the device 70 is mounted on the circuit board 90 can be obtained.

  Alternatively, the tip of the pin terminal 2 is formed in advance to form a bent portion, and the bent portion is joined to the circuit pattern of the circuit board 90, so that the semiconductor device 1 can be surface mounted.

  In the above description, the inverter circuit or the circuit including the inverter circuit is formed on the heat dissipation member, but the circuit configuration is not limited to this. A semiconductor device having various functions can be realized by changing the circuit pattern of the wiring layer and the semiconductor element mounted on the wiring layer. As described above, various semiconductor devices can be realized by changing the circuit pattern of the wiring layer and the semiconductor element. Therefore, the formation of various semiconductor devices can be handled quickly and flexibly.

  Moreover, in each example of FIG.1, FIG8, FIG.10 etc., although the heat radiating member 10 and the wiring layer 20 were formed in the rectangle, it does not restrict to this. It suffices if a multilayer circuit pattern can be formed on the heat dissipation member 10 and the semiconductor elements 30 and 40 can be mounted on the circuit pattern. Since there is no wire bonding or resin sealing process after the semiconductor elements 30 and 40 are mounted, there is no restriction by shape. For example, as shown in FIG. 11, it can be changed as appropriate according to the shape of the empty space of the circuit board 90 on which the semiconductor device 1 is mounted.

1, 60, 70 Semiconductor device 2 Pin terminal 10 Heat radiation member 11 Fin 20 Wiring layer 21 Circuit pattern 21A Circuit portion 21a, 21c Via 21b, 21d, 21e Wiring 22, 22a, 22b, 22c Insulating layer 23 Via hole 30, 40, 80 Semiconductor element 31 IGBT
32 FWD
36 RC-IGBT
33 Substrate 34a, 34b, 34c, 41a, 41b Terminal 37 Wire 35 Sealing resin 50 Joining member 90 Circuit board 91 Through hole 100 Inverter circuit 110 Rectifier circuit 120 Brake circuit 130 Inrush current suppression circuit 140 Sensor circuit 150 Control circuit

Claims (8)

A heat dissipating member;
A wiring layer formed on one main surface of the heat dissipating member, and comprising a conductor layer and an insulating layer;
An external lead terminal connected to the conductor layer;
A semiconductor chip formed by resin-sealing a semiconductor chip having both a switching function for passing and blocking current and a function for reducing current capacity compared to the switching function and conducting in a direction opposite to the direction for blocking current . 1 semiconductor element;
A second semiconductor element formed by resin-sealing a semiconductor chip on which a driving circuit for driving the first semiconductor element is integrated ,
A semiconductor device , wherein the first semiconductor element and the second semiconductor element are mounted on a conductor layer exposed from the insulating layer and connected to a compressor as an inverter device.   The semiconductor device according to claim 1, wherein an inverter circuit is configured using the wiring layer and the first semiconductor element.   3. The semiconductor device according to claim 1, wherein a third semiconductor element storing a semiconductor chip having a rectifying function is connected to the conductor layer to constitute a rectifier circuit connected to a preceding stage of the inverter circuit. .   The semiconductor device according to claim 1, wherein the wiring layer, the first semiconductor element, and the second semiconductor element are bonded using a bonding member.   5. The semiconductor device according to claim 1, wherein the wiring layer includes a via-shaped conductor layer extending from directly below the first semiconductor element toward the heat dissipation member.   The semiconductor device according to claim 1, wherein the heat dissipation member includes a fin on a main surface opposite to a main surface on which the wiring layer is formed.   Forming a wiring layer composed of a conductor layer and an insulating layer on the heat dissipation member;
  Forming an external lead terminal connected to the conductor layer;
  A semiconductor chip formed by resin-sealing a semiconductor chip having both a switching function for passing and blocking current and a function for reducing current capacity compared to the switching function and conducting in a direction opposite to the direction for blocking current. A first semiconductor element and a second semiconductor element formed by resin-sealing a semiconductor chip on which a driving circuit for driving the first semiconductor element is integrated so as to be electrically connected to the conductor layer Mounting on the wiring layer;
  And a method of manufacturing a semiconductor device, wherein the inverter device is connected to a compressor.   The method for mounting a semiconductor device according to claim 1,
  A method for mounting a semiconductor device, wherein the external lead-out terminal is connected to another circuit board while the first semiconductor element and the second semiconductor element are mounted on the conductor layer.

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