JP5358460B2 - Small low-loss inductor element - Google Patents

Description

  The present invention relates to a small and low loss inductor element formed on a semiconductor substrate.

  In recent years, various high-speed digital wireless systems such as a wireless local area network (LAN), Bluetooth, and terrestrial digital TV have been put into practical use. In the case of digital semiconductor integrated circuits, especially those that operate at a high speed of GHz or higher, analog techniques similar to those for wireless circuits are used. In such a circuit, an on-chip inductor formed on a semiconductor substrate is used as a passive element. This inductor has a shape in which a metal wiring on a semiconductor is spirally wound and has an inductance of about several nH at most, but is a practical inductance value for a circuit operating at a frequency of about GHz. .

  In such a high-frequency / wireless circuit, a plurality of inductor elements are usually integrated. However, the size of one inductor element is as large as several tens of μm to several hundreds of μm square, leading to an increase in chip area.

  As a method for reducing the area of the inductor, a structure as shown in FIG. 13 (refer to Patent Document 1, hereinafter referred to as a multilayer series method) has been proposed. This structure can increase the overall inductance value by forming a spiral-shaped inductor in a number of wiring layers using a multilayer wiring structure and connecting the inductors in series. Thereby, when the number of wiring layers is n, the chip area can be reduced to about 1 / n of an inductor having only one layer.

  However, this shape has a problem that the parasitic capacitance of the entire inductor increases due to the capacitance between the upper and lower wirings.

  In FIG. 13, all the inductor wirings were at the same position on the plane, but in order to reduce the wiring capacity, a method of shifting the position of the inductor wiring on the plane for each layer as shown in FIG. 14 was proposed. (See Patent Document 2 and Patent Document 3). In the drawing, the upper layer wiring is arranged so as to pass over the gap between the lower layer wiring and the wiring.

  However, in general, since the inductor wiring has a wiring width larger than the wiring interval, the upper and lower inductor wirings have overlapping portions as shown in FIG. For this reason, the wiring capacity could not be reduced so much.

  Therefore, as a measure for reducing the wiring capacity, a structure shown in FIG. 16 has been proposed (see Patent Document 4 and Patent Document 5, hereinafter referred to as a 3D solenoid).

  In this structure, there is a break in the wiring every round, and the via moves to the upper or lower wiring via.

  Here, the parasitic capacitance of the laminated spiral and the 3D solenoid will be described.

  FIG. 17 is a schematic diagram of a cross section of the wiring.

  In inductor wiring, a wide wiring is generally used in order to reduce the series resistance of the wiring. Therefore, the wiring width w is larger than the wiring thickness t. For this reason, if the dielectric constant of the insulator of the wiring layer is the same throughout the wiring layer, the capacitance Cv between the upper and lower sides of the wiring is larger than the capacitance Ch between the left and right. In other words, the dominant component of the parasitic capacitance of the inductor wiring in a general multilayer inductor is the capacitance Cv between the upper and lower sides of the wiring. Furthermore, the capacitance other than Cv can be further reduced by increasing the interval s between the wirings arranged side by side rather than the interlayer film thickness h of the wiring.

  18 and 19 are equivalent circuits of the inductor including Cv, FIG. 18 is the equivalent circuit of FIG. 13, and FIG. 19 is the equivalent circuit of FIG.

  In FIG. 18, since Cv is directly connected to IN and OUT, Cv is directly observed from the outside of the inductor. On the other hand, in FIG. 19, since Cv is connected to the middle of the inductor wiring, Cv is not directly observed from the outside of the inductor, and this influence becomes small. That is, the effective parasitic capacitance viewed from both ends of the inductor is smaller in the 3D solenoid structure of FIG. 19, that is, FIG.

  Although the 3D solenoid structure can reduce the parasitic capacitance in this way, it is necessary to connect the inductor wiring up and down every round, so that the upper and lower inductor wiring must be at the same position in the horizontal plane. In the wiring of the multilayer structure on the silicon substrate, the thickness of the wiring closer to the silicon substrate (lower layer) is usually thinner and the distance from the substrate, that is, the wiring of the upper layer is thicker. The minimum wiring pitch that can be manufactured in accordance with this, that is, the wiring width and the wiring interval are narrower in the lower layer, and the upper layer wiring has a wider pitch. As described above, wiring layers having different pitches are mixed in the wiring having a multilayer structure.

  However, in the 3D solenoid structure, a structure that spans wiring layers having different wiring pitches cannot be created due to the above-described restrictions. For this reason, even in a multilayer wiring structure, the number of wiring layers that can be substantially used is reduced, and the wiring use efficiency is reduced, leading to an increase in chip area.

  In the on-chip inductor, the Q value is an important performance in addition to the inductance value. This Q value increases as the series resistance of the inductor is lower. The wiring used for the on-chip inductor has a high resistance because of a thin film, and generally has a low Q value.

  As a method for solving this, a structure as shown in FIG. 20 (see Patent Document 6) has been proposed. FIG. 20 is a cross section of the inductor wiring. However, by connecting the wirings of a plurality of wiring layers by vias and connecting them in parallel as shown in FIG. 20, the substantial wiring resistance can be lowered. In FIG. 20, vias are arranged over the entire length of the wiring between the upper, middle, and lower layers, and the wiring layers are connected in parallel. As a result, the series resistance can be lowered to 1/3 when only one layer is used.

However, this structure has a problem that the chip area becomes large because the total wiring length cannot be increased even if a multilayer wiring layer is used.
Japanese Utility Model Publication No. 60-136156 JP-A 61-265857 Japanese Patent Laid-Open No. 03-089548 Japanese Patent No. 2976926 Japanese Patent Application No. 2006-209915 Japanese Patent No. 2986081

  However, the conventional technique has a problem that the laminated spiral structure has a large parasitic capacitance. In addition, although the 3D solenoid structure has a small parasitic capacitance, there is a problem in that the use efficiency of the wiring is low because a structure that spans different wiring layers cannot be created.

  Therefore, the present invention has been made in view of the above-mentioned problems, and an example of the object thereof is to reduce the parasitic capacitance of the inductor wiring as well as the wiring layers having different pitches, similarly to the 3D solenoid structure. Therefore, it is possible to provide a small-sized and low-loss inductor element capable of increasing the use efficiency of the wiring and reducing the chip area.

  In order to solve the above-described problems, an inductor element of the present invention is an inductor element in a wiring layer in an insulating film on a semiconductor substrate, and the inductor wiring that is a peripheral wiring of the inductor element includes at least two Cross sections of the wiring layer are formed at different wiring pitches, and one end of the two wiring layers has an end portion in the circumferential wiring that circulates around the circumference approximately one or two times. Connected to the end of the peripheral wiring of the other wiring layer directly above or directly below by the via, and the peripheral wiring connected by the via has the same current direction in the wiring layer Features.

  According to the present invention, at least two wiring layers are formed at different wiring pitches in the cross section, and therefore an inductor that extends over wiring layers having different wiring pitches can be formed.

  According to the present invention, similar to the 3D solenoid structure, the parasitic capacitance of the inductor wiring can be reduced, and wirings of wiring layers having different pitches can be mixed. The area can be reduced.

  The above-described object and other objects, features, and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.

It is a figure which shows the top view of the inductor structure which concerns on embodiment of this invention, and sectional drawing of the part of (alpha)-(beta). It is a figure which shows embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a figure which shows other embodiment of this invention. It is a layout for demonstrating the effect of the conventional inductor. It is a layout diagram for demonstrating the effect of the inductor of this invention. It is a figure which compares the series inductance value of an inductor. It is a figure which compares the Q value of an inductor. It is a bird's-eye view of the conventional multilayer spiral inductor. It is a top view of the multilayer spiral inductor which shifted the conventional wiring position. It is sectional drawing of the multilayer spiral inductor which shifted the conventional wiring position. It is a bird's-eye view of the conventional 3D solenoid inductor. It is sectional drawing of the conventional inductor. It is a figure explaining the parasitic capacitance in FIG. It is a figure explaining the parasitic capacitance in FIG. It is sectional drawing of the conventional inductor wiring.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, similar constituent elements are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  Embodiment 1 suitable for the present invention will be described with reference to the drawings. In FIG. 1, an inductor element according to the present embodiment is an inductor element in a wiring layer in an insulating film on a semiconductor substrate, and an inductor wiring that is a circumferential wiring of the inductor element includes at least two wiring layers ( The lower layer and the upper layer are formed with different wiring pitches, and one of the two wiring layers (the lower layer and the upper layer) (lower layer or upper layer) has a circumference of approximately one turn (or approximately two turns). There is an end (A or B) in the peripheral wiring, and the end is connected to the end of the peripheral wiring of the other wiring layer (upper layer or lower layer) immediately above or directly below by the via. An inductor element characterized in that the connected circumferential wirings (lower layer and upper layer) have the same current direction (clockwise) in each wiring layer.

  This will be described in more detail with reference to FIG. FIG. 1 is a top view of the inductor structure of the present invention and a cross-sectional view of the α-β portion in the figure.

  FIG. 1 shows a three-turn inductor that straddles the upper and lower wiring layers. Here, the wiring pitch refers to the distance between the centers of two wirings between wirings in the same layer.

  As shown in the cross-sectional view of FIG. 1, the upper layer wiring is wider than the lower layer wiring. Further, in FIG. 1, the upper layer wiring is thick and the upper layer wiring has a wide wiring pitch. That is, the upper layer wiring has a smaller number of circuit wiring than the lower layer wiring. The number of the surrounding wirings in the upper wiring layer and the number of the surrounding wirings in the lower wiring layer are different from each other, and the number of the surrounding wirings in the lower wiring layer is larger. This is because the upper layer wiring is formed on an uneven surface as compared with the lower layer wiring, and thus needs to be formed thicker. When the circumferential wirings are stacked vertically in a limited area, the number of upper layer wirings needs to be smaller than the number of lower layer wirings.

  In this way, even if the number of upper-layer circuit wirings is smaller than the number of lower-layer circuit wirings, the upper-layer circuit wiring width is larger than the lower-layer circuit wiring width. Since an overlapping portion is generated, the lower layer and the upper layer can be connected via vias. Further, the parasitic capacitance can be reduced in the non-overlapping portion.

  In this inductor, a signal input from IN moves around the lower outer wiring substantially once and then moves to the upper wiring through a via at point A. This via is formed in the above-described overlapping portion of the upper and lower wirings. This signal then goes around the upper layer wiring approximately once, then moves to the lower layer wiring via a via at point B, and then outputs from the OUT after making approximately one round of the lower layer inner wiring. Here, the point B is also formed in the overlapping portion of the upper and lower wirings. Further, “substantially one round” means that the purpose is to form a coil and it is not a complete round.

  In this way, by using the overlapping portion of the upper and lower wirings, it is possible to form an inductor that spans wiring layers having different wiring pitches.

  The arrows in the cross-sectional view of FIG. 1 indicate the movement of signals between inductor turns.

  In the cross-sectional view of FIG. 1, the signal moves between the upper and lower wirings in the order of the cross section of FIG.

  In the following, the movement of the signal every time the inductor wiring is turned around once is indicated by an arrow in the sectional view.

  Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of the inductor wiring when the lower wiring layer has a plurality of layers. In FIG. 2, the signal path between the laps is indicated by an arrow.

  In FIG. 2, there are a lower layer wiring of the metal wirings M1 to M4 and an upper layer wiring of the metal wiring M5, and the wiring pitch of the metal wiring M5 is larger than that of the metal wirings M1 to M4. Be thicker.

  Also in this case, as indicated by the arrow in FIG. 2, the signal entered from IN enters the metal wiring M5 at the point A while circling the metal wirings M1 to M4, and goes around the metal wiring M5 substantially once before the lower layer wiring. Returning to the point B, the metal wire M1 is turned around the metal wire M1 approximately twice at the point B and moved to the point C of the inner wiring. Next, the metal wire M5 enters the metal wire M5 at the point D while circling the metal wires M1 to M4, and moves around the metal wire M5 approximately two times to the point E of the inner wiring. Furthermore, it returns to the lower layer wiring and is output at OUT. Here, “substantially two rounds” is not intended to form two complete turns for the purpose of forming a coil close to two rounds.

  In this way, by adjusting the number of turns in the same wiring layer in accordance with the difference in pitch between the upper layer and lower layer wirings, inductors that extend over wiring layers having different wiring pitches can be formed.

  Next, a third embodiment of the present invention is shown in FIG. FIG. 3 shows the case where the thickness of each wiring layer is the same and only the wiring pitch is different. The signal flow is the same as in FIG.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of the inductor wiring when the upper wiring layer has a plurality of layers. In FIG. 4, the signal path between the laps is indicated by an arrow.

  As shown in FIG. 4, there are a lower layer wiring of the metal wiring M1 and an upper layer wiring of the metal wirings M2 to M5, and the wiring pitch of the metal wiring M1 is smaller than the metal wirings M1 to M4.

  Also in this case, as indicated by an arrow in FIG. 4, a signal input from IN is transmitted around the metal wiring M1 by going around the metal wiring M1 and entering the metal wiring M2 at the point A, and circulating around the metal wirings M2 to M5. At point, the metal wiring M5 is rotated approximately two times and moved to the point C of the inner wiring. Further, it travels around the metal wirings M5 to M1 and is output at OUT.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view of the inductor wiring when the upper and lower wiring layers are both a plurality of layers. Further, in FIG. 5, the signal path between each round is indicated by an arrow.

  As shown in FIG. 5, there are a lower layer wiring of the metal wirings M1 to M4 and an upper layer wiring of the metal wirings M5 to M6, and the wiring pitch of the metal wirings M1 to M4 is smaller than the metal wirings M5 to M6.

  In FIG. 5, the metal wirings M1 to M4 make approximately four turns per layer, and the metal wirings M5 to M6 make approximately three turns per layer. As indicated by the arrows in FIG. 5, the signal entered from IN moves through the wiring layer while going around each layer approximately one turn up to point F, but does not move to the metal wiring M5 on the way from point F to the upper layer. Instead, it is output from OUT.

  A sixth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view of the inductor wiring when the upper and lower wiring layers are both a plurality of layers. Further, the signal path between the laps is indicated by an arrow.

  In FIG. 6, there are a lower layer wiring of the metal wirings M1 to M4 and an upper layer wiring of the metal wirings M5 to M6, and the wiring pitch of the metal wirings M1 to M4 is smaller than the metal wirings M5 to M6.

  In FIG. 6, the metal wirings M1 to M4 are turned about 8 turns per layer, and the metal wirings M5 to M6 are turned about 6 turns per layer. As indicated by the arrows in FIG. 6, the signal input from IN moves through the wiring layer while going around each layer up to point G, but does not move to the upper metal wiring M5 at point G. Move to H point on the inner wiring.

  As a result, the pitch difference between the upper layer and lower layer wirings is filled, and thereafter, the wiring layer is moved while going around each layer substantially once, and output from OUT.

  2 to 5, the wiring pitch is constant in the same wiring layer, but in FIG. 6, the distance between the point D and the point K is wider than the other parts, and thus the same. It is also possible to arrange wirings with different pitches in the wiring layer.

  Next, a seventh embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 7, in the multilayer wiring structure, the upper layer wiring is generally wider in pitch and thicker than the lower layer wiring. For this reason, the wiring resistance of the upper layer wiring is lower than that of the lower layer wiring.

  However, in the 3D solenoid structure, since the upper layer wiring and the lower layer wiring are connected in series, the series resistance of the whole inductor is limited by the resistance of the lower layer wiring and cannot be sufficiently reduced. Therefore, even in the 3D solenoid structure, it is possible to lower the wiring resistance by partially connecting the inductor wirings of a plurality of wiring layers in parallel (backing wiring).

  In FIG. 7, the metal wirings M1 to M4 are the lower layer wirings and the metal wiring M5 is the upper layer wiring. However, the metal wiring M1 and the metal wiring M2, and the metal wiring M3 and the metal wiring M4 are set as one set, respectively. The wiring of each layer is connected in parallel by connecting vias up and down as shown in FIG.

  As a result, the wiring resistance of the lower layer wiring is substantially halved, so that the wiring resistance of the entire inductor can be reduced.

  Next, an eighth embodiment of the present invention will be described with reference to FIG.

  In FIG. 8, metal wirings M1 to M3 are lower layer wirings, and metal wirings M4 to M5 are upper layer wirings.

  In FIG. 8, it is assumed that the upper layer wiring has a larger wiring film thickness and lower resistance than the lower layer wiring. Therefore, the lower layer wiring is a set of 3 layers, the upper layer wiring is a set of 2 layers, and the lower resistance upper layer wiring reduces the number of wiring layers so that the wiring resistance around each inductor is made uniform. can do.

  Next, the effect of the present invention is shown by electromagnetic field simulation.

  The process assumes a 90-nm node 6-layer Cu wiring, the metal wirings M2 to M5 are wiring layers having the same pitch, and the metal wiring M6 is a wiring layer having a wider pitch than these.

  9 and 10 are a plan view and a cross-sectional view taken along α-β of the inductor used in the simulation.

  In the conventional structure of FIG. 9, the inductor wiring is composed only of the metal wirings M2 to M5. The metal wiring M2 and the metal wiring M3, and the metal wiring M4 and the metal wiring M5 are set as one set. The wiring of each layer is connected to the upper and lower vias as shown in FIG.

  On the other hand, in the present invention of FIG. 10, the inductor wiring is composed of metal wirings M2 to M6, and the metal wiring M2 and the metal wiring M3, and the metal wiring M4 and the metal wiring M5 are used as the backing wiring, respectively. Only M6 has no backing.

  FIG. 11 shows the series inductance values of the conventional method and the inductor of the present invention obtained by simulation.

  As shown in FIG. 11, in the low frequency region, the inductance value of the conventional method and the inductance value of the present invention are substantially the same. However, when compared in terms of area, the conventional method is 342 μm 2 and the present invention is 240 μm 2, so the area can be reduced by about 30%.

  FIG. 12 shows the Q value of the conventional method and the present invention obtained by simulation.

  As shown in FIG. 12, the Q value of the conventional method and the present invention can be substantially the same value.

  As described above, according to the present invention, the area can be reduced without degrading the characteristics of the conventional 3D solenoid inductor.

Note that these are examples of the present invention, and various configurations other than those described above can be employed.
(1) A small low-loss inductor element of the present invention is a small low-loss inductor element in a wiring layer in an insulating film on a semiconductor substrate,
Inductor wiring, which is the wiring of the inductor element, is formed in at least two different wiring pitches in the plurality of wiring layer layers, and each time the inductor wiring of each wiring layer makes one or two turns around the circumference. The wiring has a cutting portion, and is connected to a surrounding wiring directly above or below by a via at the cutting portion, and the wirings connected by the via have the same current direction in the wiring. And

(2) The small low-loss inductor element of the present invention is a small low-loss inductor element in a wiring layer in an insulating film on a semiconductor substrate. The inductor wiring that is the wiring of the inductor element includes at least two types of inductor wiring. Formed with at least two different wiring pitches in wiring layers with different minimum wiring pitches, the inductor wiring of each wiring layer has a cut portion in the wiring every time it makes one or two rounds, The cut portion is connected to a surrounding wiring immediately above or below by a via, and the wirings connected by the via have the same current direction in the wiring.

(3) In the small low-loss inductor element described above,
The small and low loss inductor element, wherein the wiring layers of the plurality of wiring pitches have different thicknesses for the wiring layers having different wiring pitches.

(4) In the small low-loss inductor element described above,
A small, low-loss inductor element characterized in that vias are formed at portions where the upper and lower wirings overlap each other at the connection portions where the upper and lower wiring layers have different wiring pitches.

(5) In the small low-loss inductor element described above,
The inductor wiring is characterized in that the number of turns in the same layer of the narrow pitch wiring layer is larger than the number of turns in the same layer of the wide pitch wiring layer.

(6) In the small low-loss inductor element described above,
The inductor wiring does not have a via between the wide pitch wiring layer and the wide pitch wiring layer in the same pitch wiring layer in the narrow pitch wiring layer. A small low-loss inductor element characterized by having a portion connected to the adjacent inductor wiring.

(7) In the small low-loss inductor element described above,
The inductor wiring includes a portion in which a plurality of wiring layers adjacent in the vertical direction are connected by the vias so that the plurality of wiring layers are connected in parallel to form an integral wiring. Compact low-loss inductor element.

(8) In the small low-loss inductor element described above,
Among the plurality of wiring layers, the thin layer of the wiring film has a smaller number of wiring layers constituting the part connected in parallel and integrated than the thick layer of wiring. Low loss inductor element.

This application claims the priority on the basis of Japanese application 2008-038410 for which it applied on February 20, 2008, and takes in those the indications of all here.
Hereinafter, examples of the reference form will be added.
1. An inductor element in a wiring layer in an insulating film on a semiconductor substrate,
Inductor wiring, which is a circular wiring of the inductor element, is formed at different wiring pitches in cross sections of at least two of the wiring layers, and the circumference of one of the two wiring layers is approximately 1 to 2 around the periphery. There is an end portion in the surrounding wiring that circulates, and the end portion is connected to the end portion of the surrounding wiring of the other wiring layer directly above or directly below by a via,
The inductor element, wherein the circumferential wirings connected by the vias have the same current direction in the wiring layers.
2. In the inductor element according to 1,
An upper layer wiring that is a circuit wiring of one of the two wiring layers;
With the lower layer wiring that is the circuit wiring of the other wiring layer,
The inductor element, wherein the number of the lower layer circuit lines is larger than the number of the upper layer circuit lines.
3. In the inductor element according to 2,
The inductor element, wherein a wiring width of the upper layer wiring is larger than a wiring width of the lower layer wiring.
4). In the inductor element according to any one of 1 to 3,
The inductor element, wherein the wiring layer having the wiring pitch has a different film thickness for each wiring layer having the different wiring pitch.
5. In the inductor element according to any one of 1 to 4,
The inductor element, wherein the connection portion of the portion where the wiring pitches of the upper and lower wiring layers are different has the via formed in a portion where the upper and lower wires overlap at the cut portion.
6). In the inductor element according to any one of 1 to 5,
The inductor element, wherein the number of turns in the wiring layer with the narrow wiring pitch is greater than the number of turns in the wiring layer with the wide wiring pitch.
7). In the inductor element according to 6,
The inductor wiring is the same as the inductor wiring in the wiring layer adjacent to the upper and lower sides of the wide pitch wiring layer in the narrow pitch wiring layer without the via between the wide pitch wiring layer. An inductor element comprising a portion connected to the adjacent inductor wiring in a wiring layer.
8). In the inductor element according to any one of 1 to 5,
The inductor wiring has a portion in which a plurality of wiring layers adjacent in the vertical direction are connected by the vias so that the plurality of wiring layers are connected in parallel to form an integral wiring. Inductor element.
9. In the inductor element according to 8,
Among the plurality of wiring layers, an inductor having a thin wiring film thickness has a larger number of the wiring layers constituting a unit connected and connected in parallel than a thick wiring film layer element.

Claims (12)

An inductor element having at least three turns disposed in a plurality of wiring layers on a semiconductor substrate,
The inductor element is
Each of the first and second round wirings formed in the first wiring layer;
A third round wiring of one round formed in the second wiring layer located above the first wiring layer;
The second circuit wiring is disposed so as to circulate inside the first circuit wiring,
One end of the first peripheral wiring and one end of the third peripheral wiring are connected to each other by a first via, and one end of the second peripheral wiring and the other of the third peripheral wiring The first peripheral wiring, the second peripheral wiring, and the third peripheral wiring form a continuous three-turn peripheral wiring by being connected to each other by a second via. And
The continuous winding of three windings circulates while maintaining the same winding direction,
The inductor element , wherein a wiring pitch in the first wiring layer and a wiring pitch in the second wiring layer are different . The inductor element according to claim 1,
  An inductor element having at least one third wiring layer in which the first and second peripheral wirings are formed at the same wiring pitch as the first wiring layer below the first wiring layer. In the inductor element according to claim 1 or 2,
  An inductor element having at least one fourth wiring layer in which the third circuit wiring is formed at the same wiring pitch as the second wiring layer above the second wiring layer. In the inductor element according to claim 3,
The inductor element, wherein the number of layers of the first wiring layer and the third wiring layer is larger than the number of layers of the second wiring layer and the fourth wiring layer . The inductor element according to claim 1 , wherein
The inductor element, wherein a wiring width of the third peripheral wiring is larger than a wiring width of the first and second peripheral wirings. The inductor element according to any one of claims 1 to 5,
The inductor element , wherein a thickness of the wiring layer in which the first and second peripheral wirings are formed is different from a thickness of the wiring layer in which the third peripheral wiring is formed . The inductor element according to any one of claims 1 to 6,
In a plan view, at least a part of the first peripheral wiring and the second peripheral wiring formed in the first wiring layer is the third peripheral wiring formed in the second wiring layer. Overlap,
Inductor element characterized in that, in the overlapping portion, the first and third circumferential wirings, and the second and third circumferential wirings are connected to each other by vias. . In the inductor element according to claim 2,
In plan view, the first peripheral wiring and the second peripheral wiring formed in the first wiring layer are respectively the first peripheral wiring and the second peripheral wiring formed in the third wiring layer. It overlaps with the circuit wiring of 2,
In the overlapping portion, the first circumferential wiring and the second circumferential wiring are connected to each other by vias .   In the inductor element according to claim 3,
  In plan view, the third circuit wiring formed in the second wiring layer overlaps the third circuit wiring formed in the fourth wiring layer,
  In the overlapping portion, the third circumferential wirings are connected to each other by vias.   The inductor element according to any one of claims 1 to 9,
  In the first wiring layer, another circuit wiring is further formed,
  In the second wiring layer, in a plan view, other peripheral wirings that are at least partially overlapped with the other peripheral wirings formed in the first wiring layer are formed,
  The inductor element, wherein the number of the surrounding wirings formed in the first wiring layer is larger than the number of the surrounding wirings formed in the second wiring layer.   The inductor element according to claim 10,
  Among the plurality of surrounding wirings formed in the second wiring layer, those connected to other surrounding wirings formed in the second wiring layer in the second wiring layer are included. Inductor element characterized by that.   The inductor element according to any one of claims 1 to 11,
  The first circuit wiring circulates outside the second circuit wiring while maintaining a constant wiring pitch between the second circuit wiring and the second circuit wiring,
  The width of the third circuit wiring is larger than the width of the gap existing between the first circuit wiring and the second circuit wiring,
  While the third circuit wiring is maintained in a state of overlapping with at least a part of the first circuit wiring and at least a part of the second circuit wiring in plan view, the first circuit wiring and An inductor element that circulates along the second circumferential wiring.

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