JP5358287B2 - Parallel computing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel computation apparatus that facilitates executing a structured program having a plurality of nests. <P>SOLUTION: In the parallel computation apparatus, each of a plurality of arithmetic processors performs parallel arithmetic processing by use of a plurality of subprocessors. The subprocessor (SPE) 102A includes: an ALU (Arithmetic and Logic Unit) 95A performing arithmetic processing of input data based on control instructions; a G flag stack 11 sequentially accumulating flag information based on results performed with the arithmetic processing; and an SPE control unit 199A making the ALU 95A perform the arithmetic processing based on composition flag information composed with the accumulated flag information by a composition part 19. The subprocessor 102B includes an ALU 95B performing the arithmetic processing of input data based on the control instructions; and an SPE control unit 199B making the ALU 95B perform the arithmetic processing based on the composition flag composed by the composition part 19. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a parallel computing device.

  In recent years, the performance of general-purpose processors (CPU (Central Processing Unit), etc.) has improved dramatically due to advances in semiconductor technology (for example, several Gflops / processor). There is a need for improvement. For example, performance of several Tflops (Tera Floating point number Operations Per Second) or several hundred GOPS (Giga Operation Per Second) or more is required. In order to meet these demands, parallel computing devices (parallel processors) that integrate multiple processors into a single LSI (Large Scale Integration) are being researched and developed. Some of such parallel computing devices have a general-purpose CPU as a core and a plurality of them are integrated in one LSI.

  Examples of products that meet these performance requirements include Cell Broadband Engine (hereinafter referred to as Cell) (for image processing and scientific and engineering calculations) jointly developed by Sony Computer Entertainment Inc., Toshiba Corporation, and IBM, NEC Corporation There are IMAP (for image processing) developed by the company and Line Dancer (for image processing) developed by CONNEX (see Non-Patent Documents 1 to 3).

  By the way, scientific and technical calculations and image processing are characterized in that almost the same processing is performed on a huge amount of data. Taking advantage of this feature, the processor adopts a SIMD (Single Instruction Multi Data) type architecture. That is, this is a control method in which separate data is given to a large number of processors, but the instructions are the same.

  The reason for making the instructions the same is because the MIMD (Multi Instruction Multi Data) method, which reads different instructions from the instruction memory at the same time and supplies them to each processor, requires multiple instruction memories and their decoding circuits, which increases the hardware cost. This is because the software development is greatly complicated and software and hardware debugging becomes very difficult.

  Next, structuring will be described. FIG. 40 is a part of a flowchart of a program having a branch. In this program, the contents of the variable abc and the variable def are compared. If the variable abc is larger, the value of the variable abc is added to the variable x1, and if not, the value of the variable def is added to the variable x2. FIG. 41 describes the flowchart of FIG. 40 in C language. Such a description method is called structured programming. FIG. 42 is obtained by converting the code of FIG. 41 into an assembler language close to a machine language of a computer. Here, it is assumed that the C compiler has assigned the variable abc to the register R2 (register 2), the variable def to the register R3, the variable x1 to the register R4, and the variable x2 to the register R5. What should be noted in FIG. 42 is that a conditional jump instruction BGT (jump when the comparison result is large) is used to implement the flow of FIG. Incidentally, the BR instruction is an instruction that always jumps.

  By the way, in the SIMD type architecture, it is not possible to implement a program branch using a conditional jump instruction when performing parallel computation. For example, consider a SIMD computer composed of eight processors. Since the registers R2 and R3 are different for each of the eight processors, the data stored in them is different. Therefore, since the comparison result between the register R2 and the register R3 is different in each processor, there occurs a state in which a jump occurs in one processor and a jump does not occur in another processor, but separate instructions cannot be executed because the SIMD type. Therefore, the flow of FIG. 40 cannot be realized as it is. This problem occurs only when the jump condition is different for each processor at the time of program execution, and the control that always matches the jump condition in all the processors, such as the control of the loop with a predetermined number of times, It can also be implemented with SIMD type architecture.

  As a method for avoiding the drawbacks of the SIMD type architecture described above, there is an architecture that makes ordinary instructions conditional. This is not a SIMD type, but there is a detailed description in Chapter A3 of ARM's ARM processor manual "ARM Architecture Reference Manual" (ARM v6.pdf). Since almost all instructions of the ARM processor can be executed conditionally, the code shown in FIG. 41 can be written as shown in FIG. 43, for example. In FIG. 43, “AL” indicates that execution is always performed, “HI” indicates that the comparison result is large, and “LS” indicates that the comparison result is small or equal. Note that since the “S” is not added to the instruction “ADD HI, R4, R4, R2”, the condition set by the CMP instruction is not changed by this instruction. (Refer to page A3-7 in the above manual.)

  Here, the meaning of "do not execute the instruction" is confirmed. In a general processor, an instruction is usually executed in the order of instruction fetch (IF), instruction decode (DEC), operand fetch (OF), operation execution (EXE), and operation result write (WB). In the current high-speed processor, this procedure is divided into five and pipelined as shown in the timing chart of FIG. 44, for example. The comparison result of the CMP instruction is not determined unless it reaches the end of the EXE part of the instruction or the WB part. Therefore, it is not in time to change the next ADD instruction to a NOP (no operation) instruction depending on the result of the CMP instruction.

  However, if the operation result of the subsequent ADD instruction is not written to a predetermined position, it is equivalent to nothing being executed (except when the internal state of the processor changes at the time of operand fetch etc.) If this happens, correction will be required later.) That is, if the WB of the next ADD instruction is controlled by the result of the CMP instruction and the writing to R4 is invalidated, the ADD instruction becomes equivalent to the NOP instruction. SIMD type processors such as CELL, IMAP, and Line Dancer implement conditional instructions based on this idea.

“CELL Programming Tutorial”, “2.5 Conditional Branches in SIMD Operations”, search April 13, 2009, Internet <URL: http://www.fixstars.com> “An Integrated Memory Array Processor Architecture for Embedded Image Recognition System”, Kyo, S.; Okazaki, S.; Arai, T., Computer Architecture, 2005. ISCA apos; 05. Proceedings. 32nd International Symposium on Volume, Issue, 4 -8 June 2005 Page (s): 134-145, §5.3 2005 IEEE “The CA1024: A fully programmable system-on-chip for cost-effective HDTV media processing”, Lazar Bivolarski, Bogdan Mitu, Anand Sheel, Gheorghe Stefan, Tom Thomson, Dan Tomescu, CA1024 document P9, April 13, 2009 <URL: http: //www.hotchips.org/archives/hc18/2_Mon/HC18.S5/HC18.S5T2.pdf>

  The technology using the conventional SIMD type architecture can deal with a flow up to one branch, but it is difficult to cope with a nested structured program having two or more branches. FIG. 45 shows an example of a program nested twice. In this example, since the condition flag is rewritten at the comparison instruction of the code (2), the comparison result (condition flag) of the code (1) is temporarily saved somewhere before the execution of the instruction of the code (2). It must be restored with the else statement of code (3). In the ARM processor, it is possible to save by writing the condition flag to the register. FIG. 46 shows a program example.

  The MRS instruction is an instruction to write a condition flag to the register R9, and the MSR instruction is an instruction to return from the register. However, CELL, IMAP, and Line Dancer cannot save the condition code. Therefore, the code in FIG. 45 must be rewritten to a code that does not nest as shown in FIG. 47 (note that the program in FIG. 47 does not operate in the same manner as FIG. 45 depending on the value of variable x1). In normal programs, it is not uncommon for the nesting to be triple and quadruple, and in such a case, rewriting becomes complicated and the descriptiveness of the program is lowered. In other words, conventional SIMD architecture technology makes it difficult to support nested structured programming.

  That is, the conventional technique has a problem that it is difficult to easily execute a structured program having a plurality of nests in a parallel computing device.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a parallel computing device capable of easily executing a structured program having a plurality of nests.

In order to solve the above problem, the invention described in claim 1 is configured to control a plurality of arithmetic processors (for example, the arithmetic processor PE102 in the embodiment) that perform arithmetic processing in parallel and each of the plurality of arithmetic processors. A control signal generation unit (for example, a control signal generation unit (PE-I) 3 in the embodiment) for supplying an instruction, and each of the plurality of arithmetic processors receives input data based on the control instruction A first arithmetic unit that performs first arithmetic processing (for example, ALU 95A in the embodiment) and a stack structure, and first control information holding in which flag information based on the result of the first arithmetic processing is sequentially accumulated Unit (for example, the G flag stack 11 in the embodiment) and a first combining unit that combines the flag information accumulated in the first control information holding unit ( For example, the first calculation process is performed by the first calculation unit based on the combination flag information without accumulating the combination flag information combined by the combination unit 19) and the first combination unit in the stack structure in the embodiment. first control unit for (e.g., SPE control unit 199A in the embodiment), a specific sub-processor with a (e.g., sub-processor SPE102A in the embodiment), the second based on the input data to the control command The second arithmetic unit (for example, ALUs 95B to 95D in the embodiment) that performs the arithmetic processing of the first and second combining units synthesized by the first synthesizing unit is not accumulated in the stack structure, and the first the second control unit for the second calculation process on the second operation unit (e.g., SPE controller 199B~199D in the embodiment) A sub processor comprising (e.g., SPE102B～SPE102D in the embodiment) parallel computing device, characterized in that it comprises a, (e.g., parallel computing device 1 in the embodiment).

According to a second aspect of the present invention, there are provided a plurality of arithmetic processors (for example, the arithmetic processor PE 202 in the embodiment) that perform arithmetic processing in parallel, and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors performs first arithmetic processing on the input data based on the control command. 1 arithmetic unit (for example, ALU 95A in the embodiment) and a stack structure, and a first control information holding unit (for example, in the exemplary embodiment) in which flag information based on the result of the first arithmetic processing is sequentially accumulated G flag stack 11) and a first combining unit (for example, in the embodiment) that combines the flag information accumulated in the first control information holding unit And a first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without accumulating the combination flag information combined by the first combination unit in the stack structure. For example, a specific sub processor (for example, the sub processor SPE 202A in the embodiment) including the SPE control unit 299A in the embodiment, and a second arithmetic process on the input data based on the control command A calculation unit (for example, ALU 95B in the embodiment) and a selection unit (for example, selecting whether to use the synthesis flag information synthesized by the first synthesis unit for controlling the second computation process of the second computation unit) The execution selection unit 24B) in the embodiment and the selection unit use the combination flag information combined by the first combination unit for the second calculation processing of the second calculation unit. When the use is selected, the second calculation unit causes the second calculation unit to perform a second calculation process based on the combination flag information without accumulating the combination flag information combined by the first combination unit in the stack structure. And a sub processor (for example, SPE 202B in the embodiment) including two control units (for example, the SPE control unit 299B in the embodiment) .

According to a third aspect of the present invention, there are provided a plurality of arithmetic processors (for example, the arithmetic processor PE302 in the embodiment) that perform arithmetic processing in parallel, and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors performs first arithmetic processing on the input data based on the control command. 1 arithmetic unit (for example, ALU 95A in the embodiment) and a stack structure, and a first control information holding unit (for example, in the exemplary embodiment) in which flag information based on the result of the first arithmetic processing is sequentially accumulated G flag stack 11A) and a first combining unit that combines the flag information stored in the first control information holding unit (for example, in the embodiment) The first arithmetic processing unit based on the synthesis flag information without storing the synthesis flag information synthesized by the first synthesis unit in the stack structure. A first control unit (for example, the SPE control unit 399A in the embodiment), a specific sub processor (for example, the sub processor SPE 302A in the embodiment), and a second input data based on the control command A second control unit (for example, ALU95B in the embodiment) and a second control information holding unit (for example, an implementation) that has a stack structure and sequentially stores flag information based on the result of the calculation process. G flag stack 11B) in the embodiment and a second combining unit (for combining the flag information accumulated in the second control information holding unit) For example, in the embodiment, the synthesis unit 19B) and the synthesis flag information synthesized by the first synthesis unit and the synthesis flag information synthesized by the second synthesis unit of its own subprocessor are accumulated in the stack structure. The selection unit (for example, the execution selection unit 34B in the embodiment) to select without, and the second calculation unit based on the combination flag information without storing the combination flag information selected by the selection unit in the stack structure A parallel computing device comprising: a sub-processor (for example, SPE302B in the embodiment) including a second control unit (for example, the SPE control unit 399B in the embodiment) that performs the second arithmetic processing. There is .

According to a fourth aspect of the present invention, there are provided a plurality of arithmetic processors (for example, the arithmetic processor PE 402 in the embodiment) that perform arithmetic processing in parallel, and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors includes a plurality of sub processors (for example, the sub processors SPE402A to SPE402D in the embodiment). Each of the sub-processors (for example, in the case of the sub-processor SPE 402A in the embodiment) an arithmetic unit (for example, ALU 95A in the embodiment) that performs processing on the input data based on the control command; , Stack structure, based on the processed result The control information holding unit (for example, the G flag stack 11A in the embodiment) that sequentially stores the flag information that has been stored, and the combining unit that combines the flag information stored in the control information holding unit of its own subprocessor (for example, implementation) And a selection unit (for example, an embodiment) that selects any one of the synthesis flag information without accumulating the synthesis flag information synthesized by the synthesis unit of any sub-processor in a stack structure. An execution selection unit 44A) and a control unit (for example, an embodiment) that causes the calculation unit to perform calculation processing based on the selected combination flag information without accumulating the combination flag information selected by the selection unit in a stack structure. SPE control unit 499A), and the arithmetic units included in the plurality of sub-processors are different from each other. A parallel computing apparatus characterized by enabling implementing calculation process.

The invention described in claim 5 includes a plurality of arithmetic processors (for example, arithmetic processor PE502 in the embodiment) that perform arithmetic processing in parallel, and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors performs first arithmetic processing on the input data based on the control command. 1 operation unit (for example, ALU 95A in the embodiment) and a stack structure, and a first control information holding unit (for example, G flag stack in the embodiment) in which flag information based on the result of operation processing is sequentially accumulated 11A) and a first combining unit that combines the flag information accumulated in the first control information holding unit (for example, combining in the embodiment) Unit 19) and a first control unit (for example, for causing the first calculation unit to perform a first calculation process based on the combination flag information without storing the combination flag information combined by the first combination unit in the stack structure) A specific sub processor (for example, sub processor SPE 502A in the embodiment), and a second operation that performs a second operation process on the input data based on the control command. Part (for example, ALU95B in the embodiment), flag information based on the result of the first arithmetic processing by the first arithmetic unit, and the second arithmetic processing by the second arithmetic unit of its own sub-processor A selection unit (for example, the execution selection unit 55B in the embodiment) for selecting any of the flag information based on the result, and a stack structure The second control information holding unit (for example, the G flag stack 51B in the embodiment) in which the flag information selected by the selection unit is sequentially stored and the flag information stored in the second control information holding unit are combined. A second synthesis unit (for example, the synthesis unit 59B in the embodiment) and the synthesis flag information synthesized by the second synthesis unit are not accumulated in the stack structure, and the second calculation unit is based on the synthesis flag information. A parallel processor comprising: a second processor (for example, the SPE controller 599B in the embodiment) that performs the second arithmetic processing; and a sub processor (for example, the sub processor SPE 502B in the embodiment). Device .

According to a sixth aspect of the present invention, a plurality of arithmetic processors (for example, the arithmetic processor PE 602 in the embodiment) that perform arithmetic processing in parallel, and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors includes a plurality of sub-processors (for example, SPE602A to SPE602D in the embodiment), Each of the sub-processors (for example, in the case of the sub-processor SPE 602A in the embodiment) has an arithmetic unit (for example, ALU 95A in the embodiment) that performs arithmetic processing on input data based on the control command, and an arbitrary The result of the arithmetic processing by the arithmetic unit of the sub processor of A selection unit (for example, an execution selection unit 645A in the embodiment) that selects any one of the flag information based on the control information holding unit (which has a stack structure and sequentially stores the flag information selected by the selection unit ( For example, the G flag stack 51A in the embodiment, a combining unit that combines the flag information accumulated in the control information holding unit (for example, the combining unit 59A in the embodiment), and a combining flag combined by the combining unit A control unit (for example, the SPE control unit 699A in the embodiment) that causes the arithmetic unit to perform arithmetic processing based on the synthesis flag information without accumulating information in a stack structure, and the plurality of sub-processors includes The arithmetic unit is a parallel computing device characterized in that different arithmetic processes can be performed .

The invention described in claim 7 includes a plurality of arithmetic processors that perform arithmetic processing in parallel (for example, arithmetic processor PE 702 in the embodiment), and a control signal generation unit that supplies a control command to each of the plurality of arithmetic processors. (For example, the control signal generation unit (PE-I) 3 in the embodiment), and each of the plurality of arithmetic processors performs first arithmetic processing on the input data based on the control command. 1 arithmetic unit (for example, ALU 95A in the embodiment) and a stack structure, and a first control information holding unit (for example, in the exemplary embodiment) in which flag information based on the result of the first arithmetic processing is sequentially accumulated G flag stack 11A) and a first combining unit that combines the flag information stored in the first control information holding unit (for example, in the embodiment) And a first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without accumulating the combination flag information combined by the first combination unit in a stack structure. (For example, the SPE control unit 799A in the embodiment), and a second sub processor (for example, the sub processor SPE 702A in the embodiment) that performs second arithmetic processing on input data based on the control command. Whether the combined flag information is output as it is or is inverted without accumulating the combined flag information combined by the two arithmetic units (for example, ALU 95B in the embodiment) and the first combining unit in the stack structure. Inversion processing unit that selects and outputs the selected information as flag information output (for example, inversion processing unit 78B in the embodiment) The selection unit that selects either the flag information output or the control information that always enables instruction execution without accumulating the flag information output from the inversion processing unit in the stack structure (for example, in the embodiment) An execution selection unit 74B) and a second control unit (for example, the SPE control unit 799B in the embodiment) that causes the second calculation unit to perform a second calculation process based on the information selected by the selection unit. And a processor (for example, the sub processor SPE 702B in the embodiment) .

  According to the first to seventh aspects of the invention, by using the technology of the present invention, in a parallel computing device combining a VLIW type with a SIMD type, hardware that supports multiple nested structured programs is provided. It can be easily realized. Therefore, since a large number of arithmetic elements (processors) can be operated in parallel efficiently, it is possible to easily realize a parallel computing device having a computing capacity of several Tflops or several hundred GOPS required for scientific calculation or image processing.

1 is a schematic block diagram showing a first embodiment of the present invention. It is a figure which shows the memory | storage part which can refer each subprocessor in the arithmetic processor 2 by embodiment of this invention. It is a block diagram which shows the structure of the arithmetic processor 2 by embodiment of this invention. 6 illustrates six instructions introduced for structured programming according to an embodiment of the present invention. It is a block diagram which shows the structural example of the flag process part by embodiment of this invention. The It is a block diagram which shows the structural example of the write-in control circuit to the accumulator by embodiment of this invention. 2 shows an example program according to an embodiment of the present invention. The correspondence between variables and registers in the example program of the first embodiment is shown. The operation | movement of the command of the example of a program of 1st Embodiment is shown. 2 is a block diagram illustrating a schematic configuration of an arithmetic processing unit of the parallel computing device 1 of the first embodiment. FIG. FIG. 2 is a block diagram showing a configuration for performing calculation control processing in the calculation processor of the first embodiment. It is a block diagram which shows the G flag process part and SPE control part of 1st Embodiment. The program which can perform the high-speed process by 1st Embodiment is shown. The program of the parallel arithmetic processing by 1st Embodiment is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 2nd Embodiment. The command added in the structure of 2nd Embodiment is shown. It is a block diagram which shows the G flag process part and SPE control part of 2nd Embodiment. In the parallel computing device 1 of the second embodiment, an example converted to a VLIW type that performs four parallel processing to execute the program of FIG. 13 is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 3rd Embodiment. The command added in the structure of 3rd Embodiment is shown. It is a block diagram which shows the G flag process part and SPE control part of 3rd Embodiment. In the parallel computing device 1 of the third embodiment, an example of conversion to a VLIW type that performs four parallel processing to execute the program of FIG. 13 is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 4th Embodiment. The command added in the structure of 4th Embodiment is shown. It is a block diagram which shows the G flag process part and SPE control part of 4th Embodiment. It is a figure which shows control of the selector of 4th Embodiment. In the parallel computing device 1 of the fourth embodiment, an example of conversion to a 4-parallel VLIW type for executing the program of FIG. 13 is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 5th Embodiment. The command added in the structure of 5th Embodiment is shown. It is a block diagram which shows the synchronization circuit of SPE of 5th Embodiment. The example which parallelized the program of FIG. 13 of 5th Embodiment is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 6th Embodiment. The command added in the structure of 6th Embodiment is shown. It is a block diagram which shows the synchronization circuit of SPE of 6th Embodiment. In the parallel computing device 1 of the sixth embodiment, an example of conversion to a 4-parallel VLIW type in order to execute the program of FIG. 13 is shown. It is a block diagram which shows schematic structure of the arithmetic processing part of the parallel computing device 1 of 7th Embodiment. The command added in the structure of 7th Embodiment is shown. It is a block diagram which shows the synchronization circuit of SPE of 7th Embodiment. In the parallel computing device 1 of the seventh embodiment, an example of conversion to a 4-parallel VLIW type to execute the program of FIG. 13 is shown. It is a part of flowchart of a program with a branch. The flowchart of FIG. 40 is described in C language. The code of FIG. 41 is converted into an assembler language close to a machine language of a computer. The code of FIG. 41 is converted into an assembler language close to a machine language of a computer. The timing chart by the example of a program by a prior art is shown. The example of a program by a prior art is shown. The example of a program by a prior art is shown. The example of a program by a prior art is shown.

(First embodiment)
An embodiment of a parallel computing device will be described with reference to the drawings.
FIG. 1 is a schematic block diagram showing a first embodiment of the present invention.
The parallel computing device 1 shown in this figure performs parallel processing by a plurality of processors included in the arithmetic processing unit 100. Prior to detailed description of each embodiment, a configuration outline of the parallel computing device 1 will be described.
The parallel computing device 1 includes an arithmetic processing unit 100, an IO-CPU 4, an instruction memory 5, and an external memory 9.
The arithmetic processing unit 100 includes 108 arithmetic processors (PE) 2-0 to 2-107 (collectively referred to as “arithmetic processor (PE) 2”), and a control signal generation unit that supplies a control command to each of the PEs 2. (PE-I) 3 is mounted.

Each of the arithmetic processors 2 includes four sub processors (SPE) 2A to 2D.
Each of the SPEs 2A to 2D has a VLIW (Very Long Instruction Word) type configuration that executes different instructions. Each PE2 has the same configuration in which SPEs are combined. In addition, 108 SPEs 2A included in all PEs 2 are configured as a SIMD (Single Instruction Multi Data) type, and the same instruction is executed in all the SPEs 2A. The same applies to SPE2B, SPE2C, and SPE2D.
These SPEs 2A to 2D are configured by a combination of two types of SPEs having different configurations. A description will be given by taking as an example a combination of SPE2A having the basic control function of the arithmetic processor 2 and SPE2B to SPE2D under the control of SPE2A.

The control signal generator (PE-I) 3 controls the execution order of instructions of the arithmetic processor 2.
The PE-I 3 controls processing that requires conditional branching such as loop processing and subroutine calls in the program of the arithmetic processor 2. When the PE-I3 and PE2 instructions are described in an assembler program, they are described as VLIW-type instructions that execute five instructions SPE2A to SPE2D and PE-I3 in parallel.
The program code executed by the SIMD + VLIW type parallel computing device 1 is read in advance from the external memory 9 by the IO-CPU 4 before the calculation is started, and is written in the instruction memory 5 attached to the PE-I 3. After that, when the IO-CPU 4 sends a calculation start signal to the PE-I3, the PE-I3 reads the instructions to be executed by itself from the instruction memory and the four instructions to be executed by the SPE2D from the SPE2A, and starts the calculation. To do. The data to be calculated is taken in from the outside by the IO-CPU 4 and transferred separately to the data input register of the PE 2. The calculation result is read from the arithmetic processing unit 100 by the IO-CPU 4 and transferred to the external device or the external memory 9.
Thus, the plurality of PEs 2 in the arithmetic processing unit 100 can perform arithmetic processing in parallel.

A programming model of the arithmetic processor 2 will be described with reference to the drawings.
FIG. 2 is a diagram illustrating a storage unit that can be referred to by each sub-processor in the arithmetic processor 2 according to the embodiment of the present invention. R0 to R15 shown in this figure indicate storage areas that can be referred to by each SPE.

Each sub-processor is formed by an accumulator (Acc) method. That is, one of the inputs of the ALU (Arithmetic and Logic Unit) is fixed to Acc, and the reference destination of the data to be input only for the other input can be designated. The calculation result is normally stored in Acc. By limiting in this way, the number of operands required for the instruction can be reduced, and the number of bits in the machine language can be reduced.
There are 12 registers R4 to R15 that can be commonly referenced from the 4 SPEs. These registers can be read from and written to by each SPE, but when writing processes from two or more SPEs overlap, they are processed preferentially in the order of SPE2A, SPE2B, SPE2C, and SPE2D. The Acc of the SPE2A can be read by referring to the register R0 from other SPEs in addition to the SPE2A. The Acc of SPE2A can be written by SPE2A, but cannot be written by SPEs other than SPE2A. Similarly, Acc of SPE2B, SPE2C, and SPE2D can be read by referring to registers R1, R2, and R3, respectively, but cannot be written to Acc that is not in the same SPE.

FIG. 3 is a block diagram showing a configuration of the arithmetic processor 2 in the embodiment of the present invention.
The arithmetic processor 2 includes SPEs 2A to 2D and a register 91 referred to by each SPE. The SPE 2A includes an Acc 93A, a selector 94A, an ALU 95A, a flag register 97A, and an SPE control unit 99A. Similarly, the SPE 2B includes an Acc 93B, a selector 94B, an ALU 95B, a flag register 97B, and an SPE control unit 99B. The SPE2C includes an Acc 93C, a selector 94C, an ALU 95C, a flag register 97C, and a control unit 99C. The SPE2D includes an Acc 93D, a selector 94D, an ALU 95D, a flag register 97D, and a control unit 99D.
Acc93A to Acc93D are accumulators referred to by ALUs 95A to 95D. The selectors 94A to 94D select inputs from the Acc93A to Acc93D. ALUs 95A to 95D are ALUs that perform operations in each SPE.

First, a configuration common to the SPEs 2A to 2D is shown, and the SPE 2A will be described as a representative.
In SPE2A, one input of ALU 95A is supplied with data from Acc93A. The other input of the ALU 95A is selected and supplied by the selector 94A from the register 91, Acc93A, Acc93B, Acc93C, and Acc93D. The calculation result by the ALU 95A is normally written in the Acc 93A, but any one of the registers R4 to R15 can be selected and written using an instruction for transferring the data of the Acc 93A to the register 91. However, data cannot be written in Acc93B to Acc93D of other SPEs other than SPE2A.
SPE2B to SPE2D also have the same configuration as SPE2A.

  The flag register 97A records and holds a flag value indicating the result of the arithmetic processing in the ALU 95A. There are four flags (C, N, V, Z) output from the ALU 95A as the flags held by the flag register 97A. The C (carry) flag indicates that a carry has occurred in the operation result. The N (negative) flag indicates that the value has become negative by the arithmetic processing. The V (overflow) flag indicates that the value has overflowed due to the arithmetic processing. The Z (zero) flag indicates that the value has become 0 by the arithmetic processing.

The control unit 99A controls the accumulator Acc93A, the register 91 (R4-R15), and the flag register 97A according to the value of the flag recorded in the flag register 97A or the like, or control from the PE-I3.
Note that the flag registers 97A to 97D and the control units 99A to 99D can set several parallel processing methods by changing the definitions of the configuration and function. For details, refer to the embodiment shown below.

Next, a configuration example for realizing conditional branch processing that enables multiple nesting (nesting) in the parallel computing device 1 will be described.
As a basic configuration common to each embodiment, rather than determining instruction execution control in each ALU for each instruction, a single flag (G) is provided, and if the value is “1”, the instruction is executed. If “0”, it is determined not to execute. With this configuration, the condition determination field (bit) for each instruction becomes unnecessary, and the object code can be made compact. Further, by holding the value of this flag by the G flag stack provided with the stack structure, the processing of PE2 can realize a conditional branch process that enables multiple nesting.
A signal obtained by taking the logical product of all the values held in the G flag stack is called a G flag. In each SPE, it is easy to perform control so that an instruction is executed when the value of the G flag is “1” and is not executed when the value is “0”. Immediately after PE2 is reset (initialized), all values in the G flag stack are set to 1. Thereby, the execution of the instruction immediately after the reset is not restricted by the G flag.

FIG. 4 shows six instructions introduced for structured programming in an embodiment of the present invention.
These six instructions are executed regardless of the value of the G flag.
The “PSH” instruction can select an arbitrary number of condition flags from among C, N, V, and Z condition flags as operands and specify them as condition determination conditions. This instruction pushes the G flag stack down one level and sets a new value at the top level. For example, in the case of the “PSH C, Z” instruction, the logical sum of the C (carry) flag and the Z (zero) flag is calculated, and if it is “1”, the value at the top of the G flag stack is set to 1. If the value is “0”, the uppermost value is set to “0”.
The “PSHI” instruction pushes the G flag stack down one level and sets a new value at the top level. In this instruction, after calculating the logical sum of the flags designated by the operand, if it is “0”, the value on the top level of the G flag stack is set to 1, and if it is “1”, the value on the top level is set to 0. To do. These instructions correspond to the process indicated by “if to then statement”.
Since the “GINV” instruction inverts the value at the top of the G flag stack, it corresponds to an “else statement”.
The “POP” instruction pops (shifts) the G flag stack up one level and sets 1 to the lowest layer. This corresponds to the end of the “if statement”.
The “POPI” instruction is a combination of a “POP” instruction and a “GINV” instruction.
The “FLSH” instruction sets all the values held in the G flag stack to 1.

FIG. 5 is a block diagram illustrating a configuration example of the flag processing unit in the embodiment of the present invention.
The flag processing unit 10 shown in the figure includes a G flag stack 11, an OR circuit 12, an AND circuit 13, an OR circuit 14, an OR circuit 17, an EXOR circuit 18, and a combining unit (AND circuit) 19. At least one flag processing unit 10 is provided for each PE.
The G flag stack 11 is a storage unit having a stack structure for storing flag values. As an example, the stack hierarchy is shown as four layers. Therefore, nesting up to four layers can be supported. A similar configuration is required for all PE2. The G flag stack always changes at the rising edge of the basic clock in the parallel computing device 1 (not shown).

In the figure, a signal indicated as cnt_xxx is a control signal that is commonly given to all SPEs of the same type (for example, SPE2A) included in each PE2 by decoding the instruction of PE2 by PE-I3. All the SPEs of the same type are processed by the same instruction in parallel by the SIMD configuration, and an SPE group is formed in that unit. These control signals are different for each SPE group.
On the other hand, a signal indicated as flag_x indicates an output signal that outputs a value obtained by holding a condition flag output by an ALU (for example, ALU 95A in FIG. 2) in a flag register (for example, flag register 97A in FIG. 2). A signal flag_x is a signal indicating a value of a specific condition flag output from each SPE. Therefore, in the configuration in which flag registers are arranged in all SPEs, there are 108 PE2s, and there are 4 SPEs in each PE2, so that a total of 432 different signals are obtained.
The signal indicated as system_reset is a common signal that resets the entire system of the parallel computing device 1, and when this signal or the cnt_FLSH signal becomes active, the values of the G flag stack all become 1.
The cnt_FLSH signal becomes active when a “FLSH” instruction is issued.

  When the “PSH” instruction is issued, the cnt_PSH signal becomes active and the G flag stack is pushed. That is, the value held in the stack G0 is shifted to the stack G1, the value held in the stack G1 is shifted to the stack G2, and the value held in the stack G2 is shifted to the stack G3. The value held in the stack G3 is discarded. At the same time, the cnt_C_en, cnt_N_en, cnt_V_en, and cnt_Z_en signals become active according to the operand specification of the “PSH” instruction, and OR with the carry flag (C), negative flag (N), overflow flag (V), and zero flag (Z). Is taken and its value is written to stack G0. The “PSHI” instruction performs the same operation as the push operation of the “PSH” instruction described above. However, after taking the logical sum of the condition flags, they are inverted and then written to the stack G0.

When the “GINV” instruction is issued, the cnt_GINV signal becomes active, and the value of the stack G0 is inverted.
When the “POP” instruction is issued, the cnt_POP signal becomes active and the G flag stack is popped. That is, the value held in the stack G1 is shifted to the stack G0, the value held in the stack G2 is shifted to the stack G1, and the value held in the stack G3 is shifted to the stack G2. Further, 1 is set in the stack G3.
The “POPI” instruction is executed at once by combining the “POP” instruction and the “GINV” instruction. That is, the G flag stack is popped by one stage, and then the uppermost stack G0 is inverted.
In the synthesizer 19, a signal indicating the result of ANDing all the values of the stack G0 to the stack G3 becomes a signal Global_Inst_en (G flag) for controlling the execution of the instruction. This signal is different for each SPE.

  In the control of PE2, the operation of “not executing the instruction” can be realized by “not writing the operation result”. Therefore, an Acc write control signal supplied from an instruction decoder (not shown) in PE-I3, a write control signal for registers R4 to R15, or a write control signal for the C, N, V, and Z condition flags, By executing a logical product with the G flag (Global_Inst_en signal), an instruction execution control mechanism is realized.

FIG. 6 is a block diagram showing a configuration example of a write control circuit for Acc in the embodiment of the present invention.
In the figure, an Acc control unit 92 and Acc 93 are shown. The ALU_out signal is a signal output from an ALU (for example, ALU 95A), and the Acc_out signal is a signal input from the Acc 93 to an ALU (for example, ALU 95A). The Acc control unit 92 calculates the logical product of the write control signal cnt_Acc_wr to the Acc 93 from the instruction decoder (not shown) in the PE-I 3 and the G flag (Global_Inst_en signal) as a load enable signal for the Acc 93. Yes. When the load enable signal becomes active, the state of Acc 93 changes at the rising edge of the basic clock inside the parallel computing device 1 (not shown).

A program example of the first embodiment will be described with reference to FIGS. 7, 8, and 9.
FIG. 7 shows an example in which a double nested program is described by the assembler program of the parallel computing device 1. In this program, it is assumed that each variable in the code of FIG. 7 is allocated to each register as shown in FIG. In addition to the instructions shown in FIG. 42, the operations of the instructions used in FIG. 7 are described in FIG. In FIG. 7, after the symbol “//”, a comment for making it easy to understand the operation of the program is shown in C language. These comments correspond to the codes shown in FIG. As described above, a structured program can be easily converted into an assembler code by using the technique of the present invention. That is, it can be easily converted into machine language.

FIG. 10 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. Refer to FIG. 3 for the basic configuration regarding the arithmetic processing.
The arithmetic processing unit 100 shown in the figure includes a plurality of arithmetic processors (PE) 102 that perform arithmetic processing in parallel, and a control signal generation unit (PE−) that supplies control commands to the plurality of PEs 102 via SPE control signal lines. I) 3 is provided.

Each of the PEs 102 includes a sub processor 102A (SPE 102A) and sub processors 102B to 102D (SPEs 102B to 102D).
The SPEs 102A to SPE102D have the same configuration as the basic configuration of the arithmetic processing of the SPEs 2A to 2D in FIG.
The SPE 102A includes a G flag processing unit 10 and an SPE control unit 199A, and the SPEs 102B to 102D include SPE control units 199B to 199D.
Further, the G flag processing unit 10 in the SPE 102A supplies the G flag signal to the SPE control units 199A to 199D. The SPE control units 199A to 199D perform calculation control in each SPE based on the supplied G flag signal.

FIG. 11 is a block diagram showing a configuration for performing arithmetic control processing in the arithmetic processor.
This figure shows the configuration of the SPEs 102A to 102D in the PE 102.
The SPE 102A shows the detailed configuration of the SPE calculation processing unit 190A and the G flag processing unit 10, and the SPE 102B shows the detailed configuration of the SPE calculation processing unit 190B. Since SPE102C and SPE102D have the same configuration as SPE102B, description thereof is omitted. Further, the same components as those in FIG. 5 described above are denoted by the same reference numerals, and different components will be described.

The SPE arithmetic processing unit 190A in the SPE 102A includes the Acc 93A, selector 94A, ALU 95A, flag register 97A, and SPE control unit 199A shown in FIG.
The flag register 97A includes flag registers 97A-C, 97A-N, 97A-V, and 97A-Z, and records the values of the condition flags C, N, V, and Z that change according to the calculation result of the ALU 95A. And hold. The flag registers 97A-C, 97A-N, 97A-V, and 97A-Z each output a flag-C signal, a flag-N signal, a flag-V signal, and a flag-Z signal based on the recorded values.

The control unit 199A in the SPE 102A includes an Acc control unit 92A and a flag control unit 96A.
The Acc control unit 92A has the same configuration as that of the Acc control unit 92 shown in FIG. 6, but a reference numeral “A” is added to indicate that the configuration is the SPE 102A. The Acc control unit 92A obtains a logical product of the write signal cnt_Acc_wr_A from the instruction decoder (not shown) in the PE-I3 to the accumulator and the G flag (Global_Inst_en signal) to obtain a load enable signal for the Acc93A.
The flag control unit 96A controls the writing of the value of each condition flag stored in the flag register 97A according to the G flag and the control signal from the PE-I3. The flag register 97A is written when the G flag is active and a command to write the state of each flag is output from the PE-I3. The commands to write the condition flag are the values of the carry flag (C), negative flag (N), overflow flag (V), and zero flag (Z) when the cnt_C_wr_A, cnt_N_wr_A, cnt_V_wr_A, and cnt_Z_wr_A signals are active. It is. Similarly, the register 91 (R4-R15) is ANDed with the value of the G flag in the write command output from the PE-I3.

Similarly, the SPE arithmetic processing unit 190B in the SPE 102B includes the Acc 93B, selector 94B, ALU 95B, and SPE control unit 199B shown in FIG. The SPE arithmetic processing unit 190B does not include the flag register 97B illustrated in FIG.
The SPE control unit 199B in the SPE arithmetic processing unit 190B includes an Acc control unit 92B. The Acc control unit 92B has the same configuration as the Acc control unit 92A, and takes the logical product of the write signal cnt_Acc_wr_B to the Acc93B from the instruction decoder (not shown) in the PE-I3 and the G flag (Global_Inst_en signal). Acc93B load enable signal.

The G flag processing unit 10 in the SPE 102A will be described with reference to the relationship between the G flag processing unit and the SPE control unit.
FIG. 12 is a block diagram illustrating the G flag processing unit and the SPE control unit.
This figure shows the G flag processing unit 10 and the SPE control units 199A to 199D included in each SPE. As shown in FIG. 10 described above, the G flag processing unit 10 inputs the G flag signal (Global_Inst_en) to be output to the SPE control units 199A to 199D.
The G flag processing unit 10 shown in the figure has the same configuration as the G flag processing unit 10 shown in FIG.

  With the configuration described above, the G flag stack is provided only in the SPE 2A, and the Global_Inst_en signal output from the G flag stack is used not only for the SPE 102A but also for all execution controls of the SPE 102B, SPE 102C, and SPE 102D. As a result, the SPE 102A makes a condition determination and writes the result to the G flag stack. At the same time, all other SPEs execute instructions according to the result of the condition determination.

Referring to the drawing, it will be shown by using a program example that the processing speed is increased by the parallel computing device 1 shown in the first embodiment.
FIG. 13 shows a program that can perform high-speed processing.
The program shown in this figure is the same as that shown in FIG. 7 described above. However, in order to make the following explanation easy to understand, “*” is assigned to each processing unit and classified.
FIG. 14 shows a program for parallel arithmetic processing according to the first embodiment.
The program shown in this figure shows an example in which the program is converted into four parallels using the configuration shown in the first embodiment. The SPE 102A determines the condition, and the SPE 102B or the like controls instruction execution according to the result.
First, the instruction part marked with “* 1” will be described. Until the condition is judged by the SPE 102A (step 3), the SPE 102B executes up to the “ADD R7” instruction. The SPE 102B writes the operation result in the register R7 by the “MV R7” instruction in Step 4 immediately after executing the “PSHI C, Z” instruction.

Similarly, for the instruction part with “* 2”, the step in which Acc-B is set to “0” by the “CLR” instruction in the SPE 102B in advance and the result of the “CMP R6” instruction is pushed to the G flag stack in the SPE 102A. Immediately after 6, “0” is written to the register R7.
Care must be taken in the part of the instruction with “* 3” and “* 4”. Although data is prepared in advance by the SPE 102C and the SPE 102D and it is desired to write the prepared data immediately after the instruction execution condition is determined, in step 3, the “PSHI C, Z” instruction is executed in the SPE 102A.
After the “PSHI C, Z” instruction in step 3 is executed in the SPE 102A, it is unclear whether the instructions are executed in the SPE 102C and the SPE 102D because the condition is determined. Therefore, before the “PSHI C, Z” instruction in step 3 is executed in the SPE 102A, the SPE 102C and the SPE 102D prepare data. By performing parallel processing with four SPEs in this way, processing that took 21 clocks in FIG. 13 can be completed in about half, 11 clocks in FIG.

  In FIG. 14, portions that are not effectively used in the SPEs 102A to 102D are indicated by blanks or shades. Arbitrary instructions can be placed in the blank part, but the shaded part can be executed in synchronization with the state of the SPE 102A (there is no target in the code of FIG. 13) or the “NOP” instruction shown in the figure Can be arranged.

According to the present embodiment, each of the plurality of arithmetic processors PE102 is formed by the sub processor SPE 102A and the sub processors SPE 102B to 102D.
In the sub processor SPE102A, the ALU 95A performs arithmetic processing on the input data based on the control command. The G flag stack 11 is a storage unit having a stack structure, and flag information based on the result of arithmetic processing is sequentially accumulated. The combining unit 19 combines the flag information accumulated in the G flag stack 11. The SPE control unit 199A controls writing to the Acc 93A, the flag register 97A, and the register 91 based on the synthesis flag information synthesized by the synthesis unit 19.
In the sub processors SPE102B to 102D, the ALUs 95B to 95D perform arithmetic processing on the input data based on the control command. The SPE control units 199B to 199D control writing to the Acc 93B and the register 91 based on the synthesis flag information synthesized by the synthesis unit 19.
This makes it easy to implement hardware that supports multiple nested structured programs in a parallel computing device that combines the VLIW type with the SIMD type.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 15 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. As for the arithmetic processing, the arithmetic processing unit 200 shown in the figure includes a plurality of arithmetic processors (PE) 202 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 202 via an SPE control signal line. A generation unit (PE-I) 3 and execution control units 20B to 20D that synchronize the SPEs under the control of the PE-I3 are provided.

Each of the PEs 202 includes a sub processor (SPE) 202A and sub processors (SPE) 202B to 202D.
The SPE 202A includes a G flag processing unit 10 and an SPE control unit 299A.
The SPEs 202B to 202D include SPE control units 299B to 299D and execution selection units 24B to 24D, respectively.
The G flag processing unit 10 supplies a G flag signal to the SPE control units 299A to 299D.
The execution selection units 24B to 24D output execution permission signals to the SPE control units 299B to 299D, respectively, based on the supplied G flag signal and execution permission signal.
The SPE control units 299A to 299D perform calculation control of each SPE based on the supplied execution permission signal.

FIG. 16 shows instructions to be added in the configuration of the second embodiment.
As shown in FIG. 15 described above, the G flag processing unit 10 is provided only in the SPE 202A. The SPEs other than the SPE 202A can select whether instruction execution is controlled according to the value of the G flag output from the SPE 202A, or whether the instruction is always executed regardless of the G flag of the SPE 202A.
To make this selection, the instructions shown in this figure are added. These instructions can always be executed by the SPE 202B, SPE 202C, and SPE 202D.
For example, when the “SYNC” instruction is executed in the SPE 202B, the SPE 202B uses the value of the G flag of the SPE 202A for the instruction execution control thereafter. When the “ASYNC” instruction is executed, the S flag of the SPE 202A after that The instruction will be executed regardless of the value.

Further, the G flag processing unit 10 in the SPE 102A will be described with reference to the connection between the G flag processing unit and the SPE control unit.
FIG. 17 is a block diagram illustrating the G flag processing unit and the SPE control unit.
This figure shows the G flag processing unit 10, and SPE control units 299A to 299D, execution selection units 24B to 24D, and execution control units 20B to 20D included in each SPE. The same reference numerals are given to the same components as those shown in FIGS.
The G flag processing unit 10 has the same configuration as that shown in FIG. 5 described above, and the output signal is Global_Inst_en_A. Global_Inst_en_A is the same as the Global_Inst_en signal in FIG. 5 except that it is clearly indicated that the signal is SPE 202A.

The execution control unit 20B outputs a control signal (en0_B) for controlling the execution of the SPE 202B by a control signal from the PE-I 3 (not shown).
The output en0_B from the execution control unit 20B enters the execution selection unit 24B and generates a control signal Global_Inst_en_B signal for controlling the SPE control unit 299B. The Global_Inst_en_B signal is used for instruction execution control in the SPE 202B. When the system_reset signal that initializes the parallel computing device 1 becomes active (“1”), the flip-flop 21 is set and the en0_B signal becomes “1”. As a result, the Global_Inst_en_B signal input to the SPE control unit 299B by the execution selection unit 24B is always “1”, so that the instruction is always executed in the SPE 202B.
When the “SYNC” instruction is issued, the cnt_SYNC_B signal becomes active, but the cnt_ASYNC_B signal remains inactive (“0”), so the output en0_B of the flip-flop 21 becomes “0”. Accordingly, the state of Global_Inst_en_B is determined according to the state of Global_Inst_en_A. That is, the instruction execution of the SPE 202B is controlled according to the G flag of the SPE 202A.

When the “ASYNC” instruction is issued, the cnt_ASYNC_B signal becomes active, and the output en0_B of the flip-flop 21 becomes “1”. Note that the flip-flop 21 changes at the rising edge of the basic clock in the parallel computing device 1 (not shown).
The execution control units 20C and 20D have the same configuration as the execution control unit 20B, and are different in that input signals are control signals for the SPE 202C and SPE 202D, respectively.
The execution selection units 24C and 24D are controlled by control signals en0_C and en0_D from the execution control units 20C and 20D, respectively, and control the SPE 202C and SPE 202D via the SPE control units 299C and 299D connected to the outputs.

  With the configuration described above, the G flag stack is provided only in the SPE 202A, and the SPEs other than the SPE 202A are controlled to execute instructions according to the G flag of the SPE 202A, or always execute instructions regardless of the G flag of the SPE 202A. You can choose what to do.

As shown in the second embodiment, it is shown by using a program example that the processing speed is increased by the parallel computing device 1.
FIG. 18 shows an example in which the parallel computing device 1 shown in the present embodiment is converted to a VLIW type that performs four parallel processing in order to execute the program of FIG.
The SPE 202A performs condition determination and the like, and the SPE 202B and the like execute an instruction in synchronization with the result.
First, the part of the instruction marked with “* 1” is executed up to the “ADD R7” instruction in the SPE 202B until the condition is judged in the SPE 202A (step 3). Immediately after executing the “PSHI C, Z” instruction in the SPE 202A, the result is written in the register R7 with the “MV R7” instruction. The same applies to the part of the instruction with “* 2”. In step 6, by preparing “0” in advance in Acc-B, the result of the “CMP R6” instruction is pushed to the G flag stack by SPE202A. Immediately after writing, “0” is written to the register R7. At the same time, as indicated by the instruction with “* 3”, data is prepared in advance in the SPE 202C, and writing to the register R9 can be performed immediately.

  Care should be taken with respect to the instruction part with “* 4” executed by the SPE 202D. These instructions are determined to be executed or not after the “GINV” instruction (step 7) in the SPE 202A. That is, data cannot be prepared in advance like the SPE 202C. Therefore, the SPE 202D executes the “MVA R10” instruction and the “INC” instruction regardless of the value of the G flag of the SPE 202A, and executes the “SYNC” instruction simultaneously with the “GINV” instruction in the SPE 202A. The execution control of the “MV R10” instruction is synchronized with the SPE 202A.

By performing parallel processing with four SPEs in this way, processing that took 21 clocks in FIG. 13 can be performed with 12 clocks in this embodiment.
In FIG. 18, portions not used in the SPEs 202B to 202D are indicated by blanks or shaded areas. Arbitrary instructions can be placed in the blank portion, and instructions that do not need to be synchronized with the SPE 202A can be executed in parallel. On the other hand, an instruction synchronized with the SPE 202A or a “NOP” instruction can be arranged in the shaded portion. In this embodiment, one extra clock is required as compared with the first embodiment, but other instructions can be arranged in the blank portion. Therefore, since the execution efficiency can be improved as compared with the first embodiment, the processing can be completed in a short time in the entire arithmetic processing.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 19 is a block diagram illustrating a schematic configuration of an arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. As for the arithmetic processing, the arithmetic processing unit 300 shown in the figure includes a plurality of arithmetic processors (PE) 302 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 302 via the SPE control signal line. A generation unit (PE-I) 3 and execution control units 30 </ b> B to 30 </ b> D that synchronize each SPE under the control of the PE-I 3 are provided.

Each of the PEs 302 includes a sub processor (SPE) 302A and sub processors (SPE) 302B to 302D.
The SPE 302A includes a G flag processing unit 10A and an SPE control unit 399A.
The SPE 302B includes a G flag processing unit 10B, an SPE control unit 399B, and an execution selection unit 34B. The SPE 302B includes an execution selection unit 34B in addition to the configuration corresponding to the SPE 102A shown in FIG. The G flag processing unit 10B and the SPE control unit 399B correspond to the G flag processing unit 10 and the SPE control unit 199A, respectively, and input / output signals replace the connection as the SPE 302B. In addition, the G flag processing unit 10B and the SPE control unit 399B are connected via the execution selection unit 34B.
The SPE 302C includes a G flag processing unit 10C, an SPE control unit 399C, and an execution selection unit 34C. The SPE 302D includes a G flag processing unit 10D, an SPE control unit 399D, and an execution selection unit 34D. SPE302C and SPE302D have the same configuration as SPE302B.

The G flag processing unit 10A supplies the G flag signal to the SPE control units 399B to 399D via the SPE control unit 399A and the execution selection units 34B to 34D. The G flag processing unit 10B supplies a Gb flag signal to the SPE control unit 399B via the execution selection unit 34B. The G flag processing unit 10C supplies a Gc flag signal to the SPE control unit 399C via the execution selection unit 34C. The G flag processing unit 10D supplies a Gd flag signal to the SPE control unit 399D via the execution selection unit 34D.
The execution selection unit 34B outputs either the supplied G flag signal or Gb flag signal as an execution permission signal of the SPE control unit 399B. The execution selection unit 34C outputs either the supplied G flag signal or Gc flag signal as an execution permission signal of the SPE control unit 399C. The execution selection unit 34D outputs either the supplied G flag signal or Gd flag signal as an execution permission signal for the SPE control unit 399D.
The SPE control units 399A to 399D perform arithmetic control of each SPE based on the supplied execution permission signal.

  In this embodiment, the G flag stack shown in FIG. 5 is provided in each of the SPE 302A, SPE 302B, SPE 302C, and SPE 302D. Each SPE is normally individually controlled by the respective G, Gb, Gc, and Gd flags, but the instruction execution is controlled according to the G flag of a specific SPE as necessary. Here, a specific SPE is assumed to be SPE 302A as an example.

In order to control the execution selection unit, an instruction shown in this figure is added.
FIG. 20 shows instructions to be added in the configuration of the third embodiment.
These instructions can be executed by the SPE 302B, SPE 302C, and SPE 302D.
For example, when the “SYNC” instruction is executed in the SPE 302B, the SPE 302B uses the G flag of the SPE 302A for instruction execution control thereafter. When the “ASYNC” instruction is executed, the SPE 302B switches from the G flag of the SPE 302A thereafter. The value of the G flag (Gb) of the SPE 302B is used for instruction execution control. The same applies to SPE302C and SPE302D.

Further, the G flag processing unit 10 in the SPE 102A will be described with reference to the connection between the G flag processing unit and the SPE control unit.
FIG. 21 is a block diagram illustrating the G flag processing unit and the SPE control unit.
In this figure, G flag processing units 10A to 10D, SPE control units 399A to 399D, execution selection units 34B to 34D included in each SPE, and execution control units 30B to 30D are shown. The same components as those shown in FIGS. 10 and 12 are denoted by the same reference numerals.
The G flag processing sections 10A to 10D have the same configuration as that shown in FIG. Global_Inst_en_A is the same as the Global_Inst_en signal in FIG. 5 except that it is clearly indicated that the signal is SPE 302A. The same applies to Global_Inst_en_B (Gb) to Global_Inst_en_D (Gd).

The execution control unit 30B outputs a control signal (sel_B) that controls the execution of the SPE 302B by a control signal from the PE-I 3.
The execution control unit 30B generates a control signal sel_B signal for controlling the execution selection unit 34B. When the system_reset signal for initializing the parallel computing device 1 becomes active (“1”), the flip-flop 31B is set and the sel_B signal becomes “1”. Therefore, the Global_Inst_en_B signal is selected by the selector 34B and becomes the Global_Inst_en_act_B (Gba) signal for controlling the instruction of the SPEB 302B. That is, immediately after resetting, instruction execution is controlled by the Gb flag of the SPE 302B.

When the “SYNC” instruction is issued, the cnt_SYNC_B signal becomes active. At that time, since the cnt_ASYNC_B signal remains inactive, the sel_B signal becomes “0”. Therefore, in the selector 34B, the Global_Inst_en_A signal is selected and becomes a lobal_Inst_en_act_B signal. That is, the instruction execution of the SPE 302B is controlled according to the G flag of the SPE 302A.
When the “ASYNC” instruction is issued, the cnt_ASYNC_B signal becomes active, and “1” is written in the flip-flop 31B. Accordingly, the SPE 302B uses the value of the Gb flag for execution control. The flip-flop 31B changes at the rising edge of the basic clock in the parallel computing device 1 (not shown).
The execution control circuits 30C and 30D (synchronization circuits) of the SPE 302C and SPE 302D are the same as the execution control circuit 30B, but the signals to the B input of the selector (not shown) are not Global_Inst_en_B but Global_Inst_en_C and Global_Inst_en_D, respectively, and the selector S input Is different from sel_B in that sel_C and sel_D respectively, and the selector outputs Global_Inst_en_act_C (Gca) and Global_Inst_en_act_D (Gda).

It will be shown by using a program example that the processing speed is increased by the parallel computing device 1 shown in the third embodiment.
FIG. 22 shows an example in which the program of FIG. 13 is converted in the parallel computing device 1 for the VLIW type that performs four parallel processing in order to execute the program of FIG.
The SPE 302A performs condition judgment and the like, and the SPE 302B etc. executes an instruction in synchronization with the result.
First, the part of the instruction marked with “* 1” is executed by the SPE 302B up to the “ADD R7” instruction until the condition is judged by the SPE 302A (step 3). Immediately after executing the “PSHI C, Z” instruction in the SPE 302A, the result is written in the register R7 with the “MV R7” instruction. The same applies to the part of the instruction with “* 2”. By preparing 0 in advance in Acc-B, register R7 immediately after the result of “CMP R6” instruction is pushed to G flag stack 11A by SPE302A. Can be cleared. At the same time, as indicated by the instruction with “* 3”, data is also prepared in advance in the SPE 302C, and writing to the register R9 can be performed immediately.
Care must be taken with respect to the instruction part with “* 4” executed by the SPE 302D. These instructions are determined to be executed or not after the “GINV” instruction in the SPE 302A. That is, data cannot be prepared in advance like the SPE 302C. Therefore, the “MVA R10” instruction and the “INC” instruction are executed regardless of the G flag of the SPE 302A, and the “MV R10” instruction is executed by executing the “SYNC” instruction simultaneously with the “GINV” instruction in the SPE 302A. Only with the SPE 302A. By performing parallel processing with four SPEs in this way, the processing that took 21 clocks in FIG. 13 can be completed in 12 clocks.

In FIG. 22, portions not used in the SPE 302B, SPE 302C, and SPE 302D are indicated by blanks or shades. Arbitrary instructions can be placed in the blank portion, and instructions that do not need to be synchronized with the SPE 302A can be executed in parallel. On the other hand, an instruction synchronized with the SPE 302A or a “NOP” instruction can be arranged in the shaded portion.
In this example, the same result as in the second embodiment described above is obtained, but since each SPE can execute a nested program independently, the flexibility of instruction execution is improved, and the overall arithmetic processing is shorter than in the second embodiment. Can be processed in time.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 23 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. As for the arithmetic processing, the arithmetic processing unit 400 shown in the figure includes a plurality of arithmetic processors (PE) 402 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 402 via the SPE control signal line. A generation unit (PE-I) 3 and execution control units 40 </ b> A to 40 </ b> D that synchronize the SPEs under the control of the PE-I 3 are provided.

Each of the PEs 402 includes a sub processor (SPE) 402A and sub processors (SPE) 402B to 402D.
The SPE 402A includes a G flag processing unit 10A, an SPE control unit 499A, and an execution selection unit 44A. The SPE 402A includes an execution selection unit 44A in addition to the configuration corresponding to the SPE 102A shown in FIG. The G flag processing unit 10A and the SPE control unit 499A correspond to the G flag processing unit 10 and the SPE control unit 199A, respectively, and input / output signals indicate connection as the SPE 402A. In addition, the G flag processing unit 10A and the SPE control unit 499A are connected via the execution selection unit 44A.
The SPE 402B includes a G flag processing unit 10B, an SPE control unit 499B, and an execution selection unit 44B. The SPE 402B includes an execution selection unit 44B in addition to the configuration corresponding to the SPE 102A shown in FIG. The G flag processing unit 10B and the SPE control unit 499B correspond to the G flag processing unit 10 and the SPE control unit 199A, respectively, and input / output signals replace the connection as the SPE 402B. Further, the G flag processing unit 10B and the SPE control unit 499B are connected via the execution selection unit 44B.
In addition, the SPE 402C includes a G flag processing unit 10C, an SPE control unit 499C, and an execution selection unit 44C. The SPE 402D includes a G flag processing unit 10D, an SPE control unit 499D, and an execution selection unit 44D. SPE402C and SPE402D have the same configuration as SPE402B.

The G flag processing unit 10A supplies the G flag signal to the SPE control units 499A to 499D via the execution selection units 44A to 44D. The G flag processing unit 10B supplies the Gb flag signal to the SPE control units 499A to 499D via the execution selection units 44A to 44D. The G flag processing unit 10C supplies the Gc flag signal to the SPE control units 499A to 499D via the execution selection units 44A to 44D. The G flag processing unit 10D supplies the Gd flag signal to the SPE control units 499A to 499D via the execution selection units 44A to 44D.
The execution selection units 44A to 44D select either the G flag signal or the Gb flag signal to the Gd flag signal, respectively, and output them as execution permission signals of the SPE control units 499A to 499D.
The SPE control units 499A to 499D perform arithmetic control of each SPE based on the supplied execution permission signal.

  In this embodiment, the G flag stack shown in FIG. 5 is provided in each of the SPE 402A, SPE 402B, SPE 402C, and SPE 402D. Each SPE is normally individually controlled by the G, Gb, Gc, and Gd flag values, but the instruction execution is controlled according to the G flag value of a specific SPE as necessary. To.

FIG. 24 shows instructions to be added in the configuration of the fourth embodiment.
The difference from FIG. 20 described above is that any one operand of A, B, C, or D can be specified in the “SYNC” instruction. For example, when the “SYNC B” instruction is executed in the SPE 402A, the value of the G flag of the SPE 402B is used for instruction execution control thereafter. After executing the “ASYNC” instruction, the G flag provided in each SPE 402 is referred to and used for the value instruction execution control.

FIG. 25 is a block diagram illustrating the G flag processing unit and the SPE control unit.
Further, the G flag processing unit 10 in the SPE 102A will be described with reference to the connection between the G flag processing unit and the SPE control unit.
This figure shows G flag processing units 10A to 10D, SPE control units 499A to 499D, execution selection units 44B to 44D included in each SPE, and execution control units 40B to 40D. The same reference numerals are given to the same components as those shown in FIGS.
The G flag processing units 10A to 10D have the same configuration as that shown in FIG. Global_Inst_en_A is the same as the Global_Inst_en signal in FIG. The same applies to Global_Inst_en_B (Gb) to Global_Inst_en_D (Gd).

The operation of this circuit is shown for the SPE 402A. Global_Inst_en_A (Ga) is the same as the Global_Inst_en signal in FIG. 5, but _A is added at the end to distinguish it from other SPE signals. The same applies to Global_Inst_en_B.
When system_reset or “ASYNC” instruction is issued and cnt_ASYNC_A becomes active, the two flip-flops 41A and 42A in the figure are reset, and both the sel1_A signal and the sel0_A signal become “0”. Therefore, Global_Inst_en_A (Ga) is selected by the selector 44A and becomes the signal Global_Inst_en_act_A for controlling the instruction of the SPE 402A. That is, immediately after resetting, the value of its own G flag is used for execution control. When the “SYNC” instruction is issued, cnt_SYNC_A becomes active, and the values of cnt_Gsel_1_A and cnt_Gsel_0_A are written to the flip-flops 41A and 42A. The G flag signal selected by these values becomes Global_Inst_en_act_A.

FIG. 26 is a diagram illustrating control of the flip-flops 41A and 42A.
The flip-flops 41A and 42A are controlled by setting cnt_Gsel_1_A and cnt_Gsel_0_A.
As shown in this figure, the value is determined according to the operand of the “SYNC” instruction. Flip-flops 41A and 42A shown in FIG. 25 are for the SPE 402A. The same applies to the execution control circuits 40B to 40D of the SPE 402B, SPE 402C, and SPE 402D. However, when system_reset or cnt_ASYNC_B to cnt_ASYNC_D become active, the values output by flip-flops 41B to 41D and 42B to 42D that hold sel1_B to sel1_D and sel0_B to sel0_D are different, SPE402B is (0, 1) (1,0), and SPE402D is (1,1).

It will be shown by using a program example that the processing speed is increased by the fourth embodiment.
FIG. 27 shows an example in which the program of FIG. 13 is converted for the 4-parallel VLIW type in order to execute the program of FIG. 13 in the parallel computing device 1.
The condition determination can be executed by any SPE, but here, the SPE 402B performs the condition determination and the other SPEs execute the instruction in synchronization with the result. First, the part of the instruction marked with “* 1” is executed until the “ADD R7” instruction (step 3) is executed by the SPE 402A while the condition is judged by the SPE 402B, and the “PSHI C, Z” instruction is issued by the SPE 402B. Immediately after execution, the result is written to the register R7 by the “MV R7” instruction. The same applies to the part of the instruction marked with “* 2”. By setting Acc93A to “0” in advance by the SPE 402A, the result of the “CMP R6” instruction is pushed to the G flag stack by the SPE 402B (step 6). You can clear register R7. At the same time, as indicated by the instruction with “* 3”, the SPE 402C also prepares data in advance and can immediately write to the register R9.

  Care should be taken with respect to the instruction part with “* 4” executed by the SPE 402D. These instructions are determined to be executed after the “GINV” instruction in the SPE 402B. That is, data cannot be prepared in advance like the SPE 402C. Therefore, the “MVA R10” instruction and the “INC” instruction are executed regardless of the value of the G flag of the SPE 402B, and the “SYNC B” instruction is executed simultaneously with the “GINV” instruction in the SPE 402B. Only the “R10” instruction is synchronized with SPE 402B. By performing parallel processing with four SPEs in this way, the processing of 21 clocks in FIG. 13 can be completed in 12 clocks.

  In FIG. 27, portions that are not used in SPE 402A, SPE 402C, and SPE 402D are indicated by blanks or shaded areas. Arbitrary instructions can be placed in the blank portion, and instructions that do not need to be synchronized with the SPE 402B can be executed in parallel. On the other hand, an instruction synchronized with the SPE 402B or a “NOP” instruction can be arranged in the shaded portion. In this example, the processing speed is the same as that of the third embodiment, but any SPE can be set as a master PE that performs condition determination, so that the flexibility in using the SPE is remarkably improved. Processing can be performed in a shorter time than the embodiment.

(Fifth embodiment)
A fifth embodiment of the present invention will be described.
Here, as an example, the SPE 502A is a special SPE, and it is possible to control whether other SPEs synchronize with it.

FIG. 28 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. Regarding the arithmetic processing, the arithmetic processing unit 500 shown in the figure includes a plurality of arithmetic processors (PE) 502 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 502 via the SPE control signal line. A generation unit (PE-I) 3 and execution control units 50SCB to 50SCD that synchronize each SPE under the control of PE-I3 are provided.

Each of the PEs 502 includes a sub processor (SPE) 502A and sub processors (SPE) 502B to 502D.
The SPE 502A includes a G flag source 50FSA, a G flag stack 50STA, and an SPE control unit 599A.
The SPE 502A has a configuration in which the G flag processing unit 10 is divided into two in the configuration corresponding to the SPE 102A shown in FIG. The G flag source 50FSA that performs one pre-stage processing collects and outputs the output of the selected flag register into one signal. The G flag stack 50STA that performs the other post-processing corresponds to the G flag stack 11 and the combining unit 19 described above. The G flag stack 50STA records the signal output from the preceding flag source 50FSA according to the condition. The SPE control unit 599A corresponds to the SPE control unit 199A.
The SPE 502B includes a G flag source 50FSB, a G flag stack 50STB, an SPE control unit 599B, and an execution selection unit 55B. That is, the SPE 502B includes an execution selection unit 55B in addition to the configuration corresponding to the SPE 502A described above. Also, the G flag source 50FSB and the G flag stack 50STB are connected via the execution selection unit 55B.
The SPE 502C includes a G flag source 50FSC, a G flag stack 50STC, an SPE control unit 599C, and an execution selection unit 55C. The SPE 502D includes a G flag source 50FSD, a G flag stack 50STD, an SPE control unit 599D, and an execution selection unit 55D. SPE502C and SPE502D have the same configuration as SPE502B.

The G flag source 50FSA supplies a G flag source signal to the G flag stacks 50STA to 50STD. The G flag source 50FSB supplies the G flag source signal to the G flag stack 50STB via the execution selection unit 55B. The G flag source 50FSC supplies the G flag source signal to the G flag stack 50STC via the execution selection unit 55C. The G flag source 50FSD supplies a G flag source signal to the G flag stack 50STD via the execution selection unit 55D.
The execution selectors 55B to 55D respectively select one of the G flag source signal and the Gb flag source signal to the Gd flag source signal, and store them in the respective G flag stacks 50STB to 50STD. Each of the G flag stacks 50STB to 50STD outputs an execution control signal of the SPE control units 599A to 599D based on the accumulated G flag source signal.
The SPE control units 599A to 599D perform arithmetic control of each SPE based on the supplied execution permission signal.

  In the present embodiment, the G flag stack shown in FIG. 5 is provided in each of the SPE 502A, SPE 502B, SPE 502C, and SPE 502D. Each SPE is normally individually controlled based on the G, Gb, Gc, and Gd flag source signals, but if necessary, the instruction execution is controlled according to the G flag source of a specific SPE. Like that.

FIG. 29 shows instructions to be added in the configuration of the fifth embodiment.
These instructions are valid only in the SPE 502B, SPE 502C, and SPE 502D, and can be executed only when the G flag stack is pushed by the “PSH” instruction or the “PSHI” instruction in the SPE 502A.

FIG. 30 is a block diagram showing a synchronization circuit of the SPE 502B.
This figure shows a schematic configuration of the SPE 502A and a configuration of the SPE 502B.
The SPE 502A includes a G flag source 50FSA, a flag stack 50STA, and an SPE control unit 599A.
The G flag source 50FSA performs a gate process on the value of the condition flag output from the flag register 97 (not shown) and the control signal designated by the PE-I3, and detects the state of the condition flag to be determined. (Gflag_org_A) is output. Each input signal is the same as in FIG.
The G flag source 50FSA supplies the G flag source signal (Gflag_org_A) to the G flag stack 50STA in the SPE 502A, and controls the SPE 502A. The G flag source 50FSA supplies a G flag source signal (Gflag_org_A) to the SPE 502B and SPE 502C and SPE 502D (not shown). The SPE control unit 599A corresponds to the SPE control unit 199A.

The SPE 502B includes a G flag source 50FSB, a flag stack 50STB, an SPE control unit 599B, an execution selection unit 55B, and an execution control unit 50SCB.
The G flag source 50FSB and the SPE control unit 599B have the same configuration as the SPE 502A described above.
The execution selection unit 55B selects the signals of the input G flag source 50FSA and G flag source 50FSB and outputs them to the flag stack 50STB.
The execution control unit 50SCB controls selection of the input signal of the execution control unit 55B in accordance with the “PSH” instruction or the “PSHI” instruction in the SPE 502B.
The flag stack 50STB sequentially accumulates the results selected by the execution selection unit 55B in the G flag stack 51B.
Although SPE 502B is shown, SPE 502C and SPE 502D are also connected with the same configuration.

  In this embodiment, the G flag stacks 50STA to 50STD are provided in all the SPEs, and the value itself pushed to the SPE is controlled, which is different from the second, third, and fourth embodiments. The G flag stack of the SPE 502A is basically the same as that in FIG. 5, except that a signal Gflag_org_A obtained by ORing operands is extracted and supplied to other SPEs.

  When the “PSH” instruction or the “PSHI” instruction is executed in the SPE 502B, the value pushed to the G flag stack is the same as in FIG. Accordingly, the SPE 502B can execute a program nested in an asynchronous manner with the SPE 502A. When the “SYNC” instruction or the “SYNCI” instruction is issued in the SPE 502B, the cnt_SYNC_B or cnt_SYNCI_B signal becomes active, and Gflag_org_A selected by sel1 is pushed onto the G flag stack. In the case of the “SYNCI” instruction and the “PSHI” instruction, the value of the condition code selected by sel1 is inverted and written to the G flag stack. In addition, the operation when the “POP” instruction or the “FLSH” instruction is issued and the operation when the system reset signal system_reset becomes active are the same as those in FIG.

The speeding up of processing according to the fifth embodiment will be described using a program example.
FIG. 31 shows an example of parallelizing the program of FIG. 13 in order to execute the program of FIG. 13 in the parallel computing device 1.
In SPE 502A, the condition is judged twice and pushed to the G flag stack by the “PSHI” instruction. At the same time, the SPE 502B and the SPE 502C are both pushed to the G flag stack by the “SYNCI” instruction. As a result, since the G flag of SPE502B and SPE502C holds the same value as the G flag of SPE502A, the instruction executed in SPE502A is executed in SPE502B and SPE502C, and the instruction not executed in SPE502A is not executed in SPE502B and SPE502C.

What is characteristic is the operation of the SPE 502D. In the SPE 502D, when the first “PSHI C, Z” instruction is executed in the SPE 502A, the inversion of the value pushed to the G flag stack of the SPE 502A by the “SYNC” instruction is pushed to its own G flag stack. Therefore, the SPE 502D can immediately execute the instruction part with “* 5” corresponding to the “else statement” and the subsequent.
Therefore, data is prepared in advance by the “MVA R8” instruction and the “ADD R5” instruction, and the result is written in the register R8 by the “MV R8” instruction immediately after the “SYNC” instruction. Care must be taken with the “GINV” instruction immediately after the “MV R8” instruction. The instruction portion with “* 4” in FIG. 13 is executed when the first condition judgment at SPE 502A is true and the second condition judgment is false. Since the SPE 502D pushes a value opposite to that of the SPE 502A to the G flag stack in the first condition determination, the instruction portion with “* 4” cannot be executed as it is. Therefore, the value pushed first by the “GINV” instruction is inverted. After that, when the second “PSHI C, Z” instruction is executed in SPE502A, the instruction part with “* 4” can be assigned by pushing the opposite value to SPE502A with “SYNC” instruction. Become. In this embodiment, all processing is completed in 10 clocks.

  In the SPE 502A, the “POP” instruction is repeated twice last, but it can be replaced with one “FLSH” instruction as in the SPE 502B. In addition, although a portion not used in SPE502A, SPE502B, and SPE502C is blank, an arbitrary instruction can be placed here, and an instruction that does not need to be synchronized with SPE502A can be executed in parallel.

(Sixth embodiment)
A sixth embodiment of the present invention will be described.
FIG. 32 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. As for the arithmetic processing, the arithmetic processing unit 600 shown in the figure includes a plurality of arithmetic processors (PE) 602 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 602 via the SPE control signal line. A generation unit (PE-I) 3 and execution control units 50SCA to 50SCD that synchronize each SPE under the control of PE-I3 are provided.

Each of the PEs 602 includes a sub processor (SPE) 602A and sub processors (SPE) 602B to 602D.
The SPE 602A includes a G flag source 50FSA, a G flag stack 60STA, an SPE control unit 699A, and an execution selection unit 645A.
The SPE 602A has a configuration that selects an input G flag source signal based on a control signal from the execution selection unit 645A in addition to the configuration corresponding to the SPE 502A described above. The G flag stack 60STA has the same configuration as the G flag stack 50STA. The SPE control unit 699A corresponds to the SPE control unit 199A.
The SPE 602B includes a G flag source 50FSB, a G flag stack 60STB, an SPE control unit 699B, and an execution selection unit 645B. The SPE 602C includes a G flag source 50FSC, a G flag stack 60STC, an SPE control unit 699C, and an execution selection unit 645C. The SPE 602D includes a G flag source 50FSD, a G flag stack 60STD, an SPE control unit 699D, and an execution selection unit 645D.
SPE 602B to SPE 602D have the same configuration as SPE 602A.

The G flag sources 50FSA to 50FSD supply G flag source signals to the G flag stacks 60STA to 60STD via the execution selection units 645A to 645D.
The execution selection units 645A to 645D respectively select one of the G flag source signals (Ga flag source signal to Gd flag source signal) supplied from the G flag sources 50FSA to 50FSD, and set the values of the selected signals to the respective values. The G flag stacks 60STA to 60STD are accumulated. Each of the G flag stacks 60STA to 60STD outputs an execution control signal of the SPE control units 699A to 699D based on the accumulated G flag source signal.
The SPE control units 699A to 699D perform calculation control of each SPE based on the supplied execution permission signal.

  In this embodiment, the G flag stack shown in FIG. 5 is provided in each of the SPE 602A, SPE 602B, SPE 602C, and SPE 602D. Each SPE is usually individually controlled for instruction execution based on the values of the respective Ga, Gb, Gc, and Gd flag source signals, but instruction execution is controlled according to the G flag of any SPE as required. Is done.

FIG. 33 shows instructions to be added in the configuration of the sixth embodiment.
FIG. 34 is a block diagram illustrating an SPE synchronization circuit according to the sixth embodiment.
FIG. 34 shows a configuration example of the SPE 602A as a representative. The SPE 602A includes a G flag source 50 FSA, a G flag stack 60STA, an SPE control unit 699A, and an execution selection unit 645A.
The execution selection unit 645A includes execution selection units 64A and 65A.
The execution selection unit 64A has the same configuration as the execution selection unit 44A shown in FIG. 25, and the execution selection unit 65A has the same configuration as the execution selection unit 55B shown in FIG.
Further, the execution control unit 60SCA includes both the configuration of the execution control unit 50SCA corresponding to the execution control unit 50SCB shown in FIG. 30 and the configuration of the execution control unit 40A shown in FIG.

The execution selection unit 64A in the execution selection unit 645A selects one of the signals of the input G flag source 50FSA to the G flag source 50FSD and outputs the value. The execution selection unit 65A selects either the flag source signal output from the execution selection unit 64A or the signal from the G flag source 50FSA, and outputs the value to the flag stack 60STA.
The execution control unit 60SCA controls selection of the input signal of the execution control unit 645A in accordance with the “PSH” instruction or the “PSHI” instruction in the SPE 602A.
The flag stack 60STA sequentially accumulates the results selected by the execution selection unit 645A in the G flag stack 51A.
Although SPE 602A is shown, SPE 602B, SPE 602C, and SPE 602D are also connected in the same configuration.

In the “SYNC” instruction and the “SYNCI” instruction, any one of A, B, C, and D can be specified as an operand, and the cnt_Gsel — 1_A and cnt_Gsel — 0_A signals are determined accordingly as shown in FIG. In accordance with these instructions, the execution control unit 40A in the execution control unit 60SCA synchronizes the SPE execution control with any other SPE by referring to the G flag of any other SPE for the condition of the SPE execution control. Let me.
Further, when the “PSH” instruction or the “PSHI” instruction is executed, the value pushed to the G flag stack is the same as in FIG. The condition flag selected by the operands of these instructions is also supplied to other SPEs as Gflag_org_A. Gflag_org_B, Gflag_org_C, and Gflag_org_D are signals generated by SPE602B, SPE602C, and SPE602D, respectively.
When a “SYNC” instruction or a “SYNCI” instruction is issued, the cnt_SYNC_A or cnt_SYNCI_A signal becomes active, the condition code selected by the execution selection unit 64A is selected by the execution selection unit 65A, and the value is set to the G flag stack. Pushed to. In the case of the “SYNCI” instruction and the “PSHI” instruction, the value of the selected condition code is inverted and then written to the G flag stack. The operation when the “POP” instruction, “POPI” instruction, “GINV” instruction, and “FLSH” instruction are issued, and the operation when the system reset signal system_reset becomes active are the same as those in FIG. .

The speeding up of processing according to the sixth embodiment will be described using a program example.
FIG. 35 shows an example in which the program of FIG. 13 is converted for the 4-parallel VLIW type in order to execute the program of FIG. 13 in the parallel computing device 1 of the sixth embodiment.
In this example, the condition is judged twice in SPE 602B and pushed to the G flag stack by the “PSHI” instruction.
At the same time, the SPE 602A and SPE 602C push the G flag stack with the “SYNCIB” instruction. Therefore, since the G flag of SPE 602A and SPE 602C holds the same value as the G flag of SPE 602B, the instruction executed in SPE 602B is executed in SPE 602A and SPE 602C, and the instruction not executed in SPE 602B is not executed in SPE 602A or SPE 602C.

  What is characteristic is the operation of SPE602D. Here, when the first “PSHI C, Z” instruction is executed in the SPE 602B, the inversion of the value pushed to the G flag stack of the SPE 602B by the “SYNC B” instruction is pushed to its own G flag stack. Therefore, the SPE 602D can immediately execute the instruction part with “* 5” corresponding to the “else statement” and the subsequent. Therefore, data is prepared in advance by the “MVA R8” instruction and the “ADD R5” instruction, and the result is written in the register R8 by the “MV R8” instruction immediately after the “SYNC B” instruction. Care must be taken with the “GINV” instruction immediately after the “MV R8” instruction. The instruction portion with “* 4” in FIG. 13 is executed when the first condition judgment at SPE 602B is true and the second condition judgment is false. Since the SPE 602D pushes a value opposite to that of the SPE 602B to the G flag stack in the first condition determination, the instruction portion with “* 4” cannot be executed as it is. Therefore, the first pushed value is inverted by the “GINV” instruction. Then, when the second “PSHI C, Z” instruction is executed in the SPE 602B, the “SYNC B” instruction pushes a value opposite to that of the SPE 602B, thereby handling the instruction portion with “* 4”. In this embodiment, all processing is completed in 10 clocks.

  Note that although portions not used in the SPE 602A, SPE 602B, and SPE 602C are blank, any instruction can be placed here, and instructions that do not need to be synchronized with the SPE 602B can be executed in parallel. In this example program, the number of clocks required for processing is the same as in the fifth embodiment, but since the SPE for determining the condition can be set arbitrarily, the flexibility of how to use the SPE is improved, and generally more than in the fifth embodiment. Processing can be speeded up.

(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described.
In this embodiment, the G flag stack shown in FIG. 5 is provided only in the SPE 702A, and the SPEs other than the SPE 702A are controlled to execute instructions according to the G flag of the SPE 702A or an inverted signal of the G flag, or the G flag of the SPE 702A. Select whether to always execute the instruction without being affected.

FIG. 36 is a block diagram illustrating a schematic configuration of the arithmetic processing unit of the parallel computing device 1.
Here, a main configuration necessary for explaining the arithmetic control process is shown. As for the arithmetic processing, the arithmetic processing unit 700 shown in the figure includes a plurality of arithmetic processors (PE) 702 that perform arithmetic processing in parallel, and a control signal that supplies a control command to the plurality of PEs 702 via the SPE control signal line. A generation unit (PE-I) 3 and execution control units 70SCB to 70SCD that synchronize each SPE under the control of PE-I3, and an inversion control unit 79B that inverts the signal of the G flag under the control of PE-I3 79D.

Each of the PEs 702 includes a sub processor (SPE) 702A and sub processors (SPE) 702B to 702D. The SPE 702A includes a G flag processing unit 10 and an SPE control unit 799A. The SPEs 702B to 702D include SPE control units 799B to 799D and process selection units 75B to 75D, respectively.
The process selection units 75B to 75D in the SPEs 702B to 702D include execution selection units 74B to 74D and inversion processing units 78B to 78D, respectively.
The G flag processing unit 10 supplies the G flag signal to the SPE control units 799B to 799D via the SPE control unit 799A, the inversion processing units 78B to 78D, and the execution selection units 74B to 74D.
The inversion processing units 78B to 78D perform inversion processing on the G flag supplied from the G flag processing unit 10 based on the control signals from the inversion control units 79B to 79D. The execution selection units 74B to 74D output execution permission signals to the SPE control units 799B to 799D based on the supplied G flag signal or the inverted G flag signal and the execution permission signals of the execution control units 70SCB to 70SCD, respectively. To do.
The SPE control units 799A to 799D perform arithmetic control of each SPE based on the supplied execution permission signal.

FIG. 37 shows instructions to be added in the configuration of the seventh embodiment.
These instructions can only be executed by SPE 702B, SPE 702C and SPE 702D. For example, when the “SYNC” instruction is executed in the SPE 702B, the G flag of the SPE 702A is used for instruction execution control. When the “SYNCI” instruction is executed, the inversion of the G flag value of the SPE 702A is used for instruction execution control. When the “ASYNC” instruction is executed, the instruction is executed regardless of the value of the G flag of the SPE 702A.

FIG. 38 is a block diagram showing an SPE synchronization circuit.
This example is the case of SPE702B, and since it becomes complicated, illustration of the same circuit as FIG. 5 is omitted.
This figure shows a G flag processing unit 10, SPE control units 799A and 799B included in SPEs 702A and 702B, an execution selection unit 74B and an execution control unit 70SCB, an inversion control unit 79B, and an inversion processing unit 78B. The same reference numerals are given to the same components as those shown in FIGS.
The G flag processing unit 10 has the same configuration as that shown in FIG. 5 described above, and the output signal is Global_Inst_en_A. Global_Inst_en_A is the same as the Global_Inst_en signal in FIG. 5 except that it is clearly indicated that the signal is SPE 702A.

  The execution control unit 70SCB outputs a control signal (Async_B) for controlling the execution of the SPE 702B by a control signal from the PE-I3. The execution control unit 70SCB generates a control signal Global_Inst_en_B signal by controlling the execution selection unit 74B. The inversion processing unit 78B performs inversion processing of the value of the G flag. Here, an EXOR circuit is shown. The inversion control unit 79B outputs a control signal (Inv_B) for controlling the execution of the SPE 702B by the control signal from the PE-I3.

  Global_Inst_en_B is a signal used for instruction execution control in the SPE 702B. When system_reset becomes active (“1”), the flip-flop 71B is set and the Async_B signal becomes “1”. Therefore, since Global_Inst_en_B is always “1”, the instruction is always executed in the SPE 702B. When the “SYNC” instruction is issued, the cnt_SYNC_B signal becomes active, the Inv_B signal becomes “0”, and the Async_B signal also becomes “0”. Therefore, Global_Inst_en_B is the same as Global_Inst_en_A. That is, the instruction execution of the SPE 702B is controlled according to the value of the G flag of the SPE 702A.

When the “SYNCI” instruction is issued, the cnt_SYNCI_B signal becomes active, the Inv_B signal becomes “1”, and the Async_B signal becomes “0”. Therefore, Global_Inst_en_B is an inversion of Global_Inst_en_A. That is, the instruction execution of the SPE 702B is controlled according to the inversion of the value of the G flag of the SPE 702A. When the “ASYNC” instruction is issued, the cnt_ASYNC_B signal becomes active, the Inv_B signal becomes “0”, and the Async_B signal becomes “1”. Note that the flip-flop 71B and the inversion control unit 79B change at the rising edge of the basic clock in the parallel computing device 1 (not shown).
The SPE 702C and SPE 702D have the same configuration as that shown in the SPE 702B.

It will be shown by using a program example that the processing speed is increased by the seventh embodiment.
FIG. 39 shows an example in which the program of FIG. 13 is converted for the 4-parallel VLIW type in order to execute the program of FIG. 13 in the parallel computing device 1 of the seventh embodiment.
The SPE 702A performs condition determination and the like, and the SPE 702B executes an instruction in synchronization with the result. First, it is the part of the instruction with “* 1”. Until the condition is judged by SPE 702A, the SPE 702B executes up to the “ADD R7” instruction, and the SPE 702A executes the “PSHI C, Z” instruction. Immediately after that, the result is written to the register R7 by the “MV R7” instruction. The same applies to the instruction part with “* 2”. By setting Acc-A to “0” in advance with the “CLR” instruction, the result of the “CMP R6” instruction is pushed onto the G flag stack by the SPE 702A. Immediately after that, register R7 can be cleared.
Similarly, as indicated by the instruction with “* 3”, data is prepared in advance in the SPE 702C, and writing to the register R9 can be performed immediately.

  In the instruction part marked with “* 5” in SPE702D, first, the “MVA R8” instruction and “ADD R5” instruction are executed regardless of the state of SPE702A, and the “PSHI C, Z” instruction is executed in SPE702A. Sometimes "SYNCI" instruction is executed. Therefore, since execution control is performed by reversing the value of the G flag of the SPE 702A, the “MV R8” instruction corresponding to the “else statement” and the subsequent can be executed immediately. The instruction part with “* 4” is also the same. Once the “ASYNC” instruction is executed, the “MVA R10” instruction and the “INC” instruction are executed irrespective of the value of the G flag of the SPE 702A. By executing the “SYNC” instruction after the “GINV” instruction, only the “MV R10” instruction is synchronized with the SPE 702A. By performing parallel processing with four SPEs in this way, in FIG. 13, the processing that took 21 clocks is completed in 10 clocks.

  In FIG. 39, portions not used in SPE 702B, SPE 702C, and SPE 702D are indicated by blanks or shaded areas. Arbitrary instructions can be placed in the blank portion, and instructions that do not need to be synchronized with the SPE 702A can be executed in parallel. On the other hand, an instruction synchronized with the SPE 702A or a “NOP” instruction can be arranged in the shaded portion. In the present embodiment, processing can be performed with two clocks fewer than in the second embodiment. Therefore, it is highly likely that the entire arithmetic processing will be completed in a shorter time than in the second embodiment.

  According to the embodiment of the present invention described above, hardware that supports multiple nested structured programs can be easily realized in a parallel computing device combining a VLIW type with a SIMD type. Therefore, since a large number of arithmetic elements (processors) can be efficiently operated in parallel, a computer having an arithmetic capability of several Tflops or several hundred GOPS required for scientific calculation or image processing can be easily realized.

The present invention is not limited to the above embodiments, and can be modified without departing from the spirit of the present invention.
For example, although the number of arithmetic processors incorporated in one parallel processing device 1 of the present invention is 108, the present invention is not limited to this, and a computer generally incorporating two or more arithmetic processors. Applicable to. Although the program nesting hierarchy is four, the present invention is not limited to this, and is generally effective for a structure having two or more nests.
Further, although the number of sub processors to be parallelized in the VLIW type is four for each arithmetic processor, the present invention is not limited to this, and can be applied to a system having two or more sub processors.
In addition, as flag information for controlling instruction execution, the carry (C) flag, negative (N) flag, overflow (V) flag, and zero (Z) flag are used, but the present invention is not limited to this. Some of them, for example, the V flag can be omitted, or conversely, half carry (H) can be adopted.
In the embodiment of the present invention, the number of bits of the accumulator (Acc) and ALU is not particularly mentioned, but the present invention can be applied to a parallel computing device having an arbitrary number of bits.

102 Computing processor (PE)
102A Sub operation processor (SPE, specific sub processor)
102B, 102C, 102D Sub arithmetic processor (SPE, sub processor)
11 G flag stack (first control information holding unit)
19 Synthesizer (first synthesizer)
95A ALU (first arithmetic unit)
199A SPE controller (first controller)
95B ALU (second arithmetic unit)

Claims (7)

A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors is
A first operation unit for the first processing the input data based on the control command,
A first control information holding unit that has a stack structure and sequentially stores flag information based on a result of the first arithmetic processing;
A first combining unit that combines the flag information stored in the first control information holding unit;
A first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without storing the synthesis flag information combined by the first combination unit in a stack structure ;
A specific subprocessor comprising:
A second arithmetic unit for the second arithmetic processing the input data based on the control command,
A second control unit that causes the second calculation unit to perform a second calculation process based on the combination flag information without storing the combination flag information combined by the first combination unit in a stack structure ;
A subprocessor comprising:
A parallel computing device comprising: A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors is
A first operation unit for the first processing the input data based on the control command,
A first control information holding unit that has a stack structure and sequentially stores flag information based on a result of the first arithmetic processing;
A first combining unit that combines the flag information stored in the first control information holding unit;
A first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without storing the synthesis flag information combined by the first combination unit in a stack structure ;
A specific subprocessor comprising:
A second arithmetic unit for the second arithmetic processing the input data based on the control command,
A selection unit that selects whether or not to use the synthesis flag information synthesized by the first synthesis unit for controlling the second computation process of the second computation unit;
Synthesis flag information synthesized by the first synthesis unit when the selection unit selects to use the synthesis flag information synthesized by the first synthesis unit for controlling the second computation process of the second computation unit . A second control unit that causes the second calculation unit to perform a second calculation process based on the synthesis flag information without storing the data in the stack structure ;
A subprocessor comprising:
A parallel computing device comprising: A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors is
A first operation unit for the first processing the input data based on the control command,
A first control information holding unit that has a stack structure and sequentially stores flag information based on a result of the first arithmetic processing;
A first combining unit that combines the flag information stored in the first control information holding unit;
A first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without storing the synthesis flag information combined by the first combination unit in a stack structure ;
A specific subprocessor comprising:
A second arithmetic unit for the second arithmetic processing the input data based on the control command,
A second control information holding unit that has a stack structure and sequentially stores flag information based on the result of the arithmetic processing;
A second combining unit that combines the flag information accumulated in the second control information holding unit;
A selection unit that selects any one of the synthesis flag information synthesized by the first synthesis unit and the synthesis flag information synthesized by the second synthesis unit of the sub processor without being accumulated in a stack structure ;
A second control unit that causes the second calculation unit to perform a second calculation process based on the combination flag information without storing the combination flag information selected by the selection unit in a stack structure ;
A subprocessor comprising:
A parallel computing device comprising: A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors includes a plurality of sub-processors,
Each of the sub-processors
An arithmetic unit that performs arithmetic processing on the input data based on the control command;
A control information holding unit that has a stack structure and sequentially stores flag information based on the result of the arithmetic processing;
A combining unit that combines the flag information accumulated in the control information holding unit of its own sub-processor;
A selection unit that selects any one of the synthesis flag information without accumulating the synthesis flag information synthesized by the synthesis unit of any sub-processor in a stack structure ;
A control unit that causes the calculation unit to perform calculation processing based on the selected combination flag information without storing the combination flag information selected by the selection unit in a stack structure ;
Equipped with a,
The arithmetic units included in the plurality of sub-processors are:
A parallel computing device characterized in that different arithmetic processing can be performed . A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors is
A first operation unit for the first processing the input data based on the control command,
A first control information holding unit that has a stack structure and sequentially stores flag information based on the result of the arithmetic processing;
A first combining unit that combines the flag information stored in the first control information holding unit;
A first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without storing the synthesis flag information combined by the first combination unit in a stack structure ;
A specific subprocessor comprising:
A second arithmetic unit for the second arithmetic processing the input data based on the control command,
Either flag information based on the result of the first arithmetic processing by the first arithmetic unit or flag information based on the result of the second arithmetic processing by the second arithmetic unit of the sub processor is selected. A selection section;
A second control information holding unit that has a stack structure and sequentially stores flag information selected by the selection unit;
A second combining unit that combines the flag information accumulated in the second control information holding unit;
A second control unit that causes the second calculation unit to perform a second calculation process based on the combination flag information without accumulating the combination flag information combined by the second combination unit in a stack structure ;
A subprocessor comprising:
A parallel computing device comprising: A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors includes a plurality of sub-processors,
Each of the sub-processors
An arithmetic unit that performs arithmetic processing on the input data based on the control command;
A selection unit that selects any one of flag information based on a result of calculation processing by the calculation unit of any sub-processor;
A control information holding unit that has a stack structure and sequentially stores flag information selected by the selection unit;
A combining unit that combines the flag information stored in the control information holding unit;
A control unit that causes the calculation unit to perform calculation processing based on the combination flag information without storing the combination flag information combined by the combination unit in a stack structure ;
Equipped with a,
The arithmetic units included in the plurality of sub-processors are:
A parallel computing device characterized in that different arithmetic processing can be performed . A plurality of arithmetic processors that perform arithmetic processing in parallel;
A control signal generator for supplying a control command to each of the plurality of arithmetic processors;
With
Each of the plurality of arithmetic processors is
A first operation unit for the first processing the input data based on the control command,
A first control information holding unit that has a stack structure and sequentially stores flag information based on a result of the first arithmetic processing;
A first combining unit that combines the flag information stored in the first control information holding unit;
A first control unit that causes the first calculation unit to perform a first calculation process based on the combination flag information without storing the synthesis flag information combined by the first combination unit in a stack structure ;
A specific subprocessor comprising:
A second arithmetic unit for the second arithmetic processing the input data based on the control command,
The synthesis flag information synthesized by the first synthesis unit is selected to be output as it is or inverted and output as flag information output without being accumulated in the stack structure. An inversion processing unit;
A selection unit that selects either the flag information output or the control information that always enables instruction execution without accumulating the flag information output output by the inversion processing unit in a stack structure ;
A second control unit that causes the second calculation unit to perform a second calculation process based on the information selected by the selection unit;
A subprocessor comprising:
A parallel computing device comprising:

Images