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JP5332120B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5332120B2
JP5332120B2 JP2007066098A JP2007066098A JP5332120B2 JP 5332120 B2 JP5332120 B2 JP 5332120B2 JP 2007066098 A JP2007066098 A JP 2007066098A JP 2007066098 A JP2007066098 A JP 2007066098A JP 5332120 B2 JP5332120 B2 JP 5332120B2
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semiconductor substrate
semiconductor
oxide film
adhesive sheet
semiconductor device
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JP2007281446A (en
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里美 梶原
邦雄 望月
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can prevent the separation of an enforcing sheet from an adhering surface in a semiconductor process subsequent to the bonding together of the surface of a semiconductor wafer and the enforcing sheet. <P>SOLUTION: In the semiconductor device manufacturing method after the surface side of a semiconductor substrate 1 is processed, a photoresist film 7 is coated for flattening surface roughness formed on the surface of the semiconductor substrate 1, and the back of the semiconductor substrate 1 is ground while the enforcing sheet 4 is bonded together to the flat surface of the photoresist film 7 via an adhesive agent 5. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

半導体基板の裏面研削に際して、半導体基板の表面側の保護と機械的補強のために、半導体基板の表面側に補強板を張り合わせる工程を有する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, which includes a step of attaching a reinforcing plate to a front surface side of a semiconductor substrate in order to protect and mechanically reinforce the front surface side of the semiconductor substrate when the back surface of the semiconductor substrate is ground.

半導体装置として構成される半導体基板は、阻止電圧(耐圧)を確保するためには阻止電圧の大きさに比例して広くなる所要の高抵抗層幅を必要とする。この高抵抗層幅が広くなれば半導体基板もそれに応じて厚くなる。耐圧に必要な前記高抵抗層幅は半導体シリコンの場合、たとえば、600Vで70μm、1200Vで120μm位である。一方、半導体ウエハプロセスでは、半導体ウエハ(半導体基板)の厚さが薄いと、プロセス中でのウエハ割れが多くなるが、500μm以上の厚さがあれば、ウエハプロセスでの割れ不良はほとんど問題にならない程度に抑えられる。ウエハ割れが多いと、不良となる割合が高くなって作業効率が悪くなるだけでなく、コストの面からも好ましくないので、プロセス中の半導体ウエハはなるべく厚い方が好ましい。そのため、半導体ウエハプロセスへの投入時には、前記耐圧に係わらず、500μm以上の厚いウエハが用いられる。しかし、ウエハの厚さが耐圧に必要な厚さ以上に(特に高抵抗層部分が)厚いと、オン電流を流した時の電圧降下、すなわち、オン抵抗が大きくなるので、実際には、半導体ウエハプロセスでは、半導体基板の表面側のプロセスが終了するまでは厚いウエハでプロセスを進め、半導体ウエハの裏面側のプロセスに移行する前に、オン抵抗を小さくするために半導体ウエハの裏面を耐圧に必要な厚さ近くまで研削する製造方法が採られる場合がある。そのような製造方法では、半導体ウエハの表面に形成されている各種半導体パターンや電極膜の保護と半導体ウエハを機械的に補強する目的の補強板または補強フィルムを張り合わせた状態で裏面研削工程以降の工程を進行させている。この時の半導体ウエハと補強板または補強フィルムとの貼り合わせには、一般的に粘着剤などを介して行われる。
従来の半導体装置について説明すると、図3に示すように、半導体シリコン基板1に対して、この基板1内部に形成される半導体素子機能に必要な加工工程(図示せず)を経て、最終的に半導体基板1の内部に形成された半導体機能要素が表面に配置される金属電極および配線金属2に接続配線される。さらにそれらの最表面には保護膜として、ポリイミド樹脂膜などのパッシベーション膜3が成膜されている。但し、このパッシベーッション膜3は、前記半導体基板表面で酸化膜や配線金属2などが載置される結果生じるすべての段差(凹凸)を吸収するほど厚く形成されていないため、パッシベーション膜3の表面には凹凸が残っている。また、このパッシベーション膜3は半導体基板の最表面に塗布された後、アルミニウムワイヤなどの外部接続リード線をボンディングにより固着する金属電極部やダイシングにより半導体基板をチップ化するための切断分離線に相当する部分を開口するために、フォトリソグラフィ(フォトエッチング)が施される。その結果、このパッシベーション膜3は全面に塗布したままの被覆膜とは言えず、欠落部を有するパターン化された膜である。特に前記切断分離線のパターンは半導体基板の端から端まで格子状に形成されている。この状態でたとえば、補強板としてガラス板を粘着シートを介してパッシベーション膜3の最表面に貼り付けると図4(図4では図3の半導体基板1が180度反転されている)に示すように、貼り付け界面に隙間6などが必ずできる。この隙間6が前述の切断分離線に相当する部分の隙間である場合、前述のように、染み込んだガスや薬液により粘着シートの粘着力が劣化し前記粘着シートが剥がれ易くなるのである。
A semiconductor substrate configured as a semiconductor device requires a required high resistance layer width that increases in proportion to the magnitude of the blocking voltage in order to ensure the blocking voltage (breakdown voltage). If the width of the high resistance layer is increased, the semiconductor substrate is correspondingly thickened. In the case of semiconductor silicon, the width of the high resistance layer necessary for the breakdown voltage is, for example, about 70 μm at 600 V and about 120 μm at 1200 V. On the other hand, in the semiconductor wafer process, if the thickness of the semiconductor wafer (semiconductor substrate) is thin, the number of wafer cracks in the process increases. However, if the thickness is 500 μm or more, crack defects in the wafer process are almost a problem. It is suppressed to the extent that it does not become. If the number of wafer cracks is large, not only does the defect rate increase and work efficiency deteriorates, but it is also not preferable from the viewpoint of cost. Therefore, it is preferable that the semiconductor wafer in the process is as thick as possible. Therefore, a thick wafer having a thickness of 500 μm or more is used at the time of introduction into the semiconductor wafer process regardless of the withstand voltage. However, if the wafer is thicker than the thickness required for withstand voltage (particularly in the high resistance layer), the voltage drop when an on-current is passed, that is, the on-resistance increases, In the wafer process, the process is performed on a thick wafer until the process on the front side of the semiconductor substrate is completed, and before the process on the back side of the semiconductor wafer is started, the back side of the semiconductor wafer is made to withstand pressure to reduce the on-resistance. There is a case where a manufacturing method of grinding to near a necessary thickness is employed. In such a manufacturing method, various semiconductor patterns and electrode films formed on the surface of the semiconductor wafer are protected and the reinforcing plate or film for the purpose of mechanically reinforcing the semiconductor wafer is bonded to each other after the back grinding step. The process is progressing. Bonding of the semiconductor wafer and the reinforcing plate or the reinforcing film at this time is generally performed via an adhesive or the like.
A conventional semiconductor device will be described. As shown in FIG. 3, the semiconductor silicon substrate 1 is finally subjected to processing steps (not shown) necessary for a semiconductor element function formed in the substrate 1, and finally. Semiconductor functional elements formed inside the semiconductor substrate 1 are connected and wired to metal electrodes and wiring metal 2 disposed on the surface. Further, a passivation film 3 such as a polyimide resin film is formed on the outermost surface as a protective film. However, the passivation film 3 is not formed so thick as to absorb all the steps (unevenness) resulting from the oxide film, the wiring metal 2 and the like being placed on the surface of the semiconductor substrate. Unevenness remains on the surface. The passivation film 3 is applied to the outermost surface of the semiconductor substrate, and then corresponds to a metal electrode portion for fixing an external connection lead wire such as an aluminum wire by bonding or a cutting separation line for dicing the semiconductor substrate into chips. Photolithography (photoetching) is performed to open a portion to be formed. As a result, the passivation film 3 is not a coating film as it is applied to the entire surface, but is a patterned film having a missing portion. In particular, the pattern of the cutting separation lines is formed in a lattice shape from end to end of the semiconductor substrate. In this state, for example, when a glass plate is attached as a reinforcing plate to the outermost surface of the passivation film 3 through an adhesive sheet, as shown in FIG. 4 (in FIG. 4, the semiconductor substrate 1 of FIG. 3 is inverted 180 degrees). A gap 6 or the like is always formed at the pasting interface. When the gap 6 is a gap corresponding to the above-described cutting separation line, as described above, the adhesive force of the pressure-sensitive adhesive sheet is deteriorated by the soaked gas or chemical solution, and the pressure-sensitive adhesive sheet is easily peeled off.

従来技術としては、凹凸を有する半導体ウエハ表面に、基材フィルムの片面に粘着材層を有する粘着シ−トを貼り合わせる工程、貼り合わせた基材フィルムの表面を研磨する工程、その状態で、半導体ウエハ裏面を研削する工程を有する半導体ウエハの研削方法にかかる発明が知られている(特許文献1)。
さらに、ウエハ表面でパターン形成に用いたフォトレジスト材をそのまま残して、その上に表面保護用粘着シートを貼り付けた状態でウエハの裏面を研削し、ついで上記粘着シート類を剥離して、上記レジスト材を上記粘着シート類に転着させて上記ウエハから除去する半導体装置の製造法の発明が知られている(特許文献2)。
特開2005−19666号公報(要約) 特開平11−288907号公報(要約)
As a prior art, a process of bonding an adhesive sheet having an adhesive layer on one side of a base film to a semiconductor wafer surface having irregularities, a process of polishing the surface of the bonded base film, in that state, An invention relating to a semiconductor wafer grinding method including a step of grinding a semiconductor wafer back surface is known (Patent Document 1).
Furthermore, leaving the photoresist material used for pattern formation on the wafer surface as it is, grinding the back surface of the wafer with the surface protective adhesive sheet affixed thereon, then peeling the adhesive sheets, An invention of a manufacturing method of a semiconductor device in which a resist material is transferred to the pressure-sensitive adhesive sheets and removed from the wafer is known (Patent Document 2).
Japanese Patent Laying-Open No. 2005-19666 (Summary) JP 11-288907 A (summary)

しかしながら、前述のような半導体基板の表面側へ粘着シートなどを貼り合わせた状態で行われる裏面側の研削を含む様々な工程では、前記基板と粘着シートの貼り合わせの際に、半導体ウエハ表面側に形成されている凹凸やパターン化されたレジストと、貼り合わせる粘着シートの間に必然的に生じる隙間に、裏面側の様々な加工プロセスで使用されるガスや薬液の染み込みが避けられない。その結果、染み込んだガスや薬液により粘着シートの粘着力が劣化し前記粘着シートが剥がれることがあってプロセスの安定性が悪いという問題がある。   However, in various processes including grinding of the back surface side performed in a state where the adhesive sheet or the like is bonded to the front surface side of the semiconductor substrate as described above, when the substrate and the adhesive sheet are bonded, the semiconductor wafer surface side Gases and chemicals used in various processing processes on the back side are unavoidable in the gaps inevitably generated between the unevenness and patterned resist formed on the substrate and the adhesive sheet to be bonded. As a result, there is a problem that the adhesive strength of the pressure-sensitive adhesive sheet is deteriorated by the gas or chemical solution soaked and the pressure-sensitive adhesive sheet is peeled off, and the process stability is poor.

また、前述の特許文献1の記載では、半導体ウエハ表面と基材フィルムとを粘着材を介して貼り合わせた場合、基材フィルムの表面が半導体表面の凹凸の影響を受けて不規則な凹凸面になってウエハ裏面研削精度に悪影響を及ぼすのを防ぐことを目的とするものであり、基材フィルムおよび粘着剤と、半導体ウエハ表面との間の隙間に起因する剥がれの問題には示唆すらされておらず、当然ながら対策もされず、全く解消されないのである。   Moreover, in the description of the above-mentioned patent document 1, when the surface of a semiconductor wafer and a base film are bonded together via an adhesive material, the surface of the base film is affected by irregularities on the semiconductor surface and has irregular irregular surfaces. It is intended to prevent adverse effects on wafer backside grinding accuracy, and is even suggested for the problem of peeling due to the gap between the base film and adhesive and the semiconductor wafer surface. It is not, and of course, no measures are taken and it is not solved at all.

さらに、前述の特許文献2の記載では、さらにウエハ表面にフォトレジストを挟み、さらに粘着剤を介して基材フィルムが貼り合わせられ、ウエハ裏面の研削が行われる。しかし、このフォトレジストは前工程でフォトエッチングに用いられたパターン化されたフォトレジストであり、当然ながら部分的にフォトレジスト膜の欠けたところがあるので、半導体ウエハ表面との間の隙間を充分に防ぐことはできない。従って、前述した基材フィルムの剥がれ問題を充分に解消することはできない。   Furthermore, in the description of Patent Document 2 described above, a photoresist is further sandwiched between the wafer surfaces, a base film is further bonded through an adhesive, and the wafer back surface is ground. However, this photoresist is a patterned photoresist used for photoetching in the previous process, and naturally there is a part where the photoresist film is partially missing, so that there is sufficient clearance between the surface of the semiconductor wafer. It cannot be prevented. Therefore, the above-mentioned peeling problem of the base film cannot be sufficiently solved.

本発明は、以上述べた点に鑑みてなされたものであり、半導体ウエハ表面と補強板との貼り合わせ後の半導体プロセスにおいて、貼り合わせ面からの剥離を防止することのでき、さらに、裏面研削精度を悪くしない半導体装置の製造方法を提供することである。   The present invention has been made in view of the above points, and can prevent peeling from a bonding surface in a semiconductor process after bonding a semiconductor wafer surface and a reinforcing plate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not deteriorate accuracy.

特許請求の範囲の請求項1記載の発明によれば、半導体基板の表面側に半導体素子機能に必要な加工を施した後、この加工により半導体基板表面に形成された凹凸を平坦化するためにフォトレジストを塗布し、このフォトレジスト乾燥膜の平坦な表面に、該表面に貼られる粘着シートを介して補強板を貼り合わせた状態で、前記半導体基板の裏面研削を行い、前記半導体基板の裏面研削の終了後、フォトレジスト剥離液を用いて前記フォトレジスト乾燥膜を剥離することにより前記補強板を除去することにより、前記本発明の目的は達成される。 According to the invention described in claim 1, in order to flatten the unevenness formed on the surface of the semiconductor substrate by performing processing necessary for the function of the semiconductor element on the surface side of the semiconductor substrate. The back surface of the semiconductor substrate is ground by applying a photoresist and grinding the back surface of the semiconductor substrate in a state where a reinforcing plate is bonded to the flat surface of the dry photoresist film via an adhesive sheet attached to the surface. After the grinding is completed, the object of the present invention is achieved by removing the reinforcing plate by peeling the photoresist dry film using a photoresist stripping solution.

特許請求の範囲の請求項2記載の発明によれば、半導体基板の表面側に半導体素子機能に必要な加工を施した後、この加工により半導体基板表面に形成された凹凸が埋まる膜厚でプラズマCVD酸化膜を堆積し、この酸化膜をCMPにより平坦化し、この酸化膜の表面に、該表面に貼られる粘着シートを介して補強板を貼り合わせた状態で、前記半導体基板の裏面研削を行うことを特徴とする半導体装置の製造方法とすることが好ましい。
特許請求の範囲の請求項3記載の発明によれば、前記粘着シートが紫外線硬化型粘着シートであり、前記半導体基板の裏面研削の終了後、前記紫外線硬化型粘着シートに紫外線を照射し、前記紫外線硬化型粘着シートとともに前記補強板を除去する請求項2に記載の半導体装置の製造方法とすることが好ましい。
According to the second aspect of the present invention, after the processing necessary for the function of the semiconductor element is performed on the surface side of the semiconductor substrate, the plasma is formed in such a thickness that the unevenness formed on the surface of the semiconductor substrate is buried by this processing. A CVD oxide film is deposited, the oxide film is flattened by CMP, and the back surface of the semiconductor substrate is ground with a reinforcing plate attached to the surface of the oxide film via an adhesive sheet attached to the surface. It is preferable to provide a method for manufacturing a semiconductor device.
According to the invention of claim 3, the pressure-sensitive adhesive sheet is an ultraviolet curable pressure-sensitive adhesive sheet, and after the back surface grinding of the semiconductor substrate, the ultraviolet-curable pressure-sensitive adhesive sheet is irradiated with ultraviolet rays, The semiconductor device manufacturing method according to claim 2, wherein the reinforcing plate is removed together with the ultraviolet curable adhesive sheet.

特許請求の範囲の請求項4記載の発明によれば、前記CMPにより平坦化された酸化膜表面の段差の最大深さが0.1μm以下であることを特徴とする請求項2または3に記載の半導体装置の製造方法とすることが好ましい。
特許請求の範囲の請求項5記載の発明によれば、半導体基板が半導体シリコンであり、硬質補強板が石英板、無機ガラス板、有機ガラス板のいずれかである特許請求の範囲の請求項1ないし4のいずれか一項記載の半導体装置の製造方法とすることが望ましい。
According to the fourth aspect of the present invention in the claims, claim 2 or 3 maximum depth of the step of the flattened oxide film surface by the CMP is equal to or is 0.1μm or less It is preferable to use the method for manufacturing the semiconductor device.
According to the invention described in claim 5, the semiconductor substrate is semiconductor silicon, and the hard reinforcing plate is any one of a quartz plate, an inorganic glass plate, and an organic glass plate. Preferably, the method for manufacturing a semiconductor device according to any one of claims 1 to 4 is used.

本発明によれば、平坦化表面同士を貼り合わせた界面には、実質的に隙間が発生しないため、その後の様々な加工処理に用いられるガスや薬液に、貼り合わせ界面が晒されることがほとんどない。そのため貼り合わせた時のままの粘着力が維持され、意図的に貼り合わせたものを剥がすまで、剥がれることがなく安定したウエハプロセスを行うことができる。さらに、補強板に石英版やガラス板などの硬質補強板を用いると、応力の影響により補強板表面に歪み生じ、裏面研削精度を悪くすることも無くなる。   According to the present invention, since there is substantially no gap at the interface where the planarized surfaces are bonded together, the bonded interface is almost exposed to gases and chemicals used in various subsequent processing. Absent. Therefore, the adhesive force as it was when it was bonded is maintained, and a stable wafer process can be performed without being peeled until the intentionally bonded one is peeled off. Further, when a hard reinforcing plate such as a quartz plate or a glass plate is used for the reinforcing plate, the surface of the reinforcing plate is distorted due to the influence of stress, and the back surface grinding accuracy is not deteriorated.

以下、本発明の半導体装置の製造方法にかかる実施例を図1〜図4を参照して説明する。本発明は、以下説明する実施例の記載のみに限定されるものではない。   Embodiments according to a method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. The present invention is not limited to the description of the examples described below.

本発明にかかる実施例では、図1に示すように、半導体基板1の内部に所要の半導体機能に必要な処理工程を加えた後、基板1の表面側に所定の半導体デバイス機能を奏するために必要なプロセスを施すと、半導体基板1表面は、パターン化された酸化膜による段差(図示せず)、金属電極、配線などによる段差2、トレンチ(図示せず)、さらにはパッシベーション膜3などにより凹凸が数多く形成される。このような凹凸のある半導体基板1表面であっても、フォトレジスト感光液を塗布すれば、凹部がフォトレジスト液で埋められ、そのレジスト膜7表面を平坦にすることができる。たとえば、使用するフォトレジストは120cp(センチポイズ)のネガレジストを用い、2500rpmの回転数でスピンナ塗布する。半導体基板1表面の凹部にフォトレジストを埋め、90℃で90秒程度の乾燥を行ってから、表面の平坦部の厚さが2μm(乾燥時)で、最表面が全面で平坦な膜を形成する。図2に示すように、(図2では図1の半導体基板1の表裏が180度反転されている)後工程である半導体基板1の研削工程における半導体基板1の表面保護や機械的補強のために、粘着剤(粘着シート)5を用いて約500μm厚の無機ガラス板4を貼り合わせた。このように凹部のない平坦なフォトレジスト膜7の表面上への無機ガラス板4の貼り合わせによれば、半導体基板1の最表面と無機ガラス板4の界面に、もはや隙間が発生しない貼り合わせとすることができるため、その後の種々の加工で使用されるガスや薬液が前記界面に染み込むことがなく、貼り合わせ面からの剥離を防止するこが可能になるのである。   In the embodiment according to the present invention, as shown in FIG. 1, in order to perform a predetermined semiconductor device function on the surface side of the substrate 1 after adding processing steps necessary for a required semiconductor function to the inside of the semiconductor substrate 1. When a necessary process is performed, the surface of the semiconductor substrate 1 is formed by a step (not shown) due to a patterned oxide film, a step 2 due to a metal electrode, wiring, etc., a trench (not shown), and further a passivation film 3 or the like. Many irregularities are formed. Even on the surface of the semiconductor substrate 1 having such irregularities, if a photoresist photosensitive solution is applied, the recesses are filled with the photoresist solution, and the surface of the resist film 7 can be flattened. For example, a 120 cp (centipoise) negative resist is used as a photoresist to be used, and a spinner is applied at a rotational speed of 2500 rpm. A photoresist is buried in the concave portion of the surface of the semiconductor substrate 1 and dried at 90 ° C. for about 90 seconds. Then, a flat film with a thickness of 2 μm (at the time of drying) and a flat surface on the entire surface is formed. To do. As shown in FIG. 2, for surface protection and mechanical reinforcement of the semiconductor substrate 1 in the grinding process of the semiconductor substrate 1, which is a subsequent process (in FIG. 2, the front and back of the semiconductor substrate 1 of FIG. 1 are inverted 180 degrees). Then, an inorganic glass plate 4 having a thickness of about 500 μm was bonded using an adhesive (adhesive sheet) 5. In this way, according to the bonding of the inorganic glass plate 4 onto the surface of the flat photoresist film 7 having no recesses, the bonding is such that no gap is generated at the interface between the outermost surface of the semiconductor substrate 1 and the inorganic glass plate 4. Therefore, gas and chemicals used in various subsequent processes do not permeate the interface, and peeling from the bonded surface can be prevented.

その後、CMP(化学機械研磨装置)により、半導体基板の裏面を所定の厚さになるように研削、研磨する。裏面研削工程が終了した後、無機ガラス板を除去するために、フォトレジスト剥離液に浸漬させる。フォトレジストが剥離すると、その上に貼付されている無機ガラス板も同時に剥離される。その後、半導体基板の裏面側に必要な半導体処理工程を経て裏面上に金属電極膜を被着すれば、目的の半導体装置の機能を有する半導体基板が完成する。   Thereafter, the rear surface of the semiconductor substrate is ground and polished to a predetermined thickness by CMP (chemical mechanical polishing apparatus). After the back grinding step is completed, the substrate is immersed in a photoresist stripping solution in order to remove the inorganic glass plate. When the photoresist is peeled off, the inorganic glass plate adhered thereon is also peeled off at the same time. After that, if a metal electrode film is deposited on the back surface through a necessary semiconductor processing step on the back surface side of the semiconductor substrate, a semiconductor substrate having the function of the target semiconductor device is completed.

この実施例では、レジストを使用することにより、耐アルカリ、耐酸の機能を持たすことが可能になり、加工時に使用されるガスや薬品が染み込み、粘着剤5の粘着力が低下することを防止できる。   In this embodiment, by using a resist, it becomes possible to have functions of alkali resistance and acid resistance, and it is possible to prevent the gas and chemicals used at the time of processing from permeating and reducing the adhesive strength of the adhesive 5. .

本実施例が実施例1と異なる点は、実施例1では、フォトレジスト膜7を形成したところを本実施例では、TEOS酸化膜7を形成した点である。フォトレジスト膜は耐熱性に問題があり、半導体基板1の裏面工程に電極アニール(400℃程度)などの熱処理工程があると使用することができない。そこで、半導体基板1の裏面工程に熱処理工程がある場合にプラズマCVD酸化膜を用いたものである。   This embodiment differs from the first embodiment in that the photoresist film 7 is formed in the first embodiment but the TEOS oxide film 7 is formed in the present embodiment. The photoresist film has a problem in heat resistance, and cannot be used if there is a heat treatment process such as electrode annealing (about 400 ° C.) in the back surface process of the semiconductor substrate 1. Therefore, the plasma CVD oxide film is used when the back surface process of the semiconductor substrate 1 includes a heat treatment process.

図1に記載のように、凹凸のある半導体基板1表面プラズマCVDによりTEOS酸化膜7を凹凸が埋まる膜厚で堆積させ、CMPによりTEOS酸化膜7を研削し平坦化を行う。この実施例では、TEOS酸化膜を形成したが、プラズマCVDにより形成される酸化膜であればTEOS酸化膜以外の酸化膜であってもよい。プラズマCVD酸化膜は、低温(300℃以下の温度)で形成できるため、半導体基板1の表面側に形成された半導体機能に影響を及ぼすことなく形成できる。   As shown in FIG. 1, a TEOS oxide film 7 is deposited with a film thickness that fills the unevenness by surface plasma CVD of an uneven semiconductor substrate 1, and the TEOS oxide film 7 is ground and planarized by CMP. In this embodiment, the TEOS oxide film is formed. However, an oxide film other than the TEOS oxide film may be used as long as it is an oxide film formed by plasma CVD. Since the plasma CVD oxide film can be formed at a low temperature (300 ° C. or less), it can be formed without affecting the semiconductor function formed on the surface side of the semiconductor substrate 1.

次に、図2に示すように、(図2では図1の半導体基板1の表裏が180度反転されている)後工程である半導体基板1の研削工程における半導体基板1の表面保護や機械的補強のために、粘着剤(粘着シート)5を用いて約500μm厚の無機ガラス板4を貼り合わせた。粘着剤5としては、耐熱性の材料からなるものであればよい。本実施例では、紫外線照射により粘度が弱まる紫外線硬化型粘着テープを使用した。   Next, as shown in FIG. 2, the surface protection and mechanical properties of the semiconductor substrate 1 in the grinding process of the semiconductor substrate 1, which is a subsequent process (in FIG. 2, the front and back of the semiconductor substrate 1 of FIG. 1 are inverted 180 degrees). For reinforcement, an inorganic glass plate 4 having a thickness of about 500 μm was bonded using an adhesive (adhesive sheet) 5. The pressure-sensitive adhesive 5 may be made of a heat resistant material. In this example, an ultraviolet curable adhesive tape whose viscosity is weakened by ultraviolet irradiation was used.

平坦なTEOS酸化膜7の表面上への無機ガラス板4の貼り合わせによれば、半導体基板1の最表面と無機ガラス板4の界面に、もはや隙間が発生しない貼り合わせとすることができるため、その後の種々の加工で使用されるガスや薬液が前記界面に染み込むことがなく、貼り合わせ面からの剥離を防止するこが可能になるのである。ここで、TEOS酸化膜7は耐薬品性、耐ガス性と共に耐熱性を有していることにより裏面工程で400℃程度の熱処理工程があっても十分に機能を維持することが可能になる。   According to the bonding of the inorganic glass plate 4 on the surface of the flat TEOS oxide film 7, the bonding can be performed so that no gap is generated at the interface between the outermost surface of the semiconductor substrate 1 and the inorganic glass plate 4. Gases and chemicals used in various subsequent processes do not soak into the interface, and it is possible to prevent peeling from the bonded surface. Here, since the TEOS oxide film 7 has heat resistance as well as chemical resistance and gas resistance, the TEOS oxide film 7 can sufficiently maintain its function even if there is a heat treatment process at about 400 ° C. in the back surface process.

その後、CMPにより、半導体基板1の裏面を所定の厚さになるように研削、研磨する。裏面研削工程が終了した後、無機ガラス板4を除去するために、粘着剤5に紫外線を照射し、粘着剤5とともに無機ガラス板4を除去した。なお、TEOS酸化膜7は半導体基板1に形成されたままでもパッシベーション膜として用いることが可能である。また、TEOS酸化膜7が不要な場合はフッ酸を用いることにより簡単に除去することができる。   Thereafter, the back surface of the semiconductor substrate 1 is ground and polished to a predetermined thickness by CMP. After the back grinding process was completed, in order to remove the inorganic glass plate 4, the adhesive 5 was irradiated with ultraviolet rays, and the inorganic glass plate 4 was removed together with the adhesive 5. The TEOS oxide film 7 can be used as a passivation film even if it is formed on the semiconductor substrate 1. Further, when the TEOS oxide film 7 is unnecessary, it can be easily removed by using hydrofluoric acid.

その後、半導体基板1の裏面側に必要な半導体処理工程を経て裏面上に金属電極膜(図示せず)を被着すれば、目的の半導体装置の機能を有する半導体基板が完成する。
次に、無機ガラス板4を張り合わせる前のTEOS酸化膜7表面の凹凸がどのように影響するか実験を行った。
CMP法を用いてTEOS酸化膜7を段差の最大の深さが0.01μmとなるまで研削を行った後に、TEOS酸化膜7にドライエッチングにより幅0.5μmで深さを0.05μm、0.1μm、0.15μmと変えた段差を形成した複数の半導体基板1を形成した。前記の0.01μmに研削したものも含めて、それぞれ、粘着剤5を介して無機ガラス板4を貼り合わせた。その後、バッファードフッ酸に10分間浸しTEOS酸化膜7がどの程度エッチングされるか確認を行った。通常TEOS酸化膜7をエッチングする場合、400nm/分のエッチング速度であり、ベタ膜では4μm程度エッチングされる。
Thereafter, if a metal electrode film (not shown) is deposited on the back surface through a necessary semiconductor processing step on the back surface side of the semiconductor substrate 1, a semiconductor substrate having the function of the target semiconductor device is completed.
Next, an experiment was conducted on how the unevenness on the surface of the TEOS oxide film 7 before the inorganic glass plate 4 was bonded was affected.
After grinding the TEOS oxide film 7 using the CMP method until the maximum depth of the step becomes 0.01 μm, the TEOS oxide film 7 is dry etched to a width of 0.5 μm and a depth of 0.05 μm. A plurality of semiconductor substrates 1 formed with steps different from 0.1 μm and 0.15 μm were formed. Inorganic glass plates 4 were bonded to each other through adhesive 5 including those ground to 0.01 μm. Thereafter, it was immersed in buffered hydrofluoric acid for 10 minutes to check how much the TEOS oxide film 7 was etched. When the TEOS oxide film 7 is normally etched, the etching rate is 400 nm / min, and the solid film is etched by about 4 μm.

図5は、TEOS酸化膜表面の段差の影響を示す図である。
形成された段差の幅が初期値0.5μmからどのように増えるかについて測定した結果を示している。この結果、段差の深さが0.1μmまではほとんど上昇せず、段差の深さが0.15μm以上となると幅が広くなることが判明した。これは、毛細管現象でバッファードフッ酸が段差内に流入するが、その深さが0.1μm以下であるとほとんど流入しないために得られた結果であると考えられる。
FIG. 5 is a diagram showing the influence of the step on the TEOS oxide film surface.
The result of measuring how the width of the formed step increases from the initial value of 0.5 μm is shown. As a result, it was found that the depth of the step hardly increased to 0.1 μm, and the width became wider when the depth of the step was 0.15 μm or more. This is considered to be a result obtained because buffered hydrofluoric acid flows into the step due to capillary action, but hardly flows when the depth is 0.1 μm or less.

よって、CMPによる研削を、TEOS酸化膜7表面の段差の最大深さが0.1μm以下となるまで行えばよいことが分かった。段差の最大深さが0.1μmとなるように研削する場合は、段差の最大深さが0.01μmとなるように研削する場合に比べて研削時間を短くすることができる。
以上の説明では、半導体基板1の機械的補強板として、無機ガラス板を用いたが、その他に石英ガラス板や有機ガラス板を用いることもできる。
Accordingly, it has been found that grinding by CMP may be performed until the maximum depth of the step on the surface of the TEOS oxide film 7 is 0.1 μm or less. When grinding so that the maximum depth of the step becomes 0.1 μm, the grinding time can be shortened compared to when grinding so that the maximum depth of the step becomes 0.01 μm.
In the above description, an inorganic glass plate is used as the mechanical reinforcing plate of the semiconductor substrate 1, but a quartz glass plate or an organic glass plate can also be used.

本発明の半導体装置の製造方法にかかる実施例を示す半導体基板の模式的断面図である。It is typical sectional drawing of the semiconductor substrate which shows the Example concerning the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法にかかる実施例を示す補強板を張り合わせた半導体基板の模式的断面図である。It is typical sectional drawing of the semiconductor substrate which bonded together the reinforcement board which shows the Example concerning the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の製造方法にかかる半導体基板の模式的断面図である。It is typical sectional drawing of the semiconductor substrate concerning the manufacturing method of the conventional semiconductor device. 従来の半導体装置製造方法にかかる補強板を貼り合わせた半導体基板の模式的断面図である。It is typical sectional drawing of the semiconductor substrate which bonded the reinforcement board concerning the conventional semiconductor device manufacturing method. TEOS酸化膜表面の段差の影響を示す図である。It is a figure which shows the influence of the level | step difference of a TEOS oxide film surface.

符号の説明Explanation of symbols

1 半導体基板
2 金属電極、配線金属部
3 パッシベーション膜
4 無機ガラス板
5 粘着剤(粘着シート)
6 隙間
7 フォトレジスト膜、TEOS酸化膜。
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Metal electrode, wiring metal part 3 Passivation film 4 Inorganic glass plate 5 Adhesive (adhesive sheet)
6 Gap 7 Photoresist film, TEOS oxide film.

Claims (5)

半導体基板の表面側に半導体素子機能に必要な加工を施した後、この加工により半導体基板表面に形成された凹凸を平坦化するためにフォトレジストを塗布し、このフォトレジスト乾燥膜の平坦な表面に、該表面に貼られる粘着シートを介して補強板を貼り合わせた状態で、前記半導体基板の裏面研削を行い、前記半導体基板の裏面研削の終了後、フォトレジスト剥離液を用いて前記フォトレジスト乾燥膜を剥離することにより前記補強板を除去することを特徴とする半導体装置の製造方法。 After processing necessary for the function of the semiconductor element on the surface side of the semiconductor substrate, a photoresist is applied to flatten the unevenness formed on the surface of the semiconductor substrate by this processing, and the flat surface of this photoresist dry film In addition, the back surface of the semiconductor substrate is ground in a state in which a reinforcing plate is bonded to the surface through an adhesive sheet that is pasted on the surface. After the back surface grinding of the semiconductor substrate is finished, the photoresist is removed using a photoresist stripping solution. A method of manufacturing a semiconductor device, wherein the reinforcing plate is removed by peeling a dry film. 半導体基板の表面側に半導体素子機能に必要な加工を施した後、この加工により半導体基板表面に形成された凹凸が埋まる膜厚でプラズマCVD酸化膜を堆積し、この酸化膜をCMPにより平坦化し、この酸化膜の表面に、該表面に貼られる粘着シートを介して補強板を貼り合わせた状態で、前記半導体基板の裏面研削を行うことを特徴とする半導体装置の製造方法。After processing necessary for the function of the semiconductor element on the surface side of the semiconductor substrate, a plasma CVD oxide film is deposited with a thickness that fills the irregularities formed on the surface of the semiconductor substrate by this processing, and this oxide film is planarized by CMP. A method for manufacturing a semiconductor device, comprising: grinding a back surface of the semiconductor substrate on a surface of the oxide film with a reinforcing plate bonded to the surface of the oxide film via an adhesive sheet attached to the surface. 前記粘着シートが紫外線硬化型粘着シートであり、The pressure-sensitive adhesive sheet is an ultraviolet curable pressure-sensitive adhesive sheet,
前記半導体基板の裏面研削の終了後、前記紫外線硬化型粘着シートに紫外線を照射し、前記紫外線硬化型粘着シートとともに前記補強板を除去することを特徴とする請求項2記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein after the back surface grinding of the semiconductor substrate is finished, the ultraviolet curable adhesive sheet is irradiated with ultraviolet rays, and the reinforcing plate is removed together with the ultraviolet curable adhesive sheet. .
前記CMPにより平坦化された酸化膜表面の段差の最大深さが0.1μm以下であることを特徴とする請求項2または3に記載の半導体装置の製造方法。 4. The method for manufacturing a semiconductor device according to claim 2 , wherein the maximum depth of the step on the surface of the oxide film flattened by the CMP is 0.1 [mu] m or less. 前記半導体基板が半導体シリコンであり、前記補強板が石英板、無機ガラス板、有機ガラス板のいずれかであることを特徴とする請求項1ないし4のいずれか一つに記載の半導体装置の製造方法。   5. The semiconductor device manufacture according to claim 1, wherein the semiconductor substrate is semiconductor silicon, and the reinforcing plate is any one of a quartz plate, an inorganic glass plate, and an organic glass plate. Method.
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