JP5322176B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a driver for driving a power semiconductor element at low cost, and to provide an electronic apparatus with the same. <P>SOLUTION: The semiconductor device 101 includes a first switching function unit for receiving a drive signal from a high side drive unit 62, and a second switching function unit having a control electrode for receiving a drive signal from a low side drive unit 64, the high side drive unit 62 includes a normally-on type field effect transistor, and outputs a drive signal obtained by shifting reference voltage of a switching control signal to a potential of an output node, the first switching function unit includes a first normally-on type field effect transistor Tr1, the second switching function unit includes a second normally-on type field effect transistor Tr2, and the high side drive unit 62 and the first field effect transistor Tr1 are included in a first semiconductor chip 71. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

The present invention relates to semiconductor equipment, in particular, relates to a semiconductor equipment comprising a normally-on type or normally-off type field effect transistor.

  Group III nitride semiconductors typified by gallium nitride (GaN), AlGaN, and InGaN have high voltage resistance, high speed operation, high heat resistance, and low on-state when used in power devices due to their material superiority. Good device characteristics such as resistance can be expected. For this reason, development of a power device using a group III nitride semiconductor is being promoted in place of the conventional Si material whose performance limit as a power device is approaching.

  In particular, for a field effect transistor (FET), for example, a transistor having high electron mobility is realized by forming a high-concentration two-dimensional electron gas (2DEG) in the vicinity of the heterojunction interface between AlGaN and GaN. That is, the on-resistance of the FET can be further reduced. Various device structures using such heterojunction interfaces have been proposed.

  Such a GaN field effect transistor usually has a negative voltage threshold, is on when the gate voltage is 0 V, and is normally on, in which a drain current flows.

  On the other hand, for example, an insulated gate field effect transistor and an insulated gate bipolar transistor are normally normally-off type. That is, it has a positive voltage threshold and is off when the gate voltage is 0 V, and no drain current flows.

  Normally-on GaN field effect transistors have good characteristics such as high breakdown voltage, high speed operation, high heat resistance, and low on-resistance, while it is necessary to supply a negative voltage to the gate. Further, in order to make the GaN field effect transistor normally-off type, it is necessary to take measures such as adding a gate material to the tip of the gate electrode.

  A driver IC (Integrated Circuit) for driving such a power semiconductor element has been developed. For example, Japanese Patent Laid-Open No. 8-65143 (Patent Document 1) discloses a driver having a level shift circuit as described below. Is disclosed. That is, a reset priority level shift circuit for converting a logic voltage state from one voltage level to a different voltage level, the level shift circuit for turning on a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) A set level circuit for generating an output signal; a reset level circuit for turning off the power MOSFET; and the set level circuit coupled to the reset level circuit and responsive to a reset signal and an input signal to the pulse generator. A pulse generator for generating a combined set level signal; and connected to the level shift circuit to operate the reset level circuit with an input signal lower than a value required to operate the set level shift circuit; Reset priority to turn off MOSFET Circuit means.

JP-A-8-65143

  However, in order to manufacture the driver IC described in Patent Document 1, in addition to a general CMOS (Complementary Metal Oxide Semiconductor) process, a process for forming a high voltage MOSFET constituting a level shifter is required. Cost increases.

The present invention has been made to solve the problems described above, and its object is to provide a semiconductor equipment capable of providing a driver for driving the power semiconductor device at low cost.

In order to solve the above problems, a semiconductor device according to an aspect of the present invention includes an input signal processing unit for outputting a switching control signal based on an input signal, and the switching control signal received from the input signal processing unit. A high-side drive unit for outputting a drive signal based on the input signal, a low-side drive unit for outputting a drive signal based on the switching control signal received from the input signal processing unit, and a first power supply voltage are supplied A first switching function unit having a first conduction electrode to be performed, a second conduction electrode coupled to an output node, a control electrode that receives the drive signal from the high-side drive unit, and an output node A coupled first conductive electrode, a second conductive electrode to be supplied with a second power supply voltage lower than the first power supply voltage, and the low side driver And a second switching function unit having a control electrode for receiving the driving signal, wherein the high-side driving unit includes a normally-on field effect transistor, and a reference voltage of the switching control signal is supplied to the output node. The first switching function unit includes a normally-on type first field effect transistor, and the second switching function unit includes a normally-on type second electric field. The high-side driver and the first field effect transistor are included in a first semiconductor chip.
The high side driving unit includes a first diode having an anode for receiving a first switching control signal from the input signal processing unit, a cathode, and a first end coupled to the cathode of the first diode; , A first resistor having a second end, a drain coupled to the second end of the first resistor, a source coupled to a node to which a predetermined voltage is supplied, and from the input signal processing unit A normally-on fourth field effect transistor having a gate for receiving a second switching control signal; a second end having a first end coupled to the cathode of the first diode; and a second end. A resistor, a drain coupled to the second end of the second resistor, a source coupled to a node to which a predetermined voltage is supplied, and a gate for receiving a third switching control signal from the input signal processor. A normally-on fifth field effect transistor having a gate, a drain coupled to the cathode of the first diode, a source coupled to the gate of the first field effect transistor, and the second A normally-on sixth field effect transistor having a second end of a first resistor and a gate coupled to the drain of the fifth field effect transistor, and a first coupled to the cathode of the first diode. A capacitor having an end and a second end coupled to the output node.

  Preferably, the first field effect transistor includes a first conduction electrode to which the first power supply voltage is to be supplied, a second conduction electrode coupled to the output node, and the high-side driving unit. A normally-on field effect transistor having a control electrode for receiving a drive signal.

  Preferably, the second switching function unit includes a first conduction electrode coupled to the output node, a second conduction electrode, and a normally on having a control electrode to which the second power supply voltage is to be supplied. Type second field effect transistor, a first conduction electrode coupled to a second conduction electrode of the second field effect transistor, a second conduction electrode to which the second power supply voltage is to be supplied, and A normally-off third field effect transistor having a control electrode for receiving the drive signal from the low-side drive unit.

  More preferably, the high side driving unit further includes a drain coupled to the gate of the first field effect transistor, a source coupled to a node to which a predetermined voltage is supplied, and the input signal processing unit. A normally-on seventh field effect transistor having a gate for receiving a fourth switching control signal.

A semiconductor device according to another aspect of the present invention includes an input signal processing unit for outputting a switching control signal based on an input signal, and a drive signal based on the switching control signal received from the input signal processing unit. A high-side driving unit for outputting, a low-side driving unit for outputting a driving signal based on the switching control signal received from the input signal processing unit, and a first continuity to be supplied with a first power supply voltage A normally-off first field-effect transistor having an electrode, a second conduction electrode coupled to the output node, and a control electrode for receiving the drive signal from the high-side driver, and coupled to the output node From the first conductive electrode, the second conductive electrode to be supplied with a second power supply voltage lower than the first power supply voltage, and the low-side drive unit. A normally-off type second field effect transistor having a control electrode for receiving the drive signal, wherein the high-side drive unit includes a normally-off type field effect transistor, and a reference voltage of the switching control signal Is output to the potential of the output node, and the high-side driver and the first field effect transistor are included in the first semiconductor chip.
The high side driving unit includes a first diode having an anode for receiving a first switching control signal from the input signal processing unit, a cathode, and a first end coupled to the cathode of the first diode; , A first resistor having a second end, a drain coupled to the second end of the first resistor, a source coupled to a node to which a fixed voltage is supplied, and from the input signal processing unit A normally-off third field effect transistor having a gate for receiving a second switching control signal; a drain coupled to the cathode of the first diode; and a gate coupled to the gate of the first field effect transistor. A normally-off fourth current source having a source coupled to the second end of the first resistor and a gate coupled to a drain of the third field effect transistor. A normally-off fifth field effect transistor having an effect transistor, a drain coupled to the gate of the first field effect transistor, a source coupled to the output node, and a gate; A first capacitor having a first end coupled to the cathode of the diode and a second end coupled to the output node; and a first end receiving a third switching control signal from the input signal processor. A second capacitor having a second end coupled to the gate of the fifth field effect transistor; a cathode coupled to the gate of the fifth field effect transistor; and the fifth field effect transistor. A second diode having an anode coupled to its source, a drain coupled to the gate of the fifth field effect transistor, and a fixed It includes a source coupled to a node supplied voltage, and a sixth field-effect transistor of the normally-off type having a gate receiving a fourth switching control signal from the input signal processing unit.

  ADVANTAGE OF THE INVENTION According to this invention, the driver for driving a power semiconductor element can be obtained at low cost.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the structure of the output stage of the high side drive part which concerns on the 1st Embodiment of this invention, and a semiconductor device. 3 is a timing chart showing an operation of the semiconductor device according to the first exemplary embodiment of the present invention. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transitions from a logic low level to a logic high level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transitions from a logic low level to a logic high level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transitions from a logic low level to a logic high level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transitions from a logic low level to a logic high level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic high level to a logic low level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic high level to a logic low level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic high level to a logic low level. FIG. 3 is a diagram showing, in time series, the state of a circuit when an output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic high level to a logic low level. 2 is a diagram illustrating a configuration of a power supply device 401. FIG. FIG. 6 is a diagram illustrating a simulation result of potentials of respective nodes in the semiconductor device 101. It is a figure which shows in detail the electric potential of each node when the electric potential of the node a enclosed with the dotted line in FIG. 13 changes from a logic low level to a logic high level. It is a figure which shows in detail the electric potential of each node when the electric potential of the node a enclosed with the dotted line in FIG. 13 changes from a logic high level to a logic low level. FIG. 6 is a diagram illustrating a simulation result of potentials of respective nodes in the semiconductor device 101. It is a figure which shows in detail the electric potential of each node when the electric potential of the node a enclosed by the dotted line in FIG. 16 changes from a logic low level to a logic high level. It is a figure which shows in detail the electric potential of each node at the time of the electric potential of the node a enclosed with the dotted line in FIG. 16 changing from a logic high level to a logic low level. It is a figure which shows the simulation result of the output voltage of a power supply device. 1 is a cross-sectional view of a field effect transistor Tr1 according to a first embodiment of the present invention. It is a figure which shows the structure of a normal GaN transistor roughly. It is a figure which shows roughly the structure of a GaN transistor of a high voltage resistance on both sides. It is a figure which shows roughly the structure of the modification of field effect transistor Tr5. 1 is a diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the structure of the electronic device which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the compressor part in the electronic device which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the output stage of the high side drive part which concerns on the 2nd Embodiment of this invention, and a semiconductor device. 6 is a timing chart illustrating an operation of the semiconductor device according to the second embodiment of the present invention. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic low level to a logic high level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the state of a circuit in time series when the output signal of the semiconductor device which concerns on the 2nd Embodiment of this invention changes from a logic high level to a logic low level. It is a figure which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structure of the output stage of the high side drive part which concerns on the 3rd Embodiment of this invention, and a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 101 includes an input signal processing unit 65, a high side driving unit 62, a low side driving unit 64, and field effect transistors Tr1, Tr2, Tr12.

  The field effect transistors Tr1 and Tr2 are normally on, for example, GaN field effect transistors. The field effect transistor Tr12 is a normally-off type, for example, an insulated gate field effect transistor.

  A set of cascode-connected field effect transistors Tr2 and Tr12 operates like a normally-off type transistor. The level of power supply voltage VH is 400V, for example. The level of power supply voltage VCC is, for example, 15V.

  The input signal processing unit 65 outputs a switching control signal based on a signal received from the outside of the semiconductor device 101. That is, the input signal processing unit 65 performs preprocessing for converting a signal received from the outside of the semiconductor device 101 into a signal that can be easily handled inside the semiconductor device 101.

  The high side drive unit 62 outputs a drive signal based on the switching control signal received from the input signal processing unit 65. The high side drive unit 62 also serves as a level shifter, and the drive signal output from the high side drive unit 62 is a signal obtained by shifting the reference voltage of the switching control signal output from the input signal processing unit 65.

  The low side drive unit 64 outputs a drive signal based on the switching control signal received from the input signal processing unit 65.

  When the high side of the semiconductor device 101 is turned on by these drive signals, the field effect transistor Tr1 is turned on, and the transistor constituted by the field effect transistors Tr2 and Tr12 is turned off. At this time, the level of the output voltage VA becomes the power supply voltage VH.

  Further, when the low side of the semiconductor device 101 is turned on by these drive signals, the field effect transistor Tr1 is turned off, and the transistor constituted by the field effect transistors Tr2 and Tr12 is turned on. At this time, the level of the output voltage VA is zero volts.

  That is, the field effect transistor Tr1 corresponds to a first switching function unit that is controlled by a drive signal from the high-side drive unit to turn on / off the supply of the power supply voltage VH to the output node NOUT. The operation of the first switching function unit corresponds to a normally-on type switching function. Further, the combination circuit of the cascode-connected field effect transistors Tr2 and Tr12 corresponds to a second switching function unit that is controlled by a driving signal from the low-side driving unit to turn on / off the supply of the ground potential to the output node. . The operation of the second switching function unit corresponds to a normally-off type switching function.

  The high side driver 62, the field effect transistor Tr1, and the field effect transistor Tr2 are included in a semiconductor chip 71 manufactured by a GaN process. The field effect transistor Tr2 used for the low-side output can be formed on another semiconductor chip without being included in the semiconductor chip 71. However, forming the semiconductor device on the same semiconductor chip 71 as described above can reduce the number of components, thereby reducing the size of the semiconductor device.

  The input signal processing unit 65 and the low side driving unit 64 are included in a semiconductor chip 72 manufactured by a CMOS process. In a particularly preferred embodiment, the field effect transistor Tr12 is also mounted on the semiconductor chip 72.

  A load (not shown) is coupled to an output node NOUT which is a connection node between the field effect transistors Tr1 and Tr2. The voltage at the output node NOUT becomes the output voltage to the load.

  The input signal processing unit 65 operates using the ground voltage as the reference voltage, and operates using the power supply voltage VCC lower than the power supply voltage VH and higher than the ground voltage as the operation power supply voltage. High side driver 62 is coupled to input signal processor 65 and output node NOUT. Further, the high-side drive unit 62 shifts the drive signal to the field effect transistor Tr1 according to the potential of the output node NOUT, that is, the level of the drive signal to the field effect transistor Tr1 depends on the potential of the output node NOUT. Control. As a result, the field effect transistor Tr1 is driven while preventing an excessive potential difference from being applied between the gate and the source of the field effect transistor Tr1 to destroy the field effect transistor Tr1. The low side driver 64 operates using the ground voltage as a reference voltage and operates using the power supply voltage VCC as an operation power supply voltage.

  FIG. 2 is a diagram illustrating a configuration of the high-side drive unit and the output stage of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 2, semiconductor device 101 further includes diodes D16 and D17. The high side driving unit 62 includes field effect transistors Tr3 to Tr6, resistors R1 and R2, a capacitor C1, and a diode D2.

  The field effect transistors Tr3 to Tr6 are normally on, for example, GaN field effect transistors. The field effect transistors Tr1 to Tr3, Tr4, and Tr6 have, for example, a gate-source breakdown voltage of 30 V (volt) or less, a gate-drain breakdown voltage of 600 V or more, and high drive with high current driving capability. GaN field effect transistor. The field effect transistor Tr5 is, for example, a double-sided high breakdown voltage GaN field effect transistor having a gate-source breakdown voltage and a gate-drain breakdown voltage of 600 V or more.

  Diode D2 has an anode receiving control signal S5, a first end of resistor R1, a first end of resistor R2, a drain of field effect transistor Tr5, and a cathode coupled to a first end of capacitor C1. Field effect transistor Tr3 has a drain coupled to the second end of resistor R1, a source coupled to the ground node, and a gate for receiving control signal S2. Field effect transistor Tr4 has a drain coupled to the second end of resistor R2, a source coupled to a node to which a fixed voltage VN1 of, for example, −10V is supplied, and a gate receiving control signal S3. Field effect transistor Tr5 has a drain coupled to the cathode of diode D2, a source, and a gate coupled to the second end of resistor R2 and the drain of field effect transistor Tr4. Field effect transistor Tr6 has a drain coupled to the source of field effect transistor Tr5, a source coupled to a node to which a fixed voltage VN2 of, for example, -5V is supplied, and a gate receiving control signal S4.

  Field effect transistor Tr1 has, for example, a drain coupled to a node to which power supply voltage VH of 400 V is supplied, a source coupled to the second end of capacitor C1 and output node NOUT, a source of electric field effect transistor Tr5, and an electric field And a gate coupled to the drain of effect transistor Tr6. Diode D16 has a cathode coupled to the drain of field effect transistor Tr1 and an anode coupled to the source of field effect transistor Tr1. Field effect transistor Tr2 has a drain coupled to output node NOUT, a source, and a gate coupled to a ground node. Field effect transistor Tr12 has a drain coupled to the source of field effect transistor Tr2, a source coupled to the ground node, and a gate for receiving control signal S1. Diode D17 has a cathode coupled to the drain of field effect transistor Tr2 and an anode coupled to the source of field effect transistor Tr12.

  The high-side drive unit 62 includes a node a that is a coupling node of the second end of the capacitor C1, the source of the field effect transistor Tr1 and the drain of the field effect transistor Tr2, the cathode of the diode D2, the first end of the resistor R1, A node b which is a coupling node of the first end of the resistor R2, the drain of the field effect transistor Tr5 and the first end of the capacitor C1, the second end of the resistor R2, the drain of the field effect transistor Tr4 and the gate of the field effect transistor Tr5. The node c is a coupling node, and the node d is a coupling node of the source of the field effect transistor Tr5, the drain of the field effect transistor Tr6, and the gate of the field effect transistor Tr1.

  When the output signal of the semiconductor device 101 is switched from the logic low level to the logic high level, and when the output signal is switched from the logic high level to the logic low level, an appropriate potential difference is applied across the capacitor C1.

  That is, when switching from the logic low level to the logic high level, first, the field effect transistor Tr12 is turned on and the voltage from the control signal S5 is applied to the node b in the state where the potential of the node a is almost the ground potential. And the potential Va of the node a are set so that Vb ≧ Va. In this state, the field effect transistor Tr12 is turned off and the field effect transistor Tr5 is turned on, whereby a part of the charge at the node b moves to the node d, the potential at the node d rises and the field effect transistor Tr1 is turned on. . When the potential of the node a rises, the potential of the node b is pushed up through the capacitor C1. Along with this, the potential of the node d also rises via the field effect transistor Tr5, so that a drive signal having a level corresponding to the potential of the output node NOUT can be given to the field effect transistor Tr1.

  On the other hand, when switching from the logic high level to the logic low level, first, the field effect transistor Tr1 is turned on and the potential of the node a is almost equal to the power supply voltage VH. The electric charge is appropriately discharged, and the potential of the node b is slightly lowered so that Vb <Va. When the field effect transistor Tr5 is turned on in this state, a part of the charge at the node d moves to the node b, and the potential at the node d is also slightly lowered. When Vd <Va, the field effect transistor Tr1 is turned off. . When the potential of the node a is lowered by turning on the field effect transistor Tr12 or the like, the potential of the node b is also lowered through the capacitor C1. Along with this, the potential of the node d also decreases through the field effect transistor Tr5. Therefore, while maintaining the field effect transistor Tr1 in the OFF state, it is further possible to prevent the potential effect transistor from causing breakdown due to an excessive potential difference between the gate (node d) and the source (node a) of the field effect transistor Tr1. Switching to can be realized. That is, a drive signal having a level corresponding to the potential of the output node NOUT can be applied to the field effect transistor Tr1.

  FIG. 3 is a timing chart showing the operation of the semiconductor device according to the first embodiment of the present invention.

  4 to 7 are diagrams showing the circuit states in time series when the output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic low level to a logic high level. 8 to 11 are diagrams showing the circuit states in time series when the output signal of the semiconductor device according to the first embodiment of the present invention transits from a logic high level to a logic low level. 4 to 11, the direction and thickness of the arrows indicate the direction and magnitude of the current, respectively.

  Referring to FIG. 3, the output signal of semiconductor device 101 repeats a logic high level (high level output) and a logic low level (low level output) in a predetermined cycle.

  First, an operation in which the output signal of the semiconductor device 101 transitions from a logic low level to a logic high level will be described.

  3 and 4, at time t1, control signal S1 is set to 10V, control signal S2 is set to -10V, control signal S3 is set to -15V, and control signal S4 is set to -5V. Thus, the control signal S5 is set to -5V. At this time, the field effect transistor Tr12 is turned on by the control signal S1, and the potential of the node a becomes 0V. Further, the field effect transistor Tr4 is turned off by the control signal S3, the potentials of the nodes b and c are -5V, and the field effect transistor Tr5 is turned on. Further, when the field effect transistor Tr6 is turned on by the control signal S4, the potential of the node d is fixed to −5V. Thereby, the field effect transistor Tr1 is turned off. Therefore, a logic low level signal is output from output node NOUT to the load. An energization state is established between the output node NOUT side, that is, the load and the ground node via the field effect transistors Tr2 and Tr12.

  3 and 5, next, at time t2 to time t3, control signal S3 is set to -10V, at time t3 to time t4, control signal S4 is set to -10V, and from time t3 to time t4. The control signal S5 is set to 15V. At this time, the field effect transistor Tr6 is turned off by the control signal S4. Further, the field effect transistor Tr4 is turned on by the control signal S3. Since the current driving capability of the field effect transistor Tr4 is set higher than that of the resistor R2, the potential of the node c substantially matches the fixed voltage VN1, and the potential of the node c becomes −10V. As a result, the field effect transistor Tr5 is turned off. Further, a current flows from the anode to the cathode of the diode D2 by the control signal S5, and the node b is charged to 15V. During this time, a current flows from the output node NOUT side, that is, the load, to the ground node via the field effect transistors Tr2 and Tr12. The output signal of the semiconductor device 101 is maintained at a logic low level.

  3 and 6, next, control signal S1 is set to 0V from time t4 to time t5, and control signal S3 is set to -15V from time t5 to time t6. At this time, the field effect transistor Tr12 is turned off by the control signal S1. Further, when the field effect transistor Tr4 is turned off by the control signal S3, a current flows from the node b via the resistor R2, and the potential of the node c rises. Thereby, the field effect transistor Tr5 is turned on, a current flows from the node b through the field effect transistor Tr5, and the potentials of the nodes c and d rise. When the potential of the node d exceeds the threshold value of the field effect transistor Tr1, the field effect transistor Tr1 is turned on, and a current flows from the node supplied with the power supply voltage VH to the node a through the field effect transistor Tr1.

  Referring to FIGS. 3 and 7, since time field effect transistor Tr1 is turned on after time t6, the potential of node a rises to the potential of power supply voltage VH, for example, 400V. That is, a logic high level signal is output from the output node NOUT to the load. Further, as the potential of the node a rises toward 400V, the potential of the node a pushes up the potential of the node b through the capacitor C1, and the potential of the node b also rises. Furthermore, since a current flows from the node b to the node c via the resistor R2, the potential of the node c also rises, and the on state of the field effect transistor Tr5 is maintained. Since the node b and the node d are made conductive by the field effect transistor Tr5, the potential of the node d increases as the potential of the node b increases. Therefore, the on state of the field effect transistor Tr1 is maintained, and the output signal of the semiconductor device 101 is maintained at a logic high level.

  Next, an operation in which the output signal of the semiconductor device 101 transitions from a logic high level to a logic low level will be described.

  3 and 8, control signal S3 is set to -10V from time t8 to time t9, and control signal S5 is set to -5V from time t7 to time t8. At this time, since the field effect transistor Tr1 is on, the potential of the node a is maintained at 400V. Then, the field effect transistor Tr4 is turned on by the control signal S3, and a current flows from the node b through the resistor R2 and the field effect transistor Tr4 to the ground node. Since the current flowing through the field effect transistor Tr4 is much larger than the current flowing through the resistor R2, the potential of the node c decreases. As a result, the field effect transistor Tr5 is turned off. The output signal of the semiconductor device 101 is maintained at a logic high level.

  3 and 9, next, control signal S2 is set to 0V from time t9 to time t10. At this time, the field effect transistor Tr3 is turned on by the control signal S2, whereby current flows from the node b to the ground node via the resistor R1, and the potential of the node b gradually decreases to about 380V. The output signal of the semiconductor device 101 is maintained at a logic high level.

  3 and 10, next, control signal S2 is set to -10V from time t13 to time t14, and control signal S3 is set to -15V from time t10 to time t11. At this time, the field effect transistor Tr3 is turned off by the control signal S2. Further, the field effect transistor Tr4 is turned off by the control signal S3, whereby the potential of the node c is increased by the current flowing from the node b through the resistor R2. Thereby, the field effect transistor Tr5 is turned on, and a current flows from the node d to the node b through the field effect transistor Tr5. As a result, the potentials of the nodes b, c, and d become about 390 V, for example, which is lower than the potential of the node a that is 400 V, so that the field effect transistor Tr1 is turned off. The output signal of the semiconductor device 101 is maintained at a logic high level.

  Referring to FIGS. 3 and 11, next, control signal S <b> 1 is set to 10 V from time t <b> 15 to time t <b> 16. At this time, the field effect transistor Tr12 is turned on by the control signal S1, and the potential of the node a is reduced to 0V. Then, due to the potential drop of the node a, the potential of the node b drops via the capacitor C1. Here, since the field effect transistor Tr5 is on, the potential of the node b and the potential of the node d are substantially equal, and the potential of the node a is maintained higher than the potentials of the nodes b and d. That is, while maintaining the off state of the field effect transistor Tr1, the nodes b and d are lowered to, for example, about −5V. During this time, a voltage difference exceeding the withstand voltage of the field effect transistor Tr1 does not occur between the node d and the node a, that is, the gate and source of the field effect transistor Tr1, and the device can be prevented from being destroyed. Further, the node c is also electrically connected to the node b through the resistor R2, so that the voltage drops to the same level as the nodes b and d. Then, a current flows from the output node NOUT side, that is, from the load to the ground node via the field effect transistors Tr2 and Tr12, that is, a logic low level signal is output from the output node NOUT to the load.

  After that, the control signal S4 is set to −5 V from time t17 to time t18, the field effect transistor Tr6 is turned on, and the potential of the node d becomes the potential VN2.

  Here, in the semiconductor device 101, a circuit for raising the potential of the node b when transitioning from a logic low level to a logic high level, that is, a circuit constituted by the capacitor C1, transitions from a logic high level to a logic low level. At this time, it can be used as a circuit for lowering the potential of the node b. As a result, the circuit can be simplified.

  Further, if the high-side drive unit 62 having the function of the level shift circuit is constituted by, for example, MOS transistors, a large number of MOS transistors, for example, about 70 MOS transistors are usually required. However, in the high side drive unit 62, by using the GaN field effect transistor, the number of elements can be greatly reduced by using four transistors. Accordingly, the power semiconductor element and the driver for driving the power semiconductor element can be formed on the same substrate with a small area, and the manufacturing cost can be reduced.

FIG. 12 is a diagram illustrating a configuration of the power supply device 401.
In FIG. 12, a power supply device 401 coupled to the output node NOUT is shown as a load driven by the semiconductor device 101.

  In power supply device 401, the winding ratio of the transformer is set to 1: 0.133, and a DC voltage of 27V is output from node LOUT with a power supply voltage VH of 400V at a duty of 1/2.

  FIG. 13 is a diagram illustrating a simulation result of the potential of each node in the semiconductor device 101. FIG. 14 is a diagram showing in detail the potential of each node when the potential of the node a surrounded by the dotted line in FIG. 13 transits from the logic low level to the logic high level. FIG. 15 is a diagram showing in detail the potential of each node when the potential of the node a surrounded by the dotted line in FIG. 13 transits from the logic high level to the logic low level. 13 to 15 show an initial state immediately after the semiconductor device is started up.

  Referring to FIG. 13, it can be seen that the potential of node a, that is, the output voltage level of semiconductor device 101, repeats a logic high level and a logic low level in a predetermined cycle.

  Referring to FIG. 14, at timing T1, field effect transistor Tr4 is turned on, so that the potential of node c decreases. Next, at timing T2, the control signal S5 is set to 15V, so that the potential of the node b is charged to 15V. Next, at the timing T3, the field effect transistor Tr12 is turned off. Next, at the timing T4, the field effect transistor Tr4 is turned off, so that the potential of the node c rises. When the field effect transistor Tr1 is turned on slightly after the timing T4, the potentials of the nodes a, b, c, and d rise.

  Referring to FIG. 15, at timing T11, control signal S5 is set to −5V. Next, at the timing T12, the field effect transistor Tr4 is turned on, so that the potential of the node c rapidly drops and the field effect transistor Tr5 is turned off. In this simulation, unlike the circuit shown in FIG. 2, the potential of the node c is lowered to 0V instead of −10V. However, the potential of the node c can be lowered to a level at which the field effect transistor Tr5 is turned off. That's fine. Next, at the timing T13, the field-effect transistor Tr3 is turned on, so that the potential at the node b gradually decreases. Next, at the timing T14, the field effect transistor Tr4 is turned off, so that the potential of the node c rapidly increases. As the potential of the node c rises and the field effect transistor Tr5 is turned on, the potentials of the nodes b, c, and d gradually become equal. Next, at the timing T15, the field effect transistor Tr3 is turned off. Next, at the timing T16, the field effect transistor Tr12 is turned on, so that the potentials of the nodes a, b, c, and d are lowered. Next, at the timing T17, the field effect transistor Tr6 is turned on. However, since the potential of the node d is already -5V, the potential fluctuation does not occur.

  FIG. 16 is a diagram illustrating a simulation result of the potential of each node in the semiconductor device 101. FIG. 17 is a diagram showing in detail the potential of each node when the potential of the node a surrounded by the dotted line in FIG. 16 transits from the logic low level to the logic high level. FIG. 18 is a diagram showing in detail the potential of each node when the potential of the node a surrounded by the dotted line in FIG. 16 transits from the logic high level to the logic low level. 16 to 18 show a steady state after the semiconductor device is started up and the operation is stabilized. Here, differences from FIGS. 13 to 15 will be described.

  Referring to FIG. 17, the timing at which the potentials of nodes a, b, c and d rise is earlier than in the initial state (FIG. 14). Node c rises later than the other nodes. That is, the potentials of the nodes a, b, and d are increased before the field effect transistor Tr5 is turned on. This is because the potentials of the nodes a, b, and d are increased not by the current from the field effect transistor Tr1 but by the current from the load.

  Referring to FIG. 18, at the timing T14, the field effect transistor Tr4 is turned off, so that the potential of the node c rapidly increases. The timing at which the potentials at nodes a, b, c, and d decrease after the potential at node c increases is earlier than in the initial state (FIG. 15). At the timing T15, when the field effect transistor Tr3 is turned off, the potentials of the nodes a, b, c, and d have already started to decrease. At the timing T16, when the field effect transistor Tr12 is turned on, the potential reduction of the nodes a, b, c, and d is completed.

FIG. 19 is a diagram illustrating a simulation result of the output voltage of the power supply device.
Referring to FIG. 19, it can be seen that the power supply device 401 is driven by the semiconductor device 101, so that the output voltage rises to 27 V in about 1 millisecond, and good characteristics are obtained.

  Here, if the drive capability of the field effect transistors Tr1 and Tr2 which are output power transistors is not sufficient to drive the load circuit, the load circuit does not operate normally.

  On the other hand, if the capacitances of the field effect transistors Tr1 and Tr2 are large, it is necessary to increase the capacitance of each element in the high-side drive unit 63 and the low-side drive unit 64 for normal operation, resulting in an increase in power consumption.

  In the semiconductor device 101, by using GaN transistors having high drive capability and low capacity as the field effect transistors Tr1 and Tr2, it is possible to obtain a circuit with low power consumption while suppressing the capacity of the entire circuit.

  Further, in the semiconductor device 101, since the power transistor, the high side logic, and the level shifter can be formed on the same substrate by using the GaN transistor in the high side driving unit 63, the number of elements is small, and the manufacturing is inexpensive. It becomes possible. Further, by eliminating the impedance component as much as possible, a high speed and stable operation is possible.

  Further, for a while after the semiconductor device 101 is started up, there is a time zone in which the on / off transition timings of the field effect transistors Tr1 and Tr12 do not match the transition timings between the logic low level and the logic high level of the load output. . This is because the resonance operation of the power supply device 401 serving as a load is not stably synchronized with the switching timing of the logic low level and the logic high level of the output signal of the semiconductor device 101, particularly at the initial startup of the semiconductor device 101. For this reason, if the drive capability of the field effect transistors Tr1, Tr2, and Tr12 is insufficient, an excess current may be caused to flow through these field effect transistors due to the current flowing through the load, and these field effect transistors may be destroyed. . Specifically, for example, due to the current flowing through the load, the potential of the node a is lowered to near the ground potential or the field effect transistor Tr12 is turned on even though the field effect transistor Tr1 is turned on. In some cases, the potential of the node a may rise to around 400V despite being in the middle. In such a case, the field effect transistor Tr1 or Tr2 is exposed to a short-circuit state in which 400 V or a high voltage close thereto is applied between the source and the drain in the on state, and may be destroyed.

  On the other hand, the larger the gate width of the field effect transistor Tr1, the larger the capacity of the capacitor C1 for raising the potential of the node b is required. Increasing the capacitance of the capacitor C1 increases the power consumption when the potential of the node b is lowered during the period from time t9 to time t10.

  However, in the semiconductor device 101, by using a GaN field effect transistor, the drive capability can be increased while suppressing the gate capacitance of the transistor, so that the capacitor C1 can be reduced. As a result, energy consumed in the period from time t9 to time t10 can be reduced, and as a result, the efficiency of the circuit can be increased.

  In the semiconductor device 101, the gate width of the field effect transistor Tr1 may be set smaller than that of the field effect transistor Tr2. Thus, by reducing the capacitance of the field effect transistor Tr1, the capacitances of the capacitor C1 and the field effect transistor Tr5 can be reduced. Then, the potential lowering speed of the node b through the resistor R1 and the field effect transistor Tr3 is increased, and the resistor R1 can be relatively increased. Further, since the potential fluctuation at the node a becomes smooth, the period during which the field effect transistor Tr3 is turned on can be shortened, so that the power consumption of the resistor R1 can be reduced.

  By reducing the gate widths of the field effect transistors Tr1 and Tr2, the device size can be reduced and the chip area can be reduced, so that the manufacturing cost can be reduced. Therefore, it is preferable to set the gate width as small as possible within a range that does not impair the normal operation and reliability of the semiconductor device 101. The gate width of the field effect transistor Tr1 necessary for ensuring normal operation and reliability can be made smaller than that required for the field effect transistor Tr2. That is, setting the gate width of the field effect transistor Tr1 to be smaller than the gate width of the field effect transistor Tr2 has an effect of reducing the cost by reducing the chip area. In the simulations of FIGS. 13 to 19, the ratio of the gate widths of the field effect transistor Tr1 and the field effect transistor Tr2 is 2: 3.

  FIG. 20 is a cross-sectional view of the field effect transistor Tr1 according to the first embodiment of the present invention.

  Referring to FIG. 20, field effect transistor Tr1 is, for example, a gallium nitride HFET (Hetero Structure Field Effect Transistor).

  The field effect transistor Tr1 includes a silicon substrate 91, a buffer layer 92, a GaN layer 93, an AlGaN layer 94, a SiN layer 95, a gate electrode ELG, a source electrode ELS, and a drain electrode ELD. The silicon substrate 91 may be an epitaxial growth substrate using another material. That is, any substrate may be used as long as a semiconductor layer is formed on the substrate by epitaxial growth.

  Buffer layer 92 is an AlGaN layer, for example, and is formed on the main surface of silicon substrate 91. The GaN layer 93 is formed on the buffer layer 92. The AlGaN layer 94 is formed on the GaN layer 93.

  The source electrode ELS and the drain electrode ELD are formed on the AlGaN layer 94 and are electrically connected to the AlGaN layer 94. A resistance junction is formed by the source electrode ELS and the AlGaN layer 94. A resistance junction is formed by the drain electrode ELD and the AlGaN layer 94.

  The gate electrode ELG is formed on the AlGaN layer 94 and is electrically connected to the AlGaN layer 94. A Schottky junction is formed by the gate electrode ELG and the AlGaN layer 94, that is, a Schottky barrier diode is formed across the gate electrode ELG and the AlGaN layer 94.

  In addition, not only a Schottky junction but it is good also as a PN junction gate structure which formed the PN junction between the gate electrode and the AlGaN layer 94 by using a p-type AlGaN layer as a gate electrode.

  The SiN layer 95 is formed on the AlGaN layer 94 so as to be sandwiched between a part of the gate electrode ELG and the AlGaN layer 94, and the source electrode ELS, the drain electrode ELD, and the gate in the extending direction of each layer in the field effect transistor Tr1. It is provided between the electrodes ELG. Further, a high-concentration two-dimensional electron gas (2DEG) 96 is formed in the vicinity of the heterojunction interface between the AlGaN layer 94 and the GaN layer 93.

  Thus, the field effect transistor Tr1 has a non-insulated gate, and a Schottky barrier diode is formed across the gate electrode ELG and the AlGaN layer 94. Therefore, depending on the potential relationship of each electrode of the field effect transistor Tr1 A gate leakage current IGL may flow from the drain electrode ELD to the gate electrode ELG. This gate leakage current IGL is, for example, on the order of 10 uA to 100 uA.

  Since the configuration of field effect transistors Tr2, Tr3, Tr4, Tr6 is similar to that of field effect transistor Tr1, detailed description will not be repeated here.

  The gate widths of the field effect transistor Tr1 and the field effect transistor Tr2 may be substantially the same, but the gate width of the field effect transistor Tr1 is smaller than the gate width of the field effect transistor Tr2, for example, with respect to the gate width of the field effect transistor Tr2 It is preferable to set the gate width of the field effect transistor Tr1 to about 2/3. The field effect transistors Tr3, Tr4, and Tr6 can be operated with a smaller driving capability. For example, if the gate width is appropriately designed to be 1/30 to 1/500 of the gate width of the field effect transistor Tr1. Good. The same applies to the field effect transistor Tr5 described later.

  FIG. 21 is a diagram schematically showing the structure of a normal GaN transistor. FIG. 22 is a diagram schematically showing the structure of a GaN transistor having a high breakdown voltage on both sides.

  Referring to FIG. 21, a normal power device has a gate and a drain electrode ELD separated from each other by providing a gate electrode ELG and a drain electrode ELD as in the field effect transistors Tr1, Tr2, Tr3, Tr4, Tr6 shown in FIG. While a high breakdown voltage is realized between the drains, the breakdown voltage is low because the gate electrode ELG and the source electrode ELS are provided close to each other in order to increase the drive capability.

  Referring to FIG. 22, field effect transistor Tr5 does not require a high drive capability like a power device, but instead requires a high breakdown voltage between the source and gate. This is because, as described above, there is a timing when the gate voltage becomes 0V and the source voltage becomes the power supply voltage VH. For this reason, in the field effect transistor Tr5, the source electrode ELS, the gate electrode ELG, and the drain electrode ELD are provided at regular intervals, for example. The other structure of the field effect transistor Tr5 is the same as that shown in FIG.

  The transistors other than the field effect transistors Tr1, Tr2, and Tr5 may have either the structure shown in FIG. 21 or the structure shown in FIG. 22, but the structure shown in FIG. 21 is preferable because it has a lower resistance.

FIG. 23 schematically shows a structure of a modification of field effect transistor Tr5.
Referring to FIG. 23, field effect transistor Tr5 may have a structure in which the low breakdown voltage sides of two normal GaN transistors are connected to each other instead of the structure shown in FIG.

FIG. 24 is a diagram showing the structure of the semiconductor device according to the first embodiment of the present invention.
Referring to FIG. 24, semiconductor device 101 is manufactured by a high-density mounting technique such as MCM (multi-chip module), for example.

  More specifically, the photosensitive polyimide resin layer RS is formed on the substrate B, and the metal wiring LN is provided in the photosensitive polyimide resin layer RS.

  The semiconductor chip 71 and the semiconductor chip 72 have solder bumps SBP. The semiconductor chip 71 and the semiconductor chip 72 are mounted on the substrate B when the solder bumps SBP are heated and bonded to the substrate B. As described above, by adopting the high-density mounting technique, the wiring length can be shortened, so that the inductor component can be greatly reduced.

  The input signal processing unit 65 in the semiconductor chip 72 and the high side driving unit 62 in the semiconductor chip 71 are connected via a metal wiring LN.

  In the configuration disclosed in Patent Document 1, the high breakdown voltage MOSFET is manufactured by a process different from that of other circuits and externally attached to the other circuits. Will add a lot of noise.

  On the other hand, in the semiconductor device according to the first embodiment of the present invention, a GaN field effect transistor is used in the high-side drive unit 62. Since the gate capacity of the GaN field effect transistor is extremely small compared to the high breakdown voltage MOS, even when the high side driving unit 62 and another circuit are connected via the metal wiring LN, noise can be suppressed to the minimum. it can.

  Note that, for example, the semiconductor chip 71 and the semiconductor chip 72 may be provided on different substrates without using the high-density mounting technique in the manufacture of the semiconductor device 101. In this case, the input signal processing unit 65 and the high side driving unit 62 are connected between different substrates through wire bonds or the like. As described above, even when the input signal processing unit 65 and the high side driving unit 62 are connected by wire bonding or the like, the use of the GaN field effect transistor in the high side driving unit 62 can suppress noise to the minimum. it can.

  In the configuration described in Patent Document 1, a power MOSFET is used as one corresponding to the field effect transistors Tr1 and Tr2, and a lateral type high voltage MOS transistor called “LDMOS” as one corresponding to the field effect transistors Tr3 to Tr6. Is used. Since it is difficult to integrally form a power MOSFET and a high breakdown voltage MOSFET, the configuration described in Patent Document 1 increases the process cost.

  On the other hand, in the semiconductor device according to the first embodiment of the present invention, the high-side driver 62, the field effect transistor Tr1, and the field effect transistor Tr2 are included in the semiconductor chip 71. That is, by using a normally-on type GaN field effect transistor in the high side drive unit 62, the field effect transistors Tr1 and Tr2 used as power semiconductor elements and the field effect transistors Tr3 to Tr6 used as high breakdown voltage transistors are the same. It can be formed on a substrate. Therefore, a driver for driving the power semiconductor element can be obtained at low cost.

  In the semiconductor device 101, the output voltage range can be set to, for example, 0V to 400V while the input voltage range is set to, for example, 0V to 20V. As a result, the logic circuit for controlling the high-side driver can be manufactured by a general MOS process, and the manufacturing cost can be reduced. In the semiconductor device according to the first embodiment of the present invention, the input signal processing unit 65 and the low side driving unit 64 are included in the semiconductor chip 72. That is, the control logic which is a circuit other than the field effect transistors Tr1 and Tr2 and the high-side drive unit 62 is integrally formed using only the CMOS process. Thereby, the manufacturing cost can be further reduced.

  Particularly preferably, the field effect transistor Tr12 is also formed on the semiconductor chip 72, whereby the number of parts can be further reduced and the cost can be reduced. Furthermore, since the wiring length between the low-side drive unit 64 and the field effect transistor Tr12 can be shortened, noise due to an inductor component or the like can be reduced, and reliability can be improved.

  In the semiconductor device 101, a high drive GaN field effect transistor and a high breakdown voltage GaN field effect transistor are formed on the same substrate. With such a configuration, since the power semiconductor element and the driver for driving the power semiconductor element can be integrally formed on the same substrate, noise can be reduced and reliability can be increased.

  The GaN field effect transistor can be switched at high speed, that is, at high speed, but noise increases with high speed switching. However, in the semiconductor device 101, since the power semiconductor element and the driver for driving the power semiconductor element can be integrally formed on the same substrate, the wiring capacity is reduced, and the noise increase due to high-speed switching is increased. Can be suppressed.

  That is, by integrally forming the field effect transistors Tr1 and Tr2 and the high-side drive unit 62, it is possible to reduce the length of the wiring that connects the field-effect transistors Tr1 and Tr2 and the high-side drive unit 62, respectively. In addition, noise caused by the inductor component of the wiring can be reduced. Therefore, a highly reliable driver can be obtained.

  In the semiconductor device according to the first embodiment of the present invention, the high-side drive unit 62 includes the field effect transistor Tr6. However, the present invention is not limited to this. When the potential of the output node NOUT is started from a logic low level at the start of power-on of the semiconductor device 101, the node d needs to be a negative voltage that is equal to or lower than the threshold voltage of the field effect transistor Tr1 in order to turn off the field effect transistor Tr1. However, instead of using the field effect transistor Tr6, for example, by setting the control signal S3 to -10V and turning on the field effect transistor Tr4, the potentials of the nodes b, c, and d are made negative by the fixed voltage VN1. It can also be lowered. After the semiconductor device 101 once outputs a logic high level, when transitioning to a logic low level, the potential of the node d is lower than that of the node a (the field effect transistor Tr1 is in an off state) from the logic high level to the logic low level. The level shifts to a level, and finally the nodes b, c and d are controlled to -5V by the control signal S5. For this reason, the configuration may be such that the field effect transistor Tr6 is deleted, the control signal S4 and the fixed voltage VN2 are not required, and the circuit and control are simplified. However, the configuration in which the high-side drive unit 62 includes the field effect transistor Tr6 is a preferable configuration because a means for directly controlling the potential of the node d can be obtained, so that controllability is increased and noise is enhanced.

  In the semiconductor device according to the first embodiment of the present invention, the voltage VN1 is set to a fixed voltage of −10V and the voltage VN2 is set to a fixed voltage of −5V. In practice, it is necessary to always supply these voltages. Absent. It is sufficient that these voltages are applied at least while the field effect transistors Tr4 and Tr6 are turned on. In other time periods, the voltages VN1 and VN2 are set to the ground potential, or the voltages VN1 and VN2 are applied. The corresponding node may be in a floating state. In particular, the voltage VN1 of −10V only needs to be applied at least when switching from the low level output to the high level output (between time t2 and time t6 in FIG. 3) in the timing chart of FIG. In other time zones, the voltage VN1 can be set to the ground potential including the time t8 to the time t11. In this case, the voltage level of the control signal S3 to be given between time t8 and time t11 is preferably set to 0 V, for example, in order to turn on the field effect transistor Tr4. This voltage application method is also adopted in the simulations shown in FIGS.

  In addition, instead of giving two pulses per cycle as the control signal S3 in this way, two nodes of the field effect transistor Tr4 and the control signal S3 are installed in parallel, one of the time t2 to the time t6, the other The same control can be performed by turning on at time t8 to time t11.

  In the semiconductor device according to the first embodiment of the present invention, the anode of the diode D17 is connected to the ground node. For example, when the field effect transistor Tr12 has a built-in diode, the field effect transistor Tr12 It can also be connected to a node between the field effect transistor Tr2.

  In the above embodiment, a normally-on field effect transistor Tr1 is used as the first switching function unit that receives the drive signal from the high-side drive unit and controls the output to the output node NOUT. As a second switching function unit that receives a drive signal from the low-side drive unit and controls output to the output node NOUT, a normally-on type field effect transistor Tr2 and a normally-off type field effect transistor Tr12 are cascode-connected. This configuration is used. Here, it is also possible to use only the normally-on field effect transistor Tr2 as the second switching function unit. In this case, the drain of the field effect transistor Tr2 is connected to the output node NOUT, the source is connected to the ground potential node, the gate is connected to the signal line of the control signal S1 from the low side driver, and the voltage level of the control signal S1 May be appropriately reduced in accordance with the threshold value of the field effect transistor Tr2. For example, in FIG. 3, by setting the control signal S1 set to 10V and 0V to 0V and −10V, respectively, the semiconductor device can be operated as in the above embodiment. In this case, since the normally-on field effect transistor Tr12 can be omitted, the number of parts can be reduced. However, since both the first switching function unit and the second switching function unit are normally-on type switches, the first switching function unit and the second switching function should be stopped if the drive signal stops due to a trouble. Both parts are turned on, and a through current path from the supply node of the power supply voltage VH to the ground node is generated, which generates a large amount of heat due to a large current and may cause various problems. On the other hand, in the above embodiment, since the second switching function unit is a normally-off type switch by cascode connection, it is possible to prevent a through current path from occurring even when the drive signal is stopped. For this reason, from the viewpoint of fail-safe, the above-described embodiment in which the cascode connection is adopted using the normally-off field effect transistor Tr12 is more preferable.

FIG. 25 is a diagram showing the configuration of the electronic apparatus according to the first embodiment of the invention.
Referring to FIG. 25, electronic device 301 is, for example, a refrigerator, and includes a compressor unit 201 for compressing a refrigerant, a refrigerator compartment 202, a freezer compartment 203, and a vegetable compartment 204.

  FIG. 26 is a diagram showing a configuration of a compressor unit in the electronic device according to the first embodiment of the present invention.

  Referring to FIG. 26, compressor unit 201 includes an AC voltage supply unit 165, a motor 160, and a compressor 170. AC voltage supply unit 165 includes a coil 120, a diode unit 130, a capacitor 140, an inverter unit 150, a base driver 180, a voltage detector 190, and a microprocessor 200. Inverter unit 150 includes power semiconductor elements 151 to 156 and a plurality of diodes connected in parallel to power semiconductor elements 151 to 156, respectively. The base driver 180 and the power semiconductor elements 151 to 156 correspond to the semiconductor device 101.

  Diode section 130 performs full-wave rectification on the AC voltage received from AC power supply 110 via coil 120. The capacitor 140 smoothes the AC voltage rectified by the diode unit 130. The power semiconductor elements 151 to 156 in the inverter unit 150 are switched based on the drive signal received from the base driver 180, thereby converting the DC voltage smoothed by the capacitor 140 into an AC voltage to convert the U phase of the motor 160, Supply to the V-phase and W-phase coils. The motor 160 rotates based on the AC voltage supplied from the inverter unit 150 and drives the compressor 170. The voltage detector 190 detects an AC voltage supplied from the inverter unit 150 to the motor 160. The microprocessor 200 outputs a control signal to the base driver 180 based on the detection result of the AC voltage by the voltage detector 190. Base driver 180 generates a drive signal based on a control signal received from microprocessor 200.

  Usually, in a refrigerator, an IGBT (Insulated Gate Bipolar Transistor) having a withstand voltage of about 600 V and an output current of about 5 A is used. In the electronic device 301, field effect transistors Tr1, Tr2, Tr12 are used in place of the IGBTs conventionally used as the power semiconductor elements 151-156.

  Although the electronic device according to the first embodiment of the present invention is a refrigerator, the present invention is not limited to this. A load and an AC voltage supply unit for supplying an AC voltage to the load may be provided, and the AC voltage supply unit may be an electronic device including the semiconductor device 101.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a semiconductor device using a normally-off type field effect transistor as compared with the semiconductor device according to the first embodiment. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

FIG. 27 is a diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention.
Referring to FIG. 27, the semiconductor device 102 includes a high-side drive unit 63 instead of the high-side drive unit 62 as compared with the semiconductor device according to the first embodiment of the present invention, and includes field effect transistors Tr1, Field effect transistors Tr21 and Tr22 are provided instead of Tr2 and Tr12.

  The field effect transistors Tr21 and Tr22 are normally off type, for example, GaN field effect transistors.

  The high side driver 63, the field effect transistor Tr21, and the field effect transistor Tr22 are included in a semiconductor chip 71 manufactured by a GaN process.

  The input signal processing unit 65 and the low side driving unit 64 are included in a semiconductor chip 72 manufactured by a CMOS process.

  A load (not shown) is coupled to an output node NOUT which is a connection node between the field effect transistors Tr21 and Tr22. The voltage at the output node NOUT becomes the output voltage to the load.

  The input signal processing unit 65 operates using the ground voltage as the reference voltage, and operates using the power supply voltage VCC lower than the power supply voltage VH and higher than the ground voltage as the operation power supply voltage. The high-side driver 63 is coupled to the output node NOUT, operates using the voltage of the output node NOUT, that is, the output voltage VA as a reference voltage, and operates using (output voltage VA + power supply voltage VCC) as an operation power supply voltage. The low side driver 64 operates using the ground voltage as a reference voltage and operates using the power supply voltage VCC as an operation power supply voltage.

  FIG. 28 is a diagram showing a configuration of a high-side drive unit and an output stage of a semiconductor device according to the second embodiment of the present invention.

  Referring to FIG. 28, high side drive unit 63 includes field effect transistors Tr13 to Tr16, a resistor R11, capacitors C11 and C14, and diodes D11 and D12.

  Field effect transistors Tr13 to Tr16 are normally off type, for example, GaN field effect transistors. The field effect transistors Tr14, Tr16, Tr21, Tr22 have a gate-source breakdown voltage of 30 V (volts) or less, a gate-drain breakdown voltage of 600 V or more, and a high drive with high current driving capability. GaN field effect transistor. The field effect transistors Tr13 and Tr15 are, for example, high breakdown voltage GaN field effect transistors having a gate-source breakdown voltage and a gate-drain breakdown voltage of 600 V or more.

  The diode D11 has an anode that receives the control signal S11 from the input signal processing unit 65, and a cathode. Resistor 11 has a first end coupled to the cathode of diode D11, and a second end. Field effect transistor Tr14 has a drain coupled to the second end of resistor 11, a source coupled to the ground node, and a gate for receiving control signal S12 from input signal processing unit 65. Field effect transistor Tr13 has a drain coupled to the cathode of diode D11, a source coupled to the gate of field effect transistor Tr21, and a gate coupled to the second end of resistor 11 and the drain of field effect transistor Tr14. Have. Field effect transistor Tr15 has a drain coupled to the gate of field effect transistor Tr21, a source coupled to output node NOUT, and a gate. Capacitor C11 has a first end coupled to the cathode of diode D11, and a second end coupled to output node NOUT. Capacitor C14 has a first end that receives control signal S13 from input signal processing unit 65, and a second end coupled to the gate of field effect transistor Tr15. Diode D12 is, for example, a Zener diode, and has a cathode coupled to the gate of field effect transistor Tr15 and an anode coupled to the source of field effect transistor Tr15. Field effect transistor Tr16 has a drain coupled to the gate of field effect transistor Tr15, a source coupled to the ground node, and a gate for receiving control signal S14 from input signal processing unit 65.

  Field effect transistor Tr21 has a drain coupled to a node to which power supply voltage VH of 400 V, for example, is supplied, a source coupled to the second end of capacitor C1 and output node NOUT, a source of electric field effect transistor Tr13, and an electric field And a gate coupled to the drain of effect transistor Tr15. Diode D16 has a cathode coupled to the drain of field effect transistor Tr21 and an anode coupled to the source of field effect transistor Tr21. Field effect transistor Tr22 has a drain coupled to output node NOUT, a source coupled to the ground node, and a gate for receiving control signal S15 from input signal processing unit 65. Diode D17 has a cathode coupled to the drain of field effect transistor Tr22 and an anode coupled to the source of field effect transistor Tr22.

  In the above description, a Zener diode is used as the diode D12 because, when an insulated gate field effect transistor is used as the field effect transistor Tr15, the gate electrode has a positive potential higher than the source and drain. This is because the insulating film may break down. That is, an object of the field effect transistor Tr15 is to provide a function for preventing the potential of the gate electrode from becoming higher than a predetermined voltage with respect to the potential of the source and drain. As long as the high-side drive unit 63 has this function, other configurations can be adopted. For example, a normal diode is used as the diode D12, and a circuit in which a plurality of diodes are connected in series (hereinafter also referred to as a series diode circuit) is connected in parallel in the opposite direction to the diode D12 (that is, the anode side of the series diode circuit). May be connected to the cathode of the diode D12, and the cathode side of the series diode circuit may be connected to the anode side of the diode D12). When the gate potential of the field effect transistor Tr15 becomes higher than the source and drain potentials and reaches the threshold value of the series diode circuit, the series diode circuit is turned on to prevent a potential difference of a predetermined voltage or more. it can. However, if a Zener diode is used as the diode D12 as in the present embodiment, such a series diode circuit is unnecessary, and the number of components can be reduced.

  Further, when a field effect transistor having a Schottky gate structure or a PN junction gate structure is used as the field effect transistor Tr15 instead of an insulated gate type, if the gate potential becomes higher than a predetermined voltage with respect to the source and drain potentials, Current flows from the gate to the source and drain, preventing an excessive potential difference. That is, the field effect transistor Tr15 itself has a function of preventing the potential of the gate electrode from becoming higher than a predetermined voltage with respect to the potential of the source and drain. In this case, a normal diode can be used as the diode D12.

  FIG. 29 is a timing chart showing the operation of the semiconductor device according to the second embodiment of the present invention.

  FIG. 30 and FIG. 31 are diagrams showing the state of the circuit in time series when the output signal of the semiconductor device according to the second embodiment of the present invention transits from the logic low level to the logic high level. FIG. 32 and FIG. 33 are diagrams chronologically showing the state of the circuit when the output signal of the semiconductor device according to the second embodiment of the present invention transits from a logic high level to a logic low level. 30 to 33, the direction and thickness of the arrow indicate the direction and magnitude of the current, respectively. 30 to 33 show the initial state immediately after the semiconductor device is started up.

  First, an operation in which the output signal of the semiconductor device 102 transitions from a logic low level to a logic high level in the initial state will be described.

  29 and 30, at time t1, control signal S11 is set to 0V, control signal S12 is set to 20V, control signal S13 is set to 0V, control signal S14 is set to 20V, The control signal S15 is set to 20V. At this time, the field effect transistor Tr14 is turned on by the control signal S12, the field effect transistor Tr16 is turned on by the control signal S14, and the field effect transistor Tr22 is turned on by the control signal S15. Then, a logic low level signal is output from the output node NOUT to the load. Current flows from the output node NOUT side, that is, from the load to the ground node via the field effect transistor Tr22.

  Next, at time t2 to time t3, the control signal S11 is set to 20V. Thereby, a current flows from the node b to the ground node through the resistor R11, the node c, and the field effect transistor Tr14. At this time, the potential Vb of the node b is 20V, the potential Vc of the node c is 0V, the potential Vd of the node d is 0V, and the potential Ve of the node e is 0V.

  29 and 31, next, at time t3 to time t4, control signal S14 is set to 0V, and control signal S15 is set to 0V. At this time, the field effect transistor Tr16 is turned off by the control signal S14, and the field effect transistor Tr22 is turned off by the control signal S15.

  Next, from time t4 to time t5, the control signal S12 is set to 0V. At this time, the field effect transistor Tr14 is turned off by the control signal S12. Then, a current flows from the node b to the node c, the potential Vc of the node c rises, and the field effect transistor Tr13 is turned on. Further, the electric charge corresponding to 20 V charged in the node b flows into the node d, and the potential Vd of the node d rises. As the potential Vd of the node d rises, the field effect transistor Tr21 is turned on. As a result, a current flows from the node supplied with the power supply voltage VH to the node a, and the potential Va of the node a rises.

  When the potential Va at the node a rises, a potential rise from the node a to the node b via the capacitor C1 occurs, and the potential Vb at the node b rises. That is, the potential Vb of the node b rises while maintaining a potential higher than Va. Since the node c is connected to the node b via the resistor R1, the potential Vc of the node Vc rises while maintaining approximately Vc≈Vb. Since Vc≈Vb, the field effect transistor Tr13 continues to be turned on, and the node d and the node b are conducted through the field effect transistor Tr13. For this reason, the potential Vd of the node d also rises following the rise of the potentials Vb and Vc. Eventually, the potentials Vb, Vc, and Vd rise together with the potential Va while maintaining a potential higher than the potential Va, so that the field effect transistor Tr21 continues to be turned on, and the node to which the power supply voltage VH is supplied is electrically connected to the node a. Then, the power supply voltage VH is supplied to the node a. That is, a logic high level signal is output from the output node NOUT to the load. Further, the potential Ve of the node e is substantially equal to the potential Va of the node a. Then, from time t6 to time t7, the control signal S11 is set to 0V.

  Next, an operation in which the output signal of the semiconductor device 102 transitions from a logic high level to a logic low level in the initial state will be described.

  29 and 32, at time t5 to time t8, since field effect transistor Tr21 is on, potential Va at node a and potential Ve at node e are, for example, 400V, and potential Vb at node b. The potential Vd of the node d is higher than that of the node a and the node e, for example, about 410V, which is higher by about 10V.

  Next, from time t8 to time t9, the control signal S12 is set to 20V. Thereby, the field effect transistor Tr14 is turned on, a current flows from the node b to the ground node via the field effect transistor Tr14, and the potential Vc of the node c becomes 0V. Then, the field effect transistor Tr13 is turned off.

  Next, from time t9 to time t10, the control signal S13 is set to 20V. As a result, the potential of the node e is pushed up via the capacitor C14, and the potential Ve of the node e becomes a value exceeding the potential Va = 400V, for example, about 410V. Thereby, since the field effect transistor Tr15 is turned on, the node d and the node a are brought into conduction, and the node d and the node a have substantially the same potential. Thereby, the field effect transistor Tr21 is turned off.

  Referring to FIGS. 29 and 33, control signal S15 is set to 20V from time t10 to time t11. Thereby, the field effect transistor Tr22 is turned on. Then, the potential Va of the node a becomes 0 V, and a logic low level signal is output from the output node NOUT to the load. Current flows from the output node NOUT side, that is, from the load to the ground node via the field effect transistor Tr22. At this time, since the node d and the node a are electrically connected via the field effect transistor Tr15 in the on state, the potential of the node d also decreases as the potential of the node a decreases, and the field effect transistor Tr21 is turned off. State is maintained. Further, when the potential Va of the node a decreases and the difference from the potential Ve of the node e reaches the Zener breakdown voltage of the Zener diode D12, a current flows from the node e to the node a, and the potential Ve also decreases as the potential Va decreases. It goes down. Thereby, since the potential difference between the node e and the node a can be suppressed to an appropriate potential difference, the gate insulating film of the field effect transistor Tr15 can be prevented from being broken.

  Next, from time t12 to time t13, the control signal S13 is set to 0V, and the control signal S14 is set to 20V. Thereby, the field effect transistor Tr15 is turned off and the field effect transistor Tr16 is turned on. Then, the potential Ve of the node e becomes 0V. The potentials Vc, Vd, Ve of the nodes c, d, e are all 0V.

  34 to 37 are diagrams showing the circuit states in time series when the output signal of the semiconductor device according to the second embodiment of the present invention transits from the logic low level to the logic high level. 38 to 41 are diagrams showing, in time series, circuit states when the output signal of the semiconductor device according to the second embodiment of the present invention transits from a logic high level to a logic low level. 34 to 41, the direction and thickness of the arrow indicate the direction and magnitude of the current, respectively. 34 to 41 show a steady state after the semiconductor device is started and the operation is stabilized.

  First, an operation in which the output signal of the semiconductor device 102 transitions from a logic low level to a logic high level in a steady state will be described.

  29 and 34, from time t13 to time t14, control signal S11 is set to 0V, control signal S12 is set to 20V, control signal S13 is set to 0V, and control signal S14 is set to 20V. The control signal S15 is set to 20V. At this time, the field effect transistor Tr14 is turned on by the control signal S12, the field effect transistor Tr16 is turned on by the control signal S14, and the field effect transistor Tr22 is turned on by the control signal S15. At this time, a logic low level signal is output from the output node NOUT to the load. Current flows from the output node NOUT side, that is, from the load to the ground node via the field effect transistor Tr22. The potentials of the nodes a, b, c, d, and e are all 0V. Strictly speaking, however, there is a case where the charge at the time of the previous logic high level output remains, and the potential of the node b may remain about several volts. However, in this case, there is no problem in circuit operation. In this case, a slight current flows from the node b to the ground node via the resistor R11, the node c, and the field effect transistor Tr14.

  Referring to FIGS. 29 and 35, next, at time t14 to time t15, control signal S11 is set to 20V. As a result, the potential Vb of the node b becomes about 20V. Further, since the field effect transistor Tr14 is in the on state, a slight current flows from the node b to the ground node via the resistor R11, the node c, and the field effect transistor Tr14. For example, when a 10 kΩ resistor is used as the resistor R11, a current of about 2 mA flows. At this time, by setting the current driving capability of the field effect transistor Tr14 higher than that of the resistor R11, the potential of the node c remains 0V, and the field effect transistor Tr13 is continuously in the OFF state.

  Referring to FIGS. 29 and 36, next, from time t15 to time t16, control signal S14 is set to 0V, and control signal S15 is set to 0V. At this time, the field effect transistor Tr16 is turned off by the control signal S14, and the field effect transistor Tr22 is turned off by the control signal S15. As a result, no current flows from the load to the ground node via the field effect transistor Tr22.

  On the other hand, since the current continues to flow from the load to the node a, the potential Va of the node a starts to rise even though the field effect transistor Tr21 is not yet turned on. Then, the node a pushes up the potential of the node b through the capacitor C1, and the potential Vb of the node b rises. That is, the potential Vb of the node b rises while maintaining a state higher than the potential Va of the node a. However, the difference between the potential Vb and the potential Va is less than 20V because the current leaks from the node b to the ground node through the field effect transistor Tr14 as described above. Here, since the potential Vc of the node c remains 0 V, the field effect transistor Tr13 is off.

  In addition, a current flows from the node a to the node e through the diode D12, the potential Ve of the node e increases, and becomes substantially equal to the potential Va of the node a. As a result, the field effect transistor Tr15 is turned on, a current flows from the node a to the node d via the field effect transistor Tr15, and the potential of the node d increases as the potential of the node a increases. In other words, the field effect transistor Tr15 is used when transitioning from a logic low level to a logic high level in addition to being used when transitioning from a logic high level to a logic low level.

  Referring to FIGS. 29 and 37, control signal S12 is then set to 0V from time t16 to time t17. At this time, the field effect transistor Tr14 is turned off by the control signal S12. Then, due to the current flowing from the node b to the node c, the potential Vc of the node c rises and the field effect transistor Tr13 is turned on. As a result, a current flows from the node b to the node d via the field effect transistor Tr13. In particular, it is preferable to set the time t16 so that the field effect transistor Tr13 is turned on after the potential Va of the node a reaches 400V due to the current from the load (the potential Va due to the current from the load). Is increased to 400V, the diode D16 is turned on and the current flows to the node of the power supply voltage VH, so that the potential Va does not increase beyond 400V). Eventually, since the node c is connected to the node b by the resistor R11, the field effect transistor Tr13 is in the ON state and approaches Vb = Vc = Vd. By charging the node b with 20V from time t14 to time t15, the potential of the node b becomes higher than Va = 400V, for example, about 410V. Since Vd = Vb> Va is maintained, the field effect transistor Tr21 is kept on, the node to which the power supply voltage VH is supplied and the node a are conducted, and the power supply voltage VH is supplied to the node a. That is, a logic high level signal is output from the output node NOUT to the load. The potential Ve of the node e is equal to the potential Va of the node a. Then, from time t18 to time t19, the control signal S11 is set to 0V.

  Next, an operation in which the output signal of the semiconductor device 102 transitions from a logic high level to a logic low level in a steady state will be described.

  Referring to FIGS. 29 and 38, since field effect transistor Tr21 is on from time t17 to time t20, potential Va at node a and potential Ve at node e are 400 V, and potential Vb at node b and The potential Vd of the node d is 410V, which is 10V higher than the nodes a and e, for example.

  Next, from time t20 to time t21, the control signal S12 is set to 20V. Thereby, the field effect transistor Tr14 is turned on, a current flows from the node b to the ground node via the field effect transistor Tr14, and the potential Vc of the node c becomes 0V. Then, the field effect transistor Tr13 is turned off. Further, the potential Vb of the node b gradually decreases.

  Next, with reference to FIGS. 29 and 39, control signal S13 is set to 20 V at time t21 to time t22. As a result, the potential Ve of the node e is pushed up by S13 via the capacitor C14 and rises. Thereby, since the field effect transistor Tr15 is turned on, the node d and the node a are brought into conduction, and the node d and the node a have substantially the same potential. Thereby, the field effect transistor Tr21 is turned off.

  Here, since the current continues to flow from the node a to the load, the potential Va of the node a starts to decrease even though the field effect transistor Tr22 is turned off. Since the field effect transistor Tr15 is turned on, the potential Vd of the node d is decreased due to the decrease of the potential Va of the node a, and the potential Vb of the node b is also decreased via the capacitor C11. Further, when the potential Va decreases and Ve−Va reaches the Zener breakdown voltage of the Zener diode D12, a current flows from the node e to the node a, and the potential Ve also decreases as the potential Va decreases. Thereby, since the potential difference between the node e and the node a can be suppressed to an appropriate potential difference, the gate insulating film of the field effect transistor Tr15 can be prevented from being broken. Eventually, as the current to the load continues to flow, the potential Va drops to the ground voltage (at this time, the diode D17 shown in FIG. 29 is turned on and a current path from the ground node to the load is generated, so the potential Va is Never fall below ground potential).

  Next, with reference to FIGS. 29 and 40, control signal S15 is set to 20 V from time t22 to time t23. This timing is preferably adjusted to be after the potential Va has dropped to the ground potential. Thereby, the field effect transistor Tr22 is turned on. As a result, a current flows from the node a to the ground node via the field effect transistor Tr22, and a logic low level signal is output from the output node NOUT to the load. Current flows from the output node NOUT side, that is, from the load to the ground node via the field effect transistor Tr22. At this time, since the field effect transistor Tr15 is on, the potential Vd of the node d also decreases. The potentials of the nodes a, c, d are 0V. In addition, the node a pulls down the potential of the node b through the capacitor C1, and the potential of the node b also decreases to several volts.

  Next, referring to FIG. 29 and FIG. 41, from time t24 to time t25, control signal S13 is set to 0V, and control signal S14 is set to 20V. Thereby, the node e becomes the ground potential by the turned on field effect transistor Tr16, and the field effect transistor Tr15 is turned off. That is, the potentials of the nodes a, c, d, and e are all 0V. In addition, the charge remaining at the node b is slowly decreased until the output signal of the semiconductor device 102 is changed to the next operation of transition from the logic low level to the logic high level.

  Note that in the semiconductor device according to the second embodiment of the present invention, when switching from the logic high level output to the logic low level output, the control signal S12 is set to 20 V (such as t8 to t9 in FIG. 29), and then again the logic high level. Until switching to the level output (t16 to t17 in FIG. 29), 20 V is continuously applied as the control signal S12, and the field effect transistor Tr14 is kept on. However, this timing control is not necessarily employed. For example, the field effect transistor Tr14 may be turned off by setting the control signal S12 to 0 V when the potential Vc of the node c becomes 0 V.

  In the semiconductor device 102, since both the field effect transistors Tr21 and Tr22 are controlled so as not to be turned on, it is possible to prevent a through current from flowing through the field effect transistors Tr21 and Tr22.

  In the configuration described in Patent Document 1, a power MOSFET is used as one corresponding to the field effect transistors Tr21 and Tr22, and a lateral high voltage MOS transistor called “LDMOS” as one corresponding to the field effect transistors Tr13 to Tr16. Is used. Since it is difficult to integrally form a power MOSFET and a high breakdown voltage MOSFET, the configuration described in Patent Document 1 increases the process cost.

  On the other hand, in the semiconductor device according to the second embodiment of the present invention, the high-side drive unit 63, the field effect transistor Tr21, and the field effect transistor Tr22 are included in the semiconductor chip 71. That is, by using a normally-off GaN field effect transistor in the high side drive unit 63, the field effect transistors Tr21 and Tr22 used as power semiconductor elements and the field effect transistors Tr13 to Tr16 used as high breakdown voltage transistors are the same. It can be formed on a substrate. Therefore, a driver for driving the power semiconductor element can be obtained at low cost.

  Further, in the semiconductor device 102, the output voltage range can be set to, for example, 0V to 400V while the input voltage range is set to, for example, 0V to 20V. As a result, the logic circuit for controlling the high-side driver can be manufactured by a general MOS process, and the manufacturing cost can be reduced. That is, in the semiconductor device according to the second embodiment of the present invention, the input signal processing unit 65 and the low-side drive unit 64 are included in the semiconductor chip 72. That is, the control logic which is a circuit other than the field effect transistors Tr21 and Tr22 and the high-side drive unit 63 is integrally formed using only the CMOS process. Thereby, the manufacturing cost can be further reduced.

  In the present embodiment, normally-off transistors are used as the field effect transistors Tr21 and Tr22. Therefore, even if the drive signals from the high-side drive unit and the low-side drive unit are stopped due to some trouble, the power supply voltage VH This is a preferable form from the viewpoint of fail-safe because a through path from the power supply for supplying power to the ground node does not occur.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
This embodiment relates to a semiconductor device in which a normally-off field effect transistor is added as compared with the semiconductor device according to the first embodiment. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

FIG. 42 is a diagram showing a configuration of a semiconductor device according to the third embodiment of the present invention.
Referring to FIG. 42, the semiconductor device 103 further includes a field effect transistor Tr11 as compared with the semiconductor device 101.

  The field effect transistor Tr11 is a normally-off type, for example, an insulated gate field effect transistor.

  The pair of cascode-connected field effect transistors Tr1 and Tr11 operates like a single transistor as a normally-off type first switching function unit.

  When the high side of the semiconductor device 103 is turned on by the drive signal from the high side drive unit 62 and the drive signal from the low side drive unit 64, the transistor constituted by the field effect transistors Tr1 and Tr11 is turned on. The transistor composed of Tr2 and Tr12 is turned off. At this time, the level of the output voltage VA becomes the power supply voltage VH.

  Further, when the low side of the semiconductor device 103 is turned on by these drive signals, the transistor constituted by the field effect transistors Tr1 and Tr11 is turned off, and the transistor constituted by the field effect transistors Tr2 and Tr12 is turned on. At this time, the level of the output voltage VA is zero volts.

  The high side driver 62, the field effect transistor Tr1, and the field effect transistor Tr2 are included in a semiconductor chip 71 manufactured by a GaN process. The field effect transistor Tr2 used for the low-side output can be formed on another semiconductor chip without being included in the semiconductor chip 71. However, forming the semiconductor device on the same semiconductor chip 71 as described above can reduce the number of components, thereby reducing the size of the semiconductor device.

  The input signal processing unit 65 and the low side driving unit 64 are included in a semiconductor chip 72 manufactured by a CMOS process. In a particularly preferred embodiment, field effect transistors Tr11 and Tr12 are also included in the semiconductor chip 72.

  FIG. 43 is a diagram showing a configuration of a high-side drive unit and an output stage of a semiconductor device according to the third embodiment of the present invention.

  Referring to FIG. 43, field effect transistor Tr1 has a drain coupled to a node supplied with power supply voltage VH of, for example, 400V, a source coupled to the drain of field effect transistor Tr11, and a second capacitor C1. And a gate coupled to the output node NOUT. Field effect transistor Tr11 has a drain coupled to the source of field effect transistor Tr1, a source coupled to the second end of capacitor C1 and output node NOUT, a source of field effect transistor Tr5, and a drain of field effect transistor Tr6. And a coupled gate. Diode D16 has a cathode coupled to the drain of field effect transistor Tr1 and an anode coupled to the source of field effect transistor Tr11. Field effect transistor Tr2 has a drain coupled to output node NOUT, a source, and a gate coupled to a ground node. Field effect transistor Tr12 has a drain coupled to the source of field effect transistor Tr2, a source coupled to the ground node, and a gate for receiving control signal S1. Diode D17 has a cathode coupled to the drain of field effect transistor Tr2 and an anode coupled to the source of field effect transistor Tr12.

  Further, the high-side drive unit 62 includes a node a that is a coupling node of the second end of the capacitor C1, the source of the field effect transistor Tr11 and the drain of the field effect transistor Tr2, the cathode of the diode D2, the first end of the resistor R1, A node b which is a coupling node of the first end of the resistor R2, the drain of the field effect transistor Tr5 and the first end of the capacitor C1, the second end of the resistor R2, the drain of the field effect transistor Tr4 and the gate of the field effect transistor Tr5. The node c is a coupling node, and the node d is a coupling node of the source of the field effect transistor Tr5, the drain of the field effect transistor Tr6, and the gate of the field effect transistor Tr11.

  Since various operations of semiconductor device 103 are the same as those of semiconductor device 101, detailed description thereof will not be repeated here.

  In the semiconductor device 103, since the polarity of the threshold voltage of the field effect transistor Tr11 is positive, the use of a negative voltage can be reduced. Thereby, the configuration of the input signal processing unit 65 can be simplified. Specifically, in the semiconductor device 101, for example, the fixed voltage VN1 is −10V, the fixed voltage VN2 is −5V, the voltage level of the control signal S2 is 0V and −10V, and the voltage level of the control signal S3 is −10V. And −15V, the voltage level of the control signal S4 was −5V and −10V, and the voltage level of the control signal S5 was 15V and −5V.

  On the other hand, in the semiconductor device 103, as shown in FIG. 43, for example, the fixed voltage VN1 is -5V, the fixed voltage VN2 is 0V, the voltage level of the control signal S2 is 0V and -5V, and the control signal S3 Can be -5V and -10V, the voltage level of the control signal S4 can be 0V and -5V, and the voltage level of the control signal S5 can be 15V and 0V. That is, since the absolute value of each negative voltage can be made lower than that of the semiconductor device 101, the circuit can be further simplified.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here. Therefore, in the semiconductor device according to the third embodiment of the present invention, the field effect transistors Tr1 and Tr2 used as power semiconductor elements and the high breakdown voltage transistor are used as in the semiconductor device according to the first embodiment. Since the field effect transistors Tr3 to Tr6 can be formed on the same substrate, a driver for driving the power semiconductor element can be obtained at low cost.

  When field effect transistors Tr11 and Tr12 have built-in diodes, the anodes of diodes D16 and D17 may be connected to the drains of field effect transistors Tr11 and Tr12, respectively.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  62, 63 High-side drive unit, 64 Low-side drive unit, 65 Input signal processing unit, 91 Silicon substrate, 92 Buffer layer, 93 GaN layer, 94 AlGaN layer, 95 SiN layer, 101, 102, 103 Semiconductor device, 120 coil, 130 diode section, 140 capacitor, 150 inverter section, 151 to 156 power semiconductor element, 160 motor, 165 AC voltage supply section, 170 compressor, 180 base driver, 190 voltage detector, 200 microprocessor, 201 compressor section, 202 refrigerator compartment , 203 Freezer room, 204 Vegetable room, 301 Electronic equipment, 401 Power supply, Tr1, Tr2, Tr3 to Tr6, Tr11, Tr12, Tr13 to Tr16, Tr21, Tr22 Field effect transistors, D2, D11 D12, D16, D17 diodes, R1, R2, R11 resistor, C1, C11, C14 capacitor, ELG gate electrode, ELS source electrode, ELD drain electrode.

Claims (5)

An input signal processing unit for outputting a switching control signal based on the input signal;
A high-side drive unit for outputting a drive signal based on the switching control signal received from the input signal processing unit;
A low-side drive unit for outputting a drive signal based on the switching control signal received from the input signal processing unit;
A first switching function having a first conduction electrode to which a first power supply voltage is to be supplied, a second conduction electrode coupled to an output node, and a control electrode that receives the drive signal from the high-side drive unit And
A first conduction electrode coupled to the output node; a second conduction electrode to which a second power supply voltage lower than the first power supply voltage is to be supplied; and a control for receiving the drive signal from the low-side drive unit A second switching function unit having an electrode,
The high-side drive unit includes a normally-on type field effect transistor, and outputs a drive signal obtained by shifting a reference voltage of the switching control signal to the potential of the output node,
The first switching function unit includes a normally-on type first field effect transistor,
The second switching function unit includes a normally-on type second field effect transistor,
The high side driver and the first field effect transistor are included in a first semiconductor chip ,
The high side drive unit is
A first diode having an anode for receiving a first switching control signal from the input signal processing unit; and a cathode;
A first resistor having a first end coupled to the cathode of the first diode and a second end;
A node having a drain coupled to the second end of the first resistor, a source coupled to a node to which a predetermined voltage is supplied, and a gate for receiving a second switching control signal from the input signal processing unit. A fourth field-effect transistor of the marion type,
A second resistor having a first end coupled to the cathode of the first diode and a second end;
A node having a drain coupled to the second end of the second resistor, a source coupled to a node to which a predetermined voltage is supplied, and a gate receiving a third switching control signal from the input signal processing unit. A marion-on fifth field effect transistor;
A drain coupled to the cathode of the first diode; a source coupled to the gate of the first field effect transistor; a second end of the second resistor; and a drain of the fifth field effect transistor. A normally-on sixth field effect transistor having a coupled gate;
A semiconductor device including a capacitor having a first end coupled to the cathode of the first diode and a second end coupled to the output node . The first field effect transistor includes a first conduction electrode to which the first power supply voltage is to be supplied, a second conduction electrode coupled to the output node, and the drive signal from the high side driver. The semiconductor device according to claim 1 , wherein the semiconductor device is a normally-on field effect transistor having a control electrode. The second switching function unit includes:
A normally-on type second field effect transistor having a first conduction electrode coupled to the output node, a second conduction electrode, and a control electrode to which the second power supply voltage is to be supplied;
A first conduction electrode coupled to a second conduction electrode of the second field-effect transistor; a second conduction electrode to which the second power supply voltage is to be supplied; and the drive signal from the low-side drive unit. and a third field effect transistor of the normally-off type having a control electrode, the semiconductor device according to claim 1 or 2. The high side driving unit further includes:
A node having a drain coupled to the gate of the first field effect transistor, a source coupled to a node to which a predetermined voltage is supplied, and a gate receiving a fourth switching control signal from the input signal processing unit. 4. The semiconductor device according to claim 1, comprising a seventh field effect transistor of a marion type. An input signal processing unit for outputting a switching control signal based on the input signal;
A high-side drive unit for outputting a drive signal based on the switching control signal received from the input signal processing unit;
A low-side drive unit for outputting a drive signal based on the switching control signal received from the input signal processing unit;
A normally-off type having a first conduction electrode to which a first power supply voltage is to be supplied, a second conduction electrode coupled to an output node, and a control electrode that receives the drive signal from the high-side drive unit. A first field effect transistor;
A first conduction electrode coupled to the output node; a second conduction electrode to which a second power supply voltage lower than the first power supply voltage is to be supplied; and a control for receiving the drive signal from the low-side drive unit A normally-off second field effect transistor having an electrode,
The high side driving unit includes a normally-off type field effect transistor, and outputs a driving signal obtained by shifting a reference voltage of the switching control signal to the potential of the output node,
The high side driver and the first field effect transistor are included in a first semiconductor chip ,
The high side drive unit is
A first diode having an anode for receiving a first switching control signal from the input signal processing unit; and a cathode;
A first resistor having a first end coupled to the cathode of the first diode and a second end;
A node having a drain coupled to the second end of the first resistor, a source coupled to a node to which a fixed voltage is supplied, and a gate for receiving a second switching control signal from the input signal processor. A third field-off transistor of the marry-off type,
A drain coupled to the cathode of the first diode; a source coupled to the gate of the first field effect transistor; a second end of the first resistor; and a drain of the third field effect transistor. A normally-off fourth field effect transistor having a coupled gate;
A normally-off fifth field effect transistor having a drain coupled to the gate of the first field effect transistor, a source coupled to the output node, and a gate;
A first capacitor having a first end coupled to the cathode of the first diode and a second end coupled to the output node;
A second capacitor having a first end for receiving a third switching control signal from the input signal processing unit and a second end coupled to the gate of the fifth field effect transistor;
A second diode having a cathode coupled to the gate of the fifth field effect transistor and an anode coupled to the source of the fifth field effect transistor;
A node having a drain coupled to the gate of the fifth field effect transistor, a source coupled to a node to which a fixed voltage is supplied, and a gate receiving a fourth switching control signal from the input signal processing unit. A semiconductor device including a sixth field-effect transistor of a marily-off type .

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