JP5318051B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  Field effect transistors (FET) using compound semiconductors such as GaN (Gallium Nitride) have excellent high-frequency characteristics and are widely put into practical use as semiconductor devices that operate in the microwave / millimeter / submillimeter wave bands. Has been.

  A typical planar pattern configuration of a conventional semiconductor device includes, for example, a substrate, a gate electrode, a source electrode and a drain electrode, which are arranged on the substrate, each having a plurality of fingers, and are arranged on the substrate. A gate terminal electrode formed by bundling a plurality of fingers for each drain electrode, a source terminal electrode and a drain terminal electrode, and a VIA hole formed for each source terminal electrode.

  A general semiconductor device in which a VIA hole is formed and a manufacturing method thereof have already been disclosed (for example, refer to Patent Document 1).

  On the other hand, FETs using compound semiconductors such as GaAs are also widely used as semiconductor devices having excellent high frequency characteristics and operating in the microwave band. In a conventional FET used in the microwave band, a source electrode, a drain electrode, and a gate electrode are arranged on a semi-insulating semiconductor substrate. In order to protect each of these electrodes and the semiconductor surface, an insulating film is deposited. In general, in order to extract the capabilities of these FETs, FETs and synthetic circuits are combined and incorporated into a package. Each gate electrode and drain electrode of the FET and the synthetic circuit element are bonded and connected with a wire using a gold wire.

Japanese Patent Application Laid-Open No. 08-78437

  In the conventional technology, for example, when the metal forming the gate pad electrode is aluminum (Al) or the like, the adhesion between Al and the GaAs substrate is not good, and therefore the gate pad electrode peels off when the bonding strength is increased. There was a point.

  For this reason, an ohmic metal electrode may be laid under the gate pad electrode, and the ohmic metal electrode and GaAs may be reacted to improve adhesion.

  However, if a negative potential is applied to the gate electrode side and a positive potential is applied to the source electrode of the back surface metal electrode between the reacted ohmic metal electrode and the FET back surface metal electrode, excess current flows between the gate electrode and the back surface metal electrode. As a result, the performance of the FET is lowered and the reliability is lowered.

The semiconductor device according to the present embodiment includes a substrate, and a gate electrode, a source electrode, a drain electrode, and an ohmic electrode layer that are disposed on the first surface of the substrate and each have a plurality of fingers. In addition, a gate terminal electrode / source terminal electrode and a drain terminal electrode formed by bundling a plurality of fingers for each of the gate electrode / source electrode and the drain electrode are provided. In addition, a gate pad electrode disposed on the ohmic electrode layer and connected to the gate terminal electrode is provided. In addition, the semiconductor device includes a first conductive semiconductor layer formed in the substrate so as to cover a reaction layer formed at the interface between the ohmic electrode layer and the substrate. In addition, a second conductivity type semiconductor layer opposite to the first conductivity type formed in the substrate is provided so as to cover the first conductivity type semiconductor layer. A back surface metal electrode connected to a source electrode is provided on a second surface opposite to the first surface of the substrate, and the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are substrates immediately below the ohmic electrode layer. it is formed within, and the first conductivity type p-type, the second conductivity type is n-type.

The typical plane pattern block diagram of the semiconductor device which concerns on embodiment. FIG. 2 is a schematic cross-sectional structure diagram taken along line II in FIG. 1. The typical cross-section figure which follows the II line | wire of the semiconductor device which concerns on a comparative example. FIG. 2 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 1.

  A schematic planar pattern configuration of the semiconductor device 1 according to the embodiment is expressed as shown in FIG. A schematic cross-sectional structure taken along line II in FIG. 1 is expressed as shown in FIG.

  As shown in FIGS. 1 to 2, the semiconductor device 1 according to the embodiment includes a semi-insulating GaAs substrate 10 and a gate disposed on the first surface of the semi-insulating GaAs substrate 10 and having a plurality of fingers. The electrode 24, the source electrode 20 and the drain electrode 22, the ohmic electrode layer 18, and the semi-insulating GaAs substrate 10 are arranged on the semi-insulating GaAs substrate 10, and a plurality of fingers are bundled for each of the gate electrode 24, the source electrode 20 and the drain electrode 22. The formed gate terminal electrodes GE1 to GE3, the source terminal electrodes SE1 to SE4, the drain terminal electrode DE, and the gate pad disposed on the ohmic electrode layer 18 and connecting the ohmic electrode layer 18 and the gate terminal electrodes GE1 to GE3. Reaction layer 1 formed at the interface of electrode (GP) 30, ohmic electrode layer 18 and semi-insulating GaAs substrate 10 Semi-insulating so as to cover the first conductive semiconductor layer (p-type layer) 16 formed in the semi-insulating GaAs substrate 10 so as to cover and the first conductive semiconductor layer (p-type layer) 16. And a second conductivity type semiconductor layer (n-type layer) 14 opposite to the first conductivity type formed in the conductive GaAs substrate 10.

  Here, the reaction layer 12 is a layer in which the semi-insulating GaAs substrate 10 and the ohmic electrode layer 18 react in an alloying process. For example, when the ohmic electrode layer 18 is formed of, for example, Pt / AuGe, alloy processing is performed by heat treatment at several hundred degrees C. Therefore, GaAs and AuGe react to form an ohmic alloy layer. This ohmic alloy layer is the reaction layer 12.

  The first conductive semiconductor layer (p-type layer) 16 and the second conductive semiconductor layer (n-type layer) 14 form a pn junction.

  The first conductive semiconductor layer (p-type layer) 16 and the second conductive semiconductor layer (n-type layer) 14 are formed in the semi-insulating GaAs substrate 10 immediately below the ohmic electrode layer 18.

  The gate terminal electrodes GE1 to GE3, the source terminal electrodes SE1 to SE4, and the drain terminal electrode DE are disposed on the semi-insulating GaAs substrate 10 in the direction in which the gate electrode 24, the source electrode 20, and the drain electrode 22 extend. Also good.

  On the second surface facing the first surface of the semi-insulating GaAs substrate 10, a back metal electrode 15 is provided.

  In the semiconductor device 1 according to the embodiment, as shown in FIG. 2, an ohmic electrode layer 18 made of, for example, Pt / AuGe is formed on the semi-insulating GaAs substrate 10 below the gate pad electrode 30. Has been. By disposing the ohmic electrode layer 18 under the gate pad electrode 30, the bonding strength can be increased.

  The gate pad electrode 30 is made of, for example, Ti / Pt / Au.

  Further, an insulating layer 34 is formed on the first surface of the semi-insulating GaAs substrate 10, and the gate electrode 24, the source electrode 20, the drain electrode 22, the gate terminal electrodes GE1 to GE3, the source on the first surface. The terminal electrodes SE1 to SE4, the drain terminal electrode DE, and the ohmic electrode layer 18 are insulated from each other. As the insulating layer 34, for example, a silicon nitride film, a silicon oxide film, or the like can be applied.

  A back metal electrode 15 made of Au / Ti is disposed on the back side of the semiconductor device 1 according to the embodiment for grounding. The back surface metal electrode 15 includes, for example, a barrier metal layer and a ground metal layer disposed on the barrier metal layer. The barrier metal layer is made of, for example, a Ti layer or a Ti / Pt layer, and the ground metal layer is made of, for example, an Au layer.

  Therefore, the back surface metal electrode 15 may have any one of an Au layer, a Ti / Au layer, a Ti / W / Au layer, and a Ti / Pt / Au layer. The thickness of the back metal electrode 15 is, for example, about 5 μm to 30 μm.

  The source electrode 20 and the drain electrode 22 are made of, for example, Pt / AuGe.

  The gate electrode 24 can be formed of, for example, Ti / Au.

  In the semiconductor device according to the embodiment, the pattern lengths in the longitudinal direction of the gate electrode 24, the source electrode 20, and the drain electrode 22 are set shorter as the operating frequency becomes higher, that is, microwave / millimeter wave / submillimeter wave. . For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  The width of the source electrode 20 is about 10 μm, for example, and the width of the source terminal electrodes SE1 to SE4 is about 100 μm, for example. The width of the gate terminal electrodes GE1 to GE3 is, for example, about 5 μm.

  The width W1 of the ohmic electrode layer 18 is, for example, about 100 μm, and the length W2 is, for example, about several hundred μm to several 1 mm.

  A first conductive semiconductor layer (p-type layer) 16 is formed immediately below the ohmic electrode layer 18 by an ion implantation technique or the like, and further covers the first conductive semiconductor layer (p-type layer) 16. A second conductivity type semiconductor layer (n-type layer) 14 opposite to the first conductivity type is formed.

  Here, as ion species for forming the first conductive semiconductor layer (p-type layer) 16, for example, carbon (C), beryllium (Be), or the like can be applied. As an ion species for forming the second conductivity type semiconductor layer (n-type layer) 14, for example, silicon (Si) or the like can be applied.

  As described above, by configuring the pn junction, a reverse bias voltage between the gate and the source of the semiconductor device 1 according to the embodiment, for example, a negative potential is applied to the gate pad electrode 30 and a positive potential is applied to the source terminal electrode SE. In the applied state, an excessive current flows between the gate electrode and the back electrode, which has conventionally occurred, due to a potential barrier generated between the ohmic electrode layer 18 and the first conductive semiconductor layer (p-type layer) 16. Can be prevented. Thereby, it is possible to improve reliability while maintaining the performance of the semiconductor device 1 according to the embodiment at high performance.

  As described above, according to the semiconductor device according to the embodiment, in the semi-insulating GaAs substrate 10 between the gate pad electrode 30 and the back surface metal electrode 15, the ohmic electrode layer 18 and the semi-insulating GaAs substrate 10 are separated. A first conductivity type semiconductor layer (p-type layer) 16 is formed so as to cover the reaction layer 12 formed therebetween, and a first conductivity type is further formed so as to cover the first conductivity type semiconductor layer (p-type layer) 16. By forming the second conductivity type semiconductor layer (n-type layer) 14 of the opposite conductivity type, a metal (30, 18) -p (16) -n (14) structure is formed, and the first conductivity type semiconductor layer and The pn junction barrier barrier is formed by the second conductivity type semiconductor layer. For this reason, it is possible to prevent a leak current from flowing between the gate pad electrode 30 and the back surface metal electrode 15, to improve the bonding strength, and to achieve high performance and high reliability.

  Here, the depth X1 of the reaction layer 12 is, for example, about 0.1 μm, the junction depth of the first conductive semiconductor layer (p-type layer) 16 is, for example, about 0.2 μm, and the second The junction depth of the conductive semiconductor layer (n-type layer) 14 is, for example, about 0.3 μm.

(Comparative example)
A schematic cross-sectional structure taken along line II of the semiconductor device according to the comparative example is expressed as shown in FIG. In the semiconductor device according to the comparative example, in the semi-insulating GaAs substrate 10 between the gate pad electrode 30 and the back surface metal electrode 15, the reaction layer 12 formed between the ohmic electrode layer 18 and the semi-insulating GaAs substrate 10. The first conductive semiconductor layer (p-type layer) 16 and the second conductive semiconductor layer (n-type layer) 14 covering the first conductive semiconductor layer (p-type layer) 16 are not provided. For this reason, only a low Schottky barrier between the metal (M) and the semiconductor substrate is formed as compared with the pn junction. For this reason, a reverse bias leakage current flows between the metal (30, 18) -substrate (10) -back metal electrode 15, and it is difficult to achieve high reliability.

  As shown in FIG. 4, a schematic cross-sectional configuration taken along line II-II in FIG. 1 includes a semi-insulating GaAs substrate 10, a source region 26 and a drain region 28 arranged on the semi-insulating GaAs substrate 10, A source electrode 20 disposed on the source region 26; a gate electrode 24 disposed on the semi-insulating GaAs substrate 10; and a drain electrode 22 disposed on the drain region 28. A Schottky contact is formed at the interface between the semi-insulating GaAs substrate 10 and the gate electrode 24. Further, a current conducting channel is formed on the surface of the semi-insulating GaAs substrate 10 between the source region 26 and the drain region 28 by using an ion implantation technique or the like. In the configuration example shown in FIG. 4, a metal-semiconductor field effect transistor (MESFET) is shown. The back metal electrode 15 is not shown in FIG.

  According to the semiconductor device of the embodiment, since the pn junction barrier barrier is formed by the first conductive semiconductor layer and the second conductive semiconductor layer opposite to the first conductive type, the gate pad electrode and Leakage current between backside metal electrodes can be suppressed, bonding strength can be improved, and high performance and high reliability can be achieved.

[Other embodiments]
Although several embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Semi-insulating GaAs substrate 12 ... Reaction layer 14 ... 2nd conductivity type semiconductor layer (n-type layer)
15 ... back metal electrode 16 ... first conductivity type semiconductor layer (p-type layer)
18 ... Ohmic electrode layer 20 ... Source electrode 22 ... Drain electrode 24 ... Gate electrode 26 ... Source region 28 ... Drain region 30 ... Gate pad electrode 32, GE1, GE2, GE3 ... Gate terminal electrode 34 ... Insulating layers SE1, SE2, SE3, SE4, SE5 ... Source terminal electrode DE ... Drain terminal electrode

Claims (3)

A substrate,
A gate electrode, a source electrode and a drain electrode, and an ohmic electrode layer, each disposed on the first surface of the substrate, each having a plurality of fingers;
A gate terminal electrode formed by bundling a plurality of fingers for each of the gate electrode, the source electrode and the drain electrode, a source terminal electrode and a drain terminal electrode;
A gate pad electrode disposed on the ohmic electrode layer and connected to the gate terminal electrode;
A first conductivity type semiconductor layer formed in the substrate so as to cover a reaction layer formed at an interface between the ohmic electrode layer and the substrate;
A second conductivity type semiconductor layer opposite to the first conductivity type formed in the substrate so as to cover the first conductivity type semiconductor layer ;
On the second surface facing the first surface of the substrate, a back surface metal electrode connected to the source electrode is provided,
The first conductive semiconductor layer and the second conductive semiconductor layer are formed in the substrate immediately below the ohmic electrode layer ,
The first conductivity type is p-type, and the second conductivity type is n-type .   The semiconductor device according to claim 1, wherein the first conductive semiconductor layer and the second conductive semiconductor layer form a pn junction.   The gate terminal electrode, the source terminal electrode, and the drain terminal electrode are disposed on the substrate in a direction in which the gate electrode, the source electrode, and the drain electrode extend. Semiconductor device.

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