JP5314943B2 - Semiconductor device and data reading method - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor memory, and more particularly to a semiconductor device including a mechanism for reading data from the semiconductor memory.

  Some semiconductor memories perform current sensing to read data written in memory cells. For this purpose, the semiconductor memory includes a cascode circuit that applies a voltage to a bit line connected to the memory cell and performs current-voltage conversion of a current flowing through the bit line, and a sense amplifier.

  In the case of a NOR type nonvolatile memory which is a kind of semiconductor memory, a predetermined voltage is applied to the drain terminal of the memory cell by the bit line, the source terminal is grounded, and a high level voltage is applied to the gate terminal by the word line. Then, a current flows through the bit line according to the data written in the memory cell. The current flowing through the bit line is subjected to current-voltage conversion by the cascode circuit and then compared with a predetermined comparison voltage by the sense amplifier. The value (“0” or “1”) of data written in the memory cell is detected depending on whether the voltage is higher or lower than the comparison voltage.

  The cascode circuit includes a sense voltage application circuit that applies a voltage to the bit line and a current-voltage conversion circuit that converts a current flowing through the bit line into a voltage. The sense voltage application circuit includes an operational amplifier and a transistor. A power supply voltage is applied to the source terminal of the transistor, and the drain terminal is connected to the bit line. The output terminal of the operational amplifier is connected to the gate terminal. In the operational amplifier, the positive input terminal is connected to the bit line, and the same voltage as the reference voltage necessary for reading is input to the negative input terminal. With such a configuration, the reference voltage is applied to the bit line.

  Since the current ratio between the transistor and the memory cell in the sense voltage application circuit is reflected, the bit line voltage is slightly lower than the reference voltage. Conventionally, since no current flows through the bit line until a high level voltage is applied to the gate terminal of the memory cell by the word line, the bit line is charged to the reference voltage by the transistor of the sense voltage application circuit.

When data is read from one memory cell, bit lines not related to the memory cell are in a floating state. The floating bit line is interfered by coupling with the bit line related to the memory cell. At the time of reading data, the floating bit line interferes with other bit lines during detection by the sense amplifier. As a result, noise is generated in the bit line. Since the sense amplifier may malfunction in the sensing operation due to noise, it is necessary to wait until the noise disappears. For this reason, the read operation cannot be performed at high speed.
In order to perform the reading speed at high speed, inventions such as Patent Documents 1 and 2 have been proposed.

Patent Document 1 describes a semiconductor memory including a switch that divides a bit line into a memory cell side and a sense amplifier side. At the time of reading, a lower voltage is applied to the bit line on the memory cell side than on the bit line on the sense amplifier side. When the switch is closed and the bit lines on the memory cell side and the sense amplifier side are connected, discharging is performed at high speed. This speeds up the reading of data from the memory cell.
Patent Document 2 describes that a second current is supplied in advance to a bit line before reading, and a first current larger than the second current is supplied during reading. As a result, a high-speed read operation is realized.
JP-A-7-141890 JP 2002-269991 A

Patent Documents 1 and 2 do not consider the noise generated in the bit lines as described above. Therefore, Patent Documents 1 and 2 do not solve the above problem.
In addition, the transistor of the sense voltage application circuit may generate a so-called overshoot due to a delay in the response of the feedback voltage from the operational amplifier, for example, and may apply a voltage higher than the reference voltage to the bit line. In this case, the voltage applied to the bit line does not return to the reference voltage until a high level voltage is applied to the gate terminal of the memory cell. In particular, when the operational amplifier is arranged outside the memory cell array, the distance to the bit line having a long wiring length and a large time constant is increased, and the overshoot is increased. Such a phenomenon also becomes a factor that hinders the speeding up of the read operation.

  In view of such a problem, it is a main object of the present invention to provide a sensing technique capable of reading data from a memory cell at high speed regardless of noise generated in a bit line.

  A semiconductor device of the present invention that solves the above problems includes a memory cell in which at least binary data is recorded, a bit line connected to the memory cell, a reference voltage necessary for reading the data, and the A sense voltage application circuit that applies any one of a first voltage lower than a reference voltage, a current-voltage conversion circuit that converts a current flowing through the bit line into a voltage during reading, and a current-voltage conversion circuit A sense circuit that compares the voltage with a predetermined comparison voltage to determine the value of the data recorded in the memory cell. The sense voltage application circuit applies the first voltage to the bit line prior to the comparison by the sense circuit, and applies the reference voltage to the bit line instead of the first voltage during the comparison.

In the semiconductor device of the present invention, a first voltage lower than a reference voltage necessary for reading is applied to the bit line prior to reading. Since the first voltage is applied in advance, there is less interference from the floating bit line when the reference voltage is used. Therefore, noise generated on the bit line to which the memory cell to be read is connected is suppressed. Further, since overshoot is suppressed, a voltage higher than the reference voltage is not applied to the bit line. As a result, the sensing operation can be performed without waiting for the noise to settle, so that the read operation can be speeded up.
Note that data is read from the memory cell by current sensing regardless of whether it is nonvolatile, volatile, or rewritable.
In addition, the sense voltage application circuit is disposed, for example, outside a memory cell array in which the memory cells are configured in an array.

The semiconductor device of the present invention further includes, for example, a control unit that generates a first control signal for causing the sense voltage application circuit to output the first voltage and a second control signal for outputting the reference voltage. May be. In this case, the sense voltage application circuit includes, for example, a voltage generation unit that outputs the first voltage when the first control signal is input and outputs the reference voltage when the second control signal is input. Have.
The voltage generation unit, for example, inputs a constant voltage source capable of outputting the same voltage as the input voltage, the first voltage to the constant voltage source by the first control signal, and the second control signal The switch may have a switch that inputs a reference voltage to the constant voltage source.
The voltage generation unit may include, for example, a first constant voltage source that can output the first voltage and a second constant voltage source that can output the reference voltage. In such a configuration, for example, the first constant voltage source is activated by the first control signal, and the second constant voltage source is activated by the second control signal. A voltage is applied to the bit line. The first constant voltage source capable of outputting the first voltage may be provided outside the voltage generator. In such a configuration, for example, when the first control signal is input, the voltage generation unit acquires the first voltage from the first constant voltage source, outputs the first voltage, and outputs the second control signal. Is input, the reference voltage is output from the second constant voltage source.

The data reading method of the present invention is a method executed by a device including a memory cell in which data that can take at least two values is recorded, and a reading circuit that reads the data from the memory cell. The reading circuit applies a first voltage lower than a reference voltage required for reading to the bit line connected to the memory cell prior to reading, and the first voltage is applied to the bit line during reading. Instead of applying the reference voltage, generating a voltage using the current flowing through the bit line when the reference voltage is applied, and the voltage generated from the current flowing through the bit line Comparing with a predetermined comparison voltage to determine a value of data recorded in the memory cell.
The first voltage is applied to the first voltage, for example, when the device is activated or during a predetermined intermittent operation after the device is activated.
For example, the reference voltage is applied when a read command that is an external access command of the device is input. In this case, the first voltage is applied in conjunction with the read command when an active command that is an external access command of the device is input.

According to the present invention as described above, since the first voltage is applied to the bit line prior to reading, the influence of noise from the floating bit line can be suppressed even if the reference voltage is applied to the bit line during reading. it can. Therefore, since the sensing operation can be performed without waiting for the noise to settle, the reading operation can be speeded up. Furthermore, since overshoot can be suppressed, the read operation can be speeded up. Further, by suppressing overshoot, the drain disturb phenomenon due to the voltage applied to the bit line of the nonvolatile memory cell can be suppressed, and the change (deterioration) of data written in the memory cell can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the semiconductor device of the present invention.
The semiconductor memory device 1 includes a memory cell array 10 having memory cells 11 arranged in an array, and a read circuit 20 for reading data from the memory cells 11. Read circuit 20 is arranged outside memory cell array 10. The memory cell array 10 and the read circuit 20 are connected by a data bus B. Data read by the read circuit 20 is output to an external device (not shown) outside the semiconductor memory device 1. Although the semiconductor memory device 1 includes a peripheral circuit such as a writing circuit for writing data to the memory cell 11, it is not directly related to the present invention, and its illustration and description are omitted.

In this embodiment, the memory cell array 10 is a NOR nonvolatile memory, and memory cells are connected in a ladder manner between the bit lines, and the memory is accessed by a virtual ground method. In each memory cell 11, memory cells 11 in which data that can take at least two values “1” and “0” can be written and read are arranged vertically and horizontally. The gate terminals of the memory cells 11 arranged in the row direction are connected by a common word line WL, and the source terminals and drain terminals of the memory cells 11 arranged in the column direction are connected by a common bit line BL. Data is written to and read from the memory cell 11 by voltages applied to the word line WL and the bit line BL. A voltage is applied to the word line WL from a peripheral circuit such as a row decoder (not shown). A voltage is applied to the bit line BL from the read circuit 20 via the data bus B.
For example, when data is read from the memory cell 11, a high level voltage is applied to the word line WL connected to the memory cell 11, and a high level voltage is applied to one of the two bit lines connected to the memory cell 11. Voltage and the ground voltage is applied to the other.

  A plurality of bit lines BL are provided, but at the time of reading and writing, the bit line BL connected to the target memory cell 11 is connected to the data bus B, and the other bit lines BL are in a floating state. Therefore, a switch element (not shown) is provided between the bit line BL and the data bus B.

  The memory cell array 10 is not limited to a NOR type nonvolatile memory, and may be volatile, nonvolatile, or rewritable as long as it is a semiconductor memory from which data is read by current sensing.

  The read circuit 20 includes a reference voltage generation circuit 21, a cascode circuit 22, a control circuit 23, and a sense amplifier 24.

  The reference voltage generation circuit 21 generates a voltage applied to the bit line BL via the data bus B. The reference voltage generation circuit 21 generates a reference voltage Vref necessary for reading data from the memory cell 11 and a first voltage V1 lower than the reference voltage Vref. These voltages are sent to the cascode circuit 22. The reference voltage generation circuit 21 also generates a comparison voltage VC used by the sense amplifier 24.

The cascode circuit 22 includes a sense voltage application circuit for applying the reference voltage Vref and the first voltage V1 generated by the reference voltage generation circuit 21 to the bit line BL via the data bus B. The cascode circuit 22 is arranged outside the memory cell array 10 and is far away from the bit line BL to which the reference voltage Vref is applied and which has a very long parasitic time constant. The cascode circuit 22 applies the first voltage V1 to the bit line BL prior to reading, and applies the reference voltage Vref instead of the first voltage V1 during reading.
The cascode circuit 22 includes a current-voltage conversion circuit that converts a current flowing through the bit line BL into a voltage when data is read from the memory cell 11.

  The control circuit 23 inputs a first control signal C1 for outputting the first voltage V1 and a second control signal C2 for outputting the reference voltage Vref to the cascode circuit 22.

  The sense amplifier 24 compares the voltage converted from the current flowing through the bit line BL in the current-voltage conversion circuit of the cascode circuit 22 with the comparison voltage VC sent from the reference voltage generation circuit 21, and is written in the memory cell 11. Determine the value of the data. The determination result is sent to the external device as data read from the memory cell 11.

FIG. 2 is an exemplary diagram of the first control signal C1 and the second control signal C2. As can be seen from FIG. 2, the control circuit 23 inputs the first control signal C1 to the cascode circuit 22 before the sensing period by the sense amplifier 24 starts, and inputs the second control signal C2 to the cascode circuit 22 only during the sensing period. Since the first and second control signals C1 and C2 are input at such timing, the cascode circuit 22 applies the first voltage V1 to the bit line BL in response to the active command prior to reading, and uses it as a read command. At the time of corresponding reading, the reference voltage Vref can be applied instead of the first voltage V1. Sensing is performed when the word line WL is at a high level. The first control signal C1 depends on, for example, an active command. The second control signal C2 depends on, for example, a read command.
Note that the first control signal C1 (the first pulse waveform in FIG. 2) operates in addition to the sensing period. For example, an intermittent pulse operation for a power-on reset period of the semiconductor device or a predetermined period thereafter may be performed.
However, in this case, the first control signal C1 and the second control signal C2 are not linked.
During the power-on reset period, the cascode circuit 22 sets the bit line to the first voltage V1 even when there is an external request to read data from the memory cell 11. The intermittent pulse operation is performed according to the access frequency to the memory cell 11.
Even when the bit line BL is set to the first voltage V1 by the intermittent pulse operation and no request for reading data from the memory cell 11 is made for a certain period of time (that is, when the idle period is long), the bit line It is possible to prevent the voltage of the bit line BL from lowering than the first voltage V1 due to a junction leak or the like due to the drain of the memory cell 11 connected to BL.

  After the sensing period, the cascode circuit 22 resets the bit line to the first voltage V1. For example, the recharging of the discharged bit line BL to the first voltage V1 according to the data stored in the memory cell 11 and the equalization from the reference voltage Vref of the bit line BL that has not been discharged to the first voltage V1 are performed. . As a result, when data is continuously read from the memory cell 11, normal reading from the memory cell 11 in the second and subsequent sensing periods can be realized. The resetting in this case corresponds to, for example, an address transition detection signal (ATD) automatically generated inside the semiconductor memory device 1. In addition to this, the resetting may correspond to a precharge command from the outside of the semiconductor memory device 1 or may correspond to an auto precharge signal automatically generated inside the semiconductor memory device 1. Here, the active command, read command, and precharge command are standard synchronous memory access methods such as SDRAM.

FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of the cascode circuit 22.
As described above, the cascode circuit 22 includes a current-voltage conversion circuit and a sense voltage application circuit. In FIG. 3, current-voltage conversion circuits are configured by P-channel transistors 221 and 223, a resistor 222, and an operational amplifier 224. Further, the transistors 223, 225, 226 and the operational amplifier 224 constitute a sense voltage application circuit.

  The current-voltage conversion circuit has a current mirror configuration, and the same current that flows through the transistor 223 flows through the transistor 221 as well. The current flowing through the transistor 221 is converted into a voltage by the resistor 222 and sent to the sense amplifier 24. Since the current flowing through the transistor 223 is the same as the current flowing through the bit line BL via the data bus B, a voltage corresponding to the current flowing through the bit line BL is obtained by the current-voltage conversion circuit with the above configuration.

The sense voltage application circuit is a constant voltage source that outputs the same voltage as the voltage applied to the positive input terminal of the operational amplifier 224 from the drain terminal of the transistor 223. The drain terminal of the transistor 223 is connected to the negative input terminal of the operational amplifier 224. The positive input terminal of the operational amplifier 22 4, the drain terminals of the two transistors 225 and 226 connected in parallel is connected. The output terminal of the operational amplifier 224 is connected to the gate terminal of the transistor 223.
In the transistor 225, the first voltage V1 is applied to the source terminal, and the first control signal C1 is applied to the gate terminal. When the first control signal C1 becomes high level, the transistor 225 becomes conductive, and the first voltage V1 is applied to the positive input terminal of the operational amplifier 224.
In the transistor 226, the reference voltage Vref is applied to the source terminal, and the second control signal C2 is applied to the gate terminal. When the second control signal C2 becomes high level, the transistor 226 becomes conductive, and the reference voltage Vref is applied to the positive input terminal of the operational amplifier 224.

In the cascode circuit 22 having such a configuration, the first control signal C 1 and the second control signal C 2 as shown in FIG. 2 are input from the control circuit 23, and the first voltage V 1 and the reference voltage Vref are supplied from the reference voltage generation circuit 21. By being input, the first voltage V1 is input to the operational amplifier 224 prior to the sensing period. As a result, the first voltage V1 is applied to the bit line BL via the data bus B.
Next, in the sensing period, the reference voltage Vref is input to the operational amplifier 224 instead of the first voltage V1. As a result, the reference voltage Vref is applied to the bit line BL via the data bus B.
As described above, the transistors 225 and 226 act as a switch that inputs the first voltage V1 to the operational amplifier 224 by the first control signal C1 and inputs the reference voltage Vref to the operational amplifier 224 by the second control signal C2.

FIG. 4 is a circuit diagram showing another example of the specific circuit configuration of the cascode circuit 22.
In the cascode circuit 22, transistors 221 and 223, a resistor 222, and operational amplifiers 227 and 228 constitute a current-voltage conversion circuit. The transistor 223 and operational amplifiers 227 and 228 constitute a sense voltage application circuit.
The current-voltage conversion circuit is different from the example of FIG. 3 in that two operational amplifiers 227 and 228 are used. However, as described later, only one of the operational amplifiers 227 and 228 is activated by the first control signal C1 and the second control signal C2. For this purpose, the same operation as in the example of FIG. 3 is performed. Therefore, the description of the current-voltage conversion circuit is omitted.

The operational amplifiers 227 and 228 of the cascode circuit 22 have the following characteristics.
In the operational amplifier 227, the reference voltage V ref is input to the positive input terminal, and the negative input terminal is connected to the drain terminal of the transistor 223. The operational amplifier 227 is provided with a control terminal to which the second control signal C2 is input. The operational amplifier 227 is activated or deactivated by the second control signal C2.
In the operational amplifier 228, the first voltage V1 is input to the positive input terminal, and the negative input terminal is connected to the drain terminal of the transistor 223. The operational amplifier 228 is provided with a control terminal to which the first control signal C1 is input. The operational amplifier 228 is activated or deactivated by the first control signal C1.
The activated operational amplifier and the transistor 223 serve as a constant voltage source for outputting the same voltage as the voltage applied to the positive input terminal of the activated operational amplifier from the drain terminal of the transistor 223. In other words, the configuration includes a constant voltage source including an operational amplifier 227 and a transistor 223, and a constant voltage source including an operational amplifier 228 and a transistor 223.

In the cascode circuit 22 having such a configuration, the first control signal C 1 and the second control signal C 2 as shown in FIG. 2 are input from the control circuit 23, and the first voltage V 1 and the reference voltage Vref are supplied from the reference voltage generation circuit 21. by the input, prior to the sensing period, inputting the first voltage V1 to the operational amplifier 22 8. As a result, the same voltage as the first voltage V1 is applied to the bit line BL via the data bus B.
Then, in the sensing period, the reference voltage Vref instead of the first voltage V1 is input to the operational amplifier 22 7. As a result, the same voltage as the reference voltage Vref is applied to the bit line BL via the data bus B.

In the cascode circuit 22 configured as shown in FIGS. 3 and 4, the bit line BL is precharged with the first voltage V1 prior to the sensing period. The floating bit line is coupled by the bit line to which the first voltage V1 is applied, but converges by the sensing period. In the sensing period, the reference voltage Vref is applied to the bit line BL instead of the first voltage V1. The floating bit line receives the coupling of the difference between the reference voltage Vref and the first voltage V1, but does not substantially vary because the difference is small. Thereby, only the memory cell current flows through the data bus B, and a sensing operation faster than the conventional one is realized. Further, by suppressing the overshoot, the drain disturb phenomenon due to the voltage supplied to the bit line of the nonvolatile memory cell can be suppressed, and the change (deterioration) of the data written in the memory cell can be suppressed. This is because a voltage higher than the reference voltage Vref is not applied to the bit line due to a delay in the response of the feedback voltage from the operational amplifier. In the case of a nonvolatile memory cell, when a voltage equal to or higher than the reference voltage Vref is applied to the bit line, the memory cell connected to the bit line becomes an environment of a stress voltage in a weak program state. In particular, the memory cell connected to the selected word line is the most severe stress voltage environment. However, the cascode circuit 22 can prevent the occurrence of such a stress voltage environment.

FIG. 5 is a configuration diagram for explaining the cascode circuit 22 and the constant voltage source 30 that apply the first voltage V1 and the reference voltage Vref to the bit lines BL of the plurality of memory cell arrays 10.
A plurality of cascode circuits 22 are provided. The cascode circuits 22 are connected to bit lines BL of different memory cell arrays 10 via different data buses B, respectively. The constant voltage source 30 is a circuit that supplies the first voltage V <b> 1 to each cascode circuit 22. With such a configuration, data can be read from the memory cells 11 of the plurality of memory cell arrays 10.

  The current-voltage conversion circuit of each cascode circuit 22 includes transistors 221, 223, a resistor 222, and an operational amplifier 227. The operational amplifier 227 is activated by the second control signal C2 as in the example of FIG. The operation at the time of activation is the same as the example of FIG. Description of the current-voltage conversion circuit is omitted.

The sense voltage application circuit of each cascode circuit 22 includes transistors 223, 229 and 230, an operational amplifier 227, and a constant voltage source 30. The structures and operations of the transistor 223 and the operational amplifier 227 are the same as those in FIG.
The sense voltage application circuit of each cascode circuit 22 includes transistors 229 and 230 that are not conventional. The transistor 229 is controlled to be turned on and off by the first control signal C1. When the transistor 229 is conductive, the first voltage V1 is input from the constant voltage source 30. The transistor 230 is controlled to be conductive or nonconductive by a third control signal C3 that determines which cascode circuit 22 is applied with the first voltage V1 or the reference voltage Vref. The third control signal C3 is input from the control circuit 23, for example.

The constant voltage source 30 includes an operational amplifier 31 and a P-channel transistor 32. The first voltage V <b> 1 is input to the positive input terminal of the operational amplifier 31. The drain terminal of the transistor 32 is connected to the negative input terminal of the operational amplifier 31. Further, the first control signal C <b> 1 is input to the operational amplifier 31. The operational amplifier 31 is activated by the first control signal C1. The output terminal of the operational amplifier 31 is input to the gate terminal of the transistor 32. The drain terminal of the transistor 32 is connected to the source terminal of the transistor 229. The constant voltage source 30 has a driving force corresponding to the number of cascode circuits 22 in order to supply the first voltage to the plurality of cascode circuits 22.

When the first voltage V1 is input to the operational amplifier 31 and the operational amplifier 31 is activated by the first control signal C1, the constant voltage source 30 outputs the same voltage as the first voltage V1. In the cascode circuit 22, when the operational amplifier 227 is deactivated by the first control signal C1, the second control signal C2, and the third control signal C3 when the transistors 229 and 230 are in a conductive state, the first voltage V1 is The voltage is applied to the bit line BL of the memory cell array 10 via the bus B. When the transistor 230 is turned on, the transistor 229 is turned off, and the operational amplifier 227 is activated, the reference voltage Vref is applied to the bit line BL of the memory cell array 10 via the data bus B. The transistor 229 may be a P-channel transistor. In this case, an inverted signal of the first control signal C1 is input to the gate electrode.

  In this case, the same effect as that obtained when the cascode circuit 22 shown in FIGS. 3 and 4 is used can be obtained. Compared with the cascode circuits of FIGS. 3 and 4, the configuration can be reduced by providing the constant voltage source 30 outside. Furthermore, by controlling the transistor 229 with the first control signal C1, it is possible to prevent malfunction due to interference between data buses.

It is a block diagram of the semiconductor memory device of this embodiment. It is an illustration figure of a 1st control signal and a 2nd control signal. It is a circuit diagram which shows an example of the concrete circuit structure of a cascode circuit. It is a circuit diagram which shows another example of the concrete circuit structure of a cascode circuit. It is a block diagram for explaining a cascode circuit and a constant voltage source for applying a first voltage and a reference voltage to bit lines of a plurality of memory cell arrays.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 10 ... Memory cell array, 11 ... Memory cell, 20 ... Read-out circuit, 21 ... Reference voltage generation circuit, 22 ... Cascode circuit, 23 ... Control circuit, 24 ... Sense amplifier, 221, 223, 225, 226 , 229, 230, 32 ... transistor, 222 ... resistor, 224,227,228,31 ... op amp, 30 ... constant voltage source

Claims (10)

A memory cell in which data that can take at least two values is recorded;
A sense voltage applying circuit that applies either a reference voltage necessary for reading the data or a first voltage lower than the reference voltage to the bit line connected to the memory cell;
A current-voltage conversion circuit for converting a current flowing through the bit line into a voltage at the time of reading;
A sense circuit that compares a voltage converted by the current-voltage conversion circuit with a predetermined comparison voltage and determines a value of data recorded in the memory cell;
The sense voltage application circuit applies the first voltage to the bit line prior to the comparison by the sense circuit, and applies the reference voltage to the bit line instead of the first voltage during the comparison.
Semiconductor device. The sense voltage application circuit is disposed outside a memory cell array in which the memory cells are arranged in an array.
The semiconductor device according to claim 1. A controller for generating a first control signal for causing the sense voltage application circuit to output the first voltage and a second control signal for causing the reference voltage to be output;
The sense voltage application circuit includes a voltage generation unit that outputs the first voltage when the first control signal is input and outputs the reference voltage when the second control signal is input.
The semiconductor device according to claim 1. The voltage generator is
A constant voltage source capable of outputting the same voltage as the input voltage;
A switch that inputs the first voltage to the constant voltage source by the first control signal and inputs the reference voltage to the constant voltage source by the second control signal;
The semiconductor device according to claim 2. The voltage generator is
A first constant voltage source capable of outputting the first voltage;
A second constant voltage source capable of outputting the reference voltage,
The first constant voltage source is activated by the first control signal, the second constant voltage source is activated by the second control signal, and a voltage is applied to the bit line from the activated one. ,
The semiconductor device according to claim 2. A first constant voltage source capable of outputting the first voltage;
The voltage generation unit includes a second constant voltage source capable of outputting the reference voltage,
When the first control signal is input, the voltage generation unit acquires the first voltage from the first constant voltage source and outputs the first voltage, and when the second control signal is input, 2 outputting the reference voltage from a constant voltage source;
The semiconductor device according to claim 2. A method executed by a device including a memory cell in which data that can take at least two values is recorded, and a read circuit that reads the data from the memory cell,
The readout circuit comprises:
Applying a first voltage lower than a reference voltage required for reading to the bit line connected to the memory cell prior to reading;
Applying a reference voltage to the bit line instead of the first voltage at the time of reading; and generating a voltage using a current flowing through the bit line when the reference voltage is applied;
Comparing the voltage generated from the current flowing through the bit line with a predetermined comparison voltage to determine the value of the data recorded in the memory cell,
Data reading method. The readout circuit comprises:
Applying the first voltage at the time of starting the device or at a predetermined intermittent operation after the device is started,
The data reading method according to claim 7. The readout circuit comprises:
Applying the reference voltage when a read command that is an external access command of the device is input;
The data reading method according to claim 7. The readout circuit comprises:
Applying a pre-Symbol first voltage to the active command input is an external access command of said device,
The data reading method according to claim 7 .

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