JP5311507B2 - Synchronous semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which power consumption by an address input buffer can be reduced. <P>SOLUTION: The semiconductor device includes a first input buffer connected to an address terminal, a clock terminal receiving a clock signal being reference of a data input, and a second input buffer connected to the clock terminal and receiving a clock signal. The first input buffer is activated when a write-command is input, after the write-command is input, the buffer is non-activated after the prescribed cycle of the clock signal. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a technology for inputting information in a semiconductor device to which information used for executing the command is supplied after inputting a command for instructing the operation. For example, an SDRAM (Synchronous Dynamic) capable of DDR (Double Data Rate) operation. The present invention relates to a technique effective when applied to Random Access Memory.

  With the increase in operation speed, external interfaces such as SDRAM are also moving to small amplitude signal interfaces such as SSTL (Stub Series Terminating Transceiver Logic). A differential amplifier circuit having a current mirror load is widely used as an input buffer of the SSTL specification interface. In the active state of the differential amplifier circuit, a through current always flows, so that power consumption is larger than that of a CMOS input buffer formed of a complementary MOS circuit, but a minute signal can be input at high speed.

  The operation timing of a synchronous memory such as SDRAM is controlled based on an external clock signal such as an external system clock signal. This type of synchronous memory is characterized in that the internal operation timing can be set relatively easily by using an external clock signal, and a relatively high speed operation can be performed.

  Here, as the SDRAM, a so-called SDR (Single Data Rate) type SDRAM in which data input and output are performed in synchronization with the rising edge of the external clock signal, and data input and output are the rising edge of the external clock signal and There is known a so-called DDR type SDRAM which is performed in synchronization with both falling edges.

  The write data input timing control is different between the SDR type SDRAM and the DDR type SDRAM. In the SDRAM of the SDR format, the supply of data from the outside is defined in the same clock signal cycle as that of the external write operation instruction. Therefore, since write data is supplied at the same time as the write operation is instructed by the write command following the bank active command, the data input buffer is activated after receiving the write command. The input of the write data supplied in time is not in time. As a result, the data input buffer is activated when a bank active command instructing a row address system operation is received.

  On the other hand, in the DDR SDRAM, the supply of data from the outside synchronized with the data strobe signal is defined from the clock signal period after the clock signal period in which the external write operation is instructed. The data strobe signal is also used for data output. By using such a data strobe signal, the data propagation delay and the data strobe signal propagation delay are appropriately set for each SDRAM on the memory board. This makes it relatively easy to reduce variations in data access time depending on the distance from the memory controller to the SDRAM on the memory board.

  The present inventor examined the activation control of the data input buffer in the DDR type SDRAM. According to this, in the DDR type SDRAM, similarly to the SDR type, when the data input buffer is activated in response to the bank active command, the data input buffer is in an active state thereafter until, for example, a precharge command is accepted. It has been clarified by the present inventor that wasted power is consumed in the data input buffer until the write command is issued from the bank active command. In addition, the write command is not always issued after the bank active command, and if only the read command is issued, the active state of the data input buffer is totally wasted as a result, resulting in power consumption. It has also been clarified by the present inventors that it is completely useless. In particular, the adoption of the SSTL interface of the data input buffer of the DDR-SDRAM is defined by JEDEC (Joint Electron Engineering Engineering), and considering the case of complying with this, the activity of the input buffer in the SSTL interface It has been found by the present inventor that the control timing becomes a major factor in reducing the power consumption of the DDR-SDRAM.

  An object of the present invention is to provide a semiconductor device capable of reducing power consumption by an external interface buffer such as a data input buffer.

  Another object of the present invention is to provide a semiconductor device suitable for a DDR type SDRAM intended for low power consumption.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in a semiconductor device having a data input buffer capable of inputting write data to the memory portion, the data input buffer is changed from an inactive state to an active state after receiving an instruction for a write operation to the memory portion.

  The semiconductor device is not particularly limited, but is a clock-synchronous semiconductor device, for example, an SDRAM, which performs a data write operation to a plurality of memory cells and a data read operation from the memory cells in response to a clock signal. .

  The data input buffer is a differential input buffer having an interface specification conforming to, for example, the SSTL standard. The buffer is activated by the on state of the power switch and deactivated by the off state. An input buffer typified by the differential input buffer allows a through current to flow in its active state, and can immediately follow a minute change in a small amplitude input signal and transmit the input signal to the subsequent stage.

  Since such an input buffer is activated only after receiving a write operation instruction to the memory unit, useless power consumption is consumed by the data input buffer being activated in advance before the write operation is instructed. Is reduced.

  In the case of the SDRAM which is a preferred example of the semiconductor device, the control circuit for controlling the data write operation and the data read operation with respect to the memory cell is instructed by the write command for the data write operation specifying the bit line by the column address, and the row address. Is selected by a bank active command, a data read operation specifying a bit line by a column address is specified by a read command, and initialization of the word line is specified by a precharge command. After accepting the command, the data input buffer is changed from the inactive state to the active state, and the state of the inactive data input buffer remains unchanged even when the bank active command or read command is accepted. Thus, since the data input buffer is not activated by an instruction by a bank active command or a read command, no unnecessary power consumption is performed in the data input buffer unless a write command is instructed after bank activation.

  When a semiconductor device is specified to supply data synchronized with a data strobe signal from a clock signal cycle after the clock signal cycle in which a write command is instructed by a write command, like a DDR format SDRAM, The semiconductor device has, for example, a data latch circuit at the next stage of the data input buffer, and the data latch circuit latches data supplied in synchronization with the data strobe signal in synchronization with the data strobe signal. To do. Such a data input specification in a semiconductor device, from one point of view, ensures that write data input is not lost even if the data input buffer is activated after an instruction for a write operation by a clock-synchronized write command. .

  When data can be input / output in synchronization with both rising and falling edges of a data strobe signal synchronized with a clock signal, as in a DDR type SDRAM, the data latch circuit, for example, Data input to the data input buffer is sequentially latched in synchronization with the rise and fall of the strobe signal, and can be supplied in parallel to the memory cells in units of one or more cycles of the data strobe signal. The data latch circuit of a more specific aspect includes a first data latch circuit that latches data input from the data input buffer in synchronization with a rising change of the data strobe signal, and input from the data input buffer. A second data latch circuit for latching data in synchronism with a falling change of the data strobe signal; and latching data latched in the first data latch circuit in synchronism with a falling change of the data strobe signal. And a third data latch circuit, and the outputs of the second data latch circuit and the third data latch circuit can be supplied in parallel to the memory unit.

  Once the write data is fetched from the data input buffer, there is no need to keep the data input buffer active anymore even if the write operation has not yet been completed. Therefore, if the low power consumption of the data input buffer is given top priority, the data input buffer waits for the last write data of the write operation by the write command to be latched by the second and third data latch circuits. May be transitioned from an active state to an inactive state. Although this control can be performed in synchronization with the data strobe signal, the reliability of the write operation should be maintained even when the relationship between the data strobe signal and the write data setup / hold time fluctuates undesirably. In this case, the data input buffer may be changed from the active state to the inactive state in synchronization with the end of the write operation by the write command.

  Input buffer control from the same viewpoint as the data input buffer can be applied to an address input buffer or the like. For example, a plurality of address input terminals, a plurality of address input buffers provided corresponding to the plurality of address input terminals, a clock terminal for receiving a clock signal, and a selection terminal are connected to a word line and data input / output As an example, a semiconductor device including a plurality of memory cells whose terminals are connected to a bit line, and a control circuit that controls a data write operation and a data read operation on the memory cell in synchronization with a clock signal. The control circuit is instructed by a bank active command to select a word line by a row address, is instructed by a read command to specify a bit line by a column address, and a data write operation by which a bit line is specified by a column address. Command line and word line initialization A predetermined cycle period that is instructed by a precharge command and changes the address input buffer from an inactive state to an active state after receiving the bank active command, the read command, or the write command, and then synchronizes with the clock signal. The address input buffer may be changed from the active state to the inactive state after waiting for elapse.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device having a data input buffer capable of inputting write data to the memory portion, the data input buffer is changed from an inactive state to an active state after receiving an instruction for a write operation to the memory portion. The data input buffer is a differential input buffer having an interface specification conforming to, for example, the SSTL standard. A through-current flows in the active state, and a signal is input immediately following a minute change in a small amplitude signal. . Since such an input buffer is activated only after receiving a write operation instruction to the memory unit, useless power consumption is consumed by the data input buffer being activated in advance before the write operation is instructed. Can be reduced.

  In the case of the SDRAM which is a preferred example of the semiconductor device, the data input buffer is not activated by an instruction by the bank active command or the read command. Therefore, if no write command is instructed after the bank activation, there is nothing in the data input buffer. There is no wasteful power consumption.

  Input buffer control based on the same viewpoint as the data input buffer can be applied to an address input buffer or the like. After receiving the bank active command, the read command, or the write command, the address input buffer is changed from an inactive state to an active state, and then an address is input after a certain cycle period synchronized with the clock signal has elapsed. The buffer is changed from the active state to the inactive state.

  As described above, it is possible to provide a semiconductor device capable of reducing power consumption by an external interface buffer such as a data input buffer.

1 is a block diagram showing a DDR-SDRAM which is an example of a semiconductor device according to the present invention. It is a circuit diagram which shows the circuit structural example of SSTL2 (class II). It is explanatory drawing which illustrates the standard of the signal in SSTL2 (class 2). It is a circuit diagram showing an input first stage buffer of a data input circuit which is a specific example of a differential input buffer compliant with SSTL. FIG. 10 is a circuit diagram showing a differential input buffer for a data strobe signal DQS as another example of a differential input buffer compliant with SSTL. 3 is a block diagram showing an example of a data input circuit of the DR-SDRAM 1. FIG. It is explanatory drawing which shows roughly the connection aspect of a selector latch circuit and the memory array of a memory bank. It is a block diagram which shows the front | former stage of the control circuit of DDR-SDRAM mainly by the write control system. It is a block diagram which shows the back | latter stage of the control circuit of DDR-SDRAM mainly by the write control system. It is a block diagram which illustrates a column address input system. 4 is a timing chart illustrating a write operation timing with a burst number of 4 in the DDR-SDRAM 1; 12 is a timing chart showing a write operation timing of an SDR-SDRAM as a comparative example of FIG. 5 is a timing chart illustrating operation timing when the present invention is applied to an address input buffer.

<Outline of DDR-SDRAM>
FIG. 1 shows a DDR SDRAM (DDR-SDRAM) as an example of a semiconductor device according to the present invention. The DDR-SDRAM shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known MOS semiconductor integrated circuit manufacturing technique.

  The DDR-SDRAM 1 is not particularly limited, and has four memory banks BNK0 to BNK3. Although not shown, each of the memory banks BNK0 to BNK3 is not particularly limited, but each has four memory mats, and each memory mat is constituted by two memory arrays. One memory array is assigned to a data storage area in which the least significant bit of the column address signal corresponds to the logical value “0”, and the other memory array has data of which the least significant bit of the column address signal corresponds to the logical value “1”. Allocated to storage area. The memory bank memory mat and the memory array partition structure are not limited to the above. Therefore, in this specification, unless otherwise noted, each memory bank is composed of one memory mat. explain.

  The memory mats of the respective memory banks BNK0 to BNK3 include dynamic memory cells MC arranged in a matrix, and according to the figure, the selection terminals of the memory cells MC arranged in the same column are word lines WL for each column. The data input / output terminals of the memory cells arranged in the same row are coupled to one bit line BL of the complementary bit lines BL and BL for each row. Although only a part of the word lines WL and the complementary bit lines BL are representatively shown in the figure, a large number are actually arranged in a matrix and have a folded bit line structure with a sense amplifier as the center. Yes.

  For each of the memory banks BNK0 to BNK3, row decoders RDEC0 to RDEC3, data input / output circuits DIO0 to DIO3, and column decoders CDEC0 to CDEC3 are provided.

  The word line WL of the memory mat is selected and driven to the selected level according to the decoding result of the row address signal by the row decoders RDEC0 to RDEC3 provided for the memory banks BNK0 to BNK3.

  The data input / output circuits DIO0 to DIO3 include a sense amplifier, a column selection circuit, and a write amplifier. The sense amplifier is an amplifying circuit that detects and amplifies a minute potential difference appearing on the complementary bit lines BL and BL by reading data from the memory cell MC. The column selection circuit is a switch circuit for selecting the complementary bit lines BL and BL to conduct to the input / output bus 2 such as a complementary common data line. The column selection circuit is selected according to the decoding result of the column address signal by the corresponding one of the column decoders CDEC0 to CDEC3. The write amplifier is a circuit that differentially amplifies the complementary bit lines BL and BL via the column switch circuit in accordance with write data.

  A data input circuit 3 and a data output circuit 4 are connected to the input / output bus 2. The data input circuit 3 receives externally supplied write data in the write mode and transmits it to the input / output bus 2. The data output circuit 4 inputs read data transmitted from the memory cell MC to the input / output bus 2 in the read mode and outputs the read data to the outside. Although the input terminal of the data input circuit 3 and the output terminal of the data output circuit 4 are not particularly limited, they are coupled to 16-bit data input / output terminals DQ0 to DQ15. For convenience, reference numerals DQ0 to DQ15 may be attached to the data that the SDRAM 1 inputs and outputs to the outside.

  Although not particularly limited, the DDR-SDRAM 1 has 15-bit address input terminals A0 to A14. Address input terminals A0-A14 are coupled to address buffer 5. Of the address information supplied to the address buffer 5 in a multiplexed form, the row address signals AX0 to AX12 are regarded as a row address latch 6 and the column address signals AY0 to AY11 are regarded as a bank selection signal as a bank selection signal. The select signals AX13 and AX14 are supplied to the bank selector 8 and the mode register setting information A0 to A14 are supplied to the mode register 9.

  The operation of the four memory banks BNK0 to BNK3 is selected by the bank selector 8 according to the logical values of the 2-bit bank selection signals AX13 and AX14. That is, only the memory bank whose operation is selected can be operated. For example, sense amplifiers, write amplifiers, column decoders and the like are not activated in memory banks whose operations are not selected.

  The row address signals AX0 to AX12 latched in the row address latch 6 are supplied to the row address decoders RDEC0 to RDEC3.

  Column address signals AY0 to AY11 latched in the column address latch 7 are preset in the column address counter 10 and supplied to the column address decoders CDEC0 to CDEC3. When burst access, which is continuous memory access, is instructed, the column address counter 10 is incremented by the number of consecutive times (the number of bursts), and a column address signal is generated internally.

  The refresh counter 11 is an address counter that itself generates a row address for refreshing stored information. When the refresh operation is instructed, the word line WL is selected according to the row address signal output from the refresh counter 11, and the stored information is refreshed.

  The control circuit 12 is not particularly limited, but the clock signals CLK and CLKb, the clock enable signal CKE, and the chip select signal CSb (suffix b means that the signal to which it is attached is a low enable signal or a level inverted signal. ), Predetermined information is input from the mode register 9 together with external control signals such as a column address strobe signal CASb, a row address strobe signal RASb, a write enable signal WEb, data mask signals DMU and DML, and a data strobe signal DQS. The operation of the DDR-SDRAM 1 is determined by a command defined by a combination of the states of these input signals, and the control circuit 12 has control logic for forming an internal timing signal corresponding to the operation designated by the command.

  The clock signals CLK and CLKb are SDRAM master clocks, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK.

  The chip select signal CSb instructs the start of the command input cycle by its low level. When the chip select signal is at a high level (chip non-selected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

  The RASb, CASb, and WEb signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle to be described later.

  The clock enable signal CKE is a control signal for the power-down mode and the self-refresh mode. In the power-down mode (which is also a data retention mode in the SDRAM), the clock enable signal CKE is set to a low level.

  The data mask signals DMU and DML are mask data in units of bytes with respect to the input write data. The high level of the data mask signal DMU instructs to inhibit writing by the upper bytes of the write data, and the high level of the data mask signal DML indicates the write data. Instructs write suppression by the lower byte of.

  The data strobe signal DQS is supplied from the outside as a write strobe signal during a write operation. That is, when a write operation is instructed in synchronization with the clock signal CLK, the supply of data synchronized with the data strobe signal DQS from the clock signal period after the clock signal period in which the instruction has been issued is defined. . During a read operation, the data strobe signal DQS is output to the outside as a read strobe signal. That is, in the data read operation, the data strobe signal is changed in synchronization with the external output of the read data. For this purpose, a DLL (Delayed Lock Loop) circuit 13 and a DQS output buffer 14 are provided. In order to synchronize the clock signal CLK received by the semiconductor device 1 and the data output timing of the data output circuit 4, the DLL circuit 13 controls the data output operation control clock signal (control in phase with the data strobe signal DQS during the read operation). The phase of the clock signal 15 is adjusted. Although not particularly limited, the DLL circuit 13 reproduces the internal clock signal 15 that can compensate the signal propagation delay time characteristic of the internal circuit by the replica circuit technique and the phase synchronization technique. The data output circuit 4 that is operated to output data can output data at a timing that is reliably synchronized with the external clock signal CLK. The DQS buffer 14 outputs the data strobe signal DQS to the outside in phase with the internal clock signal 15.

  The row address signals (AX0 to AX12) are defined by the levels of address input terminals A0 to A12 in a later-described row address strobe / bank active command (active command) cycle synchronized with the rising edge of the clock signal CLK. In this active command cycle, the signals AX13 and AX14 input from the address input terminals A13 and A14 are regarded as bank selection signals. When A13 = A14 = “0”, the bank BNK0, A13 = “1”, A14 = “ When 0, bank BNK1, A13 = “0”, when A14 = “1”, bank BNK2, and when A13 = “1”, A14 = “1”, bank BNK3 are selected. The memory bank selected in this manner is subjected to data reading by a read command, data writing by a write command, and precharging by a precharge command.

  The column address signals (AY0 to AY11) are levels of the terminals A0 to A11 in a column address / read command (read command) cycle and a column address / write command (write command) cycle, which will be described later, synchronized with the rising edge of the clock signal CLK. Defined by The column address designated by this is used as the start address of burst access.

  The DDR-SDRAM 1 is not particularly limited, but commands such as the following [1] to [9] are defined in advance.

  [1] The mode register set command is a command for setting the mode register 9. This command is specified by CSb, RASb, CASb, WEb = low level, and data to be set (register set data) is given via A0 to A14. The register set data is not particularly limited, but may be burst length, CAS latency, burst type, or the like. The settable burst length is not particularly limited, but is 2, 4, 8, and the settable CAS latency is not particularly limited, but is 2,2.5.

  The CAS latency designates how many cycles of the clock signal CLK are spent from the fall of CASb to the output operation of the data output circuit 4 in a read operation instructed by a column address / read command described later. An internal operation time for data reading is required until the read data is determined, and is used for setting it according to the frequency of use of the clock signal CLK. In other words, the CAS latency is set to a relatively large value when the clock signal CLK having a high frequency is used, and the CAS latency is set to a relatively small value when the clock signal CLK having a low frequency is used.

  [2] The row address strobe / bank active command is a command for validating the instruction of the row address strobe and the selection of the memory bank by A13 and A14. CSb, RASb = low level (“0”), CASb, WEb = Instructed by a high level (“1”), the address supplied to A0 to A12 at this time is used as a row address signal, and the signals supplied to A13 and A14 are taken in as memory bank selection signals. The capturing operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is specified, the word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are respectively conducted to the corresponding complementary data lines.

  [3] The column address / read command is a command necessary for starting a burst read operation and a command for giving a column address strobe instruction. CSb, CASb, = low level, RASb, WEb = high level At this time, the address supplied to A0 to A11 is taken in as a column address signal. The column address signal thus fetched is preset in the column address counter 10 as a burst start address. In the burst read operation instructed by this, the memory bank and the word line in the row address strobe / bank active command cycle are selected before that, and the memory cell of the selected word line receives the clock signal CLK. In accordance with the address signal output from the column address counter 10 in synchronism with each other, the memory bank sequentially selects, for example, in units of 32 bits, and continuously to the outside in units of 16 bits in synchronization with the rise and fall of the data strobe signal DQS. Is output. The number of data (words) to be read continuously is the number specified by the burst length. Further, data reading from the data output circuit 4 is started after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

  [4] The column address / write command is a command necessary for starting the burst write operation when burst write is set in the mode register 9 as a mode of the write operation. Further, this command gives an instruction for column address strobe in burst write. The command is instructed by CSb, CASb, WEb, = low level, and RASb = high level. At this time, the address supplied to A0 to A11 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 10 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency setting in the write operation, and writing of the write data is started in synchronization with the data strobe signal DQS with a delay of one cycle of the clock signal CLK from the column address / write command cycle.

  [5] The precharge command is a command for starting a precharge operation for the memory bank selected by A13 and A14, and is designated by CSb, RASb, WEb, = low level, and CASb = high level.

  [6] The auto-refresh command is a command required to start auto-refresh, and is designated by CSb, RASb, CASb = low level, and WEb, CKE = high level. The refresh operation by this is the same as CBR refresh.

  [7] When the self-refresh entry command is set, the self-refresh function operates while CKE is at the low level, and during that time, refresh operation is automatically performed at a predetermined interval without giving a refresh instruction from the outside. Is done.

  [8] The burst stop command is a command necessary for stopping the burst read operation, and is ignored in the burst write operation. This command is indicated by CASb, WEb = low level and RASb, CASb = high level.

  [9] The no operation command is a command for instructing not to perform a substantial operation, and is designated by CSb = low level, RASb, CASb, WEb = high level.

  In the DDR-SDRAM 1, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle and a row address strobe / bank active command is supplied, The operation of the row address system in the other memory bank is made possible without affecting the operation in the other memory bank. That is, a row address system operation specified by a bank active command or the like and a column address system operation specified by a column address / write command or the like can be performed in parallel between different memory banks. Therefore, as long as data does not collide at the data input / output terminals DQ0 to DQ15, a precharge command for a memory bank different from the memory bank to be processed during execution of a command that has not been processed, It is possible to start the internal operation in advance by issuing a row address strobe / bank active command.

  As is clear from the above description, the DDR-SDRAM 1 is capable of data input / output synchronized with both rising and falling edges of the data strobe signal DQS synchronized with the clock signal CLK, and synchronized with the clock signal CLK. Since address and control signals can be input / output, a large-capacity memory similar to DRAM can be operated at a high speed comparable to SRAM, and several data can be accessed for one selected word line. By designating whether or not to be performed by the burst length, the built-in column address counter 10 sequentially switches the column system selection state, and a plurality of data can be read or written continuously.

<< SSTL interface >>
In the DDR-SDRAM 1, although not particularly limited, the clock signal CLK, the inverted clock signal CLKb, the clock enable signal CKE, the chip selection signal CSb, the RAS signal RASb, the CAS signal CASb, the write enable signal WEb, and the address input signals A0 to A0. The interface of A14, the input buffer that receives the data mask signal DM and the data strobe signal DQS, the data input buffer of the data input circuit 3, and the data output buffer of the data output circuit 4 is compliant with, for example, the well-known SSTL2 (Class II) standard. The

  FIG. 2 shows a circuit configuration example of SSTL2 (Class II). The transmission line 20 having a characteristic impedance of 50Ω is pulled up with a reference voltage VREF and connected to, for example, a memory controller or SDRAM. The input buffer of the SDRAM is a differential input buffer 21, and the transmission line 20 is coupled to one of the differential inputs. The reference voltage VREF is applied to the other side, and the activation of the power switch 22 is controlled by the enable signal DIE. The power supply voltage VDD is, for example, 3.3V, and the circuit ground voltage VSS is 0V. The output buffer includes a CMOS inverter at the output stage using the power supply voltage VDDQ = 2.5 V and the ground voltage VSS as operation power supplies. The memory controller has a driver and a receiver that satisfy the interface specifications. The driver drives the transmission line 20, and the receiver inputs data from the transmission line 20.

  FIG. 3 illustrates signal standards in the SSTL2 (class 2). In the SSTL2 standard, a level of 1.6 volts or higher which is 0.35 V or higher with respect to a reference potential (VREF) such as 1.25 volts is regarded as H level, and a level of 0.35 V or lower with respect to the reference potential. That is, a level of 0.90 volts or less is regarded as the L level. The above specific level is a typical example, and may be a level that conforms to the SSTL3 standard, for example.

  FIG. 4 shows an input first stage buffer of the data input circuit 3 as a specific example of the differential input buffer compliant with the SSTL. The differential input buffer 30 includes a current mirror load composed of p-channel MOS transistors Mp1 and Mp2, n-channel differential input MOS transistors Mn3 and Mn4 coupled to the drains of the MOS transistors Mp1 and Mp2, It has a differential amplifier circuit comprising an n-channel power switch MOS transistor Mn5 coupled to a common source of differential input MOS transistors Mn3 and Mn4.

  The gate of one differential input MOS transistor Mn3 is coupled to the data terminal DQj (j = 0-15), and the gate of the other differential input MOS transistor Mn4 is coupled to the reference voltage VREF. The output node of the differential amplifier circuit can be selectively precharged to the power supply voltage VDD by the p-channel type precharge MOS transistor Mp6, and the signal at the node is inverted and output via the inverter 31.

  DIE is an enable control signal for the differential input buffer 30 and is supplied to the gates of the power switch MOS transistor and the precharge MOS transistor Mp6. The differential input buffer is activated by the high level of the enable control signal DIE. In this active state, an operating current flows through the differential amplifier circuit and immediately amplifies a minute potential difference from the signal level of the terminal DQj around the reference voltage VREF. Due to the differential amplification, the signal input operation from the terminal DQj is fast. The differential input buffer is deactivated by the low level of the enable control signal DIE. In the inactive state of the differential input buffer, no power is consumed in the differential amplifier circuit, and the output of the inverter 31 is also forced to a low level by the action of the precharge MOS transistor Mp6 in the on state.

  The enable control signal DIE is asserted from a low level to a high level after an instruction to write to the DDR-SDRAM 1 by a write command. As described above, since the differential input buffer 30 is activated after the write operation is instructed by the write command, the differential input buffer 30 does not waste power before the write operation is instructed. Further, even when the bank active command or the read command is received, the state of the inactive data input buffer remains unchanged. Since the differential input buffer 30 is not activated by an instruction by a bank active command or a read command, no unnecessary power consumption is performed in the differential input buffer 30 if no write command is instructed after bank activation.

  FIG. 5 shows a differential input buffer for the data strobe section signal DQS as another example of the differential input buffer compliant with the SSTL. The differential input buffer 40 is configured by mutually connecting input terminals having different polarities of a pair of differential amplifier circuits. That is, one differential amplifier circuit includes a current mirror load composed of p-channel MOS transistors Mp11 and Mp12, n-channel differential input MOS transistors Mn13 and Mn14, and an n-channel power switch MOS transistor Mn15. The gate of the MOS transistor Mn13 serves as an inverting input terminal, and the gate of the MOS transistor Mn14 serves as a non-inverting input terminal. The other differential amplifier circuit includes a current mirror load composed of p-channel MOS transistors Mp21 and Mp22, n-channel differential input MOS transistors Mn23 and Mn24, and an n-channel power switch MOS transistor Mn25. The gate of the MOS transistor Mn23 is an inverting input terminal, and the gate of the MOS transistor Mn24 is a non-inverting input terminal.

  A data strobe signal DQS is input to the gates of the differential input MOS transistors Mn13 and Mn24, and a reference voltage VREF is input to the gates of the differential input MOS transistors Mn14 and Mn23. The internal clock signals DSCLKT and DSCLKB at a level complementary to the data strobe signal DQS can be obtained from the CMOS inverters 41 and 42 connected to the single-ended output node.

  DSEN is an enable control signal for the differential input buffer 40 and is supplied to the gates of the power switch MOS transistors Mn15 and MN25. The differential input buffer is activated by the high level of the enable control signal DSEN. In this active state, an operating current flows through the differential amplifier circuit, and immediately a minute potential difference from the signal level of the terminal DQS around the reference voltage VREF is amplified. Due to the differential amplification, the signal input operation from the terminal DQS is fast. The differential input buffer is deactivated by the low level of the enable control signal DSEN. There is no power consumption in the differential amplifier circuit when the differential input buffer is inactive.

<Data input circuit>
FIG. 6 shows an example of the data input circuit 3 of the DR-SDRAM 1. In the first stage, the SSTL specification differential input buffer 30 described in FIG. 4 is arranged. The differential input buffer 30 inputs write data supplied in synchronization with the rising and falling edges of the data strobe signal DQS. The next stage of the differential input buffer 30 is provided with a latch circuit 50 that latches data supplied in half cycle units of the data strobe signal in parallel in units of one cycle of the data strobe signal. The latch circuit 50 is different from, for example, the first data latch circuit 50A that latches the output data of the differential input buffer 30 in synchronization with the rising change of the data strobe signal, and in synchronization with the falling change of the data strobe signal. The second data latch circuit 50B that latches the output data of the dynamic input buffer 30 and the third data latch circuit 50C that latches the output data of the first data latch circuit 50A in synchronization with the falling change of the data strobe signal. And have. The data latch circuits 50A to 5C are each constituted by a master / slave type latch circuit (MSFF). The data latch circuit 50A uses DSCLKT as a master stage latch clock, DSCLKB as a slave stage latch clock, and data latch circuits 50B and 50C. DSCLKB is a master stage latch clock and DSCLKT is a slave stage latch clock. The latch clocks DSCLKT and DSCLKB are signals that are changed in synchronization with the data strobe signal DQS.

  The parallel output data DINRj and DINFj of the latch circuit 50 are supplied to selector latch circuits 51 and 52, respectively. The selector latch circuits 51 and 52 select either the parallel output data DINRj or DINFj according to the value of the signal DICY0, and latch the selected data in synchronization with the clock signal DICLK. The signal DICY0 is a signal corresponding to the logical value of the least significant bit AY0 of the column address signal (burst write start address) supplied from the outside to the column address latch 7, and the selector latch circuit 51 has DICY0 (= AY0) = 0. When DINRj is selected, DINFj is selected when DICY0 (= AY0) = 1. The selection control of the selector latch circuit 52 is opposite to that. Therefore, regardless of the logical value of the least significant bit of the column address of the write data that is input first, data whose logical value of the least significant bit is “0” is sent to the selector latch circuit 51 and data of “1” is It is latched by the selector latch circuit 52.

  The output of the selector latch circuit 51 is assigned to the data storage area corresponding to the data in which the least significant bit of the column address signal is the logical value “0” via the signal line DINBY0Bj included in the input / output bus 2. Connected to the memory array of each memory bank. The output of the selector latch circuit 52 is assigned to the data storage area corresponding to the data in which the least significant bit of the column address signal is the logical value “1” via the signal line DINBY0Tj included in the input / output bus 2. Connected to the memory array of each memory bank.

  FIG. 7 schematically shows a connection mode between the selector latch circuit and the memory array of the memory bank. FIG. 7 illustrates one memory mat MAT in each memory bank. The memory array Y0B of each memory mat MAT is for storing data in which the logical value of the least significant bit of the column address is “0”, and the memory array Y0T Is for data storage where the logical value of the least significant bit of the column address is “1”. WAmp is a write amplifier for each memory array, and is included in the corresponding data input / output circuits DIO0 to DIO3. YI0WY0T0 to YI0WY0T3, YI0WY0B0 to YI0WY0B3 are activation control signals for the write amplifier WAmp for each memory array.

  As understood from the description of the data input circuit 3, in the DDR-SDRAM 1, data is input from the outside in synchronization with both rising and falling of the data strobe signal DQS synchronized with the clock signal CLK. The internal write operation of the SDRAM 1 is performed with the cycle of the clock signal CLK as a minimum unit. Although a detailed description is omitted, the relationship between the internal operation timing of the SDRAM and the output operation timing to the outside is the same in the data read operation.

<< Control circuit of DDR-SDRAM >>
FIG. 8 shows a detailed example of the front stage of the control circuit 12 of the DDR-SDRAM and the rear stage of the control circuit 12 in FIG.

  The CLK input buffer 60, the command system input buffer 61, and the DQS input buffer 40 of FIG. 8 are differential input buffers of the SSTL specification. The DQS input buffer 40 is as illustrated in FIG. 5, and the CLK input buffer 60 includes a differential amplifier circuit having a differential input of CLK and CLKb as a first-stage differential input buffer, and is activated when the operation power is turned on. And deactivated in response to an instruction of the power down mode. The command system input buffer 61 is configured in the same manner as the differential input buffer of FIG. 4, but is activated when the operating power is turned on, and deactivated in response to an instruction for the power down mode.

  The output of the CLK input buffer 60 is supplied to a one-shot pulse generation circuit 62, whereby various internal clock signals ACLKB, BCLKB, CCLKB, and DCLKB are generated.

  Various signals CSb, RASb, CASb, and WEb input to the command system input buffer 61 are decoded by the command decode circuit 63, and an internal control signal corresponding to the above-described operation mode is generated. ACTi is a control signal that activates the bank selected by the bank selection signal when bank activation is instructed by the bank active command. Suffix i means a bank number. The meaning of suffix i is the same for other signals. WT and WTY are activated in response to a write operation instruction by a write command. WTY has an earlier activation timing than WT. The signal WTL2 is a signal obtained by delaying the signal WT by the shift register 64A. RD is activated when a read operation is instructed by a read command. PREi is a control signal that activates the bank selected by the bank selection signal when precharge is instructed by the precharge command.

  RWWi is a column selection system reference control signal when a write operation is instructed, and is a signal for each memory bank. In the write operation, the column selection timing is two clock cycles after the instruction of the write command. Therefore, the signal RWWi is delayed by the shift register circuit 64B, and the one shot pulse synchronized with the internal clock signal BCLKB from the delayed signal RWW2i. Signal RWi is output from one-shot pulse generation circuit 64C.

  The decoding result by the command decoding circuit 63 is reflected in various flags (RSFF) of the mode state circuit 66 in FIG. The flag is composed of a set / reset type flip-flop, S is a set terminal, and R is a reset terminal. BAi (i = 0 to 3) indicates a memory bank in which an active state is designated. BEND is a signal indicating the end of the burst operation, and BBi is a signal indicating that the burst write operation is being performed. Signals BWTY, BDRY, and BBYi are signals obtained by latching signals BWT, BRD, and BBNi in synchronization with clock signal BCLKB. Based on the column state signal BBYi generated based on the signal BBi, the write pulse generation circuit 67 generates the selection signals YI0WY0T0 to YI0WY0T3 and YI0WY0B0 to YI0WY0B3 of the memory array for each bank. The write clock DICLK is a signal obtained by latching the signal RWWSTOR in synchronization with the clock signal DCLKB.

  FIG. 10 shows a block diagram of a column address input system. The address buffer 5 is a differential input buffer of the SSTL specification. The address buffer 5 is configured in the same manner as the differential input buffer of FIG. 4, but is activated when the operating power is turned on, and deactivated in response to a power-down mode instruction. The column address latch 7 includes a master / slave type latch circuit 70, a shift register circuit 71, and a multiplexer 72. When the write operation is instructed so that the write operation to the memory cell is performed after two cycles of the clock signal CLK from the instruction of the write operation by the write command, the address signal delayed by the shift register circuit 71 is output by the multiplexer 72. Selected. When the read operation is instructed, the multiplexer 72 directly selects the output of the latch circuit 70. The column address counter 10 performs an increment operation in synchronization with YCLK. The burst end detection circuit 73 asserts the burst end signal BEND when the output address of the column address counter 10 reaches the number of bursts with respect to the burst start address preset in the latch circuit 70.

  A start address latch circuit 74 is provided separately from the latch circuit 70, and holds the least significant bit AY0 of the column address. A selection signal DICY0 corresponding to the logic value of the signal CAY0W held thereby is generated by the one-shot pulse generation circuit 75 in synchronization with the clock signal DICLK.

  Here, the configuration for data writing in the control circuit 12 will be described in an organized manner. When a write operation is instructed by a write command and the signal WTY is pulse-changed, the signal WTY is latched in the latch circuit 65A in synchronization with the clock BCLKB, and the enable signal DIE of the data input buffer 30 is asserted high. . Thereafter, the write data supplied in synchronization with the data strobe signal DQS is input to the latch circuit 50 in synchronization with the signals DSCLKT and DSCLKB output from the input buffer 40 as illustrated in FIG. A timing signal DICLK for controlling the selection operation and the latch operation of the selector latch circuits 51 and 52 (see FIG. 6) for inputting the data output in parallel from the latch circuit 50 is generated by the write system decode circuit 65B of FIG. . A column clock signal YCLK for controlling the write address of data supplied from the selector latch circuits 51 and 52 to the input / output bus 2 in synchronization with the timing signal DICLK is output from the decode logic 65C in the command decode circuit 63 of FIG. Is done. Write data is written to the column address in synchronization with the column clock signal YCLK. The end of the address count operation of the write data for the number of bursts is detected by the burst end detection circuit 73 in FIG. 10, and the burst end signal BEND is pulse-changed. This change is a state in which the generation of the last write column address in the burst write is determined, and is equivalent to the end of the write operation in the column address system operation. In synchronization with this change, the signal BWT output from the mode state circuit 66 of FIG. 9 is negated, and the latch circuit 65A receiving it negates the enable signal DIE of the data input buffer 30. As a result, the differential input buffer 30 is deactivated by turning off its power switch MOS transistor Mn5 (see FIG. 4).

<< Write Operation Timing of DDR-SDRAM >>
FIG. 11 illustrates the write operation timing of the burst number 4 in the DDR-SDRAM 1.

  At time t0, a row address strobe / bank active command (bank active command Active) is issued in synchronization with the clock signal CLK, and a row address signal (X-Add) is supplied. By this bank active command, the signal ACTi of the selected memory bank is changed in pulse, and the signal BAi is asserted. Although not shown in particular, the word line corresponding to the row address signal is selected in the selected memory bank, and the storage information of the memory cell whose selection terminal is connected to the word line is read to each complementary bit line. And amplified by a sense amplifier.

  At time t1, a column address / write command (Write) is issued in synchronization with the clock signal CLK, and a column address signal (Y-Add) is supplied. By this column address / write command, the signals WTY, WT, RWWi are sequentially pulse-changed, and the enable control signal DIE of the differential input buffer 30 is asserted to a high level (time t2), whereby the differential input buffer 30 is inactivated. From state to active state.

  At this time, the data strobe signal DQS rises and changes within a tolerance of ± 0.25 Tck with respect to the rising edge of the clock signal CLK next to the time t1, and is synchronized with, for example, changes in the rising and falling edges of the DQS. Then, write data D1, D2, D3, and D4 are supplied. Tck is the period of the clock signal.

  When the write data D1 is supplied, the differential input buffer 30 is already activated, and the sequentially supplied data D1 to D4 are synchronized with the signals DSCLKT and DSCLKB output from the input buffer 40. Input to the latch circuit 50. The latch circuit 50 outputs D1 and D2 in parallel at time t3 and outputs D3 and D4 in parallel at time t4. For the data output in parallel, the selector latch circuits 51 and 52 (see FIG. 6) determine the input selection according to the logical value of the signal DICY0 in synchronization with the first change (time t2a) of the timing signal DICLK. In accordance with the determination result, write data is supplied from the selector latch circuits 51 and 52 to the input / output bus 2 (DINBY0Bj, DINBY0Tj) in synchronization with the subsequent change of the timing signal DICLK (time t3a, t4a).

  The write operation to the memory cell for the write data supplied to the I / O bus 2 is after time t3a, and the column address signal CAa for writing data D1 and D2 is column synchronized with the column clock signal YCLK (time t3b). Output from the address counter 10. The column address counter 10 outputs a column address signal CAa for writing data D3 and D4 in synchronization with a pulse change next to the column clock signal YCLK (time t4b). As a result, data D1, D2 and D3, D4 are written in a predetermined memory cell.

  The end of the address count operation of the write data for the number of bursts is detected by the burst end detection circuit 73, and the burst end signal BEND is pulse-changed at time t5. This change is a state in which the generation of the last write column address in the burst write is determined, and is equivalent to the end of the write operation in the column address system operation. Therefore, the mode state circuit 66 of FIG. 9 is synchronized with this change. The signal BWT output from the latch circuit 65 is negated, and the latch circuit 65A receiving it negates the enable signal DIE of the data input buffer 30. As a result, the differential input buffer 30 is deactivated.

  FIG. 12 shows the write operation timing of the SDR-SDRAM as a comparative example of FIG. The SDR-SDRAM is supplied with write data together with a column address / write command in synchronization with the clock signal CLK. For this reason, it is not in time to activate the data input buffer after instructing the write operation by the write command. Therefore, the data input buffer enable signal DIOFF is asserted to the low level in synchronization with the instruction of the row address system operation by the bank active command (the pulse change of the signal ACTi), thereby activating the data input buffer. This state is maintained until a precharge operation is instructed by the precharge command (Pre) (pulse change of the signal PREi). Therefore, until writing by a write command is instructed after bank activation, until a write operation is finished and a precharge operation is instructed, or only a read command is issued and no write command is issued after bank activation. Since the data input buffer does not need to be operated, the data input buffer continues to be activated during that time, so that power is wasted. If such activation control of the data input buffer is applied to the DDR-SDRAM 1 as it is, a large amount of power is unnecessarily consumed compared with the DDR-SDRAM 1 of FIG. 1 because of the SSTL interface specification of the data input buffer. Is expected.

  FIG. 13 shows an operation timing chart when the present invention is applied to an address input buffer. The example in FIG. 13 assumes a specification in which the address input timing of the DDR-SDRAM in FIG. 1 is delayed by one cycle of the clock signal CLK from the command input. That is, as illustrated in FIG. 13, after the bank active command (Active), the timing of the row address strobe is delayed by one cycle of the clock signal CLK, the row address signal (X-Add) is supplied, and the column address After the write command (Write), the column address strobe timing is set one cycle later than the clock signal CLK, and the column address signal (Y-Add) is supplied. At this time, the signal ACTi is pulse-changed in response to the bank active instruction, the signal WT is pulse-changed in response to the write operation instruction by the write command, and although not illustrated. The address input buffer activation control signal AIE is asserted to activate the address input buffer in synchronization with the pulse change of the read signal in response to the read operation instruction by the column address / read command. The deactivation of the address input buffer may be performed after the timing at which the address input operation by the address input buffer is completed. For example, it may be synchronized with a predetermined change in the column system clock signal CCLKB.

  If control for activating the address input buffer after instructing operation is performed, the power consumed by the address input buffer of the SSTL specification can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the input buffer whose activation is controlled after the operation is instructed is not limited to the data and address input buffers, but may be an input buffer for other control signals. Further, the SSTL specification input buffer is not limited to the differential input buffer described with reference to FIGS. 4 and 5 and can be appropriately changed. Further, the control logic for generating the enable control signal DIE for the data input buffer or the generation logic of the intermediate signal for generating it is not limited to the above, and can be changed as appropriate. The number of data input / output terminals of the SDRAM is not limited to 16 bits, but may be 8 bits, 4 bits, or the like. Also, the number of memory banks of the SDRAM, the memory mats of the memory banks, and the configuration of the memory array are not limited to the above and can be changed as appropriate.

  In the above description, the case where the invention made mainly by the present inventor is applied to the DDR-SDRAM, which is the field of use behind the invention, is described. However, the present invention is not limited to this, and for example, the DDR-SDRAM is on-chip. The present invention can also be widely applied to semiconductor devices called microcomputers, system LSIs or accelerators.

1 DDR-SDRAM
BNK0 to BNK3 Memory bank MC Memory cell WL Word line BL Bit line DIO0 to DIO3 Data input / output circuit RDEC0 to RDEC3 Row decoder CDEC0 to CDEC3 Column decoder 2 Input / output bus 3 Data input circuit 4 Data output circuit DQ0 to DQ15 Data input / output terminal A0 to A14 Address input terminal 5 Address buffer 6 Row address latch 7 Column address latch 8 Bank selector 9 Mode register 10 Column address counter 12 Control circuit CLK, CLKb Clock signal DQS Data strobe signal 30 Differential input buffer Mn5 Power switch MOS transistor VREF Reference voltage DIE enable control signal 50 Latch circuit 50A First data latch circuit 50B Second data latch circuit 50 C third data latch circuit 51, 52 selector latch circuit

Claims (1)

A first input buffer connected to the address terminal;
A clock terminal for receiving a clock signal as a reference for data input;
A second input buffer for receiving a clock signal connected to the clock terminal, and the first input buffer is activated when an active command, a read command, or a write command is input, and an address input operation is performed. A synchronous semiconductor memory device, wherein the synchronous semiconductor memory device is deactivated after waiting for completion .

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