JP5304510B2 - Arbitration device, bus access arbitration program, and bus access arbitration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve transfer efficiency in transferring data to a common bus. <P>SOLUTION: An arbitration device holds a changeover time to be required for changing-over right to access to the common bus among a plurality of DSPs, and obtains the respective phase shift values of a plurality of DSPs, based on the change-over time and temperature information of the DSPs, which is received when the temperature of the DSPs is equal to or higher than a prescribed threshold, and then, generates and outputs different clocks by each DSP through the use of a reference clock transmitted by an oscillator and the obtained phase shift values. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a bus access arbitration device such as a computer, a bus access arbitration program, and a bus access arbitration method.

  Conventionally, when a device connected to a common bus accesses the common bus, a bus access arbitration device is used to prevent a plurality of devices from operating simultaneously and to avoid data collision. (Hereinafter referred to as “arbiter”) is used. The devices connected to the common bus include, for example, a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), a CPU (Central Processing Unit), or an MPU (Micro Processing Unit). There are arithmetic processing devices.

  Here, an example of a system configuration including the arbitrating device will be described with reference to FIG. FIG. 9 is a diagram illustrating a configuration example of a system including an arbitration device according to the related art. In FIG. 9, a DSP is described as an example of a device connected to a common bus. FIG. 9 illustrates a case where twelve DSPs, DSP1 to DSP12, access a common bus.

  For example, as illustrated in FIG. 9, a system including an arbitration device includes an arbitration device, an oscillator, DSP1 to DSP12, a memory controller, and a storage device. Among these, the storage device is, for example, a flash memory capable of reading and writing data and erasing data.

  The oscillator outputs, for example, a clock (CLK1) for operating the memory controller and DSP1 to DSP12. Further, the DSP1 to DSP12, for example, send bus right acquisition request signals (Req-1 to Req-c) to the arbitration device in order to access a common bus. Then, for example, when a bus right acquisition request signal is simultaneously input from a plurality of DSPs, the arbitration device applies the bus right acquisition permission response signals (Gnt-1 to Gnt-c) in order by round robin scheduling or the like. To the DSP.

  On the other hand, the DSP1 to DSP12 that have received the bus right acquisition permission response signal access the common bus and transfer data to the memory controller. Then, the memory controller stores the data transferred by the DSP1 to DSP12 in the storage device.

  Recently, when a shared memory is accessed by a plurality of bus masters, there is a technique for shortening the bus access waiting time by controlling arbitration while holding write data in a buffer in the memory controller.

JP 2005-316546 A

  However, the above-described conventional technique has a problem that the time required for data transfer to a common bus increases.

  Here, the access operation timing to the common bus by the DSP will be described with reference to FIG. FIG. 10 is a diagram for explaining an example of an access operation timing to a common bus by a DSP according to the related art. In FIG. 10, the access operation timing to the common bus by the DSP1 to DSP3 will be described.

  For example, as shown in FIG. 10, DSP1 to DSP3 send bus right acquisition request signals (Req-a to Req-c) to the arbitration device based on the clock (CLK1) by the oscillator. Then, the arbitrating device sends a bus acquisition permission response signal (Gnt-a to Gnt-c) to the corresponding DSP in the order of DSP1, DSP2, DSP3 by round robin scheduling or the like.

  Subsequently, the DSP 1 that has received the bus right acquisition permission response signal first accesses the common bus and transfers D1, D2, and D3, which are data of the DSP 1, to the memory controller. Thereafter, the DSP 2 receives the bus right acquisition permission response signal, accesses the common bus, and transfers D1, D2, and D3, which are data of the DSP 2, to the memory controller. Similarly, the DSP 3 receives the bus right acquisition permission response signal, accesses the common bus, and transfers the data D1, D2, and D3 of the DSP 3 to the memory controller.

  However, DSP1 to DSP3 access the common bus in synchronization with the clock and transfer data to the memory controller. However, when switching access to the common bus, the output delay of the element that drives the signal, Wiring delay occurs. In addition, when switching is performed continuously, it is desirable to provide an interval of one clock because a signal collision, that is, element destruction caused by transferring data to the common bus at the same timing may occur.

  Next, a delay time including an output delay and a wiring delay and an interval (loss time) of one clock provided to prevent signal collision will be described with reference to FIG. FIG. 11 is a diagram for explaining an example of delay time and loss time according to the prior art. Specifically, FIG. 11 is an enlarged view of a portion surrounded by a square in FIG. 10 when switching between the DSP 1 and the DSP 2 shown in FIG.

  For example, as shown in FIG. 11, a “delay time” including an output delay and a wiring delay occurs when switching between DSP1 and DSP2. In addition, since the delay time occurs, when switching is performed continuously, a signal collision may occur, so an interval of one clock, that is, a “loss time” shown in FIG. 11 is provided.

  In short, in FIG. 10 and FIG. 11, a loss time of 1 clock is given for every 3 clocks required for data transfer of D1 to D3. Therefore, together with the above delay time, about 25% of the 4 clocks. Loss time will occur.

  By the way, in order to avoid a signal collision in the bus, it is conceivable to delay by wiring. Therefore, a case where adjustment is performed by wiring delay will be described with reference to FIG. FIG. 12 is a diagram for explaining an example in which adjustment is performed by wiring delay in order to avoid a signal collision in a bus according to the prior art. In addition, FIG. 12 demonstrates the case where it switches from DSP1 to DSP2. The data lines of DSP1 and DSP2 are physically the same wiring, but in FIG. 12, the data lines of DSP1 and DSP2 will be described separately for convenience of explanation.

  For example, as shown in FIG. 12, it takes 1.5 ns (nano-second) to 6.5 ns from the time when the data line buffer of the DSP 1 closes the gate to the end of data transfer (see A in FIG. 12). On the other hand, it takes 1.5 ns to 7.6 ns after the data line buffer of the DSP 2 opens the gate until the data transfer is started (see B in FIG. 12). In A and B, an overlapping time is generated, and this overlapping time becomes a signal collision time on the bus.

  Also, as shown in the lower side of FIG. 12, for example, when the gate signal of DSP2 is delayed by wiring, it is possible to avoid signal collision at the end of data transfer of DSP1 and at the start of data transfer of DSP2. it can. However, a signal collision occurs at the end of the DSP2 data transfer.

  In short, a device such as a DSP may operate with a common clock, and data collision may occur within one clock required for bus switching. For this reason, in order to prevent data collision, time is taken until the next clock event. As a result, in the above-described conventional technology, the time required for data transfer to the common bus increases.

  Therefore, the technology disclosed in the present application has been made in view of the above, and an arbitration device, a bus access arbitration program, and a bus access arbitration method capable of improving the transfer efficiency of data transfer to a common bus The purpose is to provide.

In order to solve the above-described problems and achieve the object, the arbitration device disclosed in the present application includes a delay time, which is an output delay of the arithmetic processing device, for each of a plurality of arithmetic processing devices that give access to the bus, There is a switching time holding unit that holds a switching time that is a sum of the data output from the processing device and the holding time until the element is determined . The arbitrating device also includes a phase shift value deriving unit that obtains a phase shift value of each of the plurality of arithmetic processing devices based on the switching time. In addition, the arbitration device includes a synchronization signal output unit that generates and outputs a different synchronization signal for each of the plurality of arithmetic processing devices using the reference synchronization signal sent by the oscillator and the phase shift value.

  According to one aspect of the arbitration device, the bus access arbitration program, and the bus access arbitration method disclosed in the present application, it is possible to improve the transfer efficiency of data transfer to a common bus.

FIG. 1 is a diagram illustrating a configuration example of a system including an arbitration device according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of the arbitrating device according to the first embodiment. FIG. 3A is a diagram illustrating an example of information held in the 8-bit register. FIG. 3B is a diagram illustrating an example of information held in the slave information table. FIG. 4 is a diagram illustrating an example of a detailed circuit diagram of the PLL phase shifter according to the first embodiment. FIG. 5 is a diagram for explaining an example of an access operation timing to the common bus by the DSP according to the first embodiment. FIG. 6 is a diagram illustrating a detailed example of the operation timing at the time of switching between the DSPs according to the first embodiment. FIG. 7 is a flowchart illustrating an example of the flow of arbitration processing according to the first embodiment. FIG. 8 is a diagram illustrating an example of a computer that executes a bus access arbitration program. FIG. 9 is a diagram illustrating a configuration example of a system including an arbitration device according to the related art. FIG. 10 is a diagram for explaining an example of an access operation timing to a common bus by a DSP according to the related art. FIG. 11 is a diagram for explaining an example of delay time and loss time according to the prior art. FIG. 12 is a diagram for explaining an example in which adjustment is performed by wiring delay in order to avoid a signal collision in a bus according to the prior art.

  Embodiments of an arbitration device, a bus access arbitration program, and a bus access arbitration method disclosed in the present application will be described below with reference to the accompanying drawings. In addition, this invention is not limited by the following examples.

[System configuration]
First, the configuration of a system including the arbitrating device according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration example of a system including an arbitration device according to the first embodiment. In FIG. 1, a DSP is given as an example of a device connected to a common bus, and a case where 12 DSPs DSP1 to DSP12 access a common bus will be described.

  For example, as illustrated in FIG. 1, a system including an arbitration device includes an arbitration device, an oscillator, DSP1 to DSP12, a memory controller, and a storage device. Among these, the storage device is, for example, a flash memory capable of reading / writing and erasing data.

  Further, the oscillator sends, for example, a reference clock serving as a clock reference for operating the memory controller and the DSP1 to DSP12 to the arbitration device. Further, the DSP1 to DSP12, for example, send bus right acquisition request signals (Req-1 to Req-c) to the arbitration device in order to access a common bus.

  Then, for example, when a bus right acquisition request signal is simultaneously input from a plurality of DSPs, the arbitration device synchronizes with the clock (CLK1 to CLK12) sent to each DSP, and acquires a bus right acquisition permission response signal (Gnt-1). -Gnt-c) to the corresponding DSP.

  The clock transmitted from the arbitration device to each DSP is transmitted at the same phase as the reference clock transmitted from the oscillator or at a phase shifted by a predetermined time from the reference clock. More specifically, the arbitrating device holds the switching time required for switching the access right to the common bus among the DSP1 to DSP12 in the phase value register.

  This switching time is, for example, the minimum data determination time required from closing the DSP1 gate to opening the DSP2 gate when switching access rights between the DSP1 and the DSP2. Then, the arbitrating device obtains the phase shift values of the DSP1 to DSP12 based on the switching time.

  Subsequently, the arbitrating device generates different clocks (CLK1 to CLK12) in the DSP1 to DSP12 by using the reference clock transmitted from the oscillator and the obtained phase shift value, and outputs them to the corresponding DSP. It should be noted that the derivation of the phase shift value and the generation and output of a clock that are different for each DSP are executed by a phase shifter.

  On the other hand, the DSP1 to DSP12 having received the bus acquisition response signal access the common bus and transfer data to the memory controller. Then, the memory controller stores the data transferred by the DSP1 to DSP12 in the storage device.

  In other words, the arbitration device holds the minimum switching time required when switching access rights between DSPs, and uses the phase shift value of each DSP obtained based on the switching time and the reference clock sent by the oscillator. The DSP generates different clocks. Then, the arbitrating device outputs the generated clock to the corresponding DSP. As a result, the arbitration device transfers data transfer to the common bus by the DSP as compared with the prior art in which data collision occurs when switching access rights between DSPs because each DSP operates according to a common clock. Efficiency can be improved.

[Configuration of arbitration device]
Next, the configuration of the arbitration device according to the first embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration example of the arbitrating device according to the first embodiment.

  For example, as illustrated in FIG. 2, the arbitrating device 100 includes an 8-bit register 111, a slave information table 112, a state monitoring unit 121, an S / P conversion (Serial / Parallel Conversion) unit 122, and a slave information processing unit 123. And an 8-bit addition circuit 124 and a PLL phase shifter 125. Then, the arbitrating device 100 grants the access right to the common bus to the corresponding arithmetic processing device based on the request for the access right to the common bus by the plurality of arithmetic processing devices. Further, the arbitration device receives a reference clock that is a reference sent by the oscillator.

  For example, as illustrated in FIG. 3A, the 8-bit register 111 holds a switching time (Hold time) required when switching access rights to a common bus among DSP1 to DSPn (n is a natural number) as an arithmetic processing unit. . For example, the 8-bit register 111 holds a decomposition value obtained by dividing the switching time (Hold time) of DSP1 to DSPn by the granularity of 1 tap = 100 ps (pico second) in 8 bits (binary number).

  Specifically, the 8-bit register 111 obtains 1000 ps / 100 ps / tap = 10 tap (decimal number) from the hold time of DSP 1 = 1.0 ns, and holds “00001010” obtained by converting the obtained 10 tap into a binary number. To do. The tap is a minimum unit capable of phase shift. The value held in the 8-bit register 111 is set by software under CPU (Central Processing Unit) control. In the CPU control, for example, it is determined by “device delay time” + “substrate mounting information (delay time determined from pattern length or substrate material)”.

  An example of information held in the 8-bit register 111 is an 8-bit parameter “00001010” for the switching time “Hold = 1.0 ns” in the DSP 1. FIG. 3A is a diagram illustrating an example of information held in the 8-bit register 111.

  In addition, the switching time (hold time) held in the 8-bit register 111 includes a wiring delay obtained by desktop calculation. This wiring delay is obtained as “1 mm = 7 ps”, for example, when the printed board material is FR4 which is the standard of the base material of the printed board. Further, in switching between the arithmetic processing units, it is rare to operate at 256 tap which is the maximum value of delay, and therefore, a typical value may be set.

  For example, as shown in FIG. 3B, the slave information table 112 associates Tj (junction temperature) obtained by notification from a temperature sensor or the like on the slave side of the arbitrating device 100 with a switching time (Hold time). Hold. Specifically, the slave information table 112 holds values converted into binary numbers (8 bits) for each temperature. Note that the slave side is an external device that operates separately from the arbitration device 100 and a system including the arbitration device 100.

  Examples of information held in the slave information table 112 are Tj (junction temperature) = 61 ° C. to 65 ° C. and 65 ° C. Hold “00000001”. FIG. 3B is a diagram illustrating an example of information held in the slave information table 112.

  For example, the state monitoring unit 121 acquires temperature information that is an external environment of each of the DSPs 1 to DSPn and notifies the S / P conversion unit 122 of the temperature information. Specifically, the state monitoring unit 121 acquires ALERT from the temperature sensor on the slave side and temperature information from the slave side via an I2C (Inter-Integrated Circuit) bus. The temperature information acquired by the state monitoring unit 121 is 8-bit serial data.

  At this time, the state monitoring unit 121 does not always acquire the temperature information of each of the DSP1 to DSPn, but acquires it when ALERT is detected by the temperature sensor, so that the process by the DSP1 to DSPn is not affected. Regardless, temperature information is prevented from being acquired.

  Further, ALERT is a threshold value set in advance in the temperature sensor. For example, in this embodiment, it is set to 60 ° C. Therefore, the temperature sensor transmits an ALERT signal to the state monitoring unit 121 when it exceeds a preset threshold of 60 ° C., and negates the ALERT signal when the temperature sensor falls below 60 ° C.

  For example, the S / P conversion unit 122 converts the 8-bit serial data notified by the state monitoring unit 121 into 8-bit parallel data and notifies the slave information processing unit 123 of the converted data.

  For example, the slave information processing unit 123 stores temperature information as slave information notified by the S / P conversion unit 122 in the slave information table 112. The slave information processing unit 123 notifies the 8-bit addition circuit 124 of, for example, 8-bit temperature information stored in the slave information table 112. As an example of the information notified to the 8-bit addition circuit 123 by the slave information processing unit 123, when 62 ° C. is sensed by the temperature sensor during the operation of the DSP 1, Hold = 1 tap of 65 ° C., that is, “0000001”.

  The 8-bit addition circuit 124 acquires, for example, “00001010”, which is the binary time of the DSP1 Hold time held in the 8-bit register 111, and the hold “00000001” at 65 ° C. of the DSP1 notified by the slave information processing unit 123. To do. Then, the 8-bit addition circuit 124 adds these values “000001010” and “00000001” to obtain the phase shift value “00001011” of the DSP 1 and notifies the PLL phase shifter 125 of it. That is, the set value for DSP 1 is 10 tap + 1 tap = 11 tap.

  For example, the PLL phase shifter 125 generates a clock for the DSP 1 based on the reference clock transmitted by the oscillator and the phase shift value “00001011” of the DSP 1 obtained by the 8-bit addition circuit 124, and generates a clock for the DSP 1. Output.

  Here, a detailed circuit diagram of the PLL phase shifter 125 will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of a detailed circuit diagram of the PLL phase shifter 125 according to the first embodiment.

  For example, as illustrated in FIG. 4, the PLL phase shifter 125 includes 256 delay elements corresponding to 8 bits and a selector that selects a delay element to be used. Among these elements, each Delay element plays a role of delaying a signal by 1 tap (100 ps), for example.

  To give a specific example, the PLL phase shifter 125 selects the eleventh delay element by which the selector has the phase shift value “00001011”. Then, the PLL phase shifter 125 outputs a clock delayed by 11 tap (1.1 nsec) from the reference clock to the DSP 1.

  In short, the arbitrating device 100 determines the reference clock to which the bus right acquisition permission response signal for the DSP is to be returned based on a fixed parameter as a switching time held in advance and a variable parameter as temperature information that varies depending on the external environment. The value of tap shift is processed in units of 8 bits. Although the example in which the clock is output to the DSP 1 has been described above, the arbitrating device 100 performs the same processing on the DSP 2 and DSP 3 that are different from the DSP 1 and outputs the clock to each DSP.

[Operation timing]
Next, the access operation timing to the common bus by the DSP will be described with reference to FIG. FIG. 5 is a diagram for explaining an example of an access operation timing to the common bus by the DSP according to the first embodiment. In FIG. 5, the access operation timing to the common bus by the DSP1 to DSP3 will be described.

  For example, as shown in FIG. 5, DSP1 to DSP3 are operated by different clocks CLK1-a, CLK1-b, and CLK1-c, respectively. As described above, these clocks are clocks shifted from the reference clock based on the minimum time required for switching between the DSPs and the temperature information caused by the external environment of each DSP.

  When the bus right acquisition request signals (Req-a to Req-c) from the DSP1 to DSP3 are transmitted, the bus right acquisition permission response signals (Gnt-a to ~) synchronized with the clocks corresponding to the DSP1 to DSP3. Gnt-c) Access to the bus in order from DSP 1 at the timing of return. In FIG. 5, after the data D1, D2, and D3 transferred when the bus is accessed by the DSP1, the data D1, D2, and D3 are transferred by the DSP2, and after the data transfer by the DSP2, the data D1, D2, and D3 are transmitted by the DSP3. Shows an example in which is transferred.

  Next, the details of the operation timing at the time of switching between DSPs will be described with reference to FIG. FIG. 6 is a diagram illustrating a detailed example of the operation timing at the time of switching between the DSPs according to the first embodiment. Specifically, FIG. 6 is an enlarged view of a portion surrounded by a square in FIG. 5 when switching between the DSP 1 and the DSP 2 shown in FIG.

For example, as shown in FIG. 6, at the time of switching between DSP1 and DSP 2, and the output delay, etc. "delay time", immediately after the "Hold time" required for the element to determine the data, in the switching destination A DSP2 clock is shifted. As a result, as shown in FIG. 6, the “loss time” can be reduced from the time point of the transfer data of the conventional DSP 2 that requires a space of one clock by switching between the DSP 1 and the DSP 2.

  The total time of “delay time” and “hold time” can be changed by setting the 8-bit register 111. For this reason, even when the device such as the DSP and the operation speed of the device are changed, it is possible to flexibly cope with the change.

  In short, since the data interval at the time of switching the access right to the bus between devices is only “Hold time”, the delay amount at the time of switching can be minimized. In addition, the data transfer speed can be expected to be improved by about 25% as compared with the conventional technique that requires a space of one clock when transferring three clocks.

[Arbitration processing according to embodiment 1]
Next, the flow of the arbitration process according to the first embodiment will be described with reference to FIG. FIG. 7 is a flowchart illustrating an example of the flow of arbitration processing according to the first embodiment.

  For example, as shown in FIG. 7, when the arbitration device 100 receives an alarm from the temperature sensor on the slave side (Yes in step S101), the arbitration device 100 acquires temperature information from the slave side via the I2C bus (step S102). . Note that when the alarm by the temperature sensor is not received (No at Step S101), the arbitrating device 100 is in a state of waiting for reception of the alarm.

  Then, the arbitrating device 100 performs serial / parallel conversion on the acquired temperature information (step S103). Subsequently, the arbitrating device 100 stores the serial / parallel converted temperature information in the slave information table 112 (step S104).

  After that, the arbitrating device 100 adds the 8-bit temperature information stored in the slave information table 112 and the 8-bit Hold time of the device held in advance, and outputs a setting value for shifting (step S105). Note that the arbitrating device 100 generates a clock by a PLL phase shifter based on the obtained shift information and outputs it to the corresponding device.

[Effects of Example 1]
As described above, the arbitrating device 100 holds the minimum required bus transfer switching time between a plurality of devices, and based on the switching time and the temperature information according to the external environment in the plurality of devices. Find the value to shift from. Then, the arbitrating device 100 determines and outputs a clock to be sent to each device while shifting from the reference clock based on the obtained shift value. As a result, the arbitrating device 100 can improve the transfer efficiency of data transfer to the common bus when a plurality of devices access the common bus and perform data transfer.

  The embodiments of the arbitration device and the bus access arbitration method disclosed in the present application have been described so far, but may be implemented in various different forms other than the above-described embodiments. Therefore, different embodiments will be described in (1) using only fixed parameters, (2) configuration of the arbitration device, and (3) program.

(1) Using only fixed parameters In the first embodiment, a clock to be output to each device is determined based on a fixed parameter as a switching time held in advance and a variation parameter as temperature information that varies depending on the external environment. However, it is also possible to determine the clock using only fixed parameters.

  For example, the arbitrating device holds a switching time required when switching access rights to a common bus among a plurality of DSPs, and obtains a phase shift value of each of the plurality of DSPs based on the switching time. Then, the arbitrating device generates and outputs a different clock for each of the plurality of DSPs using the reference clock transmitted by the oscillator and the obtained phase shift value. When the ALERT from the temperature sensor is not notified, the arbitration device determines the clock using only the fixed parameter as the switching time.

(2) Configuration of Arbitration Device In addition, information including the processing procedure, control procedure, specific name, various data and parameters shown in the document and drawings (for example, in the 8-bit register 111 or the slave information table 112) The information to be held can be arbitrarily changed unless otherwise specified.

  Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various burdens or usage conditions. Can be integrated. Further, all or a part of each processing function performed in each device may be realized by a CPU and a program that is analyzed and executed by the CPU, or may be realized as hardware by wired logic.

(3) Program In the above embodiment, the case where various types of processing are realized by hardware logic has been described. However, it may be realized by executing a program prepared in advance by a computer. In the following, an example of a computer that executes a bus access arbitration program having the same function as that of the arbitration device 100 described in the above embodiment will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of a computer that executes a bus access arbitration program.

  As shown in FIG. 8, the computer 11 as the arbitrating device 100 includes an HDD 13, a CPU 14, a ROM 15, a RAM 16, and the like that are connected by a bus 18.

  In the ROM 15, a bus access arbitration program that exhibits the same function as the arbitration device 100 described in the above embodiment, that is, as shown in FIG. 8, a phase shift value derivation program 15a and a synchronization signal output program 15b, Stored in advance. Note that these programs 15a to 15b may be integrated or distributed as appropriate, as with each component of the arbitrating device 100 shown in FIG.

  Then, when the CPU 14 reads out and executes these programs 15a to 15b from the ROM 15, as shown in FIG. 8, the programs 15a to 15b function as a phase shift value derivation process 14a and a synchronization signal output process 14b. To come. The processes 14a to 14b correspond to the 8-bit addition circuit 124 and the PLL phase shifter 125 shown in FIG.

  Then, the CPU 14 executes a bus access arbitration program based on data recorded in the RAM 16 (for example, switching time required for switching the access right to the bus, temperature information of the arithmetic processing unit, etc.).

  Note that the programs 15a to 15b are not necessarily stored in the ROM 15 from the beginning. For example, a flexible disk (FD), a CD-ROM, a DVD disk, a magneto-optical disk, It is connected to the computer 11 via a “portable physical medium” such as an IC card, or a “fixed physical medium” such as an HDD provided inside or outside the computer 11, and further via a public line, the Internet, a LAN, a WAN, etc. Each program may be stored in “another computer (or server)” or the like, and the computer 11 may read and execute each program from now on.

100 Arbiter 111 8-bit register 112 Slave information table 121 Status monitoring unit 122 S / P conversion unit 123 Slave information processing unit 124 8-bit addition circuit 125 PLL phase shifter

Claims (5)

An arbitration device that grants an access right to the common bus based on a request for an access right to a common bus by a plurality of arithmetic processing units,
For each arithmetic processing unit, a switching time holding for holding a switching time that is a sum of a delay time that is an output delay of the arithmetic processing unit and a holding time until an element determines data output from the arithmetic processing unit. And
A phase shift value deriving unit for obtaining a phase shift value of each of the plurality of arithmetic processing devices based on a switching time of each arithmetic processing device held by the switching time holding unit ;
An arbitration device comprising: a synchronization signal output unit that generates and outputs a different synchronization signal for each of the plurality of arithmetic processing devices using a reference synchronization signal transmitted by an oscillator and the phase shift value .   2. The phase shift value deriving unit obtains a phase shift value of each of the plurality of arithmetic processing devices based on the switching time and temperature information of the plurality of arithmetic processing devices. Arbitration device.   When the phase shift value deriving unit receives that the temperatures of the plurality of arithmetic processing devices are equal to or higher than a predetermined threshold, based on the temperature information of the plurality of arithmetic processing devices and the switching time, The arbitration device according to claim 1, wherein a phase shift value of each of the plurality of arithmetic processing devices is obtained. A bus access arbitration program as an arbitration device that grants an access right to the common bus based on a request for access right to a common bus by a plurality of arithmetic processing units,
Based on the switching time that is the sum of the delay time that is the output delay of the arithmetic processing device and the retention time until the element determines the data output from the arithmetic processing device, the phase of each of the arithmetic processing devices A phase shift value derivation procedure for obtaining the shift value;
Using a reference synchronization signal sent by an oscillator and the phase shift value, and causing a computer to execute a synchronization signal output procedure for generating and outputting a different synchronization signal for each of the plurality of arithmetic processing units. Bus access arbitration program. A bus access arbitration method as an arbitration device that grants an access right to the common bus based on a request for access right to a common bus by a plurality of arithmetic processing units,
Based on the switching time that is the sum of the delay time that is the output delay of the arithmetic processing device and the retention time until the element determines the data output from the arithmetic processing device, the phase of each of the arithmetic processing devices A phase shift value deriving step for obtaining a shift value;
And a synchronization signal output step for generating and outputting a different synchronization signal for each of the plurality of arithmetic processing units using the reference synchronization signal transmitted by an oscillator and the phase shift value. Access mediation method.

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