JP5303161B2 - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has reduced defects of an external appearance such as cracking, chapping, and chipping due to external stress, and to improve the manufacture yield of a semiconductor device which is made thin. <P>SOLUTION: The semiconductor device 112 has a substrate 109, a semiconductor integrated circuit portion 101 provided on one surface of the substrate, and a resin layer 110 continuously covering the other surface and a side surface of the substrate and side surfaces of semiconductor integrated circuit portions. A semiconductor integrated circuit portion formation surface of the substrate where the plurality of semiconductor integrated circuit portions are formed, and a fixed substrate are fixed with wax, and the substrate is parted for each of the semiconductor integrated circuit portions. A resin layer is formed covering the substrate where the individually parted semiconductor integrated circuit portions are formed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device having a photoelectric conversion element.

Among various sensors, one having sensitivity in the visible light region with a wavelength of 400 nm to 700 nm is called an optical sensor or a visible light sensor. Optical sensors or visible light sensors are known for use in detecting information by detecting an optical signal and for controlling the operation of an electronic device by detecting the brightness of the surrounding environment.

For example, in a mobile phone or a television device, an optical sensor is used to adjust the brightness of a display screen according to the brightness of the surrounding environment where the display screen is placed.

Such a semiconductor device such as an optical sensor or a visible light sensor is formed by forming a transistor on a substrate such as glass or a wafer and then cutting (dividing) the substrate.

In general, the substrate cutting step is performed by forming a groove on the surface of the substrate (referred to as “scribe”) using a scribing device, and cutting the substrate starting from the groove. As a scribing method, there is a method using a laser in addition to a mechanical method such as a diamond cutter, and after the local heating by the laser, the irradiation region is rapidly cooled, and cracks are generated using the thermal stress generated in the substrate. Is forming. In order to avoid thermal distortion of the substrate that occurs in the rapid cooling process, a method of eliminating the rapid cooling process using a short pulse laser as a laser has been proposed (see, for example, Patent Document 1).
JP 2007-331983 A

However, the semiconductor device may be damaged by external stress such as pressure applied in the manufacturing process of the semiconductor device other than the substrate cutting process and in the inspection process. Breakage such as cracks, cracks, and cracks occurs more frequently as the substrate becomes thinner and the strength decreases.

Further, a blade (dicing blade) such as a dicer used as a scribing device is expensive and needs to be replaced because it is worn when used multiple times. Therefore, it is difficult to reduce the manufacturing cost.

In view of the above problems, an object is to reduce damage to a semiconductor device such as a crack, a crack, and a chip due to external stress. Another object is to reduce the thickness of a substrate over which a semiconductor device is provided. Another object is to improve the manufacturing yield of a thinned semiconductor device. Another object is to reduce the manufacturing cost of a thinned semiconductor device.

According to the present invention, a plurality of semiconductor devices are taken out in a chip shape by dividing a substrate provided with a plurality of semiconductor integrated circuit portions for each semiconductor integrated circuit portion. After the substrate is divided into individual semiconductor integrated circuit portions, a surface of the substrate where the semiconductor integrated circuit portion is not formed, side surfaces, and a resin layer that covers the side surfaces of the semiconductor integrated circuit portion are formed. Further, the resin layer is divided for each semiconductor integrated circuit portion, and a plurality of separated semiconductor devices are manufactured. The step of dividing the substrate and the resin layer is performed by fixing the semiconductor integrated circuit portion on the fixed substrate with wax.

The semiconductor integrated circuit portion is an integrated circuit portion including a plurality of semiconductor elements, and is configured by stacking thin films such as an insulating film, a semiconductor film, and a conductive film. In the present invention, a plurality of semiconductor integrated circuit portions are provided side by side on the same substrate before division.

Therefore, the semiconductor device of the present invention has a configuration in which one surface and the end (side surface) of the substrate opposite to the formation surface of the semiconductor integrated circuit portion, and the end portion (side surface) of the semiconductor integrated circuit portion are continuously covered with the resin layer. It is. Therefore, since the resin layer also functions as a shock absorbing layer from external stress such as pressure applied in the manufacturing process or inspection process, defects such as scratches and cracks in the semiconductor device are reduced, and the reliability of the semiconductor device is increased. Can do.

In the method for dividing a semiconductor device, first, the thickness of the substrate is processed to reduce the process time required for the division, and the wear of a processing means such as a dicer used for the division is reduced. In the dividing step, the substrate is first divided (divided), then a resin layer is formed, and the resin layer is divided (divided) between the substrates. By dividing the substrate and the resin layer in separate steps, a plurality of small semiconductor devices can be manufactured from the same substrate.

When a light-transmitting material is used for the substrate and the resin layer, light can pass through the light-transmitting substrate and the light-transmitting resin layer and be irradiated to the photoelectric conversion element provided in the semiconductor integrated circuit portion.

Further, when a chromatic colored layer functioning as a color filter is used as the resin layer, a color sensor can be obtained. A transparent resin layer may be further laminated as a shock absorbing layer on the chromatic colored layer.

The chromatic color is a color excluding achromatic colors such as black, gray, and white, and the colored layer is formed of a material that transmits only the colored chromatic light in order to function as a color filter. As the chromatic color, red, green, blue, or the like can be used. Further, cyan, magenta, yellow (yellow), or the like may be used.

A plurality of divided small semiconductor devices may be mounted on an interposer or the like. Since a plurality of semiconductor devices mounted on the interposer can be freely selected, a semiconductor device including a plurality of color sensors is mounted on the interposer by mounting semiconductor devices having different chromatic color translucent resins. Can be produced.

For example, a semiconductor device including a red light-transmitting resin, a semiconductor device including a green light-transmitting resin, and a semiconductor device including a blue light-transmitting resin are mounted on an interposer, and red (R), green ( A semiconductor device that detects light of three colors G) and blue (B) can be manufactured.

In addition, when mounting on the interposer, a chip-shaped semiconductor device can be inspected and only good products can be selected and mounted on the interposer. Therefore, the yield of the semiconductor device is improved in the manufacturing process. In particular, in the case where the chip-shaped semiconductor device has a semiconductor integrated circuit portion including a complicated configuration such as an amplifier circuit, the chip-shaped semiconductor device may be defective, so that the chip-shaped semiconductor before mounting on the interposer. It is beneficial to be able to inspect equipment for defects. Further, a high-quality semiconductor device can also be manufactured by selecting a high-quality chip-shaped semiconductor device among non-defective products and mounting it on an interposer.

The chip-shaped semiconductor device can be mounted on the interposer with solder or an anisotropic conductive layer. In addition, it is preferable to provide a resin between the chip-shaped semiconductor device and the interposer to fix the chip because the fixing strength is improved.

Similarly, the semiconductor device of the present invention can be mounted on another mounting substrate with solder or an anisotropic conductive layer. Also in this case, it is preferable to provide a resin between the semiconductor device and the mounting substrate for fixing, because the fixing strength is improved.

If the substrate is a light-transmitting substrate, the resin layer in contact with the substrate is a chromatic light-transmitting resin layer, and a light-transmitting resin layer that functions as a protective layer is formed on the light-transmitting resin layer, shock absorption is also achieved. The effect is that the deterioration of the chromatic color translucent resin layer can be prevented. Moreover, the film thickness of the translucent resin layer which functions as an impact absorption layer may be thicker than the translucent resin layer which functions as a colored layer. By forming the translucent resin layer functioning as the shock absorbing layer thick, the shock resistance can be further improved as the shock absorbing layer. On the other hand, since the chromatic translucent resin layer functions as a colored layer (color filter), the optimum film thickness may be appropriately controlled in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. .

In the case where the resin layers are stacked, the first-layer (also referred to as a lower layer) resin layer formed in contact with the substrate may be divided in the same process as the substrate. For example, after forming a chromatic color translucent resin layer on a substrate and dividing the substrate and the chromatic color translucent resin layer, a translucent resin layer may be further laminated as a protective layer. In this case, the edge part of the chromatic color translucent resin layer divided | segmented by the process same as a board | substrate corresponds with the edge part of a board | substrate.

As described above, since the semiconductor device of the present invention has a shape in which a resin layer is selectively provided, it is easy to determine the top and bottom of the semiconductor device, and false recognition can be reduced even in automatic operation by a machine.

In the semiconductor device, the semiconductor integrated circuit portion includes an amplifier circuit that amplifies the output of the photoelectric conversion element, and the photoelectric conversion element has a structure in which a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer are stacked. A structure including

In this specification, an i-type semiconductor means that a p-type or n-type impurity contained in the semiconductor has a concentration of 1 × 10 ²⁰ cm ⁻³ or less, and oxygen and nitrogen have a concentration of 1 × 10 ²⁰ cm ⁻³ or less. It means a semiconductor whose photoconductivity is 100 times or more of dark conductivity. This i-type semiconductor includes those containing an impurity element belonging to Group 13 or Group 15 of the periodic table. That is, an i-type semiconductor exhibits weak n-type conductivity when an impurity element for the purpose of controlling valence electrons is not intentionally added. Therefore, in an i-type semiconductor layer, an impurity element imparting p-type is not present. Including those added intentionally or unintentionally at the same time as film formation or after film formation.

In the step of dividing the substrate and the resin layer, a dicer, a scriber or the like can be used as a cutting tool, and a dicer is preferably used. A dicing blade is used in the step of dividing the substrate and the resin layer, and the dicing blade in the step of dividing the substrate uses a blade whose thickness is thinner than the dicing blade in the step of dividing the resin layer. That is, when the respective cutting marks are compared, the process of dividing the substrate is made wider. The cutting trace here means the width of the area where the substrate and the resin member disappeared between the semiconductor devices after the division when the positions of the substrate and the resin layer are fixed before and after the division in the division step (on the cut surface). Also known as width). Since the width of the cut mark is wider in the step of dividing the substrate than in the step of dividing the resin layer, the resin layer can cover the end surfaces of the substrate and the semiconductor integrated circuit portion.

The step of polishing the substrate and reducing the thickness can be performed by suitably combining a glass polishing machine, a glass grinding machine, and the like. This polishing step can reduce the wear of the dicing blade. Further, by providing the resin layer, it is possible to reduce the occurrence of cracks in the semiconductor device being created when handling a thin substrate and in the process of dividing. Furthermore, when handling a chip-shaped semiconductor device after division, scratches and cracks caused by collision between the semiconductor devices can be reduced, and the yield in the appearance inspection of the semiconductor device can be improved. Further, since the thickness of the divided substrate is thin, the size of the semiconductor device of the present invention can be reduced.

According to the present invention, the surface opposite to the side of the semiconductor integrated circuit formed on the substrate and a region on the side surface of the substrate are covered with the resin, thereby reducing the occurrence of scratches and cracks and increasing the yield of the semiconductor device. Can be improved.

Therefore, it is possible to provide a highly reliable semiconductor device that is easy to handle even if it is thin.

Further, by reducing the thickness of the substrate before dividing the substrate, it becomes possible to reduce the consumption of the cutting tool when the substrate is divided. As the size of the substrate increases and the size of the semiconductor device to be divided decreases, the processing area of the cutting tool increases, so that the consumption of the cutting tool further increases. Therefore, the present invention capable of reducing the consumption of the cutting tool is particularly useful in a large substrate and a smaller semiconductor device. As a result, the semiconductor device can be manufactured at a lower cost. Further, since the substrate is thin, the size of the semiconductor device can be reduced.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment mode, a semiconductor device for the purpose of providing a thinner and smaller device and a method for manufacturing the semiconductor device with high yield will be described in detail with reference to FIGS.

1A and 1B show a semiconductor device of this embodiment mode. 1A is a plan view of the semiconductor device, and FIG. 1B is a cross-sectional view taken along line YZ in FIG.

1A and 1B, a semiconductor device 112 includes a substrate 109 provided with a semiconductor integrated circuit portion 101 including terminal electrodes 115a and 115b, and a resin layer 110. The resin layer 110 is formed so as to cover the surface and the end (side) of the substrate 109 opposite to the formation surface of the semiconductor integrated circuit portion 101 and the end (side) of the semiconductor integrated circuit portion 101. In the present embodiment, the resin layer 110 is continuously formed so as to cover the ends (side surfaces) of the terminal electrodes 115a and 115b.

According to the present invention, a plurality of semiconductor devices are taken out in a chip shape by dividing a substrate provided with a plurality of semiconductor integrated circuit portions for each semiconductor integrated circuit portion. Before the cutting process, the substrate is processed to be thin, thereby shortening the process time required for the cutting and reducing wear of processing means such as a dicer used for the cutting. In the dividing step, the substrate provided with a plurality of semiconductor integrated circuit portions fixed to the fixed substrate with wax so that the fixed substrate and the semiconductor integrated circuit portion face each other is cut between the semiconductor integrated circuit portions. Thereafter, a resin layer is formed so as to cover a plurality of divided substrates provided with semiconductor integrated circuit portions fixed on wax. The resin layer continuously covering the plurality of divided substrates and the semiconductor integrated circuit portion is cut for each of the divided substrate and the semiconductor integrated circuit portion, and divided (divided) into a plurality of semiconductor devices.

Therefore, in the semiconductor device of this embodiment, one surface and the end (side surface) of the substrate opposite to the surface on which the semiconductor integrated circuit portion is formed, and the end (side surface) of the semiconductor integrated circuit portion are continuously formed with a resin layer. It is the structure which covers. Therefore, since the resin layer also functions as a shock absorbing layer from external stress such as pressure applied in the manufacturing process or inspection process, defects such as scratches and cracks in the semiconductor device are reduced, and the reliability of the semiconductor device is increased. Can do.

When a light-transmitting material is used for the substrate and the resin layer, light can pass through the light-transmitting substrate and the light-transmitting resin layer and be irradiated to the photoelectric conversion element provided in the semiconductor integrated circuit portion.

Further, when a chromatic colored layer functioning as a color filter is used as the resin layer, a color sensor can be obtained. 4A and 4B show examples of the color sensor of the present invention.

4A and 4B illustrate a structure in which a resin layer 114 that is a chromatic color translucent resin layer that functions as a color filter is provided. A transparent translucent resin layer may be further laminated as a shock absorbing layer on the chromatic colored layer. In the semiconductor devices 112CF1 and 112CF2 in FIGS. 4A and 4B, a transparent resin layer 110 is provided on the resin layer 114.

In the semiconductor device 112CF1 in FIG. 4A, after the substrate 109 is divided, the resin layer 114 and the resin layer 110 are stacked, and then the resin layer 114 and the resin layer 110 are divided. Therefore, the resin layer 114 and the resin layer 110 have a shape that continuously covers the surface and side surfaces of the substrate 109 opposite to the formation surface of the semiconductor integrated circuit portion 101 and the side surfaces of the semiconductor integrated circuit portion 101.

In the case where the resin layers are stacked, the first-layer (also referred to as a lower layer) resin layer formed in contact with the substrate may be divided in the same process as the substrate. Like the semiconductor device 112CF2 in FIG. 4B, a resin layer may be formed over the substrate before being divided, and after being divided into the substrate 109 and the resin layer 114, the resin layer 110 may be further stacked as a protective layer. In this case, an end portion of the resin layer 114 divided in the same process as the substrate 109 coincides with an end portion of the substrate 109.

The chromatic color is a color excluding achromatic colors such as black, gray, and white, and the colored layer is formed of a material that transmits only the colored chromatic light in order to function as a color filter. As the chromatic color, red, green, blue, or the like can be used. Further, cyan, magenta, yellow (yellow), or the like may be used.

The film thickness of the resin layer may be 1 μm to 20 μm. When the resin layers are laminated, the film thickness of the resin layer 110 functioning as the shock absorbing layer and the film thickness of the resin layer 114 functioning as the colored layer may be the same (for example, film thickness 1.2 μm) or may be different. .

The film thickness of the resin layer 110 that functions as the shock absorbing layer may be thicker than the chromatic resin layer 114 that functions as the colored layer. By forming the resin layer 110 functioning as the shock absorbing layer thick, the shock resistance can be further improved as the shock absorbing layer. On the other hand, since the chromatic resin layer 114 functions as a colored layer (color filter), the optimum film thickness may be appropriately controlled in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance.

For example, when the thickness of the resin layer 110 functioning as a shock absorbing layer is made thicker than the resin layer 114 functioning as a colored layer, the thickness of the resin layer 110 functioning as a shock absorbing layer is set to 2 μm or more and 10 μm or less as an example, The thickness of the resin layer 114 that functions as a coloring layer may be 0.1 μm or more and 2 μm or less.

In the semiconductor device of the present invention, even if the resin layer functioning as the shock absorbing layer is formed, the substrate is further thinned by grinding and polishing, so that a thin semiconductor device can be obtained.

Alternatively, a black matrix may be provided. 17A and 17B illustrate semiconductor devices 112BM and 112CFBM each including a light-blocking layer that functions as a black matrix.

A semiconductor device 112BM in FIG. 17A includes a light shielding layer 116 that is selectively formed between the resin layer 110 and the substrate 109. A semiconductor device 117CFBM in FIG. 17B is a color sensor provided with a chromatic resin layer 114 that functions as a color filter, and is selectively formed between the chromatic resin layer 114 and the resin layer 110. The light shielding layer 116 is provided. In the semiconductor device 117CFBM in FIG. 17B, the light shielding layer 116 may be provided between the substrate 109 and the chromatic resin layer 114. Further, since the semiconductor device 117CFBM is an example in which the chromatic resin layer 114, the light shielding layer 116, and the resin layer 110 are formed after cutting the substrate 109, the chromatic resin layer 114 and the light shielding layer 116 are also formed on the substrate 109 and the semiconductor. The side surface of the integrated circuit portion 101 is covered. After forming the chromatic color resin layer 114 and the light shielding layer 116, the substrate 109 may be cut to form the resin layer 110. In this case, the ends of the chromatic color resin layer 114 and the light shielding layer 116 are formed on the substrate 109. The resin layer 110 covers the chromatic resin layer 114, the light shielding layer 116, the substrate 109, and the semiconductor integrated circuit portion 101 end, which coincides with the end portion.

The light shielding layer 116 can be formed by a coating method or the like, and can also be formed by a droplet discharge method, a printing method, a dipping method, a dispenser method, a brush coating method, a spray method, a flow coating method, or the like. When the printing method is used, the light-shielding layer can be selectively formed, so that a processing step into a desired shape by a photolithography step can be simplified.

The light shielding layer 116 is formed to have an opening corresponding to a region where the photoelectric conversion element of the semiconductor integrated circuit portion 101 is provided. The light blocking layer 116 functions as a black matrix and blocks light so that inappropriate external light is irradiated to the photoelectric conversion element and malfunction does not occur. Therefore, the photoelectric conversion element can receive only light incident from the opening of the light shielding layer 116, so that the reliability of the semiconductor device is improved. Further, when light is irradiated to the semiconductor element formed in the semiconductor integrated circuit portion, there is a possibility that characteristic fluctuation may occur. However, such a defect can be prevented by providing a light shielding layer.

A method for manufacturing a semiconductor device in this embodiment will be described in detail below.

FIG. 2A illustrates semiconductor integrated circuit portions 101a, 101b, and 101c each including a photoelectric conversion element provided over a substrate 100. FIG. The semiconductor integrated circuit portions 101a, 101b, and 101c have terminal electrodes 115a1, 115b1, 115a2, 115b2, 115a3, and 115b3, respectively.

The terminal electrodes 115a1, 115b1, 115a2, 115b2, 115a3, and 115b3 are conductive layers that are electrically connected during mounting.

The terminal electrodes 115a1, 115b1, 115a2, 115b2, 115a3, and 115b3 may be formed of a conductive resin using a wet method, or may be formed of a conductive thin film using a dry method. Moreover, you may laminate | stack a conductive resin layer and a conductive thin film.

For example, when a conductive layer is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively printed. Can be provided. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles such as silver halide fine particles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. Further, fine particles mainly composed of solder or lead-free solder may be used.

Next, a process of reducing the thickness of the substrate 100 by grinding and polishing is performed. The substrate 100 is fixed with the semiconductor integrated circuit portions 101a, 101b, and 101c facing the fixing tape 103 that fixes the substrate 100 in the process, and the substrate 100 is processed to form a thin substrate 102 (FIG. 2 ( See B). If the substrate 100 is a glass substrate having a thickness of 0.5 mm, the substrate 102 is preferably thinned to about 0.25 to 0.3 mm. By processing the thickness of the substrate to be thin, it is possible to reduce the process time required for dividing the substrate and to reduce wear of processing means such as a dicer used for the division. The grinding process and the polishing process can be used in a suitable combination. In this embodiment, after grinding with a grinding machine, the surface is flattened by the polishing process with the polishing machine. Chemical mechanical polishing may be performed as the polishing treatment.

In the present invention, a plurality of semiconductor devices are taken out in a chip shape by dividing a substrate. The dividing step is performed by fixing the semiconductor integrated circuit portion and the substrate on the fixed substrate 171 with the wax 170. The semiconductor integrated circuit portions 101a, 101b, 101c and the substrate 102 are fixed to the fixed substrate by the wax 170 and fixed so that the surface on which the semiconductor integrated circuit portions 101a, 101b, 101c are formed and the fixed substrate 171 face each other. (See FIG. 2C.) As the fixed substrate 171, a substrate that does not deform in the cutting process is selected. If the fixed substrate 171 undergoes deformation such as bending in the dividing step, the dividing region cannot be aligned when the resin layer is divided in the subsequent step, and it becomes difficult to control the dividing portion.

As the fixed substrate 171 that can be used in this embodiment, for example, a glass substrate such as aluminosilicate glass barium borosilicate glass or aluminoborosilicate glass, or a non-flexible substrate such as a quartz substrate, a metal substrate, or a glass epoxy substrate. Are preferred.

As the wax 170 that can be used in this embodiment mode, a wax that can be held without displacement when the substrate is divided is preferable.

As the wax, a solid wax which is a hot-melt temporary fixing adhesive for precision processing can be used. In the present embodiment, water is used for cooling the heat generated when the substrate is cut and holding the dicer and for cleaning the cutting waste, so that the wax is not water-soluble. The fixed substrate 171 is heated above the softening point of the wax. Wax is applied to the heated fixed substrate 171, and the bonding surfaces of the semiconductor integrated circuit portions 101 a, 101 b, and 101 c are pasted and bonded and cooled. The wax is removed with an organic solvent after the step of dividing the substrate and the resin layer. For example, Adfix-based solid wax (trade name) manufactured by Nikka Seiko Co., Ltd. can be used.

Next, the substrate 102 is divided into the semiconductor integrated circuit portions 101a, 101b, and 101c with the dicing blade of the dicer 104 to form substrates 109a, 109b, and 109c (see FIG. 2D). In the present embodiment, an example is shown in which, in the process of dividing the substrate 102, the wax 170 is also divided into waxes 172a, 172b, and 172c by the dicer 104, and the fixed substrate 171 is also a fixed substrate 173 having grooves.

Depending on the cutting conditions, the wax 170 may not be cut or only a groove may be formed, or the groove may not be formed on the fixed substrate 171. Since the resin layer 107 is formed in the area removed by the dicer 104, the shape of the resin layer 107 is reflected in the shape of the removed area of the dicer 104.

The shape of the groove formed in the fixed substrate 173 depends on the processing means. In the present embodiment, the shape of the dicing blade having a slightly round shape of the dicer 104 is reflected, and the groove of the fixed substrate 173 has a round shape (having a curvature) in the cross section of FIG. If the shape of the dicing blade is rectangular, the shape of the groove is also rectangular, and the groove formed on the fixed substrate 173 can also have a rectangular shape.

Substrates 109a, 109b, 109c provided with semiconductor integrated circuit portions 101a, 101b, 101c including terminal electrodes 115a1, 115b1, 115a2, 115b2, 115a3, 115b3 so as to cover the regions removed by dicer 104, wax 172a, 172b , 172c and the fixed substrate 173, the resin layer 107 is formed (see FIG. 2E).

The resin layer 107 is made of a resin material that can withstand the heating temperature when heat treatment is used in a process after the resin layer is formed (for example, when mounted on an interposer or another substrate).

When the resin layer 107 is formed, more stress resistance can be imparted to the semiconductor device. For example, a semiconductor device provided with the resin layer of the present invention can withstand without being damaged even when a pressure of about 20 N is applied.

As the resin layer, a resin material such as a vinyl resin, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, a urethane resin, or a siloxane resin can be used. As a method for producing the resin layer, a coating method such as a spin coating method can be used, and a droplet discharge method, a printing method, a dipping method, a dispenser method, a brush coating method, a spray method, a flow coating method, or the like can also be used. .

Thereafter, the resin layer 107 is cut between the substrates 109a, 109b, and 109c and divided (divided) into a plurality of semiconductor devices. In the present embodiment, the resin layer 107 is cut on the fixed substrate 173 by the dicer 108. The resin layer 107 is divided by the dicer 108 to be resin layers 110a, 110b, and 110c (see FIG. 3A).

Thereafter, the waxes 172a, 172b, 172c and the fixed substrate 173 are removed. The waxes 172a, 172b, and 172c can be removed by washing with an alkaline or hydrocarbon organic solvent (for example, isopropyl alcohol).

Through the above steps, the semiconductor devices 112a, 112b, and 112c can be formed (see FIG. 3B). By making the width of the cut surface for cutting the resin layer 107 narrower than the width of the cut surface for cutting the substrate 102, the resin layer can remain on the side surfaces of the substrate and the semiconductor integrated circuit portion. In the present embodiment, the width of the dicer 104 and the dicer 108 is the thickness of the dicing blade that determines the processing area (area processed by the dicer).

Since the width a1 of the cut surface can be controlled by the width a1 of the dicing blade of the dicer 104 and the width of the groove can be controlled by the width a2 of the dicing blade of the dicer 108, the width of the dicing blade of the dicer 108 can be controlled by the width a1 of the dicing blade of the dicer 104. What is necessary is just to narrow a2. For example, in this embodiment, the width a1 of the dicing blade of the dicer 104 is 0.16 mm, and the width a2 of the dicing blade of the dicer 108 is 0.1 mm.

Accordingly, in the semiconductor devices 112a, 112b, and 112c, the surfaces and side surfaces where the semiconductor integrated circuit portions 101a, 101b, and 101c are not provided and the side surfaces of the semiconductor integrated circuit portions 101a, 101b, and 101c are resin layers 110a, 110b, and 110c. It becomes a covered structure.

In addition, since the thickness of the substrate is thicker than that of the resin layer in order to improve the coverage at the edge of the substrate, it is preferable that the resin layer is also thickened. When the resin layer has a laminated structure, it can be formed thick. The shape of the completed semiconductor device can be freely changed (varied) depending on the structure and film thickness of the resin layer, and the cut location.

Since the resin layer is formed in the removal region of the wax and the fixed substrate when the substrate is cut, in this embodiment, the semiconductor devices 112a, 112b, and 112c further protrude from the terminal electrode to protrude the resin layers 110a, 110b, 110c is formed. However, if the wax is not removed, the end portions of the resin layers 110a, 110b, 110c and the terminal electrodes can be made to coincide.

The semiconductor device of the present invention is configured to cover at least a resin layer on one surface and a side surface of the substrate opposite to the formation surface of the semiconductor integrated circuit portion, and the side surface of the semiconductor integrated circuit portion. Therefore, since the resin layer also functions as a shock absorbing layer from external stress such as pressure applied in the manufacturing process or inspection process, defects such as scratches and cracks in the semiconductor device are reduced, and a highly reliable semiconductor device is manufactured. can do.

5A to 5F, FIGS. 6A to 6C, and FIG. 7A, a method of forming a photoelectric conversion element and a field effect transistor over a substrate as a semiconductor integrated circuit portion to be divided. (B) is demonstrated using sectional drawing. In FIG. 7A, an AN 100 which is one of glass substrates which is a substrate is used as the substrate 310. As a field-effect transistor formed over a substrate, a thin film transistor is used, whereby a photoelectric conversion element and a thin film transistor can be formed over the substrate in the same process, and thus there is an advantage that mass production of a semiconductor device is easy. Note that in this embodiment, when a light-transmitting material is used for the resin layer and the substrate, the photoelectric conversion element can be irradiated with light through the light-transmitting resin layer and the substrate.

First, an insulating film 312 that functions as a base film is formed by a plasma CVD method. In this embodiment, a silicon oxide film containing nitrogen (a thickness of 100 nm) is formed as the insulating film 312. The insulating film 312 may be stacked using a silicon oxide film, a silicon nitride film, or a silicon oxide film containing nitrogen. For example, a film in which a silicon nitride film containing oxygen is stacked with a thickness of 50 nm and a silicon oxide film containing nitrogen is stacked with a thickness of 100 nm may be formed as the insulating film 312. Note that the silicon oxide film or silicon nitride film containing nitrogen functions as a blocking layer for preventing diffusion of impurities such as alkali metal from the glass substrate.

Next, a semiconductor layer 331 is formed over the insulating film 312. In this embodiment, after the insulating film 312 is formed, the semiconductor film is continuously formed without being exposed to the air and processed into the island-shaped semiconductor layer 331.

As a material for forming a semiconductor layer included in a semiconductor element, an amorphous semiconductor (also referred to as an amorphous semiconductor) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane, the amorphous material is used. A polycrystalline semiconductor obtained by crystallizing a semiconductor using light energy or thermal energy, a microcrystalline (also referred to as semi-amorphous or microcrystal) semiconductor, or the like can be used. The semiconductor layer can be formed by sputtering, LPCVD, plasma CVD, or the like.

A microcrystalline semiconductor belongs to a metastable state between an amorphous state and a single crystal state in consideration of Gibbs free energy. That is, it is a semiconductor having a third state that is stable in terms of free energy, and has a short-range order and lattice distortion. Columnar or needle-like crystals grow in the normal direction with respect to the substrate surface. Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has a Raman spectrum shifted to a lower frequency side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability can be improved and a good microcrystalline semiconductor film can be obtained.

This microcrystalline semiconductor film can be formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Typically, silicon hydride such as SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , and SiF ₄ can be formed by diluting with hydrogen. In addition to silicon hydride and hydrogen, the microcrystalline semiconductor film can be formed by dilution with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. The flow rate ratio of hydrogen to silicon hydride at these times is 5 to 200 times, preferably 50 to 150 times, and more preferably 100 times.

A typical example of the amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of the crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon obtained by crystallizing amorphous silicon using an element that promotes crystallization. Needless to say, as described above, a microcrystalline semiconductor or a semiconductor including a crystalline phase in part of a semiconductor layer can be used.

Further, as a semiconductor material, a compound semiconductor such as gallium arsenide, InP, SiC, ZnSe, GaN, SiGe, etc. can be used in addition to a simple substance such as silicon (Si) and germanium (Ge). An oxide semiconductor such as zinc oxide or tin oxide can also be used. When ZnO is used for the semiconductor layer, a gate insulating layer is preferably formed using yttrium oxide, aluminum oxide, titanium oxide, a stacked layer thereof, or the like. As the layer, the source electrode layer, and the drain electrode layer, ITO, gold, titanium, or the like is preferably used. Indium, gallium, or the like can also be added to zinc oxide.

In the case where a crystalline semiconductor film is used for a semiconductor layer, a crystalline semiconductor film can be formed by various methods (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel). A crystallization method or the like may be used. In addition, crystallinity can be increased by crystallizing a microcrystalline semiconductor by laser irradiation. In the case where an element for promoting crystallization is not introduced, a step of releasing hydrogen from the amorphous silicon film by heat treatment is performed before the amorphous silicon film is irradiated with laser light. For example, the hydrogen concentration in the amorphous silicon film is released to 1 × 10 ²⁰ atoms / cm ³ or less by heating at 500 ° C. for 1 hour in a nitrogen atmosphere. This is because the amorphous silicon film is destroyed when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light.

The method for introducing an element that promotes crystallization into the amorphous semiconductor layer is not particularly limited as long as the element that promotes crystallization can be present on the surface of the amorphous semiconductor film or inside thereof. For example, a sputtering method, a CVD method, a plasma processing method (including a plasma CVD method), an adsorption method, and a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of an element that promotes crystallization can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

In the crystallization step of crystallizing the amorphous semiconductor film and forming the crystalline semiconductor film, an element for promoting crystallization is added to the amorphous semiconductor film, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) may be crystallized. As elements that promote (promote) crystallization, iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) ), Platinum (Pt), copper (Cu), and gold (Au), or one or more kinds selected from metal elements can be used.

In order to remove or reduce an element that promotes crystallization from the crystalline semiconductor film, a semiconductor film containing an impurity element is formed in contact with the crystalline semiconductor film and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe) can be used. A semiconductor film containing a rare gas element is formed over the crystalline semiconductor film containing the element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor film moves into the semiconductor film containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor film is removed or reduced. After that, the semiconductor film containing a rare gas element that has become a gettering sink is removed.

Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

Alternatively, the crystalline semiconductor film may be directly formed over the substrate by a plasma method. Alternatively, a crystalline semiconductor film may be selectively formed over the substrate by a plasma method.

In this embodiment mode, an amorphous silicon film containing hydrogen (film thickness: 54 nm) is stacked as a semiconductor film, and a polycrystalline silicon film is formed by a crystallization method using a catalytic element. A nickel acetate solution containing 10 ppm nickel by weight is added with a spinner. Instead of adding the solution, a method of spraying nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure (here, a polycrystalline silicon film). Here, after heat treatment (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a polycrystalline silicon film.

Next, the oxide film on the surface of the polycrystalline silicon film is removed with dilute hydrofluoric acid or the like. After that, irradiation with laser light (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains is performed in the air or an oxygen atmosphere.

As the laser light, excimer laser light having a wavelength of 400 nm or less or the second harmonic or the third harmonic of a YAG laser is used. Here, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system, and irradiated with an overlap rate of 90 to 95%. May be scanned. In this embodiment mode, laser light irradiation is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² .

Note that an oxide film is formed on the surface by irradiation with a laser beam because it is performed in the air or in an oxygen atmosphere. Note that although an example using a pulse laser is shown in this embodiment mode, a continuous wave laser may be used, and continuous oscillation is possible in order to obtain a crystal with a large grain size when a semiconductor film is crystallized. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied.

In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a nonlinear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. This barrier layer is formed to remove an element added for crystallization, such as nickel (Ni), from the film. Here, the barrier layer is formed using ozone water, but the surface of the semiconductor film having a crystal structure is oxidized by a method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the oxygen plasma treatment. The barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method, plasma CVD method, sputtering method or vapor deposition method. Further, the oxide film formed by laser light irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 to 400 nm, here 100 nm, over the barrier layer by a sputtering method. Here, the amorphous silicon film containing an argon element is formed using a silicon target in an atmosphere containing argon. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are as follows: the flow ratio of monosilane to argon (SiH ₄ : Ar) is 1:99, and the film formation pressure is 6.665 Pa. The RF power density is 0.087 W / cm ² and the film formation temperature is 350 ° C.

Thereafter, the catalyst element is removed (gettering) by performing a heat treatment for 3 minutes in a furnace heated to 650 ° C. As a result, the concentration of the catalytic element in the semiconductor film having a crystal structure is reduced. A heating device using a lamp may be used instead of the furnace.

Next, the amorphous silicon film containing an argon element which is a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

Note that in the case where the semiconductor film is not crystallized using an element that promotes crystallization, the above-described barrier layer formation, gettering site formation, heat treatment for gettering, gettering site removal, and barrier Steps such as layer removal are not necessary.

Next, after forming a thin oxide film with ozone water on the surface of the obtained semiconductor film having a crystalline structure (for example, a polycrystalline silicon film), a resist mask is formed using a first photomask, and a desired film is formed. A semiconductor layer 331 separated into an island shape is formed by etching treatment into a shape (see FIG. 5A). After the semiconductor layer 331 is formed, the resist mask is removed.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold voltage of the transistor. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

Next, after removing the oxide film with an etchant containing hydrofluoric acid, the surface of the semiconductor layer 331 is washed, and then a gate insulating film 313 is formed.

The gate insulating film 313 may be formed using silicon oxide or a stacked structure of silicon oxide and silicon nitride. The gate insulating film 313 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, or may be formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because a gate insulating film formed by oxidizing or nitriding a semiconductor layer by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. For example, nitrous oxide (N ₂ O) is diluted 1 to 3 times (flow rate ratio) with Ar, and 3 to 5 kW microwave (2.45 GHz) power is applied at a pressure of 10 to 30 Pa to apply a semiconductor. The surface of the layer is oxidized or nitrided. By this treatment, an insulating film having a thickness of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. Further, nitrous oxide (N ₂ O) and silane (SiH ₄ ) are introduced, and 3-5 kW microwave (2.45 GHz) power is applied at a pressure of 10-30 Pa, and silicon oxynitride is formed by vapor phase growth. A film is formed to form a gate insulating film. A gate insulating film having a low interface state density and an excellent withstand voltage can be formed by combining a solid phase reaction and a reaction by a vapor deposition method.

As the gate insulating film 313, a high dielectric constant material such as zirconium dioxide, hafnium oxide, titanium dioxide, or tantalum pentoxide may be used. By using a high dielectric constant material for the gate insulating film 313, gate leakage current can be reduced.

In this embodiment, a silicon oxide film containing nitrogen with a thickness of 115 nm is formed as the gate insulating film 313 by a plasma CVD method.

Next, after a metal film is formed over the gate insulating film 313, a gate electrode 334, wirings 314 and 315, and a terminal electrode 350 are formed using a second photomask (see FIG. 5B). As this metal film, for example, a film in which tantalum nitride and tungsten (W) are stacked by 30 nm and 370 nm, respectively, is used.

In addition to the above, as the gate electrode 334, the wirings 314 and 315, and the terminal electrode 350, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), Zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), A single layer film made of an element selected from silver (Ag) and copper (Cu), an alloy material or a compound material containing the element as a main component, or a nitride thereof, for example, titanium nitride, tungsten nitride, nitride A single layer film made of tantalum or molybdenum nitride can be used.

Alternatively, a light-transmitting material having a property of transmitting visible light can be used for the gate electrode 334, the wirings 314 and 315, and the terminal electrode 350. As the light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, or the like can be used. Further, indium zinc oxide (IZO) containing zinc oxide (ZnO), zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), and tungsten oxide are included. Indium oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may be used.

Next, an impurity imparting one conductivity type is introduced into the semiconductor layer 331, so that the source region or the drain region 337 of the transistor 373 is formed (see FIG. 5C). Since an n-channel transistor is formed in this embodiment mode, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor layer 331. In the case of forming a p-channel transistor, an impurity element imparting p-type conductivity, for example, boron (B) may be introduced into the semiconductor layer 331.

Next, after forming a first interlayer insulating film (not shown) including a silicon oxide film by CVD with a thickness of 50 nm, a step of activating the impurity element added to each island-like semiconductor region is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

Next, a second interlayer insulating film 316 including a silicon nitride film containing hydrogen and oxygen is formed with a thickness of 10 nm, for example.

Next, a third interlayer insulating film 317 made of an insulating material is formed over the second interlayer insulating film 316 (see FIG. 5D). As the third interlayer insulating film 317, an insulating film obtained by a CVD method can be used. In this embodiment, in order to improve adhesion, a silicon oxide film containing nitrogen formed with a thickness of 900 nm is formed as the third interlayer insulating film 317.

Next, heat treatment (300 to 550 ° C. for 1 to 12 hours, for example, in a nitrogen atmosphere at 410 ° C. for 1 hour) is performed to hydrogenate the semiconductor layer. This step is performed in order to terminate dangling bonds in the semiconductor layer with hydrogen contained in the second interlayer insulating film 316. The semiconductor layer can be hydrogenated regardless of the presence of the gate insulating film 313.

Further, as the third interlayer insulating film 317, an insulating film using siloxane and a stacked structure thereof can be used. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, a compound containing at least hydrogen (for example, an alkyl group or an aryl group) is used. Fluorine may be used as a substituent. Alternatively, as a substituent, a compound containing at least hydrogen and fluorine may be used.

In the case where an insulating film using siloxane and a stacked structure thereof are used as the third interlayer insulating film 317, a heat treatment for hydrogenating the semiconductor layer is performed after the formation of the second interlayer insulating film 316. In addition, a third interlayer insulating film 317 can be formed.

Next, a resist mask is formed using a third photomask, and the first interlayer insulating film, the second interlayer insulating film 316 and the third interlayer insulating film 317 or the gate insulating film 313 are selectively etched. A contact hole is formed. Then, the resist mask is removed.

Note that the third interlayer insulating film 317 may be formed as necessary. When the third interlayer insulating film 317 is not formed, the first interlayer insulating film and the first interlayer insulating film 316 are formed after the second interlayer insulating film 316 is formed. The second interlayer insulating film 316 and the gate insulating film 313 are selectively etched to form contact holes.

Next, after a metal laminated film is formed by a sputtering method, a resist mask is formed using a fourth photomask, and the metal film is selectively etched, so that a wiring 319, a connection electrode 320, and a terminal electrode 351 are formed. A source electrode or a drain electrode 341 of the transistor 373 is formed. Then, the resist mask is removed. Note that the metal film in this embodiment is formed by stacking three layers of a Ti film with a thickness of 100 nm, an Al film containing a trace amount of Si with a thickness of 350 nm, and a Ti film with a thickness of 100 nm.

In the case where the wiring 319, the connection electrode 320, the terminal electrode 351, and the source or drain electrode 341 of the transistor 373 are formed using a single-layer conductive film, a titanium film (Ti film) is used in terms of heat resistance and conductivity. preferable. Further, in place of the titanium film, tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh) ), Palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), or a film made of an alloy material or a compound material containing the element as a main component, or a nitride thereof For example, a film formed of titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride can be used.

Through the above steps, a top-gate transistor 373 using a polycrystalline silicon film as a semiconductor layer can be manufactured.

In this embodiment mode, an n-channel transistor is described as an example of a semiconductor element included in the semiconductor integrated circuit portion. However, a p-channel transistor may be used. Various forms of field effect transistors can be used, and the type of transistors used is not limited.

In this embodiment, a single-gate transistor is described; however, a multi-gate structure such as a double-gate structure may be used. In this case, a gate electrode layer may be provided above and below the semiconductor layer, or a plurality of gate electrode layers may be provided only on one side (above or below) of the semiconductor layer.

Alternatively, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, manufacture at a low vacuum degree, or can manufacture on a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost is reduced and the number of processes can be reduced. Further, since a film is formed only on a necessary portion, the material is not wasted and cost can be reduced as compared with a manufacturing method in which etching is performed after film formation on the entire surface.

Alternatively, a transistor including an organic semiconductor or a carbon nanotube can be used. Thus, a transistor can be formed over a substrate that can be bent. Therefore, it can be strong against impact.

Alternatively, the transistor may be formed using a substrate having an SOI structure including a single crystal semiconductor layer as the semiconductor layer. Accordingly, a transistor with small variations in characteristics, size, shape, and the like, high current supply capability, and small size can be manufactured. When these transistors are used, low power consumption of the circuit or high integration of the circuit can be achieved.

The semiconductor device of this embodiment can be formed over a light-transmitting substrate such as a glass substrate by forming a field effect transistor using a thin film transistor. Therefore, even if the photoelectric conversion element is formed on the upper surface of the substrate, the light that has passed through the light-transmitting substrate from the back surface of the substrate can be received by the photoelectric conversion element.

Next, after forming a conductive metal film (titanium (Ti) or molybdenum (Mo), etc.) that hardly reacts with a photoelectric conversion layer (typically amorphous silicon) to be formed later, A resist mask is formed using a fifth photomask, and a conductive metal film is selectively etched to form a protective electrode 318, a protective electrode 345, a protective electrode 346, and a protective electrode 348 that cover the wiring 319. (FIG. 5E). Here, a 200-nm-thick Ti film obtained by sputtering is used. Note that the connection electrode 320, the terminal electrode 351, and the source or drain electrode 341 of the transistor 373 are similarly covered with a conductive metal film. Accordingly, the conductive metal film also covers the side surface of the electrode where the second Al film is exposed, and the conductive metal film can prevent diffusion of aluminum atoms into the photoelectric conversion layer.

However, in the case where the wiring 319, the connection electrode 320, the terminal electrode 351, and the source or drain electrode 341 of the transistor 373 are formed using a single-layer conductive film, the protective electrode 318, the protective electrode 345, the protective electrode 346, and the protective electrode 348 may not be formed.

Next, a photoelectric conversion layer 371 including a p-type semiconductor layer 371p, an i-type semiconductor layer 371i, and an n-type semiconductor layer 371n is formed over the third interlayer insulating film 317.

The p-type semiconductor layer 371p may be formed by forming a microcrystalline silicon film containing an impurity element belonging to Group 13 of the periodic table, for example, boron (B) by a plasma CVD method.

As an example of a method for forming a microcrystalline silicon film, a method in which a silane gas and hydrogen and / or a rare gas are mixed to form a film by glow discharge plasma can be given. Silane is diluted 10 to 2000 times with hydrogen and / or a noble gas. Therefore, a large amount of hydrogen and / or a rare gas is required. The heating temperature of the substrate is 100 ° C to 300 ° C, preferably 120 ° C to 220 ° C. In order to inactivate the growth surface of the microcrystalline silicon film with hydrogen and promote the growth of the microcrystalline silicon, the film formation is preferably performed at 120 ° C. to 220 ° C. During the film forming process, SiH radicals, SiH ₂ radicals, and SiH ₃ radicals, which are active species, grow based on crystal nuclei. Further, the energy band width may be adjusted by mixing germanium hydride or germanium such as GeH ₄ or GeF ₄ in a gas such as silane, or adding carbon or germanium to silicon. When carbon is added to silicon, the energy bandwidth is widened, and when germanium is added to silicon, the energy bandwidth is narrowed.

In addition, the wiring 319 and the protective electrode 318 are in contact with the lowermost layer of the photoelectric conversion layer 371, in this embodiment mode, the p-type semiconductor layer 371p.

After the p-type semiconductor layer 371p is formed, an i-type semiconductor layer 371i and an n-type semiconductor layer 371n are formed in order. Thus, a photoelectric conversion layer 371 including the p-type semiconductor layer 371p, the i-type semiconductor layer 371i, and the n-type semiconductor layer 371n is formed.

As the i-type semiconductor layer 371i, for example, a microcrystalline silicon film may be formed by a plasma CVD method. As the n-type semiconductor layer 371n, a microcrystalline silicon film containing an impurity element belonging to Group 15 of the periodic table, for example, phosphorus (P) may be formed, or after forming the microcrystalline silicon film, These impurity elements may be introduced.

Further, as the p-type semiconductor layer 371p, the i-type semiconductor layer 371i, and the n-type semiconductor layer 371n, not only a microcrystalline semiconductor film but also an amorphous semiconductor film may be used. Further, a polycrystalline semiconductor film formed by the above catalyst or laser crystallization treatment may be used.

Furthermore, a photoelectric conversion layer formed using microcrystalline silicon or single crystal silicon formed by a smart cut method can reduce variation in characteristics in the substrate surface.

Next, a sealing layer 324 made of an insulating material (eg, an inorganic insulating film containing silicon) is formed over the entire surface with a thickness of 1 μm to 30 μm (see FIG. 5F). Here, a silicon oxide film containing nitrogen having a thickness of 1 μm is formed as the sealing layer by a CVD method. Adhesion is improved by using an insulating film formed by CVD.

Next, after the sealing layer 324 is etched to provide openings, wirings 374 and 375 are formed by a sputtering method. As the wirings 374 and 375, a titanium film (Ti film) (200 nm) is formed by a sputtering method (see FIG. 6A).

Next, a protective film 377 is formed to cover the exposed surface. As the protective film 377, a silicon nitride film is used in this embodiment. The protective film 377 can prevent impurities such as moisture and organic substances from entering the photoelectric conversion layer 371 and the transistor 373.

Next, a sealing film 378 is formed over the protective film 377. The sealing film 378 also has a function of protecting the semiconductor integrated circuit portion from external stress. In this embodiment mode, the sealing film 378 is formed using a photosensitive epoxy-phenolic resin with a thickness of 20 μm. As the sealing film 378, ohmic coat 1012B (manufactured by NAMICS Co., Ltd.), which is an epoxy-phenol resin, may be used.

Next, a contact hole is formed by etching the protective film in a region where the upper terminal electrode is electrically connected to the lower wiring 374 or the wiring 375.

Next, on the sealing film 378, for example, a nickel (Ni) paste is used as the terminal electrode 115a and the terminal electrode 115b, and a titanium film (Ti film) (150 nm) and a nickel film (Ni A laminated film of a film (750 nm) and a gold film (Au film) (50 nm) is formed. The fixing strength of the terminal electrode 115a and the terminal electrode 115b thus obtained exceeds 5N, and has a sufficient fixing strength as a terminal electrode.

Through the above steps, the terminal electrode 115a and the terminal electrode 115b that can be connected by soldering are formed (see FIG. 6B).

Actually, one semiconductor integrated circuit portion including a photoelectric conversion element, a transistor, and the like formed at the time of FIG. 6B can be mass-produced by forming an element material on a substrate. . From a single substrate (for example, 600 cm × 720 cm), a large number of semiconductor devices (for example, 2 mm × 1.5 mm) each including a semiconductor integrated circuit portion can be manufactured. This is shown in FIGS. 7A and 7B.

In FIG. 7A, a sealing film 378 is formed over a substrate 100 so as to cover a plurality of semiconductor integrated circuits 151a, 151b, and 151c provided with terminal electrodes 115, respectively. Note that the semiconductor integrated circuit 151 includes all structures formed between the substrate 100 and the sealing film 378 in FIG.

Next, as shown in FIG. 7B, the sealing film 378 is divided between the adjacent semiconductor integrated circuits 151a, 151b, and 151c, and the sealing films 378a, 378b that cover the semiconductor integrated circuits 151a, 151b, and 151c, 378c. After this dividing step, a structure in which a plurality of semiconductor integrated circuit portions 101a, 101b, and 101c are provided at intervals on the substrate 100 as shown in FIG. 2A can be obtained.

The substrate 109 on which the semiconductor integrated circuit portion 101 formed in this manner is further mounted on the substrate 360 with solder 363 and 364 at the portions of the terminal electrodes 115a1 and 115a2 (see FIG. 6C). .) Note that the terminal electrode 115a1 is electrically connected to the electrode 361 on the substrate 360 with the solder 363, and the terminal electrode 115a2 is mounted by being electrically connected to the electrode 362 on the substrate 360 with the solder 364. .

In the photoelectric conversion element illustrated in FIG. 6C, light incident on the photoelectric conversion layer 371 can enter from the substrate 109 and the resin layer 110 side by using the light-transmitting substrate 109 and the resin layer 110.

In the present invention, the semiconductor device may be provided in a housing having a light-transmitting region formed using an opening or a light-transmitting material in an incident region of light irradiated to the photoelectric conversion element. External light other than the target light to be detected by the photoelectric conversion element in the housing can be blocked. Therefore, the accuracy of the semiconductor device as a sensor can be increased and errors can be reduced.

8 and 9 are examples in which a housing is formed in a semiconductor device and the direction in which light enters is controlled.

8A and 8B, the housing 601 is formed on the photoelectric conversion layer 371 after mounting the semiconductor device in FIG. 6C on the terminal electrodes 115a and 115b with the electrodes 361 and 362 and the solder 363 and 364 of the substrate 360. Incident light enters from the substrate 109 side. The housing 601 is provided with an opening in a region where the photoelectric conversion layer 371 on the substrate 109 side is formed.

Light incident from the substrate 109 side can enter the photoelectric conversion layer 371 through the resin layer 110 to generate a photocurrent and detect light.

The casings 601 and 603 may be made of any material having a function of blocking light, and may be formed using, for example, a metal material or a resin material having a black pigment.

FIG. 9 illustrates an example in which the light-transmitting region 602 formed using a light-transmitting material is formed in the housing 601 instead of the opening. Further, a chromatic resin layer 114 that functions as a color filter is provided as a resin layer.

If a semiconductor device is manufactured by the above manufacturing method, the unit price can be reduced and the yield can be improved.

By reducing the thickness of the substrate before dividing the substrate, it is possible to reduce the consumption of the cutting tool when the substrate is divided. As the size of the substrate increases and the size of the semiconductor device to be divided decreases, the processing area of the cutting tool increases, so that the consumption of the cutting tool further increases. Therefore, the present invention capable of reducing the consumption of the cutting tool is particularly useful in a large substrate and a smaller semiconductor device. As a result, the semiconductor device can be manufactured at a lower cost. In addition, since the substrate is thin, the size of the semiconductor device can be reduced.

Therefore, it is possible to provide a highly reliable semiconductor device that is easy to handle even if it is thin.
(Embodiment 2)
In this embodiment mode, a semiconductor device intended to be thinner and smaller and a method for manufacturing the semiconductor device with high yield will be described in detail with reference to FIGS. Specifically, an example of a semiconductor device including a plurality of divided chip sensors is shown.

A plurality of small semiconductor devices as shown in Embodiment Mode 1 can be mounted on an interposer or the like to form a semiconductor device. Since the semiconductor devices on a plurality of chips mounted on the interposer can be freely selected, a semiconductor device having a different chromatic translucent resin color is mounted on the interposer and a multi-color sensor is installed. A semiconductor device including the same can be manufactured.

18A to 18C illustrate the semiconductor device of this embodiment. 18A is a plan view of the semiconductor device, and FIGS. 18B and 18C are cross-sectional views of the semiconductor device. FIG. 18B corresponds to a cross-sectional view taken along line V-X in FIG.

The semiconductor device in FIG. 18 has a structure in which a chip-like semiconductor device 112R, a semiconductor device 112G, and a semiconductor device 112B are mounted on an interposer 160. The semiconductor device 112R, the semiconductor device 112G, and the semiconductor device 112B are provided with terminal electrodes 115aR, 115bR, 115aG, 115bG, 115aB, and 115aB, which are conductive layers for electrical connection with the outside.

The semiconductor device 112R, the semiconductor device 112G, and the semiconductor device 112B are electrically connected to respective terminal electrodes and the electrodes 161a1, 161a2, 161b1, 161b2, 161c1, and 161c2 formed on the interposer 160 by solder (not shown). Yes. As shown by a dotted line in FIG. 18, the interposer 160 has openings that penetrate the front surface and the back surface, and the electrodes 161a1 and 161a2, 161b1 and 161b2, and 161c1 and 161c2 are in continuous contact with each other through the openings. Therefore, the electrodes 161a2, 161b2, and 161c2 can be mounted on another substrate as electrodes of the semiconductor device 112R, the semiconductor device 112G, and the semiconductor device 112B.

The semiconductor device 112R, the semiconductor device 112G, and the semiconductor device 112B are substrates 109R, 109G, and 109B, semiconductor integrated circuit portions 101R, 101G, and 101B including photoelectric conversion elements, and a chromatic color translucent resin layer that functions as a color filter, respectively. It has certain resin layers 114R, 114G, and 114B and functions as a color sensor. In the present embodiment, the semiconductor device 112R includes a red resin layer 114R, the semiconductor device 112G includes a green resin layer 114G, and the semiconductor device 112B includes a blue resin layer 114B. The resin layers 114R and 114G, respectively. , 114B can be transmitted and detected. Accordingly, the semiconductor device illustrated in FIG. 18 including the chip-shaped semiconductor device 112R, the semiconductor device 112G, and the semiconductor device 112B is a semiconductor device that can detect light of three kinds of colors (red, green, and blue). is there.

In the semiconductor device in FIGS. 18A to 18C, the resin layers 114R, 114G, and 114B are chromatic colored layers that function as at least a color filter, and further, a transparent resin layer 110 as an impact absorbing layer. , 110R, 110G, and 110B.

The transparent resin layers 110, 110R, 110G, and 110B function as a protective layer, have an effect of improving shock absorption and further preventing deterioration of the chromatic resin layers 114R, 114G, and 114B.

Since the resin layers 114R, 114G, and 114B and the resin layers 110, 110R, 110G, and 110B also function as shock absorbing layers from external stress such as pressure applied in the manufacturing process or the inspection process, the semiconductor devices 112R, 112G, and 112B Thus, defects such as scratches and cracks can be reduced, and a highly reliable semiconductor device can be manufactured.

18A and 18B includes a chip-like semiconductor device 112R, a semiconductor device 112G, and a semiconductor in which resin layers 110R, 110G, and 110B are stacked on the chromatic resin layers 114R, 114G, and 114B. In this example, the device 112B is mounted on the interposer 160. Resin layers 114R, 114G, and 114B, which are chromatic translucent resin layers, are formed in contact with the substrate, and resin layers 110R, 110G that are transparent translucent resin layers are formed on the resin layers 114R, 114G, and 114B, respectively. 110B are stacked.

On the other hand, the semiconductor device in FIG. 18C is transparent on the resin layers 114R, 114G, and 114B so as to cover the semiconductor devices 112R, 112G, and 112B after the semiconductor devices 112R, 112G, and 112B are mounted on the interposer 160. This is an example of forming a resin layer 110 which is a transparent resin layer. In order to form the resin layer 110 after the semiconductor devices 112R, 112G, and 112B are mounted on the interposer 160, in FIG. 18C, the resin layer 110 is also connected to the side surfaces of the semiconductor devices 112R, 112G, and 112B and the interposer 160. The shape can be continuously covered.

FIG. 18 of this embodiment mode shows an example in which a plurality of color sensors having the structure of FIG. 4A are mounted on an interposer. Similarly, a plurality of color sensors having the structure of FIG. May be implemented. In the semiconductor device in FIG. 4B, a resin layer that is a chromatic light-transmitting resin is formed over a substrate before being divided, and after being divided into a substrate 109 and a resin layer 114, a resin layer 110 is further formed as a protective layer. Since the layers are stacked, an end portion of the resin layer 114 which is divided in the same process as the substrate 109 coincides with an end portion of the substrate 109.

A semiconductor device including a photoelectric conversion element can be mounted on an interposer with solder or an anisotropic conductive layer.

In addition, as a structure of a connection portion between the semiconductor device and the electrode of the interposer to be mounted, the wiring on the substrate and a bump which is a conductive protrusion provided on the terminal electrode of the semiconductor device are brought into contact, and the interposer and the semiconductor You may fix between apparatuses with resin. In addition, a resin in which conductive particles are dispersed is provided between the electrode of the interposer and the terminal electrode of the semiconductor device, and the conductive particles are dispersed by connecting the semiconductor device and the electrode of the interposer with the conductive particles. It may be bonded and fixed with an organic resin. As the resin used for adhesion, a photo-curing resin, a thermosetting resin, a natural-curing resin, or the like can be used.

It is preferable to provide a resin between the semiconductor device and the interposer and fix the resin because the fixing strength is improved.

The opening provided in the interposer is preferably a structure filled with a resin, a conductive material, or the like. A conductive resin or the like can also be used as the conductive material to be filled.

As the interposer, an organic polymer, an inorganic polymer, a glass epoxy type, a ceramic type, a polyimide, a fluororesin, or the like can be used.

The thickness of the interposer is about 50 μm to 300 μm (typically 100 μm to 200 μm). When an interposer having a smaller thickness is used, the effect of reducing the thickness of the semiconductor device in the present invention can be further enhanced. In the semiconductor device shown in FIG. 18, the substrates 109R, 109G, and 109B and the interposer 160 have substantially the same thickness, but the interposer may be thicker or thinner than the substrate. Also good.

In a semiconductor device, a thinly formed substrate is covered with a resin layer, so that it is easy to handle in the process and is not easily damaged. Accordingly, a thinner high-performance semiconductor device can be manufactured with high yield.

Since a plurality of chip-like semiconductor devices mounted on the interposer can be freely selected, chip-like semiconductor devices having different chromatic color translucent resin colors are mounted on the interposer, and a color sensor is mounted. A semiconductor device including a plurality of colors can be manufactured.

In addition, when mounting on the interposer, a chip-shaped semiconductor device can be inspected and only good products can be selected and mounted on the interposer. Therefore, the yield of the semiconductor device is improved in the manufacturing process. In particular, in the case of a configuration having a semiconductor integrated circuit portion including a complicated configuration such as an amplifier circuit, a defect may occur in the chip-shaped semiconductor device, so that the defect inspection of the chip-shaped semiconductor device can be performed before mounting on the interposer. It is beneficial.

Therefore, it is possible to provide a highly reliable semiconductor device that is easy to handle even if it is thin.

(Embodiment 3)
In the semiconductor device of the present invention, various types of field effect transistors can be used as semiconductor elements included in the semiconductor integrated circuit portion. In this embodiment, a field-effect transistor having a single crystal semiconductor layer will be described in detail as a semiconductor element that can be applied to the present invention.

Hereinafter, a method for forming a semiconductor element included in a semiconductor integrated circuit portion by providing a single crystal semiconductor layer over a substrate and using a single crystal semiconductor substrate will be described with reference to FIGS.

A single crystal semiconductor substrate 1108 illustrated in FIG. 15A is cleaned, and a weakened layer 1110 is formed by irradiating ions accelerated by an electric field from a surface thereof to a predetermined depth. Ion irradiation is performed in consideration of the thickness of the single crystal semiconductor layer transferred to the substrate. In consideration of such a thickness, the single crystal semiconductor substrate 1108 is irradiated with an acceleration voltage at the time of ion irradiation. In the present invention, a region weakened so that a single crystal semiconductor substrate is irradiated with ions and has minute cavities by the ions is referred to as a weakened layer.

As the single crystal semiconductor substrate 1108, a commercially available single crystal semiconductor substrate can be used. For example, a single crystal semiconductor substrate including a Group 4 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate can be used. Can be used. A compound semiconductor substrate such as gallium arsenide or indium phosphide can also be used. A polycrystalline semiconductor substrate may be used as the semiconductor substrate. Needless to say, the single crystal semiconductor substrate is not limited to a circular wafer, and single crystal semiconductor substrates having various shapes can be used. For example, a polygonal substrate such as a circle, a rectangle, a pentagon, and a hexagon can be used. Needless to say, a commercially available circular single crystal semiconductor wafer can also be used for the single crystal semiconductor substrate. Examples of the circular single crystal semiconductor wafer include semiconductor wafers such as silicon and germanium, and compound semiconductor wafers such as gallium arsenide and indium phosphide. A typical example of a single crystal semiconductor wafer is a single crystal silicon wafer having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), a diameter of 12 inches (300 mm), a diameter of 400 mm, and a diameter of 450 mm. The circular wafer can be used. The rectangular single crystal semiconductor substrate can be formed by cutting a commercially available circular single crystal semiconductor wafer. For cutting the substrate, a cutting device such as a dicer or a wire saw, laser cutting, plasma cutting, electron beam cutting, or any other cutting means can be used. In addition, a rectangular single crystal semiconductor substrate can be obtained by processing an ingot for manufacturing a semiconductor substrate before thinning as a substrate into a rectangular parallelepiped shape so that the cross section is rectangular, and thinning the rectangular ingot. Can be manufactured. Further, the thickness of the single crystal semiconductor substrate is not particularly limited. However, in consideration of reusing the single crystal semiconductor substrate, a thicker one can form more single crystal semiconductor layers from one raw material wafer. This is preferable because it is possible. The thickness of single crystal silicon wafers on the market conforms to the SEMI standard. For example, a wafer with a diameter of 6 inches has a film thickness of 625 μm, a wafer with an diameter of 8 inches has a film thickness of 725 μm, and a diameter of 12 inches. The wafer is 775 μm. The thickness of the SEMI standard wafer includes a tolerance of ± 25 μm. Needless to say, the thickness of the single crystal semiconductor substrate which is a raw material is not limited to the SEMI standard, and the thickness can be adjusted as appropriate when the ingot is sliced. Of course, when the reused single crystal semiconductor substrate 1108 is used, the thickness is thinner than that of the SEMI standard. The single crystal semiconductor layer obtained over the substrate can be determined by selecting a base semiconductor substrate.

Further, the crystal plane orientation of the single crystal semiconductor substrate 1108 may be selected depending on a semiconductor element to be manufactured (a field effect transistor in this embodiment). For example, a single crystal semiconductor substrate having a {100} plane, a {110} plane, or the like as a crystal plane orientation can be used.

This embodiment mode is formed by an ion irradiation separation method in which hydrogen, helium, or fluorine is added by ion irradiation to a predetermined depth of a single crystal semiconductor substrate and then heat treatment is performed to separate the surface single crystal semiconductor layer. However, a method of epitaxially growing single crystal silicon on porous silicon, and then cleaving the porous silicon layer with a water jet may be applied.

A single crystal silicon substrate is used as the single crystal semiconductor substrate 1108, the surface is treated with dilute hydrofluoric acid, and the surface of the single crystal semiconductor substrate 1108 is cleaned by removing a natural oxide film and removing contaminants such as dust attached to the surface. To do.

The weakening layer 1110 may be irradiated with ions by an ion doping method (abbreviated as ID method) or an ion implantation method (abbreviated as II method). The weakening layer 1110 is formed by irradiation with halogen ions typified by hydrogen, helium, or fluorine. In the case of irradiation with fluorine ions as a halogen element, BF ₃ may be used as a source gas. Note that ion implantation refers to a method in which ionized gas is mass-separated and irradiated onto a semiconductor substrate.

For example, ion-implanted hydrogen gas can be mass-separated using an ion implantation method, and H ⁺ alone (or H ₂ ⁺ alone) can be selectively accelerated and irradiated to the single crystal semiconductor substrate.

In the ion doping method, a plurality of types of ion species are generated in plasma without mass separation of ionized gas, and these are accelerated to irradiate a single crystal semiconductor substrate. For ^example, H ^_+, H 2 _+, the hydrogen containing _H ^{3 +} ions, ions irradiated is typically _H ^{3 +} ions is 50% or more, for example _H ^{3 +} ions is 80%, other ions (H ₂ ⁺ , H ₃ ⁺ ions) is typically 20%. Irradiation as only the ion species of H ₃ ⁺ ions is also referred to as ion doping here.

Moreover, you may irradiate the ion from which the mass which consists of one or several same atoms differs. For example, when irradiating with hydrogen ions, it is preferable to include H ⁺ , H ₂ ⁺ and H ₃ ⁺ ions and to increase the ratio of H ₃ ⁺ ions. In the case of irradiation with hydrogen ions, H ⁺ , H ₂ ⁺ , H ₃ ⁺ ions are included, and if the ratio of H ₃ ⁺ ions is increased, the irradiation efficiency can be increased and the irradiation time can be shortened. Can do. With such a configuration, peeling can be easily performed.

Hereinafter, the ion doping method and the ion implantation method will be described in detail. In an ion doping apparatus (also referred to as an ID apparatus) used for an ion doping method, a plasma space is large and a single crystal semiconductor substrate can be irradiated with a large amount of ions. On the other hand, an ion implantation apparatus (also referred to as an II apparatus) used for the ion implantation method is characterized by mass-analyzing ions extracted from plasma and implanting only specific ion species into a semiconductor substrate. Scan and process.

As a plasma generation method, both apparatuses create a plasma state by, for example, thermoelectrons that are generated by heating a filament. However, the proportion of hydrogen ion species when the semiconductor substrate is irradiated with the generated hydrogen ions (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ) differs greatly between the ion doping method and the ion implantation method.

From the viewpoint of irradiating more H ₃ ⁺ , it can be said that it is preferable to use an ion doping apparatus rather than an ion implantation apparatus.

When a single crystal silicon substrate is irradiated with halogen ions such as hydrogen ions or fluorine ions, the added fluorine effectively creates a blank portion by knocking out (displacing) silicon atoms in the silicon crystal lattice, making it vulnerable. Create a small cavity in the layer. In this case, a volume change of minute cavities formed in the weakened layer occurs by heat treatment at a relatively low temperature, and a thin single crystal semiconductor layer can be formed by separation along the weakened layer. After irradiation with fluorine ions, hydrogen ions may be irradiated so that hydrogen is included in the cavity. The weakened layer formed to separate the thin single crystal semiconductor layer from the single crystal semiconductor substrate is separated by utilizing the volume change of the minute cavity formed in the weakened layer. It is preferable to effectively use the action of hydrogen ions.

Further, a protective layer may be formed between the single crystal semiconductor substrate and the insulating layer bonded to the single crystal semiconductor layer. The protective layer can be formed by a single layer or a stacked layer structure including a plurality of layers selected from a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer. These layers can be formed over the single crystal semiconductor substrate before the weakening layer is formed over the single crystal semiconductor substrate. Alternatively, the weakening layer may be formed over the single crystal semiconductor substrate and then formed over the single crystal semiconductor substrate.

Note that the silicon oxynitride film has a composition that contains more oxygen than nitrogen, and includes Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). As a concentration range, oxygen is included in the range of 50 to 70 atomic%, nitrogen is 0.5 to 15 atomic%, Si is 25 to 35 atomic%, and hydrogen is 0.1 to 10 atomic%. Means what In addition, the silicon nitride oxide film has a composition containing more nitrogen than oxygen. When measured using RBS and HFS, the concentration range of oxygen is 5 to 30 atomic%, nitrogen. In the range of 20 to 55 atomic%, Si in the range of 25 to 35 atomic%, and hydrogen in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, Si, and hydrogen is included in the above range.

In formation of the weakened layer, it is necessary to irradiate ions with a high dose condition, and the surface of the single crystal semiconductor substrate 1108 may be rough. Therefore, a protective layer against ion irradiation may be provided with a thickness of 50 nm to 200 nm by a silicon nitride film, a silicon nitride oxide film, a silicon oxide film, or the like on the surface irradiated with ions.

For example, a silicon oxynitride film (film thickness: 5 nm to 300 nm, desirably 30 nm to 150 nm (eg, 50 nm)) and a silicon nitride oxide film (film thickness: 5 nm to 150 nm, desirably, as a protective layer over the single crystal semiconductor substrate 1108 by plasma CVD. Forms a stack of 10 nm to 100 nm (for example, 50 nm). As an example, a silicon oxynitride film is formed with a thickness of 50 nm over the single crystal semiconductor substrate 1108, and a silicon nitride oxide film is formed with a thickness of 50 nm over the silicon oxynitride film. The silicon oxynitride film may be a silicon oxide film manufactured by a chemical vapor deposition method using an organosilane gas.

Alternatively, the single crystal semiconductor substrate 1108 may be degreased and cleaned, and the surface oxide film may be removed to perform thermal oxidation. As the thermal oxidation, normal dry oxidation may be used, but it is preferable to perform oxidation by adding halogen in an oxidizing atmosphere. For example, heat treatment is performed at a temperature of 700 ° C. or higher in an atmosphere containing HCl at 0.5 to 10% by volume (preferably 3% by volume) with respect to oxygen. The thermal oxidation is preferably performed at a temperature of 950 ° C. to 1100 ° C. The treatment time may be 0.1 to 6 hours, preferably 0.5 to 3.5 hours. The thickness of the oxide film to be formed is 10 nm to 1000 nm (preferably 50 nm to 200 nm), for example, 100 nm.

In addition to HCl, one or a plurality selected from HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , Br ₂ , dichloroethylene, and the like can be used as the halogen-containing material.

By performing heat treatment in such a temperature range, a gettering effect by a halogen element can be obtained. Gettering is particularly effective in removing metal impurities. That is, by the action of chlorine, impurities such as metals become volatile chlorides and are released into the gas phase and removed. This is effective for the surface of the single crystal semiconductor substrate 1108 subjected to chemical mechanical polishing (CMP) treatment. Hydrogen also acts to compensate for defects at the interface between the single crystal semiconductor substrate 1108 and the insulating layer to be formed and to reduce the localized level density of the interface, so that the interface between the single crystal semiconductor substrate 1108 and the insulating layer is reduced. It is inactivated and the electrical characteristics are stabilized.

Halogen can be contained in the oxide film formed by this heat treatment. The halogen element is contained at a concentration of 1 × 10 ¹⁷ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ so that it functions as a protective layer that captures impurities such as metal and prevents contamination of the single crystal semiconductor substrate 1108. Can be made.

When the weakening layer 1110 is formed, the acceleration voltage and the total number of ions are determined by the thickness of the film deposited on the single crystal semiconductor substrate and the single crystal semiconductor which is transferred from the target single crystal semiconductor substrate and transferred onto the substrate. It can be adjusted according to the film thickness of the layer and the ion species to be irradiated.

For example, the weakened layer can be formed by using hydrogen gas as a raw material by ion doping, irradiating ions with an acceleration voltage of 40 kV and a total number of ions of 2 × 10 ¹⁶ ions / cm ² . If the thickness of the protective layer is increased, when a weakened layer is formed by irradiating ions under the same conditions, the single crystal semiconductor layer is separated from the target single crystal semiconductor substrate and transferred (transferred) onto the substrate. A thin single crystal semiconductor layer can be formed. For example, although depending on the ratio of ion species (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ions), a weakened layer is formed under the above conditions, and a silicon oxynitride film (film) is formed on the single crystal semiconductor substrate as a protective layer. When a protective layer is formed by stacking a silicon nitride oxide film (thickness 50 nm) and a silicon nitride oxide film (film thickness 50 nm), the thickness of the single crystal semiconductor layer transferred to the substrate is approximately 120 nm, and the silicon oxynitride film (film) is formed over the single crystal semiconductor substrate. When a protective layer is formed by stacking a silicon nitride oxide film (thickness: 100 nm) and a silicon nitride oxide film (thickness: 50 nm), the thickness of the single crystal semiconductor layer transferred to the substrate is approximately 70 nm.

When helium (He) or hydrogen is used as a raw material gas, irradiation is accelerated by accelerating voltage in the range of 10 kV to 200 kV and dose in the range of 1 × 10 ¹⁶ ions / cm ^{2 to} 6 × 10 ¹⁶ ions / cm ² . A layer can be formed. When helium is used as a source gas, He ⁺ ions can be irradiated as main ions without mass separation. In addition, when hydrogen is used as a source gas, irradiation can be performed using H ₃ ⁺ ions or H ₂ ⁺ ions as main ions. The ion species also varies depending on the plasma generation method, pressure, source gas supply amount, and acceleration voltage.

As an example of forming a weakened layer, a silicon oxynitride film (film thickness 50 nm), a silicon nitride oxide film (film thickness 50 nm), and a silicon oxide film (film thickness 50 nm) are stacked as a protective layer over a single crystal semiconductor substrate. Then, hydrogen is irradiated at an acceleration voltage of 40 kV and a dose of 2 × 10 ¹⁶ ions / cm ² to form a weakened layer on the single crystal semiconductor substrate. Thereafter, a silicon oxide film (film thickness: 50 nm) is formed as an insulating layer having a bonding surface over the silicon oxide film which is the uppermost layer of the protective layer. As another example of forming the weakened layer, a silicon oxide film (film thickness: 100 nm) and a silicon nitride oxide film (film thickness: 50 nm) are stacked over a single crystal semiconductor substrate as a protective layer, and hydrogen is accelerated at a voltage of 40 kV and a dose. Irradiation is performed in an amount of 2 × 10 ¹⁶ ions / cm ² to form a weakened layer on the single crystal semiconductor substrate. After that, a silicon oxide film (film thickness: 50 nm) is formed as an insulating layer having a bonding surface over the silicon nitride oxide film which is the uppermost layer of the protective layer. Note that the silicon oxynitride film and the silicon nitride oxide film may be formed by a plasma CVD method, and the silicon oxide film may be formed by a CVD method using an organosilane gas.

An insulating layer may be formed between the substrate and the single crystal semiconductor substrate. The insulating layer may be formed on either the substrate side or the single crystal semiconductor substrate side, or may be formed on both. The insulating layer formed on the surface where the bond is formed has a smooth surface and forms a hydrophilic surface. As the insulating layer, a silicon oxide film can be used. As the silicon oxide film, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas is preferable. In addition, a silicon oxide film manufactured by a chemical vapor deposition method using silane gas can be used.

Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), trimethylsilane (TMS: (CH ₃ ) ₃ SiH), tetramethylsilane (chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclo Tetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) and other silicon-containing compounds can be used. Note that in the case where a silicon oxide layer is formed by a chemical vapor deposition method using organosilane as a source gas, it is preferable to mix an oxygen-providing gas. As a gas for imparting oxygen, oxygen, nitrous oxide, nitrogen dioxide, or the like can be used. Further, an inert gas such as argon, helium, nitrogen or hydrogen may be mixed.

Alternatively, a silicon oxide film formed by a chemical vapor deposition method using silane such as monosilane, disilane, or trisilane as a source gas can be used as an insulating layer formed on a surface where a bond is formed. Also in this case, it is preferable to mix an oxygen-providing gas, an inert gas, or the like. Further, the silicon oxide film to be an insulating layer bonded to the single crystal semiconductor layer may contain chlorine. Note that in this specification, a chemical vapor deposition (CVD) method includes, in its category, a plasma CVD method, a thermal CVD method, and a photo CVD method.

In addition, as an insulating layer formed on the surface to form a bond, silicon oxide formed by heat treatment in an oxidizing atmosphere, silicon oxide grown by reaction of oxygen radicals, chemical oxide formed by an oxidizing chemical, etc. Can also be applied. An insulating layer containing a siloxane (Si—O—Si) bond may be used as the insulating layer. Further, the insulating layer may be formed by reacting the organic silane gas with oxygen radicals or nitrogen radicals.

In the insulating layer, the surface of the surface where the junction is formed preferably has an arithmetic average roughness Ra of less than 0.8 nm, a root mean square roughness Rms of less than 0.9 nm, an Ra of 0.4 nm or less, and an Rms of 0.5 nm. More preferably, Ra is 0.3 nm or less, and Rms is 0.4 nm or less. For example, Ra is 0.27 nm and Rms is 0.34 nm. In this specification, Ra is the arithmetic mean roughness, Rms is the root mean square roughness, and the measurement range is 2 μm ² or 10 μm ² .

When the substrate and the single crystal semiconductor substrate are bonded, an insulating layer made of a silicon oxide film formed preferably using organosilane as a raw material is provided on one or both of the surfaces where the bond is to be formed to form a strong bond. Can do.

In this embodiment, as illustrated in FIG. 15B, a silicon oxide film is formed as the insulating layer 1104 over a surface where a bond is formed with the substrate. As the silicon oxide film, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas is preferable. In addition, a silicon oxide film manufactured by a chemical vapor deposition method using silane gas can be used. In film formation by chemical vapor deposition, for example, a film formation temperature of 350 ° C. or less (specifically, 300 ° C.) is applied as a temperature at which degassing does not occur from the weakened layer 1110 formed over the single crystal semiconductor substrate. Is done. A heat treatment temperature higher than the deposition temperature is applied to the heat treatment for separating the single crystal semiconductor layer from the single crystal semiconductor substrate.

The substrate may be provided with a silicon nitride film or a silicon nitride oxide film which prevents diffusion of an impurity element as a blocking layer (also referred to as a barrier layer). Further, a silicon oxynitride film may be combined as an insulating film having a function of relieving stress.

FIG. 15C illustrates a mode in which the blocking layer 1109 provided over the substrate 1101 and the surface of the single crystal semiconductor substrate 1108 where the insulating layer 1104 is formed are in close contact with each other. The surface on which the bond is formed is sufficiently cleaned. The surface over which the blocking layer 1109 provided over the substrate 1101 and the insulating layer 1104 of the single crystal semiconductor substrate 1108 are formed may be cleaned by megasonic cleaning or the like. Further, after the megasonic cleaning, cleaning with ozone water may be performed to remove organic substances and improve the hydrophilicity of the surface.

When the blocking layer 1109 and the insulating layer 1104 on the substrate 1101 are made to face each other and pressed one place from the outside, the distance between the bonding surfaces is locally reduced, thereby contributing to the increase in van der Waals force and hydrogen bonding. By attracting each other. Further, since the distance between the blocking layer 1109 and the insulating layer 1104 on the opposing substrate 1101 is reduced even in the adjacent region, the region in which Van der Waals force acts strongly or the region in which hydrogen bonding is involved is expanded. (Also referred to as bonding) proceeds and the bonding spreads over the entire bonding surface.

When pressing, if one of the four corners of the substrate is suppressed by a pressure of 100 kPa to 5000 kPa, the joint surfaces approach each other, and a transition from van der Waals force to hydrogen bonding can be achieved. When one bonding surface in the substrate approaches, the adjacent bonding surfaces also approach and shift to hydrogen bonds, so that the entire bonding surface can shift to hydrogen bonds.

In order to form a good bond, the surface may be activated. For example, an atomic beam or an ion beam is irradiated to the surface on which the junction is formed. When an atomic beam or an ion beam is used, an inert gas neutral atom beam or inert gas ion beam such as argon can be used. In addition, plasma irradiation or radical treatment is performed. Such surface treatment makes it easy to form a bond between different materials even at a temperature of 200 ° C. to 400 ° C.

Further, heat treatment is preferably performed in order to improve the bonding strength at the bonding interface between the substrate and the insulating layer. For example, heat treatment is performed in a temperature condition of 70 ° C. to 350 ° C. (for example, 200 ° C. for 2 hours) in an oven or a furnace.

In FIG. 15D, after the substrate 1101 and the single crystal semiconductor substrate 1108 are attached to each other, heat treatment is performed so that the single crystal semiconductor substrate 1108 is separated from the substrate 1101 with the weakened layer 1110 serving as a cleavage plane. For example, by performing a heat treatment at 400 ° C. to 700 ° C., a volume change of a minute cavity formed in the weakened layer 1110 occurs, and it is possible to cleave along the weakened layer 1110. Since the insulating layer 1104 is bonded to the substrate 1101 through the blocking layer 1109, the single crystal semiconductor layer 1102 having the same crystallinity as the single crystal semiconductor substrate 1108 remains over the substrate 1101.

The heat treatment in the temperature range of 400 ° C. to 700 ° C. may be continuously performed with the same apparatus as the heat treatment for improving the above-described bonding strength, or may be performed with another apparatus. For example, after heat treatment at 200 ° C. for 2 hours in a furnace, the temperature is raised to near 600 ° C., held for 2 hours, the temperature is lowered to a temperature range from 400 ° C. to room temperature, and then removed from the furnace. Further, the heat treatment may be performed from room temperature. In addition, after heat treatment at 200 ° C. for 2 hours in a furnace, heat treatment is performed in a temperature range of 600 ° C. to 700 ° C. for 1 minute to 30 minutes (for example, 600 ° C. for 7 minutes, 650 ° C. for 7 minutes) using a rapid thermal annealing (RTA) apparatus. May be.

By heat treatment in the temperature range of 400 ° C. to 700 ° C., the bonding between the insulating layer and the substrate shifts from a hydrogen bond to a covalent bond, the element added to the weakened layer is precipitated, and the pressure rises, and the single crystal semiconductor substrate The single crystal semiconductor layer can be peeled more. After the heat treatment, one of the substrate and the single crystal semiconductor substrate is placed on the other, and the substrate and the single crystal semiconductor substrate can be separated without applying a large force. For example, the user can speak easily by lifting the substrate placed above with a vacuum chuck. At this time, if the lower substrate is fixed with a vacuum chuck or a mechanical chuck, both the substrate and the single crystal semiconductor substrate can be separated from each other without horizontal displacement.

15 and 16 illustrate examples in which the single crystal semiconductor substrate 1108 is smaller than the substrate 1101, the present invention is not limited thereto, and the single crystal semiconductor substrate 1108 and the substrate 1101 may have the same size. Alternatively, the single crystal semiconductor substrate 1108 may be larger than the substrate 1101.

FIG. 16 illustrates a step of forming a single crystal semiconductor layer by providing an insulating layer on the substrate side. FIG. 16A illustrates a step of forming a weakened layer 1110 by irradiating a single crystal semiconductor substrate 1108 provided with a silicon oxide film as a protective layer 1121 with ions accelerated by an electric field to a predetermined depth. . Ion irradiation is the same as in the case of FIG. By forming the protective layer 1121 over the surface of the single crystal semiconductor substrate 1108, the surface can be prevented from being damaged by ion irradiation and flatness can be prevented from being impaired. In addition, the protective layer 1121 exhibits an impurity diffusion preventing effect on the single crystal semiconductor layer 1102 formed from the single crystal semiconductor substrate 1108.

FIG. 16B illustrates a process in which a substrate 1101 over which a blocking layer 1109 and an insulating layer 1104 are formed and a surface of the single crystal semiconductor substrate 1108 on which the protective layer 1121 is formed are closely attached to form a bond. A bond is formed by closely attaching the insulating layer 1104 over the substrate 1101 and the protective layer 1121 of the single crystal semiconductor substrate 1108.

After that, the single crystal semiconductor substrate 1108 is peeled off as shown in FIG. Heat treatment for separating the single crystal semiconductor layer is performed in a manner similar to that in FIG. In this manner, the SOI structure semiconductor substrate of the present invention having a single crystal semiconductor layer through the insulating layer shown in FIG. 16C can be obtained.

In addition, the single crystal semiconductor layer separated from the single crystal semiconductor substrate and transferred to the substrate has crystal defects caused by the separation process and the ion implantation process, and the surface is not flat and uneven. May end up. In the case of manufacturing a transistor as a semiconductor element using a single crystal semiconductor layer, it is difficult to form a thin gate insulating layer with high withstand voltage on the top surface of the uneven single crystal semiconductor layer. In addition, a crystal defect in the single crystal semiconductor layer affects the performance and reliability of the transistor, such as an increase in the density of localized interface states with the gate insulating layer.

Accordingly, it is preferable to reduce crystal defects by irradiating the single crystal semiconductor layer with electromagnetic waves such as laser light. By irradiation with electromagnetic waves, at least part of the single crystal semiconductor layer can be melted and crystal defects in the single crystal semiconductor layer can be reduced. Note that an oxide film (a natural oxide film or a chemical oxide film) formed on the surface of the single crystal semiconductor layer is preferably removed with dilute hydrofluoric acid before irradiation with electromagnetic waves.

Any electromagnetic wave may be used as long as it can supply high energy to the single crystal semiconductor layer, and laser light can be preferably used.

The energy can also be supplied mainly by heat conduction by causing particles having high energy to collide with the single crystal semiconductor layer by irradiation or the like. As a heat source for providing particles having high energy, a plasma can be used, and a flame such as an atmospheric plasma, a high pressure plasma, a thermal plasma jet, a gas burner can be used, and an electron beam is used as another heat source. Etc. can be used.

The wavelength of the electromagnetic wave is a wavelength that is absorbed by the single crystal semiconductor layer. The wavelength can be determined in consideration of the skin depth of the electromagnetic wave. For example, the wavelength of the electromagnetic wave can be 190 nm to 600 nm. The energy of the electromagnetic wave can be determined in consideration of the wavelength of the electromagnetic wave, the skin depth of the electromagnetic wave, the thickness of the single crystal semiconductor layer to be irradiated, and the like.

As a laser that oscillates laser light, a continuous wave laser, a pseudo continuous wave laser, or a pulsed laser can be used. A pulsed laser is preferable for partial melting. For example, there is an excimer laser such as a KrF laser, or a gas laser such as an Ar laser or a Kr laser. Other solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, KGW laser, KYW laser, alexandrite laser, Ti: sapphire laser, and Y ₂ O ₃ laser. An excimer laser is a pulsed laser, but some solid-state lasers such as a YAG laser can be a continuous wave laser, a pseudo continuous wave laser, or a pulsed laser. In the solid-state laser, it is preferable to apply the second to fifth harmonics of the fundamental wave. A semiconductor laser such as GaN, GaAs, GaAlAs, InGaAsP, or the like can also be used.

If the single crystal semiconductor layer can be irradiated with electromagnetic wave energy, lamp light may be used. For example, light emitted from an ultraviolet lamp, black light, halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp may be used. Flash annealing using the lamp light may be used. Flash annealing that is preferably performed using a halogen lamp, a xenon lamp, or the like may be performed in an extremely short time, and thus the temperature rise of the substrate can be suppressed.

In order to adjust the shape of the electromagnetic wave and the path of the electromagnetic wave, an optical system including a reflector such as a shutter, a mirror or a half mirror, a cylindrical lens, or a convex lens may be installed.

Note that an electromagnetic wave irradiation method may selectively irradiate electromagnetic waves, or light (electromagnetic waves) may be irradiated by scanning light (electromagnetic waves) in the XY axis direction. In this case, it is preferable to use a polygon mirror or a galvanometer mirror for the optical system.

Irradiation with electromagnetic waves can be performed in an atmosphere containing oxygen such as an air atmosphere or an inert atmosphere such as a nitrogen atmosphere. In order to irradiate electromagnetic waves in an inert atmosphere, electromagnetic waves may be irradiated in an airtight chamber and the atmosphere in the chamber may be controlled. When a chamber is not used, a nitrogen atmosphere can be formed by spraying an inert gas such as nitrogen gas on the surface irradiated with electromagnetic waves.

Further, polishing treatment may be performed on the surface of the single crystal semiconductor layer which is supplied with high energy such as electromagnetic wave irradiation and crystal defects are reduced. The planarity of the surface of the single crystal semiconductor layer can be improved by the polishing treatment.

As the polishing treatment, a chemical mechanical polishing (CMP) method or a liquid jet polishing method can be used. Note that the surface of the single crystal semiconductor layer is cleaned and cleaned before the polishing treatment. Cleaning may be performed using megasonic cleaning, two-fluid jet cleaning, or the like, and dust or the like on the surface of the single crystal semiconductor layer is removed by cleaning. In addition, it is preferable that a natural oxide film or the like on the surface of the single crystal semiconductor layer be removed using diluted hydrofluoric acid to expose the single crystal semiconductor layer.

In addition, polishing treatment (or etching treatment) may be performed on the surface of the single crystal semiconductor layer before irradiation with electromagnetic waves.

In addition, when the single crystal semiconductor layer is transferred from the single crystal semiconductor substrate, the single crystal semiconductor substrate may be selectively etched and the plurality of single crystal semiconductor layers whose shapes are processed may be transferred to the substrate. A plurality of island-shaped single crystal semiconductor layers can be formed over the substrate. Since the shape is processed and transferred in advance using a single crystal semiconductor substrate, the size and shape of the single crystal semiconductor substrate are not limited. Therefore, transfer of the single crystal semiconductor layer to a large substrate can be performed more efficiently.

Furthermore, etching may be performed on the single crystal semiconductor layer bonded to the substrate, and the shape of the single crystal semiconductor layer may be processed and corrected to be precisely controlled. This allows processing into the shape of a single crystal semiconductor layer of a semiconductor element, and an error in the formation position of the single crystal semiconductor layer due to pattern misalignment due to exposure wraparound at the time of resist mask formation or misalignment due to the bonding process during transfer. And shape defects can be corrected.

Accordingly, a plurality of single crystal semiconductor layers having a desired shape can be formed over the substrate with high yield. Therefore, a semiconductor device including a precise high-performance semiconductor element and an integrated circuit can be manufactured with high throughput and high productivity.

Alternatively, the single crystal semiconductor layer may be separated from the single crystal semiconductor substrate and then bonded to the substrate. The surface of the single crystal semiconductor layer exposed by cleavage may be bonded to the substrate side, or the single crystal semiconductor layer is formed so that the surface of the single crystal semiconductor layer exposed by cleavage and the gate insulating film are in contact with each other. You may affix on a board | substrate.

In this embodiment, when a single crystal silicon substrate is used as the single crystal semiconductor substrate 1108, a single crystal silicon layer can be obtained as the single crystal semiconductor layer 1102. Further, in the method for manufacturing a semiconductor device of this embodiment, a process temperature can be set to 700 ° C. or lower, so that a glass substrate can be used as the substrate 1101. That is, it can be formed over a glass substrate in the same manner as a conventional thin film transistor, and a single crystal silicon layer can be applied to a semiconductor layer. With these features, high-performance, high-reliability transistors, such as high-speed operation, low subthreshold values, high field-effect mobility, and low-voltage consumption, can be formed over a light-transmitting substrate such as a glass substrate. Can be produced.

This embodiment can be combined with Embodiment 1 and Embodiment 2 as appropriate.

(Embodiment 4)
In this embodiment, an example in which the single crystal semiconductor layer is bonded to the substrate from the single crystal semiconductor substrate in Embodiment 3 will be described. Therefore, repetitive description of the same portions as those in Embodiment 3 or portions having similar functions is omitted.

First, processing on the single crystal substrate side will be described. In this embodiment, the single crystal semiconductor substrate is degreased and cleaned, and the surface oxide film is removed to perform thermal oxidation. As thermal oxidation, it is preferable to perform oxidation with halogen added in an oxidizing atmosphere. For example, heat treatment is performed at a temperature of 700 ° C. or higher in an atmosphere containing HCl at 0.5 to 10% by volume (preferably 3% by volume) with respect to oxygen. The thermal oxidation is preferably performed at a temperature of 950 ° C. to 1100 ° C. The treatment time may be 0.1 to 6 hours, preferably 0.5 to 3.5 hours. The thickness of the oxide film to be formed is 10 nm to 1000 nm (preferably 50 nm to 200 nm), for example, 100 nm.

In addition to HCl, one or more selected from HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , Br _{2 and the} like can be used as the halogen-containing material.

By performing heat treatment in such a temperature range, a gettering effect by a halogen element can be obtained. Gettering is particularly effective in removing metal impurities. That is, by the action of chlorine, impurities such as metals become volatile chlorides and are released into the gas phase and removed. This is effective for a single crystal semiconductor substrate whose surface has been subjected to chemical mechanical polishing (CMP). In addition, hydrogen compensates for defects at the interface between the single crystal semiconductor substrate and the insulating layer formed on the substrate to reduce the localized level density of the interface, thereby reducing the interface between the single crystal semiconductor substrate and the insulating layer. Is inactivated and the electrical characteristics are stabilized.

Halogen can be contained in the oxide film formed by this heat treatment. When the halogen element is contained at a concentration of 1 × 10 ¹⁷ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ , it captures impurities such as metal and exhibits a function as a protective layer that prevents contamination of the single crystal semiconductor substrate. be able to.

Ions are introduced into the single crystal semiconductor substrate to form a weakened layer. The depth of the region where the weakened layer is formed can be adjusted by the acceleration energy and incident angle of the introduced ions. The acceleration energy can be adjusted by the acceleration voltage, the dose amount, and the like.

As a gas used for the introduction of ions, there are a hydrogen gas, a rare gas, and the like. In this embodiment, it is preferable to use a hydrogen gas. When hydrogen gas is used in the ion doping method, the ion species to be generated are H ⁺ , H ₂ ⁺ and H ₃ ⁺ , but it is preferable that H ₃ ⁺ is introduced in the largest amount. H ₃ ⁺ has higher ion introduction efficiency than H ⁺ and H ₂ ^{+, and} can shorten the introduction time. Moreover, it becomes easy to produce a crack in a weakened layer in a later process.

Next, processing on the substrate side will be described. First, the surface of the substrate is cleaned. The cleaning may be performed by ultrasonic cleaning using hydrochloric acid / hydrogen peroxide (HPM), sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), dilute hydrofluoric acid (DHF), and the like. Perform ultrasonic cleaning with water.

Next, planarization treatment by plasma treatment is performed on the substrate from which impurities such as dust on the surface are removed by cleaning. In this embodiment mode, plasma treatment is performed in a plasma state by using an inert gas such as argon (Ar) gas in a vacuum chamber and applying a bias voltage to a substrate which is an object to be processed. Oxygen (O ₂ ) gas and nitrogen (N ₂ ) gas may be introduced together with the inert gas.

With the substrate facing the cathode, Ar cations in the plasma are accelerated toward the cathode and collide with the substrate. The substrate surface is sputter-etched by the collision of Ar cations, and the convex portion of the substrate surface can be etched to flatten the surface of the substrate. The reactive gas has an effect of repairing defects caused by sputter etching on the substrate surface.

Next, an insulating layer is formed over the substrate. In this embodiment, an oxide film containing aluminum oxide as a main component, which is an insulating layer other than a silicon-based insulating layer, is used. An oxide film containing aluminum oxide as a main component refers to an oxide film containing 10% by weight or more of aluminum oxide when the total of components contained in the oxide film is 100% by weight. In addition, as the insulating layer, a film containing aluminum oxide as a main component and containing one or both of magnesium oxide and strontium oxide can be used. Alternatively, aluminum oxide containing nitrogen may be used.

The insulating layer can be formed by a sputtering method. As a target used in the sputtering method, for example, a metal containing aluminum or a metal oxide such as aluminum oxide can be used. Note that a target material may be selected as appropriate depending on a film to be formed.

When a metal is used as the target, the insulating layer is formed by sputtering (reactive sputtering method) while introducing a reactive gas (for example, oxygen). As the metal, in addition to aluminum, magnesium (Mg), an alloy containing aluminum and magnesium, an alloy containing aluminum and strontium (Sr), or an alloy containing aluminum, magnesium and strontium can be used. In this case, sputtering may be performed using a direct current (DC) power source or a radio frequency (RF) power source.

In the case where a metal oxide is used as a target, the insulating layer is formed by sputtering using a radio frequency (RF) power source (RF sputtering method). As the metal oxide, in addition to aluminum oxide, magnesium oxide, strontium oxide, an oxide containing aluminum and magnesium, an oxide containing aluminum and strontium, or an oxide containing aluminum, magnesium and strontium may be used. it can.

In addition, the insulating layer may be formed using a bias sputtering method. When the bias sputtering method is used, both the volume of the film and the planarization of the surface can be performed.

An oxide film containing aluminum as its main component can prevent impurities such as mobile ions and moisture contained in the substrate from diffusing into a single crystal semiconductor film formed over the substrate later.

Next, the surface of the single crystal semiconductor substrate and the surface of the substrate are opposed to each other, and the single crystal semiconductor substrate and the insulating layer are bonded to each other. A bond is formed by closely contacting the single crystal semiconductor substrate and the surface of the insulating layer formed over the substrate.

Note that before the single crystal semiconductor substrate and the substrate are bonded to each other, surface treatment of the insulating layer formed over the substrate is preferably performed.

Next, similarly to Embodiment Mode 3, a single crystal semiconductor layer can be formed over the substrate with an insulating layer interposed therebetween by heat treatment and separation (cleavage) in the weakened layer.

A semiconductor integrated circuit portion can be formed using a single crystal semiconductor layer provided over a substrate.

Next, a process of repeatedly using the separated single crystal semiconductor substrate (semiconductor substrate recycling process) will be described.

First, the separated single crystal semiconductor substrate is taken out. Due to the influence of edge roll-off, bonding to the substrate may not be sufficiently performed at the end portion of the single crystal semiconductor substrate. As a result, the single crystal semiconductor substrate is not separated by the weakened layer at the end portion, and an insulating layer or the like may remain.

A residue portion at an end portion of the single crystal semiconductor substrate is removed. The residual portion can be removed by performing a wet etching process. Specifically, wet etching is performed using a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (for example, product name: LAL500, manufactured by Stella Chemifa Corporation) as an etchant.

In addition, the weakened layer into which hydrogen ions are introduced can be removed by wet etching using an organic alkaline aqueous solution typified by TMAH (Tetra Methyl Ammonium Hydroxide). By performing such treatment, a step due to a residue at the end portion of the single crystal semiconductor substrate is reduced.

Next, the single crystal semiconductor substrate is oxidized in a halogen atmosphere to form an oxide film, and then the oxide film is removed. Hydrogen chloride (HCl) can be used as the halogen. By doing so, a gettering effect by a halogen element can be obtained. Gettering is particularly effective in removing metal impurities. That is, by the action of chlorine, impurities such as metals become volatile chlorides and are released into the gas phase and removed.

Next, a CMP process is performed on the single crystal semiconductor substrate as a polishing process. As a result, a step at the end portion of the single crystal semiconductor substrate can be removed, and the surface of the single crystal semiconductor substrate can be flattened. Thereafter, the obtained single crystal semiconductor substrate is reused as a base wafer.

As described in this embodiment mode, cost reduction can be achieved by repeatedly using a single crystal semiconductor substrate in a process for regenerating the single crystal semiconductor substrate. Further, by using the single crystal semiconductor substrate regeneration process described in this embodiment, the surface of the single crystal semiconductor substrate can be sufficiently planarized even when the single crystal semiconductor substrate is repeatedly used. Therefore, adhesion between the single crystal semiconductor substrate and the substrate can be improved, and bonding defects can be reduced.

This embodiment mode can be combined with any of Embodiment Modes 1 to 3 as appropriate.

(Embodiment 5)
In this embodiment, examples of various electronic devices including a sensor obtained by the present invention will be described.

In the sensor of the present invention, even if a resin layer functioning as a shock absorbing layer is formed, the substrate is further thinned by grinding and polishing, so it is thin, so that the electronic equipment to be mounted is also thinned and miniaturized. can do.

Examples of electronic devices to which the present invention is applied include computers, displays, mobile phones, and television devices. Specific examples of these electronic devices are shown in FIGS. 10A to 10C, FIGS. 11A and 11B, FIGS. 12, 13A and 13B, and FIG.

10A to 10C illustrate a mobile phone. FIG. 10A illustrates a main body (A) 701, a main body (B) 702, a housing 703, operation keys 704, an audio output unit 705, and an audio input unit. 706, a circuit board 707, a display panel (A) 708, a display panel (B) 709, a hinge 710, a light-transmitting material portion 711, and a sensor 712.

The sensor 712 detects light transmitted through the translucent material portion 711, and controls the luminance of the display panel (A) 708 and the display panel (B) 709 according to the detected illuminance of the external light, and the illuminance obtained by the sensor 712. The illumination of the operation key 704 is controlled according to the above. Thereby, current consumption of the mobile phone can be suppressed.

FIG. 10B and FIG. 10C illustrate another example of a mobile phone. 10B and 10C, a main body 721, a housing 722, a display panel 723, operation keys 724, an audio output unit 725, an audio input unit 726, a sensor 727, and a sensor 728 are illustrated.

In the mobile phone illustrated in FIG. 10B, the brightness of the display panel 723 and the operation key 724 can be controlled by detecting external light using the sensor 727 provided in the main body 721.

In addition, in the cellular phone illustrated in FIG. 10C, a sensor 728 is provided inside the main body 721 in addition to the structure in FIG. The luminance of the backlight provided in the display panel 723 can be detected by the sensor 728.

FIG. 11A illustrates a computer, which includes a main body 731, a housing 732, a display portion 733, a keyboard 734, an external connection port 735, a pointing device 736, and the like.

FIG. 11B illustrates a television device which is an example of a display device, which includes a housing 741, a support base 742, a display portion 743, and the like.

FIG. 12 shows a detailed structure in the case where a liquid crystal panel is used as the display portion 733 provided in the computer of FIG. 11A and the display portion 743 of the display device shown in FIG.

A liquid crystal panel 762 illustrated in FIG. 12 is incorporated in a housing 761, and includes a substrate 751a and a substrate 751b, a liquid crystal layer 752 sandwiched between the substrate 751a and the substrate 751b, a polarization filter 752a and a polarization filter 752b, a backlight 753, and the like. have. A sensor 754 is formed in the housing 761.

The sensor 754 manufactured using the present invention senses the amount of light from the backlight 753, and the information is fed back to adjust the luminance of the liquid crystal panel 762.

13A and 13B are diagrams illustrating an example of a camera including a sensor 810 using the present invention, for example, a digital camera. FIG. 13A is a perspective view seen from the front side of the digital camera, and FIG. 13B is a perspective view seen from the rear side. 13A, the digital camera includes a release button 801, a main switch 802, a finder window 803, a flash 804, a lens 805, a lens barrel 806, a housing 807, and a sensor 810.

In FIG. 13B, a viewfinder eyepiece window 811, a monitor 812, and operation buttons 813a and 813b are provided.

When the release button 801 is pressed down to a half position, the focus adjustment mechanism and the exposure adjustment mechanism are operated, and when the release button 801 is pressed down to the lowest position, the shutter is opened.

A main switch 802 switches the power of the digital camera on and off when pressed or rotated.

The viewfinder window 803 is an apparatus for confirming a shooting range and a focus position from the viewfinder eyepiece window 811 shown in FIG.

The flash 804 is arranged at the upper front of the digital camera. When the subject brightness is low, the release button is pressed to open the shutter and simultaneously emit auxiliary light.

The lens 805 is disposed in front of the digital camera. The lens is composed of a focusing lens, a zoom lens, and the like, and constitutes a photographing optical system together with a shutter and a diaphragm (not shown). In addition, an imaging element such as a CCD (Charge Coupled Device) is provided behind the lens.

The lens barrel 806 moves the lens position in order to focus the focusing lens, the zoom lens, and the like. During photographing, the lens barrel 805 is extended to move the lens 805 forward. Further, when carrying the camera, the lens 805 is moved down to be compact. In the present embodiment, the structure is such that the subject can be zoomed by extending the lens barrel. However, the present invention is not limited to this structure, and the structure of the imaging optical system in the housing 807 is not limited. It may be a digital camera capable of zooming without extending the cylinder.

The viewfinder eyepiece window 811 is provided on the upper rear surface of the digital camera, and is a window provided for eye contact when confirming the photographing range and the focus position.

The operation buttons 813 are various function buttons provided on the rear surface of the digital camera, and include a setup button, a menu button, a display button, a function button, a selection button, and the like.

When the present invention is applied and the sensor 810 is incorporated in the camera shown in FIGS. 13A and 13B, the sensor 810 can detect the presence and intensity of light, thereby adjusting the exposure of the camera. It can be performed. Since the sensor of the present invention is thin, the device can be miniaturized even if it is mounted. Miniaturization of components such as sensors is particularly useful when used in portable electronic devices.

The present invention can also be applied to a portable information terminal having a sound reproduction function. FIG. 14 shows a digital player, which is one typical example of an audio device. A digital player shown in FIG. 14 includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, a sensor 2135, a sensor 2136, a control portion 2137, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134.

Since the sensor 2135 is an optical sensor that detects light according to the present invention, the sensor 2135 is provided in a region that is shielded when the earphone is worn. On the other hand, since the sensor 2136 is a pressure-sensitive sensor, the earphone is provided in a region that comes into contact with the ear when the earphone is worn. The sensor 2135 can detect whether the earphone is attached or not, depending on whether light is detected or the sensor 2136 detects pressure. Based on information detected by the sensor 2135 and the sensor 2136, the control unit 2137 performs control so that the digital player is turned on when the earphone is worn and turned off when the earphone is not worn. Therefore, the digital player can be automatically switched on and off by attaching or not wearing the earphone without directly operating the operation unit 2133 of the digital player main body 2130.

The color sensor of the present invention can be used as the sensor 2138. Light from the outside can be detected, and the luminance of the display portion 2131 can be controlled in accordance with the detected illuminance of the external light.

In addition, by operating the operation unit 2133 using the memory unit 2132, video and audio (music) can be recorded and reproduced. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. Note that the memory provided in the memory portion 2132 may be removable.

The semiconductor device of the present invention can be applied to other electronic devices such as a projection television and a navigation system. In other words, it can be used for any object that needs to detect light.

Note that this embodiment can be combined with any of Embodiments 1 to 4 as appropriate.

6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Claims (9)

Forming a plurality of semiconductor integrated circuit portions on the first surface of the first substrate having translucency;
Reducing the thickness of the first substrate;
Fixing the semiconductor integrated circuit portion and the first surface of the second substrate with an adhesive;
Between the semiconductor integrated circuit portions , cutting the first substrate having the reduced thickness,
A first of the second surface of the substrate by thinning the thickness, the first cutting surface of the substrate having a reduced plurality of said thickness, and a plurality of side surfaces of the semiconductor integrated circuit portion, the second Forming a resin layer continuously covering the first surface of the substrate;
Between the semiconductor integrated circuit portions , cutting the resin layer ,
A method for manufacturing a semiconductor device, wherein the semiconductor integrated circuit portion is separated from the second substrate by removing the adhesive . Forming a plurality of semiconductor integrated circuit portions on the first surface of the first substrate having translucency;
Reducing the thickness of the first substrate;
A chromatic first resin layer having translucency is formed on the second surface of the first substrate having the reduced thickness,
Fixing the semiconductor integrated circuit portion and the first surface of the second substrate with an adhesive;
Between the semiconductor integrated circuit portions , the first substrate having a reduced thickness and the chromatic color first resin layer having translucency are cut,
The chromatic first resin layer having translucency, the cut surface of the plurality of chromatic first resin layers having translucency, and the plurality of first substrates having the reduced thickness. and the cut surface to form a plurality of the semiconductor and the side surface of the integrated circuit portion, the second resin layer over a first surface of the second substrate continuously,
Between the semiconductor integrated circuit portions , the second resin layer is cut ,
A method for manufacturing a semiconductor device, wherein the semiconductor integrated circuit portion is separated from the second substrate by removing the adhesive . Forming a plurality of semiconductor integrated circuit portions on the first surface of the first substrate having translucency;
Reducing the thickness of the first substrate;
Fixing the semiconductor integrated circuit portion and the first surface of the second substrate with an adhesive;
Between the semiconductor integrated circuit portions , cutting the first substrate having the reduced thickness,
A first of the second surface of the substrate by thinning the thickness, the first cutting surface of the substrate having a reduced plurality of said thickness, and a plurality of side surfaces of the semiconductor integrated circuit portion, the second Forming a chromatic first resin layer having translucency by continuously covering the first surface of the substrate;
Forming a second resin layer above the first resin layer;
Between the semiconductor integrated circuit portions , the first resin layer and the second resin layer are cut ,
A method for manufacturing a semiconductor device, wherein the semiconductor integrated circuit portion is separated from the second substrate by removing the adhesive . Forming a plurality of semiconductor integrated circuit portions on the first surface of the first substrate having translucency;
Reducing the thickness of the first substrate;
Fixing the semiconductor integrated circuit portion and the first surface of the second substrate with an adhesive;
Between the semiconductor integrated circuit portions , cutting the first substrate having the reduced thickness,
A partial area of the second surface of the first substrate that thinning the thickness, the first cutting surface of the substrate having a reduced plurality of said thickness, and a plurality of side surfaces of said semiconductor integrated circuit section Forming a light shielding layer continuously covering the first surface of the second substrate;
A resin layer is continuously formed on the second surface of the first substrate with the reduced thickness and the light shielding layer ,
Between the semiconductor integrated circuit portions , cutting the light shielding layer and the resin layer ,
A method for manufacturing a semiconductor device, wherein the semiconductor integrated circuit portion is separated from the second substrate by removing the adhesive . Forming a plurality of semiconductor integrated circuit portions on the first surface of the first substrate having translucency;
Reducing the thickness of the first substrate;
Fixing the semiconductor integrated circuit portion and the first surface of the second substrate with an adhesive;
Between the semiconductor integrated circuit portions , cutting the first substrate having the reduced thickness,
A first of the second surface of the substrate by thinning the thickness, the first cutting surface of the substrate having a reduced plurality of said thickness, and a plurality of side surfaces of the semiconductor integrated circuit portion, the second Forming a chromatic first resin layer having translucency by continuously covering the first surface of the substrate;
Forming a light shielding layer in a partial region above the first resin layer;
Forming a second resin layer above the light shielding layer;
Cutting between the first resin layer, the light shielding layer, and the second resin layer between the semiconductor integrated circuit portions ;
A method for manufacturing a semiconductor device, wherein the semiconductor integrated circuit portion is separated from the second substrate by removing the adhesive . In claim 1 or 4,
The method for manufacturing a semiconductor device, wherein the resin layer is formed using a light-transmitting material. In claim 2, 3 or 5,
The method for manufacturing a semiconductor device, wherein the second resin layer is formed using a light-transmitting material. In any one of Claims 1 thru | or 7 ,
The method for manufacturing a semiconductor device, wherein the adhesive is removed by cleaning with an organic solvent. In any one of Claims 1 thru | or 8 ,
The method for manufacturing a semiconductor device, wherein the first substrate with the reduced thickness is cut using a dicer.

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