JP5294351B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact semiconductor device. <P>SOLUTION: A method of manufacturing the semiconductor device includes steps of: electrically connecting a plurality of first electrode pads (a) of a semiconductor chip 5 to a plurality of first connection portions 3b1 of a wiring board 2, respectively, through a plurality of first wires 10b1; electrically connecting second electrode pads (b) to a plurality of second connection portions 3b2 of the wiring board, respectively, through second wires 10b2; and electrically connecting third electrode pads (c) to a plurality of third connection portions 3b3 of the wiring board, respectively, through third wires 10b3. The plurality of first wires 10b1 are connected to first portions of the plurality of first connection portions 3b1, respectively, the third wires 10b3 are connected to second portions of the third connection portions 3b3, and the pluralities of first wires 10b1, second wires 10b2 and third wires 10b3 are extended from the plurality of electrode pads through a center portion of a second side of the semiconductor chip 5 in plan view at an acute angle to a virtual line 5s orthogonal to the second side. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor device in which an electrode pad of a semiconductor chip and an electrode pad of a wiring board are connected by a bonding wire.

  As a semiconductor device, for example, a semiconductor device called a BGA (Ball Grid Array) type is known. This BGA type semiconductor device is a package in which a semiconductor chip is mounted on the main surface side of a wiring board called an interposer, and a plurality of ball-like solder bumps are arranged as external connection terminals on the back surface side opposite to the main surface of the wiring board. It has a structure.

  BGA type semiconductor devices having various structures have been developed and commercialized, but are roughly classified into a face-up bonding structure (wire bonding structure) and a face-down bonding structure. In the face-up bonding structure, an electrical connection between an electrode pad arranged on the main surface (circuit forming surface) of the semiconductor chip and an electrode pad (connecting portion made up of a part of the wiring) arranged on the main surface of the wiring board. Connection is made with a bonding wire. In the face-down bonding structure, the electrical connection between the electrode pads arranged on the main surface of the semiconductor chip and the electrode pads arranged on the main surface of the wiring board is a protruding electrode (between these electrode pads ( For example, solder bumps, stud bumps, etc.).

  A BGA type semiconductor device having a face-up bonding structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-144214. A BGA type semiconductor device having a face-down bonding structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-34983.

  Japanese Patent Application Laid-Open No. 2003-31610 discloses a plurality of electrode pads arranged along one side of a main surface of a semiconductor chip, and two rows arranged along one side of the semiconductor chip on a main surface of a wiring board. In wire bonding in which a plurality of formed electrode pads are electrically connected by a plurality of bonding wires, a technique for avoiding interference between the previously formed wire and the capillary is disclosed.

JP 2001-144214 A JP-A-6-34983 JP 2003-31610 A

  In recent years, electronic devices such as mobile phones and portable personal computers have been downsized, and BGA type semiconductor devices incorporated in these electronic devices are also required to be downsized. Therefore, the present inventor has examined the downsizing of a BGA type semiconductor device having a face-up bonding structure that can be used at a low cost compared to the face-down structure because the existing manufacturing equipment can be used. I found.

  In order to reduce the size of the BGA type semiconductor device, it is necessary to reduce the plane size of the wiring board. In order to reduce the planar size of the wiring board, it is necessary to reduce the arrangement pitch of the electrode pads on the wiring board and to shorten the length of the pad row composed of a plurality of electrode pads.

  In the BGA type semiconductor device, a plurality of electrode pads (bonding pads) arranged along one side of the main surface of the semiconductor chip and a plurality of electrode pads arranged on the main surface of the wiring board corresponding to the plurality of electrode pads. The electrode pads (connection portions) are electrically connected by a plurality of bonding wires. In the conventional wiring board, a plurality of electrode pads are mainly arranged in one row. However, since this one-row pad arrangement cannot satisfy the required substrate size and wire length standard, the two-row pad is used. Multi-row pad arrangements such as an arrangement and a three-row pad arrangement are currently mainstream.

  In the multi-row pad arrangement, the length of each pad line is shorter than that in the single-row pad arrangement, but the number of electrode pads tends to increase as the integrated circuits mounted on the semiconductor chip become more multifunctional and highly integrated. Therefore, in order to reduce the size of the semiconductor device, it is necessary to reduce the arrangement pitch of the electrode pads and shorten the length of each pad row even in the multi-row pad arrangement.

  However, in the conventional multi-row pad arrangement, for example, the two-row pad arrangement, the wiring connected to the first electrode pad counted from the semiconductor chip side (wiring drawn from the electrode pad) passes between the second electrode pads. Since it is drawn, it is difficult to narrow the arrangement pitch of the electrode pads in the second row.

  Further, when the length of the pad row is increased, it is necessary to dispose the electrode pads of the wiring board away from the semiconductor chip, and accordingly, the electrode pads of the semiconductor chip and the electrode pads of the wiring board are electrically connected. The length of the bonding wire is increased. Also, because of the difference in processing accuracy, the arrangement pitch of the electrode pads on the wiring board is wider than the arrangement pitch of the electrode pads on the semiconductor chip, so that the length of the bonding wire extends from the center of the side of the semiconductor chip to its end. However, as the length of the pad row of the wiring board increases, the length of the bonding wire further increases. For this reason, when the resin sealing body is formed based on the transfer molding method, a problem that adjacent bonding wires are short-circuited easily occurs due to the wire flow in which the shape of the bonding wire is deformed by the flow of the resin. This defect causes a decrease in the manufacturing yield of the semiconductor device.

  In addition, since the arrangement pitch of the electrode pads on the wiring board is wider than the arrangement pitch of the electrode pads on the semiconductor chip, the bonding wire crosses the center of one side of the semiconductor chip with respect to a virtual line perpendicular to the one side. Although extending radially from the semiconductor chip side at an acute angle, the angle of the bonding wire with respect to the virtual line increases as the length of the pad row of the wiring board increases. For this reason, in an electrode pad of a semiconductor chip, when a bonding wire is connected to one of the two adjacent electrode pads and then the bonding wire is connected to the other electrode pad, it is connected to one electrode pad. The problem that the capillary interferes with the bonded bonding wire is likely to occur. This defect causes a decrease in the manufacturing yield of the semiconductor device.

  An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the manufacturing yield of semiconductor devices.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) The semiconductor device
A semiconductor chip having a plurality of electrode pads formed on the main surface and disposed along one side of the main surface;
A wiring board on which the semiconductor chip is mounted on the main surface;
A plurality of first connection portions formed on the main surface of the wiring board and disposed along the one side of the semiconductor chip;
A plurality of second portions formed on the main surface of the wiring board and disposed along the one side of the semiconductor chip at positions away from the one side of the semiconductor chip than the plurality of first connection portions. A connection,
A plurality of first wirings formed on the main surface of the wiring board and respectively connected to the plurality of first connection portions;
A plurality of second wirings formed on the main surface of the wiring board and respectively connected to the plurality of second connection portions;
A plurality of bonding wires respectively connecting the plurality of electrode pads and the plurality of first and second connection portions;
A resin sealing body for sealing the semiconductor chip and the plurality of bonding wires;
The plurality of first wirings extend from each of the plurality of first connection portions toward the one side of the semiconductor chip,
The plurality of second wirings extend from each of the plurality of second connection portions toward the side opposite to the one side of the semiconductor chip.
(2) In the means (1),
One end portions of the plurality of first wires are connected to the plurality of first connection portions, respectively.
One end portions of the plurality of second wires are connected to the plurality of second connection portions, respectively.
(3) In said means (1),
The arrangement pitch of the first connection parts and the arrangement pitch of the second connection parts are twice the arrangement pitch of the electrode pads.
(4) In the means (1),
The first and second connection portions and the electrode pad are formed with a rectangular plane.
One side of the first connection portion faces one side of the corresponding electrode pad,
One side of the second connection portion faces one side of the corresponding electrode pad.
(5) In the means (1),
The second connection portion is disposed between two adjacent first connection portions.
(6) In the means (5),
The second connection portion is disposed in the middle of the arrangement pitch of the two first connection portions.
(7) In the means (1),
The wiring board has a multilayer wiring structure having a surface layer and an inner layer.
(8) In the means (1),
The wiring board is a build-up board having a multilayer wiring structure having a surface layer and an inner wiring layer.
(9) In the means (1),
The wiring board is a semi-additive board having a multilayer wiring structure having a surface layer and an inner wiring layer.
(10) In manufacturing a semiconductor device,
(A) preparing a semiconductor chip formed on the main surface and having the first electrode pad, the second electrode pad, and the third electrode pad repeatedly arranged in this order along one side of the main surface; ,
(B) a chip mounting portion on which the semiconductor chip is mounted, and a plurality of first electrodes arranged along one side of the semiconductor chip corresponding to the plurality of first electrode pads outside the chip mounting portion. A plurality of second electrodes arranged along one side of the semiconductor chip corresponding to the plurality of second electrode pads at a position away from one side of the semiconductor chip than the plurality of first connection parts; And a plurality of connecting portions arranged along one side of the semiconductor chip corresponding to the plurality of third electrode pads at positions farther from one side of the semiconductor chip than the plurality of second connecting portions. Preparing a wiring board having a third connection portion of
(C) mounting the semiconductor chip on the chip mounting portion of the wiring board in a state where the plurality of first connection portions are along one side of the semiconductor chip;
(D) electrically connecting the plurality of first electrode pads and the plurality of first connection portions with a plurality of first bonding wires, respectively.
(E) The plurality of second electrode pads and the plurality of second connection portions are electrically connected to each other by a plurality of second bonding wires having a loop height higher than that of the plurality of first bonding wires. And a process of
(F) electrically connecting the plurality of third electrode pads and the plurality of third connection portions with a plurality of third bonding wires each having a loop height higher than that of the second bonding wires. When,
(G) sealing the semiconductor chip and the plurality of first to third bonding wires with a resin;
The plurality of first to third bonding wires extend at an angle that forms an acute angle with respect to a virtual line orthogonal to one side of the semiconductor chip across the center of one side of the semiconductor chip,
The connection between the third bonding wire and the third electrode pad is performed at a position farther from one side of the semiconductor chip than the connection between the first bonding wire and the first electrode pad.
The step (e), the step (d), and the step (f) are performed in this order.
(11) In the means (10),
The connection between the second bonding wire and the second electrode pad is performed at a position closer to one side of the semiconductor chip than the connection between the third bonding wire and the third electrode pad.
(12) In the means (10),
The connection between the second bonding wire and the second electrode pad is performed at a position farther from one side of the semiconductor chip than the connection between the first bonding wire and the first electrode pad.
(13) In the means (10),
The plurality of first to third electrode pads have a rectangular planar shape in which two long sides located on opposite sides extend along a direction away from one side of the semiconductor chip.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, it is possible to reduce the size of a semiconductor device.
According to the present invention, it is possible to improve the manufacturing yield of semiconductor devices.

1 is a schematic plan view showing an internal structure of a semiconductor device that is Embodiment 1 of the present invention. FIG. 2 is a schematic plan view showing a state in which a part of the bonding wire in FIG. 1 is omitted. FIG. 2 is a schematic cross-sectional view taken along the line a′-a ′ in FIG. 1. It is typical sectional drawing which follows the b'-b 'line | wire of FIG. FIG. 2 is a schematic plan view showing a part (part A) of FIG. 1 in a simplified manner. FIG. 6 is a schematic plan view in which the bonding wires in FIG. 5 are omitted. It is typical sectional drawing which follows the c'-c 'line | wire of FIG. FIG. 6 is a schematic cross-sectional view taken along line d′-d ′ in FIG. 5. FIG. 2 is a schematic plan view showing a part (part B) of FIG. 1 in a simplified manner. FIG. 10 is a schematic plan view in which the bonding wire of FIG. 9 is omitted. FIG. 10 is a schematic cross-sectional view taken along the line e′-e ′ in FIG. 9. FIG. 10 is a schematic cross-sectional view taken along line f′-f ′ in FIG. 9. FIG. 10 is a schematic cross-sectional view taken along the line g′-g ′ of FIG. 9. It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. It is a typical top view which shows schematic structure of the semiconductor device which is Example 2 of this invention. FIG. 18 is a schematic plan view in which the bonding wire of FIG. 17 is omitted. It is a typical top view which shows schematic structure of the semiconductor device which is Example 3 of this invention. FIG. 20 is a schematic plan view in which the bonding wire of FIG. 19 is omitted. It is a typical top view which shows schematic structure of the semiconductor device which is Example 4 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

[Example 1]
In the first embodiment, as a BGA type semiconductor device, the present invention is an SIP (System In Package) type semiconductor device in which a plurality of semiconductor chips each having an integrated circuit having different functions are mounted on a wiring board to construct one system. An example to which is applied will be described.

1 to 16 are diagrams related to a semiconductor device which is Embodiment 1 of the present invention.
FIG. 1 is a schematic plan view showing an internal structure of a semiconductor device.
FIG. 2 is a schematic plan view showing a part of the bonding wire in FIG.
3 is a schematic cross-sectional view taken along the line a′-a ′ of FIG.
4 is a schematic cross-sectional view taken along line b′-b ′ of FIG.
FIG. 5 is a schematic plan view showing a part (part A) of FIG.
FIG. 6 is a schematic plan view showing the bonding wire in FIG.
7 is a schematic cross-sectional view taken along the line c′-c ′ in FIG.
8 is a schematic cross-sectional view taken along the line d′-d ′ of FIG.
FIG. 9 is a schematic plan view showing a part (part B) of FIG. 1 in a simplified manner.
FIG. 10 is a schematic plan view showing the bonding wire of FIG.
FIG. 11 is a schematic cross-sectional view along the line e′-e ′ in FIG.
12 is a schematic cross-sectional view taken along line f′-f ′ in FIG.
13 is a schematic cross-sectional view taken along the line g′-g ′ of FIG.
14 to 16 are schematic plan views showing a wire bonding process in manufacturing a semiconductor device.

  As shown in FIGS. 1 to 4, in the semiconductor device 1 of the first embodiment, one semiconductor chip 5 and two semiconductor chips (7, 8) are mounted on the main surface side of a wiring board 2, also called an interposer. Thus, a package structure is formed in which a plurality of, for example, ball-shaped solder bumps 12 are arranged as external connection terminals on the back surface side opposite to the main surface of the wiring board 2.

  The semiconductor chip 5 and the semiconductor chips (7, 8) have a square shape that intersects the thickness direction. In the first embodiment, the semiconductor chip 5 has a rectangular shape of, for example, 5.0 mm × 6.7 mm, and the semiconductor chip (7, 8) has a rectangular shape of, for example, 1.539 mm × 6.137 mm. The semiconductor chip 5 and the semiconductor chips (7, 8) are not limited to this, but for example, mainly a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, and a main substrate of the semiconductor substrate. A multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the surface, and a surface protective film (final protective film) formed so as to cover the multilayer wiring layer are configured. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film such as aluminum (Al), aluminum alloy, copper (Cu), or copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  The semiconductor chip 5 has a main surface (element forming surface, circuit forming surface) and a back surface located on opposite sides of each other. On the main surface side of the semiconductor chip 5, for example, a data processor (MPU: Micro Processing Unit) is provided. Is formed.

  The main surface of the semiconductor chip 5 includes a first pad group composed of a plurality of electrode pads (bonding pads) 6a, a second pad group composed of a plurality of electrode pads (bonding pads) 6b, and a plurality of electrode pads (bonding pads). ) A third pad group composed of 6c and a fourth pad group composed of a plurality of electrode pads (bonding pads) 6d. The plurality of electrode pads 6 a of the first pad group are arranged along the first side 5 a of the semiconductor chip 5. The plurality of electrode pads 6b of the second pad group are arranged along the second side 5b located on the opposite side to the first side 5a of the semiconductor chip 5. The plurality of electrode pads 6 c in the third pad group are arranged along the third side 5 c that intersects the first side 5 a of the semiconductor chip 5. The plurality of electrode pads 6 d of the fourth pad group are arranged along the fourth side 5 d located on the opposite side to the third side 5 c of the semiconductor chip 5. The plurality of electrode pads (6a to 6d) of each pad group are formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 5, and are formed on the surface protective film of the semiconductor chip 5 corresponding to these electrode pads. It is exposed by the formed bonding opening.

  The semiconductor chips 7 and 8 have a main surface (element forming surface, circuit forming surface) and a back surface located on opposite sides, and each main surface side of the semiconductor chips 7 and 8 has, for example, a synchronous circuit as an integrated circuit. A Dyram (SDRAM: Synchronous Dynamic Random Access Memory) is formed. A plurality of electrode pads (bonding pads) 9 arranged along the first sides (7a, 8a) are formed on the main surfaces of the semiconductor chips 7 and 8, respectively.

  The semiconductor chip 5 is bonded and fixed to the main surface of the wiring substrate 2 with an adhesive interposed so that the back surface thereof faces the main surface of the wiring substrate 2. The semiconductor chip 7 is bonded and fixed to the main surface of the wiring substrate 2 with an adhesive interposed in a state where the back surface faces the main surface of the wiring substrate 2, and the back surface of the semiconductor chip 8 is in contact with the main surface of the semiconductor chip 7. In a state of facing each other, the main surface of the semiconductor chip 7 is bonded and fixed with an adhesive interposed.

  The semiconductor chips 7 and 8 are stacked in multiple stages with the positions shifted so that the electrode pads 9 of the semiconductor chip 7 are planarly positioned outside the first side 8 a of the semiconductor chip 8. Further, in the semiconductor chips 7 and 8, the direction in which each first side (7a, 8a) extends is in the same direction as the direction in which the first side 5a of the semiconductor chip 5 extends, and each first side ( 7a, 8a) and the second side (7b, 8b) on the opposite side to the first side 5a side of the semiconductor chip 5 are arranged apart from the semiconductor chip 5.

  The wiring board 2 has a rectangular planar shape that intersects the thickness direction, and in the first embodiment, the wiring board 2 has a rectangular shape of, for example, 9 mm × 11 mm. Here, in the plane of the wiring board 2, of the two short sides located on the opposite sides, one is called the first side 2 a and the other is the second side 2 b, and the two long sides located on the opposite sides One of the sides is called a third side 2c, and the other is called a fourth side 2d.

  The semiconductor chip 5 has the main side of the wiring substrate 2 in a state where the extending direction of the long side (first and second sides 5a, 5b) faces the same direction as the extending direction of the short side (2a, 2b) of the wiring substrate 2. Arranged on the surface.

  On the main surface of the wiring board 2, a pad group consisting of a plurality of electrode pads (connection portions) 3a1, a pad group consisting of a plurality of electrode pads (connection portions) 3a2, and a pad group consisting of a plurality of electrode pads (connection portions) 3b1. , A pad group consisting of a plurality of electrode pads (connection parts) 3b2, a pad group consisting of a plurality of electrode pads (connection parts) 3b3, a pad group consisting of a plurality of electrode pads (connection parts) 3c, and a plurality of electrode pads (connection parts) ) A pad group composed of 3d and a pad group composed of a plurality of electrode pads (connection portions) 3e are formed.

  The plurality of electrode pads 3a1 are arranged along the first side 5a of the semiconductor chip 5 outside the first side 5a of the semiconductor chip 5 between the semiconductor chip 5 and the semiconductor chip (7, 8). Yes. The plurality of electrode pads 3a2 are located between the semiconductor chip 5 and the semiconductor chip (7, 8) at a position farther from the first side 5a of the semiconductor chip 5 than the plurality of electrode pads 3a1. It is arranged along the side 5a. That is, a plurality of electrode pads (3a1, 3a2) are arranged in two rows along the first side 5a of the semiconductor chip 5 between the semiconductor chip 5 and the semiconductor chip (7, 8).

  The plurality of electrode pads 3b1 are arranged between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring substrate 2 outside the second side 5b of the semiconductor chip 5. Arranged along the side 5b. The plurality of electrode pads 3b2 are located farther from the second side 5b of the semiconductor chip 5 than the plurality of electrode pads 3b1 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. The semiconductor chip 5 is disposed at a position along the second side 5b. The plurality of electrode pads 3b3 are located farther from the second side 5b of the semiconductor chip 5 than the plurality of electrode pads 3b2 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. The semiconductor chip 5 is disposed at a position along the second side 5b. That is, a plurality of electrode pads (3b1, 3b2, 3b3) are arranged along the second side 5b of the semiconductor chip 5 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. Are arranged in three rows.

  The plurality of electrode pads 3 c are arranged between the third side 5 c of the semiconductor chip 5 and the third side 2 c of the wiring substrate 2, outside the third side 5 c of the semiconductor chip 5. It arrange | positions along the edge | side 5c. That is, a plurality of electrode pads 3 c are arranged in a row along the third side 5 c of the semiconductor chip 5 between the third side 5 c of the semiconductor chip 5 and the third side 2 c of the wiring board 2. ing.

  The plurality of electrode pads 3 d are arranged between the fourth side 5 d of the semiconductor chip 5 and the fourth side 2 d of the wiring substrate 2, outside the fourth side 5 d of the semiconductor chip 5. Arranged along the side 5d. That is, a plurality of electrode pads 3 d are arranged in a row along the fourth side 5 d of the semiconductor chip 5 between the fourth side 5 d of the semiconductor chip 5 and the fourth side 2 d of the wiring substrate 2. ing.

  The plurality of electrode pads 3e are arranged between the first side (7a, 8a) of the semiconductor chip (7, 8) and the first side 2a of the wiring substrate 2 so that the first side of the semiconductor chip (7, 8). The semiconductor chip (7, 8) is disposed outside the side (7a, 8a) along the first side (7a, 8a). That is, the first side (7a, 8a) of the semiconductor chip (7, 8) is between the first side (7a, 8a) of the semiconductor chip (7, 8) and the first side 2a of the wiring board 2. A plurality of electrode pads 3e are arranged in a line along 8a).

  The plurality of electrode pads 6a of the semiconductor chip 5 are electrically connected to the plurality of electrode pads (3a1, 3a2) of the wiring board 2 by a plurality of bonding wires (10a1, 10a2), respectively. The plurality of electrode pads 6b of the semiconductor chip 5 are electrically connected to the plurality of electrode pads (3b1, 3b2, 3b3) of the wiring board 2 by a plurality of bonding wires (10b1, 10b2, 10b3), respectively. The plurality of electrode pads 6c of the semiconductor chip 5 are electrically connected to the plurality of electrode pads 3c of the wiring board 2 by a plurality of bonding wires 10c, respectively. The plurality of electrode pads 6d of the semiconductor chip 5 are electrically connected to the plurality of electrode pads 3d of the wiring board 2 by a plurality of bonding wires 10d, respectively. The plurality of electrode pads 9 of the semiconductor chip (7, 8) are electrically connected to the plurality of electrode pads 3e of the wiring board 2 by a plurality of bonding wires 10e, respectively.

  For example, a gold (Au) wire is used as the bonding wire. As a bonding wire connecting method, for example, a nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with thermocompression bonding is used. The bonding wires are connected by a positive bonding method in which the electrode pads of the semiconductor chip 5 are primary connected and the electrode pads of the wiring board 2 are secondary connected.

  The semiconductor chip 5, the semiconductor chip (7, 8), and a plurality of bonding wires are sealed with a resin sealing body 11 formed on the main surface of the wiring board 2. For the purpose of reducing the stress, the resin sealing body 11 is formed of, for example, an epoxy thermosetting insulating resin to which a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added. .

  The resin sealing body 11 has a square shape that intersects with the thickness direction, and has the same planar size as the wiring board 2 in the first embodiment, for example. As a method for forming the resin sealing body 11, for example, a transfer molding method suitable for mass production is used.

  Here, in the manufacture of the BGA type semiconductor device, a multi-wiring board (multiple-wiring wiring board) having a plurality of product forming areas (device forming areas, product acquiring areas) partitioned by scribe lines is used for each product. Semiconductors mounted in each product formation area using an individual transfer molding method in which the semiconductor chip mounted in the formation area is resin-sealed for each product formation area or a multi-wiring board having multiple product formation areas A batch type transfer molding method in which chips are sealed together with a single resin sealing body is employed. In the first embodiment, for example, a batch type transfer molding method is employed.

  In the case of the collective transfer molding method, after forming the resin sealing body, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces by, for example, dicing. Therefore, the resin sealing body 11 and the wiring board 2 of Example 1 have almost the same outer size.

  As shown in FIG. 7, a plurality of electrode pads 29 a are arranged on the back surface opposite to the main surface of the wiring board 2. Solder bumps 12 are fixed (electrically and mechanically connected) to the plurality of electrode pads 29a.

  As shown in FIG. 7, the wiring board 2 has a multilayer wiring structure having a surface layer and an inner wiring layer. In the first embodiment, the wiring board 2 has a four-layer wiring structure, for example. Although not limited to this, the wiring board 2 is provided on the main surface of the core material 20 so as to cover the core material 20, the wiring layer 21 provided on the main surface of the core material 20, and the wiring layer 21. Insulating layer 23, wiring layer 24 provided on insulating layer 23, insulating layer 25 provided on insulating layer 23 so as to cover wiring layer 24, and back surface opposite to the main surface of core material 20 A wiring layer 26 provided on the back surface of the core material 20 so as to cover the wiring layer 26, a wiring layer 29 provided on the insulating layer 28, and a wiring layer 29. In this manner, the insulating layer 30 is provided on the insulating layer 28. The core material 20 is made of a highly elastic resin substrate in which, for example, glass fiber is impregnated with epoxy resin or polyimide resin. The surface insulating layers 25 and 30 are provided for the purpose of protecting the wiring formed in the surface wiring layer, and are formed of, for example, an insulating resin film (solder resist film).

  The wiring board 2 is formed by a build-up method in which an insulating layer and a wiring layer are formed on the core material 20 one by one, and the layers are stacked by stacking the wiring layers. Moreover, the wiring board forms the wiring layer by the semi-additive construction method.

  A plurality of electrode pads (3a1, 3a2, 3b1-3b3, 3c, 3d, 3e) arranged on the main surface of the wiring board 2 are formed on the first wiring layer 24 counted from above the multilayer wiring layer. The plurality of electrode pads 29a arranged on the back surface of the wiring board 2 are formed in the fourth wiring layer 29 counted from the top of the multilayer wiring layer.

  As shown in FIGS. 5 and 6, the plurality of electrode pads 6 a of the semiconductor chip 5 are formed in a rectangular planar shape, and two long sides facing each other are along a direction away from the first side 5 a of the semiconductor chip 5. In other words, the two short sides are arranged so as to face the first side 5 a of the semiconductor chip 5. In other words, the plurality of electrode pads 3a1 and 3a2 of the wiring substrate 2 are formed in a rectangular plane, and two long sides facing each other extend along a direction away from the first side 5a of the semiconductor chip. Two short sides are arranged so as to face the first side 5a of the semiconductor chip.

  Here, in the electrode pad 6a of the semiconductor chip 5, the electrode pad 6a that is electrically connected to the electrode pad 3a1 in the first row of the wiring board 2 via the bonding wire 10a1 is distinguished by the reference symbol a, and the bonding wire 10a2 The electrode pads 6b that are electrically connected to the electrode pads 3a2 in the second row of the wiring board 2 through the wiring board 2 are distinguished by the reference symbol b. Further, in the electrode pads of the wiring substrate 2, refer to the electrode pads 3a1 in the first row corresponding to the electrode pads 6a (a) of the semiconductor chip 5 and the electrode pads 3a2 corresponding to the electrode pads 6a (b) of the semiconductor chip 5, respectively. A distinction is made between symbols a and b.

  The plurality of electrode pads 3 a 1 and 3 a 2 are arranged in a staggered arrangement alternately one by one along the first side 5 a of the semiconductor chip 5. A design value of the arrangement pitch n1 of the electrode pads 3a1 and the arrangement pitch n2 of the electrode pads 3a2 is twice the arrangement pitch m1 of the electrode pads 6a. One side (short side) of the electrode pad 3a1 faces one side (short side) of the corresponding electrode pad 6a, and one side (short side) of the electrode pad 3a2 is one side (short side) of the corresponding electrode pad 6a. Facing each other. The electrode pad 3a2 is disposed between two adjacent electrode pads 3a1, and is further disposed in the middle of the arrangement pitch n2 of the electrode pads 3a1. That is, the plurality of electrode pads 3a1 and 3a2 are arranged in an arrangement in which the arrangement pitch n12 between the electrode pads 3a1 and the electrode pads 3a2 is the same (design value) as the arrangement pitch m1 of the electrode pads 6a of the semiconductor chip 5. Has been. In the first embodiment, the arrangement pitch m1 of the electrode pads 6a is about 55 [μm], for example, and the arrangement pitch n1 of the electrode pads 3a1 and the arrangement pitch n2 of the electrode pads 3a2 are about 110 [μm], for example. The arrangement pitch n12 of 3a1 and electrode pad 3a2 is, for example, about 55 [μm].

  It should be noted that the arrangement pitch of the electrode pads is a design value to the last, and it goes without saying that actual dimensions are slightly shifted due to variations in processing accuracy.

  A plurality of bonding wires 10a1 electrically connecting the plurality of electrode pads 6a and the plurality of electrode pads 3a1 respectively, and a plurality of bonding wires 10a2 electrically connecting the plurality of electrode pads 6a and the plurality of electrode pads 3a2 respectively. Further, it extends substantially in parallel, and also extends substantially parallel to a virtual line that intersects the middle of the first side 5a of the semiconductor chip 5 and is orthogonal to the first side 5a. As shown in FIGS. 7 and 8, the loop height (height from the bonding surface to the longest part of the wire) ah2 of the bonding wire 10a2 is higher than the loop height ah1 of the bonding wire 10a1.

  As shown in FIGS. 6 to 8, a plurality of wirings 4a formed in the same wiring layer as the electrode pad 3a1 are connected to the plurality of electrode pads 3a1. Also, in the plurality of electrode pads 3a2, wirings 4b formed in the same wiring layer as the electrode pads 3a2 are connected to each other. One end of each of the plurality of wirings 4a is integrally connected to the plurality of electrode pads 3a1, and each end of each of the plurality of wirings 4b is integrally connected to each of the plurality of electrode pads 3a2. . That is, the electrode pad 3a1 is formed by a part of the wiring 4a, and the electrode pad 3a2 is formed by a part of the wiring 4b.

  The plurality of wirings 4 a extend (extend) from each of the plurality of electrode pads 3 a 1 toward the first side 5 a of the semiconductor chip 5. On the other hand, the plurality of wirings 4b extend (extend) from each of the plurality of electrode pads toward the side opposite to the first side 5a of the semiconductor chip 5.

  As shown in FIGS. 9 and 10, the plurality of electrode pads 6 b of the semiconductor chip 5 are formed in a rectangular planar shape, and the two long sides facing each other are along the direction away from the second side 5 b of the semiconductor chip 5. In other words, the two short sides are arranged so as to face the second side 5 b of the semiconductor chip 5. The plurality of electrode pads 3b1 to 3b3 of the wiring board 2 are formed so that the plane is rectangular, and the two long sides facing each other extend slightly deviated from the direction away from the first side 5a of the semiconductor chip. In other words, the two short sides are arranged so as to be slightly inclined with respect to the second side 5 b of the semiconductor chip 5.

  The plurality of electrode pads 3b3 in the third row, the plurality of electrode pads 3b2 in the second row, and the plurality of electrode pads 3b1 in the first row cross the center of the second side 5b of the semiconductor chip 5 and the second side The electrode pads 3b2 in the second row and the electrode pads 3b2 in the second row rather than the electrode pads 3b3 in the third row in the electrode pads positioned in the same number of steps (order) counted from the virtual line (center line) 5s orthogonal to 5b The electrode pad 3b1 in the first row is arranged in a state of being separated from the virtual line 5s.

  Here, in the plurality of electrode pads 6b of the semiconductor chip 5, the electrode pads 6b that are electrically connected to the electrode pads 3b1 in the first row of the wiring board 2 via the bonding wires 10b1 are distinguished by the reference symbol a and bonded. The electrode pad 6b electrically connected to the electrode pad 3b2 in the second row of the wiring board 2 through the wire 10b2 is distinguished by the reference symbol b, and the electrode pad in the third row of the wiring board 2 through the bonding wire 10b3. The electrode pad 6b electrically connected to 3b3 is distinguished by reference symbol c.

  In addition, in the electrode pads of the wiring substrate 2, the electrode pads 3b1 in the first column corresponding to the electrode pads 6b (a) of the semiconductor chip 5, the electrode pads 3b2 corresponding to the electrode pads 6b (b) of the semiconductor chip 5, and the semiconductor chip The electrode pads 5b3 corresponding to the five electrode pads 6b (c) are distinguished by reference symbols a, b and c, respectively.

  The plurality of electrode pads 6b include the electrode pad c, the electrode pad b, and the electrode pad a from the center of the second side 5b of the semiconductor chip 5 toward the end portion along the second side 5b of the semiconductor chip 5. It is arranged repeatedly in order. That is, the bonding wire 10b3 that connects the electrode pad 6b (c) of the semiconductor chip 5 and the electrode pad 3b3 of the third row of the wiring substrate 2, and the second row of the electrode pad 6b (b) of the semiconductor chip 5 and the wiring substrate 2 The bonding wire 10b2 that connects the electrode pad 3b2 of the semiconductor chip 5 and the bonding wire 10b1 that connects the electrode pad 6b (a) of the semiconductor chip 5 and the electrode pad 3b1 of the first row of the wiring substrate 2 are in this order. The second side 5b is repeatedly arranged from the center toward the end thereof.

  The plurality of bonding wires 10b1 to 10b3 extend radially from the semiconductor chip 5 side starting from the center of the second side 5b of the semiconductor chip 5 at an acute angle with respect to the virtual line 5s.

  As shown in FIGS. 9 and 11 to 13, the connection between the bonding wire 10 b 3 and the electrode pad 6 b (c) of the semiconductor chip 5 is based on the connection between the bonding wire 10 b 1 and the electrode pad 6 b (a) of the semiconductor chip 5. Is also performed at a position away from the second side 5 b of the semiconductor chip 5. The connection between the bonding wire 10b2 and the electrode pad 6b (b) of the semiconductor chip 5 is farther from the second side 5b of the semiconductor chip 5 than the connection between the bonding wire 10b1 and the electrode pad 6b (a) of the semiconductor chip 5. Is done in position. As shown in FIGS. 11 to 13, the loop height bh2 (see FIG. 12) of the bonding wire 10b2 is higher than the loop height bh1 (see FIG. 11) of the bonding wire 10b1. The loop height bh3 (see FIG. 13) of the bonding wire 10b3 is higher than the loop height bh2 (see FIG. 12) of the bonding wire 10b2.

  Next, the manufacture of the semiconductor device 1 will be described.

  First, the semiconductor chip 5 and the two semiconductor chips (7, 8) are prepared, and a multi-wiring board is prepared.

  Next, the semiconductor chip 5 and the semiconductor chips 7 and 8 are mounted on the chip mounting portion in each product formation region of the multi-wiring substrate. The mounting of the semiconductor chip is performed in a state where the pad row in each product formation region is along the side of the semiconductor chip.

  Next, in each product formation region, the plurality of electrode pads of the semiconductor chip and the plurality of electrode pads arranged around the semiconductor chip are electrically connected by a plurality of bonding wires, respectively. By this process, the semiconductor chips 5 and the semiconductor chips 7 and 8 are mounted in each product formation region of the multi-wiring board.

  Here, the mounting means a state in which the semiconductor chip is bonded and fixed to the substrate, and the connection pad of the substrate and the connection pad of the semiconductor chip are electrically connected. In the first embodiment, the semiconductor chip 2 is bonded and fixed by an adhesive, and the electrical connection between the electrode pad of the multi-wiring substrate and the electrode pad of the semiconductor chip is performed by a bonding wire.

  Next, using a batch transfer molding method, a resin sealing body is formed which collectively seals the semiconductor chips mounted on each product formation region 37 of the multi-wiring board.

  Next, a plurality of solder bumps 12 are formed on the back surface opposite to the main surface of the multi-wiring board, corresponding to each product formation region. The solder bump 12 is not limited to this, but, for example, a flux material is applied on the electrode pad on the back surface of the multi-wiring board, and then a solder ball is supplied onto the electrode pad 32, and then the solder ball is melted. It is formed by bonding with an electrode pad.

  Next, the flux used in the solder bump forming process is removed by cleaning, and then, for example, a product name, a company name, a product type, and a production lot are formed on the upper surface of the resin sealing body corresponding to each product formation region 37 of the multi-wiring board. Identification marks such as numbers are formed using an inkjet marking method, a direct printing method, a laser marking method, or the like.

  Next, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces corresponding to each product formation region. This division is performed, for example, by dicing the multi-wiring board and the resin sealing body with a dicing blade along the scribe line of the multi-wiring board in a state where the resin sealing body is attached to the dicing sheet. Through this step, the semiconductor device 1 shown in FIG. 1 is almost completed.

  Next, a plurality of electrode pads 6b arranged on the main surface of the semiconductor chip 5 along the first side 5b of the main surface, and 3 on the main surface of the wiring board 2 corresponding to the plurality of electrode pads 6b. Wire bonding for electrically connecting a plurality of electrode pads (3b1, 3b2, 3b3) arranged in a row with a plurality of bonding wires (10b1, 10b2, 10b3) will be described.

  First, as shown in FIG. 14, among the plurality of electrode pads 3b1 (a) in the first row arranged on the wiring board 2 and the plurality of electrode pads 6b in the semiconductor chip 5, the first row in the wiring board 2 is provided. The plurality of electrode pads 3b1 and the corresponding plurality of electrode pads 6b (a) are electrically connected by a plurality of bonding wires 10b1, respectively. In this step, the connection between the bonding wire 10b1 and the electrode pad 6b (a) is biased to the short side of the two short sides of the electrode pad a closer to the second side 5b of the semiconductor chip 5 ( At the connection point k1). The bonding wire 10b1 extends at an angle that forms an acute angle with the virtual line 5s.

  Next, as shown in FIG. 15, among the plurality of electrode pads 3 b 2 (b) arranged in the second row and the plurality of electrode pads 6 b of the semiconductor chip 5, the second row of the wiring substrate 2 is arranged. The plurality of electrode pads 3b2 and the corresponding plurality of electrode pads 6b (b) are electrically connected by a plurality of bonding wires 10b2. The connection between the bonding wire 10b2 and the electrode pad 6b (b) is biased to the short side of the two short sides of the electrode pad 6b (b) that is farther from the second side 5b of the semiconductor chip 5 ( This is done at connection point k2). In other words, the bonding wire 10b2 is connected at a position that is biased toward the short side different from the short side of the electrode pad 6b (a) to which the bonding wire 10b1 is connected. The bonding wire 10b2 extends at an angle that forms an acute angle with the virtual line 5s. In this step, the connection position (connection point k2) of the bonding wire 10b2 in the electrode pad 6b (b) and the connection position (connection point k1) of the bonding wire 10b1 in the adjacent electrode pad 6b (a) are on different short sides. Connections are made at a biased position. In other words, since each connection point is connected to each bonding wire in a staggered relationship, when the capillary descends to the electrode pad 6b (b), the distance between the bonding wire 10b1 and the capillary is equal to that of the electrode pad 6b. It becomes larger than the arrangement pitch. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed.

  Next, among the plurality of electrode pads 3b3 (c) in the third row arranged on the wiring board 2 and the plurality of electrode pads 6b in the semiconductor chip 5, as shown in FIG. The plurality of electrode pads 3b3 and the corresponding plurality of electrode pads 6b (c) are electrically connected by a plurality of bonding wires 10b3, respectively. The connection between the bonding wire 10b3 and the electrode pad 6b (c) is a position (connection point k2) that is biased to the short side of the two short sides of the electrode pad c that is farther from the second side 5b of the semiconductor chip 5. ). In other words, it is performed at a position biased to the short side on the same side as the short side to which the bonding wire 10b2 is connected in the electrode pad 6b (b). The bonding wire 10b2 extends at an angle that forms an acute angle with the virtual line 5s.

  In this step, the bonding wire 10b2 connected to the electrode pad 6b (b) adjacent to the electrode pad 6b (c) forms an acute angle with the virtual line 5s, that is, outside the electrode pad 6b (c). Therefore, when the capillary descends to the electrode pad 6b (c), the distance between the bonding wire 10b2 and the capillary becomes larger than the arrangement pitch of the electrode pads 6b. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed. On the other hand, the bonding wire 10b1 connected to the electrode pad 6b (a) adjacent to the electrode pad 6b (c) has an acute angle with respect to the virtual line 5s, that is, faces inward with respect to the electrode pad 6b (c). However, the connection between the bonding wire 10b3 and the electrode pad 6b (c) is performed at a position farther from the second side 5b of the semiconductor chip 5 than the connection position between the bonding wire 10b1 and the electrode pad 3b1. When the capillary descends to the electrode pad 6b (c), the distance between the bonding wire 10b1 and the capillary becomes larger than the arrangement pitch of the electrode pads 6b. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed.

  Here, when the electrode pads of the wiring board 2 are in multiple rows as in the first embodiment, the bonding wires 10b1 connected to the first electrode pads 3b1 and the bondings connected to the second electrode pads 3b2 are used. The wire 10b2 and the bonding wire 10b3 connected to the third-row electrode pad 3b3 have different wire lengths. In wire bonding with different wire lengths as described above, depending on the wire droop (the state in which the wire loop hangs down in the middle) and the wire twist (the state in which the wire connecting the two points is curved instead of a straight line when viewed from above), It is necessary to change the loop height of the bonding wire in order to suppress a wire touch failure such that the bonding wire contacts the semiconductor chip or adjacent wires contact each other. In the first embodiment, the loop height bh2 (see FIG. 12) of the bonding wire 10b2 connected to the electrode pad 3b2 in the second row is the loop height of the bonding wire 10b1 connected to the electrode pad 3b1 in the first row. The loop height bh3 (see FIG. 13) of the bonding wire 10b3 connected to the third-row electrode pad 3b3 is higher than bh1 (see FIG. 11) and the bonding wire 10b2 connected to the second-row electrode pad 3b2 Is higher than the loop height bh2 (see FIG. 12).

  If the loop height of the bonding wire is not taken into consideration, interference between the bonding wire and the capillary can be suppressed by sequentially performing wire bonding from both ends of the second side 5b of the semiconductor chip 5 toward the center thereof. However, when the loop height of the bonding wire is taken into account, when wire bonding is performed from the end of the second side 5b of the semiconductor chip 5 toward the center thereof, after the connection with the bonding wire 10b3 having a high loop height, Since the connection is made with the bonding wire 10b1 having a low loop height, the capillary for performing subsequent wire bonding interferes with the bonding wire 10b3 having a high loop height.

  Accordingly, as in the first embodiment, after the wire connection of the electrode pad 3b1 in the first row, the wire connection of the electrode pad 3b2 in the second row, and the electrode pad 3b3 in the third row after the wire connection of the electrode pad 3b2 in the second row. It is effective to perform wire connection consisting of different wire lengths after completing all the wire connections consisting of the same wire length.

  In the first embodiment, as shown in FIGS. 5 to 8, a plurality of electrode pads (3 a 1, 3 a 2) arranged in two rows on the main surface of the wiring board 2 along the first side 5 a of the semiconductor chip 5. Among them, the plurality of wirings 4a connected to the plurality of electrode pads 3a1 arranged in the first column extend from each electrode pad 3a1 toward the first side 5a of the semiconductor chip 5, and are arranged in the second column. A plurality of wirings 4 b connected to the plurality of electrode pads 3 a 2 extend from the respective electrode pads 3 a 2 toward the side opposite to the first side 5 a of the semiconductor chip 5. With such a configuration, since the arrangement pitch of the electrode pads 3a2 can be reduced, the length of the second pad row can be shortened. Further, as the arrangement pitch of the electrode pads 3a2 in the second row is reduced, the arrangement pitch of the electrode pads 3b1 in the first row can be reduced, so that the length of the pad arrangement in the first row can be shortened. . Thereby, since the planar size of the wiring board 2 can be reduced, the semiconductor device 1 can be reduced in size.

  Further, since the electrode pad 3a1 in the first row and the electrode pad 3a2 in the second row can be brought close to the first side 5a of the semiconductor chip 5, the length of the bonding wire can be shortened. Thereby, when forming the resin sealing body based on the transfer molding method, it is possible to suppress the occurrence of a problem that adjacent bonding wires are short-circuited by the wire flow in which the shape of the bonding wire is deformed by the flow of the resin. Therefore, the manufacturing yield of the semiconductor device 1 can be improved.

  Further, since the arrangement pitch of the electrode pads on the wiring board 2 is wider than the arrangement pitch of the electrode pads on the semiconductor chip 5, the bonding wire crosses the center of one side of the semiconductor chip and forms a virtual line perpendicular to the one side. Although it extends radially from the semiconductor chip side at an acute angle with respect to the electrode pad of the semiconductor chip, the angle of the bonding wire with respect to the virtual line decreases as the length of the pad row of the wiring board increases. When a bonding wire is connected to one of the two adjacent electrode pads and then the bonding wire is connected to the other electrode pad, the capillary interferes with the bonding wire connected to the one electrode pad. The occurrence of defects can be suppressed. As a result, the manufacturing yield of the semiconductor device can be improved.

  In the first embodiment, as shown in FIGS. 5 and 6, a plurality of electrode pads (3 a 1, 3 a 2) arranged in two rows on the main surface of the wiring board 2 along the first side 5 a of the semiconductor chip 5. Among them, the plurality of electrode pads 3a1 in the first row are arranged to face the corresponding electrode pads 6a, and the plurality of electrode pads 3a2 in the second row are arranged to face the corresponding electrode pads 6a. ing. With such a configuration, the length of the first row of pads and the length of the second row of pads can be further shortened, so that the semiconductor device 1 can be downsized and the yield of the semiconductor device 1 can be improved. Can be further achieved.

  The wiring board 2 of Example 1 is formed by a semi-additive construction method. The semi-additive method has higher processing accuracy than the sub-traffic method and there is almost no difference between the upper and lower widths of the completed conductor pattern (wiring and electrode pads), so the wiring and electrode pads are formed with high density. I can. Therefore, since the length of the first row of pads and the length of the second row of pads can be further reduced, it is possible to further reduce the size of the semiconductor device 1 and improve the yield of the semiconductor device 1.

  A plating layer is formed on the electrode pad of the wiring board 2 in order to improve bondability with the bonding wire. For this plating layer, an electroplating method capable of plating at low cost is used. In this case, it is necessary to connect a power supply wiring to the electrode pad. The wiring board 2 of the first embodiment has a multilayer wiring structure having a surface layer and an inner layer. Accordingly, the power supply wiring can be routed using the inner wiring layer of the wiring board 2, and therefore, the power supply wiring is not supplied to the first electrode pad 3a1 without passing the power supply wiring between the second electrode pads 3a2. Wiring can be connected.

  The wiring board 2 of the first embodiment is formed by a buildup method. In the build-up method, an insulating layer and a wiring layer are formed one by one on the core material, and the layers are stacked by connecting the layers, so that the degree of freedom of wiring is high. Therefore, by using the wiring board formed by the build-up method, it is possible to arrange the electrode pads with a narrow pitch.

A plurality of electrode pads 6b arranged on the main surface of the semiconductor chip 5 along the first side 5b of the main surface, and arranged in three rows on the main surface of the wiring board 2 corresponding to the plurality of electrode pads 6b. In the wire bonding in which the plurality of electrode pads (3b1, 3b2, 3b3) are electrically connected to each other by a plurality of bonding wires (10b1, 10b2, 10b3), the plurality of electrode pads 3b2 in the second row are semiconductor chips. The electrode pads 3b2 positioned in the same order (order) as the electrode pads 3b3 in the third column are counted from a virtual line (center line) 5s orthogonal to the second side 5b across the center of the second side 5b. It arrange | positions in the state away from the virtual line 5s. The plurality of electrode pads 3b1 in the first row are arranged in a state in which the electrode pads 3b1 positioned in the same order (order) as the electrode pads 3b2 in the second row as counted from the virtual line 5s are separated from the virtual line 5s.
A step of electrically connecting a plurality of electrode pads 3b1 in the first row and a plurality of electrode pads 6b (a) corresponding thereto with a plurality of bonding wires 10b1, and a plurality of electrode pads 3b2 in the second row and A step of electrically connecting a plurality of corresponding electrode pads 6b (b) with a plurality of bonding wires 10b2, and a plurality of electrode pads 3b3 in the third row and a plurality of electrode pads 6b (c) corresponding thereto Are sequentially connected in this order by a plurality of bonding wires 10b3.
The connection between the bonding wire 10b3 and the third row electrode pad 3b3 and the connection between the bonding wire 10b2 and the second row electrode pad 3b2 are more semiconductor than the connection between the bonding wire 10b1 and the first row electrode pad 3b1. This is performed at a position away from the second side 5b of the chip 5.

  By performing the wire bonding in this way, when the capillary descends to the electrode pad, the distance between the adjacent bonding wire and the capillary becomes larger than the arrangement pitch of the electrode pad 6b. Interference can be suppressed. Thereby, the manufacturing yield of the semiconductor device 1 can be improved.

  In Example 1, the connection between the bonding wire 10b2 and the electrode pad 6b (b) is located farther from the second side 5b of the semiconductor chip 5 than the connection between the bonding wire 10b1 and the electrode pad 6b (a). However, the connection between the bonding wire 10b2 and the electrode pad 6b (b) is connected to the second side 5b of the semiconductor chip 5 in the same manner as the connection between the bonding wire 10b1 and the electrode pad 6b (a). The same effect can be obtained even if it is arranged at a position closer to the second side 5b of the semiconductor chip 5 than the bonding wire 10b3 and the electrode pad 6b (c).

  The bonding wires (10b1, 10b2, 10b3) may be connected continuously from one end side to the other end side of the second side 5b of the semiconductor chip 5, or the second side of the semiconductor chip 5 may be connected. It may be performed continuously from one end side and the other end side of 5b toward the center of the second side 5b, or from the center of the second side 5b of the semiconductor chip 5 to one end side of the second side 5b. And you may carry out continuously toward the other end side.

  However, after the first wire bonding step in which the electrode pads 6b (a) of the semiconductor chip 5 and the electrode pads 3b1 in the first row of the wiring substrate 2 are connected by the bonding wires 10b1, the electrode pads 6b (b) of the semiconductor chip 5 are connected. ) And the electrode pads 3b2 in the second row of the wiring board 2 are connected by bonding wires 10b2, and after the second wire bonding process, electrode pads 6b (c) of the semiconductor chip 5 are implemented. A third wire bonding step for connecting the electrode pads 3b3 in the third row of the wiring board 2 with the bonding wires 10b3 is performed.

  When the third wire bonding step is performed after the first wire bonding step, the capillary in the second wire bonding step easily interferes with the bonding wire 10b3 stretched in the third wire bonding step. It is important to perform the wire bonding process in the second and third order.

[Example 2]
FIG. 17 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 2 of the present invention, and FIG. 18 is a schematic plan view in which the bonding wires of FIG. 17 are omitted.

  The second embodiment is an example in which the present invention for reducing the pad arrangement pitch is applied to a three-row pad arrangement.

  17 and 18, the electrode pad 3a1 (a) faces the corresponding electrode pad 6a (a), and the electrode pad 3a2 (b) faces the corresponding electrode pad 6a (b). The pad 3a3 (c) faces the corresponding electrode pad 6a (c).

  The arrangement pitch n1 of the electrode pads 3a1 (a), the arrangement pitch n2 of the electrode pads 3a2 (b), and the arrangement pitch n3 of the electrode pads 3a3 (c) are designed values of the arrangement pitch m1 of the electrode pads 6a of the semiconductor chip 5. It has tripled.

  The arrangement pitch n12 between the electrode pad 3a1 (a) and the electrode pad 3a2 (b) and the arrangement pitch n23 between the electrode pad 3a2 (b) and the electrode pad 3a3 (c) are designed values of the arrangement pitch m1 of the electrode pad 6a. Is the same.

  Also in the second embodiment, the same effect as in the first embodiment can be obtained.

  Further, since the arrangement pitch of the electrode pads in each row is increased, the length of each pad row is not increased even if the wiring is passed between the electrode pads.

[Example 3]
FIG. 19 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 3 of the present invention, and FIG. 20 is a schematic plan view in which the bonding wires of FIG. 19 are omitted.

  The third embodiment is an example in which the present invention for reducing the pad arrangement pitch is applied to a four-row pad arrangement.

  As shown in FIGS. 19 and 20, the electrode pads 3a1 to 3a4 (a to d) face the corresponding electrode pads 6a (a to d), respectively. The arrangement pitch n1 of the electrode pads 3a1 (a), the arrangement pitch n2 of the electrode pads 3a2 (b), the arrangement pitch n3 of the electrode pads 3a3 (c), and the arrangement pitch n4 of the electrode pads 3a4 (d) are the arrangement of the electrode pads 6a. It is four times the pitch m1.

  The arrangement pitch n12 of the electrode pad 3a1 and the electrode pad 3a2, the arrangement pitch n23 of the electrode pad 3a2 and the electrode pad 3a3, and the arrangement pitch n34 of the electrode pad 3a3 and the electrode pad 3a4 are designed values of the arrangement pitch of the electrode pad 6a. It is the same as m1.

  Also in the third embodiment, the same effect as in the first embodiment can be obtained.

  Further, since the arrangement pitch of the electrode pads in each row is increased, the length of each pad row is not increased even if the wiring is passed between the electrode pads.

[Example 4]
FIG. 21 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 4 of the present invention.

  The fourth embodiment is an example in which the present invention for suppressing capillary interference is applied to a four-row pad arrangement. In the fourth embodiment, the same effect as in the first embodiment can be obtained.

  Further, the electrode pads may be arranged in four or more rows as long as the first connection position with the bonding wire and the last connection position with the bonding wire satisfy the staggered relationship.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

1 ... Semiconductor device,
2 ... wiring board, 3a1, 3a2, 3b1, 3b2, 3b3, 3c, 3d, 3e ... electrode pads (connection portions), 4a, 4b ... wiring,
5 ... Semiconductor chip, 5a, 5b, 5c, 5d ... 1st-4th edge, 6a, 6b, 6c, 6d ... Electrode pad (bonding pad),
7, 8 ... Semiconductor chip, 9 ... Electrode pad (bonding pad),
10 a 1, 10 a 2, 10 b 1, 10 b 2, 10 b 3, 10 c, 10 d, 10 e... Bonding wire, 11.

Claims (4)

A method for manufacturing a semiconductor device comprising the following steps:
(A) An upper surface having a first side, a chip mounting portion formed on the upper surface, and disposed along the first side, and disposed between the first side and the chip mounting portion in plan view. A plurality of first connection portions, and a plurality of second connection portions disposed along the first side and disposed between the first side and the plurality of first connection portions in a plan view. A plurality of third connection portions arranged along the first side and arranged between the first side and the plurality of second connection portions in plan view, and a lower surface opposite to the upper surface And a step of preparing a wiring board comprising:
(B) a surface having a second side, and a plurality of electrode pads formed on the surface in a row along the second side, and the back opposite to the surface, the semiconductor chip with the Mounting on the chip mounting portion such that the second side of the semiconductor chip is aligned with the first side of the wiring board ;
(C) electrically connecting a plurality of first electrode pads of the plurality of electrode pads and the plurality of first connection portions through a plurality of first wires, respectively;
(D) After the step (c), a step of electrically connecting a second electrode pad of the plurality of electrode pads and one of the plurality of second connection portions via a second wire. ;
(E) After the step (d), electrically connecting a third electrode pad of the plurality of electrode pads and one of the plurality of third connection portions via a third wire. ;
Here, the plurality of first electrode pads include an outer electrode pad positioned on the first end side of the second side of the semiconductor chip, and an inner electrode farther from the first end than the outer electrode pad. has a pad, the,
The second electrode pad is disposed between the outer electrode pad and the inner electrode pad in plan view,
The third electrode pad is disposed between the second electrode pad and the inner electrode pad in a plan view;
In the step (d), the second wire is electrically connected via the second wire so that a part of the second wire is positioned above each of the plurality of first wires,
In the step (e), the third wire is electrically connected via the third wire so that a part of the third wire is located above the second wire,
Each planar shape of the plurality of electrode pads is a rectangle having a first portion and a second portion located farther from the second side of the semiconductor chip than the first portion in plan view,
In the step (c), each of the plurality of first wires is connected to the first portion of each of the plurality of first electrode pads ,
In the step (e), the third wire is connected to the second portion of the third electrode pad ,
The plurality of first, second, and third wires form an acute angle with a virtual line that passes through the center of the second side of the semiconductor chip and is orthogonal to the second side in plan view. in, and in a direction away from the imaginary line, the plurality of first, extending respectively from the second and third electrode pads.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the steps (c) to (e) are performed using a capillary.   3. The method of manufacturing a semiconductor device according to claim 2, wherein after the step (e), the semiconductor chip, the plurality of first wires, the second wires, and the third wires are sealed with a resin. A method of manufacturing a semiconductor device.   4. The method of manufacturing a semiconductor device according to claim 3, wherein after sealing the semiconductor chip, the plurality of first wires, the second wire, and the third wire with the resin, a plurality of external connection terminals are connected to the semiconductor device. A method of manufacturing a semiconductor device, comprising forming the wiring substrate on the lower surface.

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