JP5292661B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device that requires a refresh operation, such as a DRAM (Dynamic Random Access Memory).

  FIG. 18 is a circuit diagram showing a part of an example of a conventional DRAM. In FIG. 18, 1 is a word line group, and 2 is a bit line group, and the memory cells electrically connected to the bit line by control via the word line are not shown.

  3 is a sense amplifier unit, 4 is a latch enable signal (LEX, LEZ) generation circuit for controlling the latch operation of the sense amplifier arranged in the sense amplifier unit 3, and 5 is a bit line pre-arranged in the sense amplifier unit 3. It is a bit line reset signal (BRSX) generation circuit for controlling the precharge operation of the charge circuit.

  FIG. 19 is a circuit diagram showing a configuration of the sense amplifier unit 3. In FIG. 19, BL0Z, BL0X, BL1Z, BL1X are bit lines, 6 is a sense amplifier, VDD is a power supply potential, 7 is a pMOS transistor for activating a sense amplifier whose on / off is controlled by a latch enable signal LEX, 8 and 9 are pMOS transistors forming pull-up elements, VSS is a ground potential, 10 is an nMOS transistor for activating a sense amplifier whose ON / OFF is controlled by a latch enable signal LEZ, and 11 and 12 are nMOS transistors forming a pull-down element It is.

  Reference numeral 13 denotes a bit line precharge circuit that precharges the bit lines BL0Z, BL0X, BL1Z, and BL1X. Reference numerals 14 to 16 denote nMOS transistors that are controlled to be turned on and off by a bit line reset signal BRSX.

  Reference numeral 17 denotes a bit line transfer gate for connecting the bit lines BL0Z and BL0X to the sense amplifier 6, and reference numerals 18 and 19 denote nMOS transistors whose on and off are controlled by a bit line transfer gate drive signal BLT0X.

  Reference numeral 20 denotes a bit line transfer gate for connecting the bit lines BL1Z and BL1X to the sense amplifier 6, and reference numerals 21 and 22 denote nMOS transistors whose on and off are controlled by a bit line transfer gate drive signal BLT1X.

  Reference numeral 23 denotes a column gate for connecting the sense amplifier 6 to the data buses GDBZ and GDBX. Reference numerals 24 and 25 denote nMOS transistors whose ON / OFF is controlled by a column selection signal CLSZ.

  FIG. 20 is a circuit diagram showing a configuration of the latch enable signal generation circuit 4. In FIG. 20, TWLX is a timing word signal for determining the time from the rise of the word line until the sense amplifier 6 is activated, and 26 to 28 are inverters.

  FIG. 21 is a circuit diagram showing a configuration of the bit line reset signal generation circuit 5. In FIG. 21, BRRZ is a bit line reset control signal for controlling the bit line reset signal BRSX, 29 and 30 are inverters, 31 to 34 are pMOS transistors, 35 and 36 are nMOS transistors, 37 is an inverter, and 38 is a pMOS transistor. , 39 are nMOS transistors, and VPP is a boosted potential obtained by boosting the power supply potential VDD.

  FIGS. 22 and 23 are waveform diagrams for explaining the read operation in the conventional DRAM shown in FIG. 18, and shows an example in which the memory cells on the bit lines BL0Z and BL0X are selected. The bit line transfer gate drive signals BLT0X and BLT1X are not shown.

  In the precharge period, the bit line reset control signal BRRZ = VSS and the timing word signal TWLX = VDD are set, and accordingly, the bit line reset signal BRSX = VPP, the latch enable signal LEX = VDD, and LEZ = VSS. Further, the bit line transfer gate drive signals BLT0X and BLT1X = VPP.

  As a result, in the bit line precharge circuit 13, the nMOS transistors 14 to 16 are turned on, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned off, and in the bit line transfer gates 17 and 20, the nMOS transistors 18, 19, 21 , 22 are turned ON, and the bit lines BL0Z, BL0X, BL1Z, BL1X are precharged to VCC / 2.

  In the active period, the bit line reset control signal BRRZ = VDD is set, and accordingly, the bit line reset signal BRSX = VSS is set. In the bit line precharge circuit 13, the nMOS transistors 14 to 16 are turned off. Further, the bit line transfer gate drive signal BLT1X = VSS is set, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned off. As a result, the bit lines BL1Z and BL1X are electrically disconnected from the sense amplifier unit 3, and the bit lines BL0Z and BL0X are disconnected from the precharge power supply (VCC / 2).

  Subsequently, the word line WL rises, data is read from the selected memory cell, and a slight difference potential is generated between the bit lines BL0Z and BL0X. In this state, the timing word signal TWLX = VSS, and accordingly, the latch enable signal LEX = VSS and LEZ = VDD. As a result, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned on, the sense amplifier 6 is activated, and the difference potential between the bit lines BL0Z and BL0X is amplified.

  When the transmission of the cell data to the data buses GDBZ and GDBX is completed, the timing word signal TWLX = VDD is set, and accordingly, the latch enable signals LEX = VDD and LEZ = VSS. In the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned off, and the sense amplifier 6 is deactivated.

  Thereafter, the bit line reset control signal BRRZ = VSS is set, and accordingly, the bit line reset signal BRSX = VPP is set. In the bit line precharge circuit 13, the nMOS transistors 14 to 16 are turned ON, and the bit lines BL0Z and BL0X are Precharged to VCC / 2. Further, the bit line transfer gate drive signal BLT1X = VPP is set, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned on.

Problems to be solved by the invention

  As described above, in the conventional DRAM shown in FIG. 18, the bit line is precharged to VCC / 2, the word line corresponding to the selected cell is raised, and a difference potential is generated between the bit lines. Cell data is read by amplifying the difference potential with a sense amplifier. However, since the DRAM cell is composed of a capacitor, the charge accumulated therein is lost with time. Therefore, the refresh operation is performed to compensate for the reduced charge.

  The charge flowing out of the cell is faster when “1” data (H level) is stored than when “0” data (L level) is stored in the cell. The holding time is a parameter that determines the time interval for performing the refresh operation. However, as miniaturization progresses, it becomes difficult in terms of process to make the retention time of “1” data equal to that of the previous generation, but as the memory capacity increases, the requirement for the retention time of “1” data also increases. Furthermore, the process becomes extremely difficult.

  Here, as a means for preventing the retention time of “1” data in the cell from being shortened, it is effective to set the precharge potential of the bit line to a potential lower than VCC / 2. Such DRAMs are disclosed in Japanese Patent Laid-Open Nos. 10-302469 and 11-26720. However, these DRAMs require a larger number of elements than DRAMs having a bit line precharge potential of VCC / 2. This causes an increase in the chip area and causes an increase in cost.

  Conventionally, in the DRAM test, the time taken for the refresh test has occupied a large proportion. This becomes even larger as the retention time and memory capacity of “1” data increase, but the increase in test time directly increases the cost.

  Therefore, the present invention is a semiconductor memory device that requires a refresh operation, and even when miniaturization or an increase in memory capacity is intended, the memory cell does not increase in cost due to an increase in chip area. Provided is a semiconductor memory device capable of preventing a 1 "data retention time from being shortened, and a semiconductor memory device capable of reducing cost by shortening a time required for a refresh test The purpose is to provide.

Means for solving the problem

  The present invention is a semiconductor memory device having a pair of first and second bit lines and a sense amplifier that amplifies a difference potential generated between the first and second bit lines when reading cell data. It has bit line potential control means for controlling the potentials of the first and second bit lines before reading the cell data using the transistors of the sense amplifier.

  According to the present invention, it is possible to control the potentials of the first and second bit lines before reading cell data using the transistor of the sense amplifier. Therefore, when the potential of the first and second bit lines is set to a potential lower than the middle between the highest potential and the lowest potential that can be taken by the first and second bit lines, miniaturization and increase in memory capacity are achieved. Even so, the retention time of “1” data can be prevented from being shortened without causing an increase in the number of elements, that is, without causing an increase in cost due to an increase in chip area.

  Further, when the bit line potential control means is configured to control the potentials of the first and second bit lines before reading the cell data in the test mode, the first and second bits before reading the cell data. The time required for the refresh test can be shortened by setting the potential of the line to a potential at which the cell data read margin becomes small.

  Hereinafter, with reference to FIGS. 1 to 17, the first to third embodiments of the present invention will be described taking the case where the present invention is applied to a DRAM as an example. 1, 2, 6, 7, 12, and 13, parts corresponding to those in FIGS. 18 and 19 are denoted by the same reference numerals, and redundant description thereof is omitted.

(First embodiment: FIGS. 1 to 5)
FIG. 1 is a circuit diagram showing a part of the first embodiment of the present invention. The first embodiment of the present invention is provided with a sense amplifier section 40 and a latch enable signal generation circuit 41 having a circuit configuration different from that of the sense amplifier section 3 and the latch enable signal generation circuit 4 provided in the conventional DRAM shown in FIG. Is configured similarly to the conventional DRAM shown in FIG.

  FIG. 2 is a circuit diagram showing a configuration of the sense amplifier unit 40. The sense amplifier section 40 deletes the nMOS transistors 15 and 16 from the bit line precharge circuit 13 shown in FIG. 19, leaves the bit line direct short circuit 42 formed of the nMOS transistor 14, and the other components are the sense amplifier shown in FIG. The configuration is the same as that of the unit 3.

  FIG. 3 is a circuit diagram showing a configuration of the latch enable signal generation circuit 41. As shown in FIG. In FIG. 3, ACTZ is an active signal which is a basic signal for starting up a word line, 43 is a NAND circuit, and 44 to 47 are inverters.

  4 and 5 are waveform charts for explaining the read operation in the first embodiment of the present invention, taking as an example the case where the memory cells on the bit lines BL0Z and BL0X are selected. The bit line transfer gate drive signals BLT0X and BLT1X are not shown.

  In the first embodiment of the present invention, the bit line reset control signal BRRZ = VSS, the active signal ACTZ = VSS, and the timing word signal TWLX = VDD are set in the precharge period, and accordingly, the bit line reset signal BRSX = VDD. VPP, latch enable signal LEX, LEZ = VDD. Further, the bit line transfer gate drive signals BLT0X and BLT1X = VPP.

  As a result, in the bit line direct short circuit 42, the nMOS transistor 14 is turned on, in the sense amplifier 6, the pMOS transistor 7 is turned off, the nMOS transistor 10 is turned on, and in the bit line transfer gates 17 and 20, the nMOS transistors 18, 19, 21 , 22 are turned ON, and the bits BL0Z, BL0X, BL1Z, BL1X are precharged to the threshold voltage Vth-n of the nMOS transistor 10.

  Thereafter, in the active period, the active signal ACTZ = VDD is set, and accordingly, the latch enable signal LEZ = VSS is set. In the sense amplifier 6, the nMOS transistor 10 is turned off and the sense amplifier 6 is inactivated. .

  Subsequently, the bit line reset control signal BRRZ = VDD is set, and accordingly, the bit line reset signal BRSX = VSS is set, and in the bit line direct short circuit 42, the nMOS transistor 14 is turned OFF. Further, the bit line transfer gate drive signal BLT1X = VSS, the nMOS transistors 21 and 22 are turned off in the bit line transfer gate 20, and the bit lines BL1Z and BL1X are electrically disconnected from the sense amplifier unit 40.

  Subsequently, the word line WL rises, data is read from the selected memory cell, and a slight difference potential is generated between the bit lines BL0Z and BL0X. In this state, the timing word signal TWLX = VSS, and accordingly, the latch enable signal LEX = VSS and LEZ = VDD. As a result, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned on, the sense amplifier 6 is activated, and the difference potential between the bit lines BL0Z and BL0X is amplified.

  When transmission of the cell data to the data buses GDBZ and GDBX is completed, the active signal ACTZ = VSS and the timing word signal TWLX = VDD are set, and accordingly, the latch enable signal LEX = VDD and the latch enable signal LEZ = In the sense amplifier 6, the pMOS transistor 7 is turned off and the nMOS transistor 10 is kept on in the sense amplifier 6.

  Thereafter, the bit line reset control signal BRRZ = VSS is set, and accordingly, the bit line reset signal BRSX = VPP is set, and the nMOS transistor 14 is turned ON in the bit line direct short circuit 42. As a result, the bit lines BL0Z and BL0X are precharged to the threshold voltage Vth-n of the nMOS transistor 10. Further, the bit line transfer gate drive signal BLT1X is set to VPP, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned on.

  As described above, according to the first embodiment of the present invention, the threshold voltage Vth of the nMOS transistor in which the precharge potential of the bit line is lower than VCC / 2 by using the nMOS transistor for activating the sense amplifier. Since it is -n, even when miniaturization or increase in memory capacity is attempted, the “1” data can be retained without increasing the number of elements, that is, without increasing the cost due to the increase in chip area. Time can be kept short.

  In the first embodiment of the present invention, the bit line potential control means includes the latch enable signal generation circuit 41, the bit line reset signal generation circuit 5, the bit line direct short circuit 42, and the nMOS transistors 10 to 12 of the sense amplifier 6. It is comprised including.

(Second Embodiment. FIG. 6 to FIG. 11)
FIG. 6 is a circuit diagram showing a part of the second embodiment of the present invention. The second embodiment of the present invention is different from the sense amplifier unit 3, latch enable signal generation circuit 4 and bit line reset signal generation circuit 5 provided in the conventional DRAM shown in FIG. A generation circuit 49 and a bit line reset signal generation circuit 50 are provided, and the others are configured in the same manner as the conventional DRAM shown in FIG.

  FIG. 7 is a circuit diagram showing a configuration of the sense amplifier unit 48. The sense amplifier unit 48 is provided with a bit line precharge circuit 51 having a circuit configuration different from that of the bit line precharge circuit 13 provided in the sense amplifier unit 3 shown in FIG. 19, and the rest is the same as the sense amplifier unit 3 shown in FIG. It is configured.

  The bit line precharge circuit 51 controls the ON / OFF of the bit line direct short nMOS transistor 14 by the bit line reset signal BRS0X, and the nMOS transistors 15 and 16 for supplying the precharge voltage to the bit line. Is configured to control ON and OFF by the bit line reset signal BRS1X.

  FIG. 8 is a circuit diagram showing a configuration of the latch enable signal generation circuit 49. In FIG. 8, WLTZ is a switching signal for controlling the generation of the latch enable signal LEZ by the timing word signal TWLX or the active signal ACTZ, 52 to 56 are inverters, and 57 and 58 are NAND circuits.

  FIG. 9 is a circuit diagram showing a configuration of the bit line reset signal generating circuit 50. As shown in FIG. In FIG. 9, BRR0Z is a bit line reset control signal for controlling the bit line reset signal BRS0X, BRR1Z is a bit line reset control signal for controlling the bit line reset signal BRS1X, 59 is a BRS0X generation circuit for generating the bit line reset signal BRS0X, Reference numeral 60 denotes a BRS1X generation circuit that generates a bit line reset signal BRS1X.

  In the BRS0X generation circuit 59, 61 and 62 are inverters, 63 to 66 are pMOS transistors, 67 and 68 are nMOS transistors, 69 is an inverter, 70 is a pMOS transistor, and 71 is an nMOS transistor.

  In the BRS1X generation circuit 60, 72 and 73 are inverters, 74 to 77 are pMOS transistors, 78 and 79 are nMOS transistors, 80 is an inverter, 81 is a pMOS transistor, and 82 is an nMOS transistor.

  FIGS. 10 and 11 are waveform diagrams for explaining the read operation in the second embodiment of the present invention, taking as an example the case where the memory cells on the bit lines BL0Z and BL0X are selected. The bit line transfer gate drive signals BLT0X and BLT1X are not shown.

  In the second embodiment of the present invention, the precharge period is set to bit line reset control signals BRR1Z, BRR0Z = VSS, active signal ACTZ = VSS, switching signal WLTZ = VSS, and timing word signal TWLX = VDD. Thus, the bit line reset signals BRS1X, BRS0X = VPP, the latch enable signal LEX = VDD, and LEZ = VSS. Further, the bit line transfer gate drive signals BLT0X and BLT1X = VPP.

  As a result, in the bit line precharge circuit 51, the nMOS transistors 14 to 16 are ON, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are OFF, and in the bit line transfer gates 17 and 20, the nMOS transistors 18, 19, 21 , 22 are turned ON, and the bits BL0Z, BL0X, BL1Z, BL1X are precharged to VCC / 2.

  Thereafter, in the active period, the bit line reset control signal BRR1Z = VDD is set, and accordingly, the bit line reset signal BRS1X = VSS is set, and in the bit line precharge circuit 51, the nMOS transistors 15 and 16 are turned off.

  Further, the active signal ACTZ = VDD is set, and accordingly, the bit line reset signal LEZ = VDD is set, and in the sense amplifier 6, the nMOS transistor 10 is turned ON. As a result, the potentials of the bit lines BL0Z and BL0X are lowered from VCC / 2 to the threshold voltage Vth-n of the nMOS transistor 10.

  Thereafter, the bit line reset control signal BRR0Z = VDD is set, and accordingly, the bit line reset signal BRS0X = VSS is set, and the nMOS transistor 14 is turned off in the bit line precharge circuit 51. Further, the switching signal WLTZ = VDD is set, and accordingly, the latch enable signal LEZ = VSS is set, and in the sense amplifier 6, the nMOS transistor 10 is turned OFF.

  Subsequently, the word line WL rises, data is read from the selected memory cell, and a slight difference potential is generated between the bit lines BL0Z and BL0X. In this state, the timing word signal TWLX = VSS, and accordingly, the latch enable signal LEX = VSS and LEZ = VDD. As a result, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned on, the sense amplifier 6 is activated, and the difference potential between the bit lines BL0Z and BL0X is amplified.

  When transmission of the cell data to the data buses GDBZ and GDBX is completed, the active signal ACTZ = VSS and the timing word signal TWLX = VDD are set, the latch enable signals LEX = VDD and LEZ = VSS. The transistor 7 and the nMOS transistor 10 are turned off, and the sense amplifier 6 is deactivated.

  Thereafter, the bit line reset control signals BRR1Z and BRR0Z = VSS are set, and the bit line reset signals BRS1X and BRS0X = VPP are set accordingly. In the bit line precharge circuit 51, the nMOS transistors 14 to 16 are turned ON. As a result, the bit lines BL0Z and BL0X are precharged to VCC / 2. Further, the bit line transfer gate drive signal BLT1X = VPP is set, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned on.

  As described above, according to the second embodiment of the present invention, the bit line is once precharged to VCC / 2, but before reading the cell data, the nMOS transistor for activating the sense amplifier is used. Thus, since the potential of the bit line is lowered to the threshold voltage Vth-n of the nMOS transistor which is lower than VCC / 2, the number of elements is increased even when miniaturization or increase in memory capacity is attempted. Without this, that is, without causing an increase in cost due to an increase in the chip area, the retention time of “1” data can be prevented from being shortened.

  In the second embodiment of the present invention, the bit line potential control means includes the latch enable signal generation circuit 49, the bit line reset signal generation circuit 50, the bit line precharge circuit 51, and the nMOS transistors 10 to 12 of the sense amplifier 6. It is comprised including.

(Third embodiment. FIG. 12 to FIG. 17)
FIG. 12 is a circuit diagram showing a part of the third embodiment of the present invention. The third embodiment of the present invention is different from the sense amplifier unit 3, latch enable signal generation circuit 4 and bit line reset signal generation circuit 5 provided in the conventional DRAM shown in FIG. The generation circuit 84 and the bit line reset signal generation circuit 85 are provided, and the others are configured in the same manner as the conventional DRAM shown in FIG.

  FIG. 13 is a circuit diagram showing a configuration of the sense amplifier unit 83. The sense amplifier unit 83 is configured in the same manner as the sense amplifier unit 48 shown in FIG.

  FIG. 14 is a circuit diagram showing a configuration of the latch enable signal generation circuit 84. In FIG. 14, TESZ is a test mode setting signal for setting a test mode, 86 to 90 are inverters, and 91 and 92 are NAND circuits. The test mode setting signal TESZ is set to VDD when the test mode is set.

  FIG. 15 is a circuit diagram showing a configuration of the bit line reset signal generation circuit 85. In FIG. 15, 93 is a BRS0X generating circuit for generating a bit line reset signal BRS0X, and 94 is a BRS1X generating circuit for generating a bit line reset signal BRS1X.

  In the BRS0X generation circuit 93, 95 and 96 are inverters, 97 to 100 are pMOS transistors, 101 and 102 are nMOS transistors, 103 is an inverter, 104 is a pMOS transistor, and 105 is an nMOS transistor.

  In the BRS1X generation circuit 94, 106 is a NOR circuit, 107 is an inverter, 108 to 111 are pMOS transistors, 112 and 113 are nMOS transistors, 114 is an inverter, 115 is a pMOS transistor, and 116 is an nMOS transistor.

  FIGS. 16 and 17 are waveform diagrams for explaining the operation in the test mode of the third embodiment of the present invention, taking as an example the case where the memory cells on the bit lines BL0Z and BL0X are selected. The bit line transfer gate drive signals BLT0X and BLT1X are not shown.

  In the third embodiment of the present invention, the precharge period is set to the test mode setting signal TESZ = VSS, the bit line reset control signal BRRZ = VSS, the active signal ACTZ = VSS, and the timing word signal TWLX = VDD. Thus, the bit line reset signals BRS1X, BRS0X = VPP, the latch enable signal LEX = VDD, and LEZ = VSS. Further, the bit line transfer gate drive signals BLT0X and BLT1X = VPP.

  As a result, in the bit line precharge circuit 51, the nMOS transistors 14 to 16 are ON, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are OFF, and in the bit line transfer gates 17 and 20, the nMOS transistors 18, 19, 21 , 22 are turned ON, and the bit lines BL0Z, BL0X, BL1Z, BL1X are precharged to VCC / 2.

  From this state, when the test mode setting signal TESZ = VDD is set and the test mode is set, the bit line reset signal BRS1X = VSS and the latch enable signal LEZ = VDD are set accordingly, and the bit line precharge circuit 51 NMOS transistors 15 and 16 are OFF, and in the sense amplifier 6, the nMOS transistor 10 is ON. Further, the bit line transfer gate drive signal BLT1X is set to VSS, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned OFF. As a result, the bit lines BL0Z and BL0X are pulled down to the threshold voltage Vth-n of the nMOS transistor 10.

  After that, the bit line reset control signal BRRZ = VSS is set, and accordingly, the bit line reset signal BRS0X = VDD is set, and the nMOS transistor 14 is turned OFF in the bit line precharge circuit 51. Further, the active signal ACTZ = VDD is set, and in response to this, the bit line reset signal LEZ becomes VSS, and in the sense amplifier 6, the nMOS transistor 10 is turned off.

  Subsequently, the word line WL rises, data is read from the selected memory cell, and a slight difference potential is generated between the bit lines BL0Z and BL0X. In this state, the timing word signal TWLX = VSS, and accordingly, the latch enable signal LEX = VSS and LEZ = VDD. As a result, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned on, the sense amplifier 6 is activated, and the difference potential between the bit lines BL0Z and BL0X is amplified.

  When the cell data is transferred to the data buses GDBZ and GDBX, the test mode setting signal TESZ = VSS, the active signal ACTZ = VSS, the timing word signal TWLX = VDD, the latch enable signal LEX = VDD, and LEZ = VSS. Thus, in the sense amplifier 6, the pMOS transistor 7 and the nMOS transistor 10 are turned off, and the sense amplifier 6 is deactivated.

  Thereafter, the bit line reset control signal BRRZ = VSS is set, and accordingly, the bit line reset signals BRS1X and BRS0X = VPP are set, and in the bit line precharge circuit 51, the nMOS transistors 14 to 16 are turned ON. As a result, the bit lines BL0Z and BL0X are precharged to VCC / 2. Further, the bit line transfer gate drive signal BLT1X = VPP, and in the bit line transfer gate 20, the nMOS transistors 21 and 22 are turned ON.

  In the third embodiment of the present invention, the bit line potential control means includes the latch enable signal generation circuit 84, the bit line reset signal generation circuit 85, the bit line precharge circuit 51, and the nMOS transistors 10 to 12 of the sense amplifier 6. It is comprised including.

  Since the test mode setting signal TESZ = VSS is set in the normal mode, in the latch enable signal generation circuit 84, the NAND circuit 92 functions as an inverter with respect to the timing word signal TWLX, and the latch enable signals LEX and LEZ are shown in FIG. The signal is substantially the same as that of the conventional DRAM shown in FIG. In the bit line reset signal generation circuit 85, since the NOR circuit 106 functions as an inverter with respect to the bit line reset control signal BRRZ, the bit line reset signals BRS0X and BRS1X are in-phase signals. Therefore, in the normal mode, the operation is the same as in the conventional DRAM shown in FIG.

  As described above, according to the third embodiment of the present invention, after the bit line is precharged to VCC / 2, in the test mode, the potential of the bit line before cell data reading is set lower than VCC / 2. Therefore, the read margin for “0” data can be reduced, and the time required for the refresh test for “0” data can be shortened.

  Note that the potential of the bit line before cell data reading is determined by the timing when the active signal ACTZ is set to VDD. Therefore, by changing the timing when the active signal ACTZ is set to VDD, the potential of the bit line before reading the cell data is changed. It can be set to a desired potential having a low range of VCC / 2 to Vth-n.

  In the third embodiment of the present invention, when the nMOS transistor 10 is turned ON in the test mode, the potential of the bit line before reading the cell data is set to a potential lower than VCC / 2. However, instead of this, by turning on the pMOS transistor 7, the potential of the bit line before cell data reading may be set higher than VCC / 2. In this case, "1 Since the “data read margin” can be reduced, the time required for the refresh test of “1” data can be shortened.

  In this case, since the potential of the bit line before reading the cell data is determined by the time when the pMOS transistor 7 is turned on, the bit line potential before reading the cell data is controlled by controlling the time when the pMOS transistor 7 is turned on. It can be set to a desired potential higher than VCC / 2.

Effect of the invention

  As described above, according to the present invention, the potentials of the first and second bit lines before cell data reading can be controlled using the transistors of the sense amplifier, so that the first and second bit lines can be controlled. The potential of the first and second bit lines is set to a potential lower than the middle between the highest potential and the lowest potential, so that the number of elements can be increased even when miniaturization or increase in memory capacity is attempted. The retention time of “1” data can be prevented from being shortened without incurring, that is, without increasing the cost due to the increase in chip area.

  Further, when the bit line potential control means is configured to control the potentials of the first and second bit lines before reading the cell data in the test mode, the potentials of the first and second bit lines are set to the cell. By setting the potential to reduce the data read margin, the time required for the refresh test can be shortened.

  It is a circuit diagram showing a part of a 1st embodiment of the present invention.   It is a circuit diagram which shows the structure of the sense amplifier part with which 1st Embodiment of this invention is provided.   1 is a circuit diagram illustrating a configuration of a latch enable signal generation circuit included in a first embodiment of the present invention. FIG.   It is a wave form diagram for demonstrating the read-out operation | movement in 1st Embodiment of this invention.   It is a wave form diagram for demonstrating the read-out operation | movement in 1st Embodiment of this invention.   It is a circuit diagram which shows a part of 2nd Embodiment of this invention.   It is a circuit diagram which shows the structure of the sense amplifier part with which 2nd Embodiment of this invention is provided.   It is a circuit diagram which shows the structure of the latch enable signal generation circuit with which 2nd Embodiment of this invention is provided.   It is a circuit diagram which shows the structure of the bit line reset signal generation circuit with which 2nd Embodiment of this invention is provided.   It is a wave form diagram for demonstrating the read-out operation | movement in 2nd Embodiment of this invention.   It is a wave form diagram for demonstrating the read-out operation | movement in 2nd Embodiment of this invention.   It is a circuit diagram which shows a part of 3rd Embodiment of this invention.   It is a circuit diagram which shows the structure of the sense amplifier part with which 3rd Embodiment of this invention is provided.   It is a circuit diagram which shows the structure of the latch enable signal generation circuit with which 3rd Embodiment of this invention is provided.   It is a circuit diagram which shows the structure of the bit line reset signal generation circuit with which 3rd Embodiment of this invention is provided.   It is a wave form chart for explaining operation at the time of test mode of a 3rd embodiment of the present invention.   It is a wave form chart for explaining operation at the time of test mode of a 3rd embodiment of the present invention.   It is a circuit diagram which shows a part of example of the conventional DRAM.   FIG. 19 is a circuit diagram showing a configuration of a sense amplifier unit included in the conventional DRAM shown in FIG. 18.   FIG. 19 is a circuit diagram showing a configuration of a latch enable signal generation circuit included in the conventional DRAM shown in FIG. 18.   FIG. 19 is a circuit diagram showing a configuration of a bit line reset signal generation circuit included in the conventional DRAM shown in FIG. 18.   FIG. 19 is a waveform diagram for explaining a read operation in the conventional DRAM shown in FIG. 18.   FIG. 19 is a waveform diagram for explaining a read operation in the conventional DRAM shown in FIG. 18.

LEX, LEZ ... Latch enable signal BRRZ, BRR0Z, BRR1Z ... Bit line reset control signal BRSX, BRS0X, BRS1X ... Bit line reset signal BLT0X, BLT1X ... Bit line transfer gate drive signal BL0X, BL0Z, BL1X, BL1Z ... Bit line GDBX, GDBZ ... Data bus CLSZ ... Column selection signal TESZ ... Test mode setting signal WLTZ ... Switching signal

Claims (2)

A pair of first and second bit lines;
A pull-up transistor, a pull-down transistor, a first sense amplifier activation transistor that supplies a first power supply voltage to the pull-up transistor, and a second power supply voltage that supplies a second power supply voltage to the pull-down transistor The first sense amplifier activating transistor and the second sense amplifier activating transistor are turned on at the time of reading cell data, whereby the first sense amplifier activating transistor is turned on . 1. A semiconductor memory device having a sense amplifier for amplifying a difference potential generated between first and second bit lines,
In the normal mode and before reading cell data, the first sense amplifier activating transistor is turned off, and the second sense amplifier activating transistor is turned on. A bit line that controls the potential of the bit line to a potential lower than the intermediate potential from the potential after reading the previous cell data or from the intermediate potential between the highest potential and the lowest potential that can be taken by the first and second bit lines. A semiconductor memory device comprising a potential control means.
The pull-up transistors are first conductivity type first and second field effect transistors,
The pull-down transistors are second conductivity type third and fourth field effect transistors,
The first sense amplifier activating transistor is a first conductivity type fifth field effect transistor,
The second sense amplifier activating transistor is a second conductivity type sixth field effect transistor,
The first field effect transistor has a drain connected to the first bit line, a gate connected to the second bit line,
The second field effect transistor has a drain connected to the second bit line, a gate connected to the first bit line,
The third field effect transistor has a drain connected to the first bit line, a gate connected to the second bit line,
The fourth field effect transistor has a drain connected to the second bit line, a gate connected to the first bit line,
The fifth field effect transistor has a source connected to a first power supply that supplies the first power supply voltage, and a drain connected to the sources of the first field effect transistor and the second field effect transistor. A first control signal is applied to the gate;
The sixth field effect transistor has a source connected to a second power supply that supplies the second power supply voltage, and a drain connected to the sources of the third field effect transistor and the fourth field effect transistor. the semiconductor memory device according to claim 1, wherein the second control signal is supplied to the gate.

Images