JP5277746B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor sensor chip for measuring a solution having a gate insulating film of a silicon oxide film having a film thickness so that a leak current does not flow into a semiconductor substrate when measuring a chemical substance in a solution with a potential applied thereto, and allowing easy inducing of an amino group by silane coupling and suppressing a leak current flowing between the solution and a wiring. <P>SOLUTION: The semiconductor sensor chip for measuring a solution is formed by a MOS transistor having an exposed gate insulating film, immersed in a solution with a potential applied thereto to detect a chemical substance by detecting the change of current flowing through the MOS transistor, and includes: an organic monomolecular layer fixed on the gate insulating film of the MOS transistor formed on the semiconductor substrate; a wiring connected to a source and a drain of the MOS transistor; and a passivation film having an opening part at which the organic monomolecular layer is exposed. The gate insulating film has an outermost layer formed with the silicon oxide film, and has a thickness of 30 nm or more. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention is a semiconductor device, and in particular, a molecular layer is provided on a gate insulating film, which is composed of an ion-sensitive (IS) MOS transistor, immersed in a solution to which a potential is applied, and detection of chemical substances in the solution is performed. The present invention relates to a semiconductor sensor chip to be performed.

Conventionally, a fluorescence detection method is often used as a base sequence detection using a DNA chip or a DNA microarray.
In recent years, a current detection method using a MOS transistor has come to be used for hybridization of a base sequence or a biological substance and detection of a chemical substance in a solution (for example, see Patent Document 1).
The field effect transistor for semiconductor sensing described in Patent Document 1 forms an organic monomolecular film as a detection unit on a gate insulating film, and a chemical substance in a solution is adsorbed or biochemically reacted to form the above organic By measuring the current flowing through the MOS transistor by changing the potential of this organic monomolecular film by attaching to the monomolecular film, it reacts with the concentration of chemical substances in the solution and reacts with the organic monomolecular film in the solution. Detection of the presence or absence of chemical substances to be performed.

Further, as a product using a MOS transistor as an ion sensitive sensor, a semiconductor sensor chip for solution measurement having a structure in which a surface layer exposed in a solution of a gate insulating film is formed of a tantalum pentoxide (Ta ₂ O ₅ ) film. Is used.
However, when measuring the pH of the solution, an ion-sensitive film such as an amino acid group must be provided on the surface of the gate insulating film of the MOS transistor in contact with the solution.
Further, in order to immobilize proteins such as DNA and antibodies, it is necessary to form an organic monomolecular film such as APTES (aminopropyl-triethoxysilane) on the gate insulating film.

When attaching molecules having amino groups to the gate insulating film, in general, when silicon is used for the semiconductor substrate, silane coupling is used to introduce amino groups into the gate insulating film.
However, since the hydroxy group is not uniformly formed on the surface of tantalum pentoxide, an organic monomolecular film for immobilizing proteins is easily formed using the silane coupling reaction in the above-described semiconductor sensor chip for solution measurement. I can't.
Therefore, as the gate insulating film in the semiconductor sensor chip for solution measurement, it is necessary that the outermost layer is formed of a silicon oxide film (SiO ₂ ) and can be modified by a silane coupling agent as an organic monomolecular film.
JP 2006-98333 A

However, in a semiconductor sensor chip for measuring a solution used by immersing it in a solution to which a potential is applied, when the gate insulating film of a MOS transistor is formed of a silicon oxide film, due to pinholes existing at a certain ratio in the silicon oxide film, The solution and the semiconductor substrate just below the gate insulating film come into contact with each other, and a leakage current flows, which adversely affects the measurement.
In addition, in a semiconductor sensor chip for measuring a solution that is immersed in a solution to which a potential is applied, holes or cracks are generated in the passivation film on the wiring of the MOS transistor, so that the solution and the wiring come into contact with each other, and a leakage current flows. become.

  The present invention has been made in view of such circumstances. When measuring a chemical substance in a solution to which a potential is applied, the gate insulating film is formed of a silicon oxide film having a thickness that prevents leakage current from flowing through the semiconductor substrate. An object of the present invention is to provide a semiconductor sensor chip for solution measurement that is formed, can easily introduce amino acid groups by silane coupling, and suppresses a leakage current flowing between the solution and the wiring.

  The semiconductor sensor chip for measuring a solution of the present invention is composed of a MOS transistor with an exposed gate insulating film, and is immersed in a solution to detect a chemical substance in the solution and to detect a change in current flowing in the MOS transistor. A semiconductor sensor chip for measuring solution, which is connected to a semiconductor substrate, an organic monolayer fixed on the gate insulating film of the MOS transistor formed on the semiconductor substrate, and a source and drain of the MOS transistor And a passivation film having an opening through which the organic monomolecular layer portion is exposed. The outermost layer of the gate insulating film is formed of a silicon oxide film, and the gate insulating film has a thickness of 30 nm or more. It is characterized by being formed.

  The semiconductor sensor chip for measuring a solution according to the present invention is characterized in that the passivation film on the wiring is formed in a multilayer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

  The semiconductor sensor chip for measuring a solution according to the present invention is characterized in that the wiring is formed so that a width of a portion immersed in the solution is narrower than a width of a portion not immersed in the solution.

  The semiconductor sensor chip for measuring a solution according to the present invention is characterized in that an inner peripheral surface of a hole in the opening immersed in the solution is covered with a silicon oxide film.

As described above, according to the present invention, the outermost layer of the gate insulating film is formed of a silicon oxide film, and the organic monomolecular film can be easily bonded to the silicon oxide film by silane coupling. Further, it is possible to easily fix a chemical material for detecting a biological sample such as DNA or protein existing in the solution or the pH concentration in the solution to the organic monomolecular film.
In addition, according to the present invention, since the gate insulating film maintains detection sensitivity, the gate insulating film is formed with a minimum film thickness that suppresses leakage current generated by applying a potential to the solution. When a chemical substance adheres in response to a material, it is possible to obtain a large change in the amount of current due to a potential change applied to the gate insulating film due to this adhesion, and the chemical substance in the solution can be detected with high sensitivity. .

In addition, according to the present invention, the passivation film is formed in a multilayer structure including three layers in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked. By introducing the tensile stress of the silicon nitride film, the stress of the entire passivation film can be reduced, the occurrence of pinholes and cracks can be suppressed, and the resistance of the passivation film can be improved.
In addition, according to the present invention, the width of the wiring in the portion immersed in the solution is narrower than the width of the wiring in the portion not immersed in the solution, so that the positions of the generated holes and cracks coincide with the positions of the wiring. Probability can be reduced, and the probability of contact between the solution and the wiring entering from the holes and cracks can be reduced, and the occurrence of leakage current can be suppressed.

The present invention is a sensor (semiconductor sensor chip for solution measurement) configured by a MOS transistor, and is immersed between the solution and the semiconductor substrate (N-SUB or P-SUB). An organic monomolecular film is formed on the exposed gate insulating film (for example, gate oxide film) by applying an electric potential, and the base sequence or biological body is applied to the organic monomolecular film or a chemical material fixed to the organic monomolecular film. When the substance or chemical substance reacts and adsorbs, the current flowing through the MOS transistor changes due to the change in potential applied to the gate insulating film, and the base sequence, biological substance or chemical substance is specified. Since a voltage is applied between the solution and the source, a constant current always flows through the MOS transistor, and the potential of the gate insulating film due to the chemical substance binding to the chemical material of the organic monomolecular film is The chemical substance is detected by the amount of change in the current.
That is, in the MOS transistor of the present invention, an organic monomolecular film as a detection unit or a chemical material fixed to the organic monomolecular film is formed on the gate insulating film, and the chemical substance in the solution is absorbed or biochemically reacted. By measuring the current flowing through the MOS transistor by the potential change of the organic monomolecular film by adhering to the organic monomolecular film or the fixed chemical material, the concentration of the chemical substance in the solution, Detection of the presence or absence of a chemical substance that reacts with the organic monomolecular film in the solution is performed.

<N-channel MOS transistor>
Hereinafter, a semiconductor sensor chip for measuring a solution (semiconductor device) according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a cross-sectional structure of a configuration example of the embodiment. FIG. 1 shows a cross section of an N-channel MOS transistor.
In FIG. 1, a well PW to which a P-type impurity is added is formed on the surface of a semiconductor substrate N-SUB to which an N-type impurity is added.
In the well PW, a diffusion layer 102 as a source of the MOS transistor N1 and a diffusion layer 103 as a drain are formed to face each other through a channel formation region 120. Each of the diffusion layers 102 and 103 is an N-type. Impurities are added.

Further, in the side portion of the diffusion layer 102, at the other end different from the one end where the channel formation region 120 is formed, the diffusion layer 102 is adjacent to the diffusion layer 102, is a well contact of the well PW, and is doped with a P-type impurity. Layer 101 is formed.
The channel formation region 120 and the diffusion layers 101, 102, and 103 are regions for forming the MOS transistor N1. Here, a gate insulating film 104 made of a silicon oxide film (SiO ₂ ) is formed on the channel formation region 120 and the diffusion layers 101, 102, and 103.
The MOS transistor N1 includes the above-described channel formation region 120, diffusion layers 101, 102 and 103, and the gate insulating film 104.
In addition, an element isolation film 100 having a set width and thickness is formed of, for example, a silicon oxide film on the outer periphery of the MOS transistor formation region.

A channel stopper NF to which a P-type impurity having a higher concentration than the well PW is added is formed immediately below the element isolation film 100 in order to suppress inversion of the interface between the element isolation film 100 and the well PW.
On the upper surface of the gate insulating film 104, a polycrystalline silicon film mask 501 is formed on the outer peripheral portion of the exposed region so as to surround the exposed region of the gate insulating film 104 including the channel forming region 120 which is a detection region of the MOS transistor sensor. A pattern having a set width is formed. The exposed region is set as a range including the channel forming region 120 in plan view.

An interlayer insulating film 106 is formed on the entire surface including the upper portions of the element isolation film 100 and the gate insulating film 104. As a contact region for electrically connecting the wiring 108S and the diffusion layers 101 and 102, the interlayer insulating film 106 and A contact hole 107S penetrating the gate insulating film 104 is formed. Thereby, the wiring 108S and the diffusion layers 101 (well contact) and 102 (source) are electrically connected.
Similarly, a contact hole 107D penetrating the interlayer insulating film 106 and the gate insulating film 104 is formed as a contact region for electrically connecting the wiring 108D and the diffusion layer 103. Thereby, the wiring 108D and the diffusion layer 103 (drain) are electrically connected.

Further, a passivation film 122 that protects the MOS transistor N1 (wiring or contact region) is formed on the entire surface including the interlayer insulating film 106 and the upper portions of the wiring 108S and the wiring 108D.
In the present embodiment, for example, the passivation film 122 is formed in a multilayer structure including three layers of a silicon oxide film 109, a silicon nitride film 110, and a silicon oxide film 111.
Further, in the interlayer insulating film 106 and the passivation film 122, an opening 121 that penetrates to the surface of the gate insulating film 104 is formed above the exposed area in order to expose the exposed area.
An organic monomolecular film is formed on the upper surface of the gate insulating film 104 exposed in the exposed region.

<P-channel MOS transistor>
Hereinafter, a semiconductor sensor chip for measuring a solution (semiconductor device) according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a cross-sectional structure of a configuration example of the embodiment. FIG. 1 shows a cross section of a P-channel MOS transistor P1.
In FIG. 2, a well NW to which an N-type impurity is added is formed on the surface of the semiconductor substrate P-SUB to which a P-type impurity is added.
In the well NW, a diffusion layer 102 as a source of the MOS transistor P1 and a diffusion layer 103 as a drain are formed to face each other through a channel formation region 120. Each of the diffusion layers 102 and 103 is a P-type. Impurities are added.

Further, on the side of the diffusion layer 202, on the side opposite to the channel formation region 120, adjacent to the diffusion layer 202, is a well contact of the well NW, and the diffusion layer 201 to which an N-type impurity is added is formed. Yes.
The channel formation region 120 and the diffusion layers 201, 202, and 203 are regions for forming the MOS transistor P1. Here, a gate insulating film 104 made of a silicon oxide film (SiO ₂ ) is formed on the channel formation region 120 and the diffusion layers 201, 202, and 203.
The MOS transistor N1 includes the above-described channel formation region 120, diffusion layers 201, 202, and 203, and the gate insulating film 104.
In addition, an element isolation film 100 having a set width and thickness is formed of, for example, a silicon oxide film on the outer periphery of the MOS transistor formation region.

A channel stopper PF to which an N-type impurity having a higher concentration than the well NW is added is formed immediately below the element isolation film 100 in order to suppress inversion of the interface between the element isolation film 100 and the well NW.
On the upper surface of the gate insulating film 104, a polycrystalline silicon film mask 501 is formed on the outer peripheral portion of the exposed region so as to surround the exposed region of the gate insulating film 104 including the channel forming region 120 which is a detection region of the MOS transistor sensor. A pattern having a set width is formed. The exposed region is set in a range including the channel forming region 120 in plan view.

An interlayer insulating film 106 is formed on the entire surface including the upper portions of the element isolation film 100 and the gate insulating film 104. As a contact region for electrically connecting the wiring 108S and the diffusion layers 201 and 202, the interlayer insulating film 106 and A contact hole 107S penetrating the gate insulating film 104 is formed. Thereby, the wiring 108S and the diffusion layers 201 (well contact) and 202 (source) are electrically connected.
Similarly, a contact hole 107D penetrating the interlayer insulating film 106 and the gate insulating film 104 is formed as a contact region for electrically connecting the wiring 108D and the diffusion layer 203. Thereby, the wiring 108D and the diffusion layer 203 (drain) are electrically connected.

A passivation film 122 that protects the MOS transistor P1 is formed on the entire surface including the interlayer insulating film 106 and the upper portions of the wiring 108S and the wiring 108D.
In the present embodiment, the passivation film 122 is formed in a multi-layered structure including a silicon oxide film 109, a silicon nitride film 110, and a silicon oxide film 111, like the N-channel MOS transistor N1. Yes.
Further, in the interlayer insulating film 106 and the passivation film 122, an opening 121 that penetrates to the surface of the gate insulating film 104 is formed above the exposed area in order to expose the exposed area.
Further, an organic monomolecular film is formed on the upper surface of the gate insulating film 104 exposed in the exposed region in the same manner as the MOS transistor N1.

<Setting of thickness of silicon oxide film used for gate insulating film 104>
As already described, for the purpose of bonding an organic monomolecular film to silane coupling, in the case of a MOS transistor, it is necessary to use a silicon oxide film as a gate insulating film of the transistor. Therefore, as the thickness of the gate insulating film 104 in the MOS transistors N1 and P1 (hereinafter referred to as a transistor in the case of a MOS transistor) is thinner, the sensitivity of sensing increases. On the other hand, the thinning causes a pinhole. When the probability increases and the sensitivity is improved by reducing the film thickness, a leak current is generated by the pinhole.
Therefore, it is used in a highly sensitive and durable solution by setting the thickness of the gate insulating film 104 that does not generate pinholes that cause leakage current while reducing the film thickness to improve sensitivity. It is conceivable to create a MOS transistor as a sensor.

In addition, as described above, since the semiconductor sensor chip for solution measurement according to the present embodiment is immersed in a solution and a chemical substance contained in the solution is detected, it may be immersed in a solution having a wide pH range. Therefore, it is necessary to set the film thickness of the gate insulating film with a solution having a pH at which leakage current is more likely to occur in the pH dependency of the resistance of the silicon oxide film.
Therefore, as an experiment on the pH dependence of the increase in leakage current, an oxide film having the same thickness is prepared by the same process, immersed in solutions having a plurality of different pHs, and the voltage applied to this solution is changed, as shown in FIG. In addition, the voltage at which a leak current was generated was measured at a plurality of measurement points at different positions from the outer periphery of the wafer toward the center. Here, the variation of the silicon oxide film in the wafer surface has a range of +5 nm and −5 nm, that is, the thickness of the silicon oxide film in the wafer surface is 15 nm to 25 nm. As measurement conditions, a voltage of 0.1 V was applied between the source (diffusion layer 102) and the drain (diffusion layer 103) in the MOS transistor at the measurement point (using the MOS transistor N1), and the solution and source ( A voltage Vg of 0 to 25 V was sequentially applied to the diffusion layer 102).

As a result of the above experiment, the results shown in FIG. 4 (solution is pH 4), FIG. 5 (solution is pH 7) and FIG. 6 (solution is pH 9) were obtained. 4, 5, and 6, the horizontal axis indicates the voltage value of the voltage Vg, and the vertical axis indicates the current value of the leakage current that flows between the solution and the source.
From the above results, it can be seen that the leakage current is generated by the voltage Vg having a low voltage value as the pH of the solution increases.
In the pH 4 solution, an increase in leakage current was confirmed at a voltage Vg of about 15 V, and an increase in leakage current was confirmed at pH 9 at a voltage Vg of about 10 V. It can be seen that the voltage value of the generated voltage Vg decreases.

  Since the pH of the solution used for most measurements is pH 9 or less, the film thickness of the silicon oxide film is set at this pH 9. At pH 9, a plurality of silicon oxide film thicknesses were taken, and tests similar to those shown in FIGS. 7 shows that the thickness of the silicon oxide film (gate insulating film 104) is 35 nm (ie, the in-plane variation in the well is 5 nm, so that the range is substantially 30 to 40 nm), and FIG. 8 shows the silicon oxide film. The film thickness of the (gate insulating film 104) was 55 nm (that is, the in-plane variation in the well is 5 nm, so that it is substantially in the range of 50 to 60 nm). 4 and 5, the source (diffusion layer 102) and drain (diffusion layer) of the MOS transistor (using the MOS transistor N1) at the measurement point at a plurality of measurement points in the well as in FIG. A voltage of 0.1 V was applied between the layer 103) and a voltage Vg of 0 to 35 V was sequentially applied between the solution and the source (diffusion layer 102).

  As a result of the above experiment, when the film thickness of FIG. 7 is 30 to 40 nm, a leakage current is generated in the voltage value range of 17V to 24V. This variation in leakage current is considered to depend on the variation in film thickness, and is considered to be the voltage value of the voltage Vg at which the lowest leakage current occurs at the thinnest measurement point. Therefore, the thickness of the gate insulating film 104 of the MOS transistor at the measurement point where the voltage Vg is 17V and the leakage current is generated is approximately 30 nm, and the leakage current is generated when the voltage Vg is 24V. It can be estimated that the thickness of the gate insulating film 104 in the point MOS transistor is approximately 40 nm.

  In addition, when the film thickness in FIG. 8 is 50 to 60 nm, a leakage current is generated in the range where the voltage value of the voltage Vg is 30 V to 36 V. As in the case of FIG. 7 described above, it is considered that the voltage value of the voltage Vg at which the lowest leakage current is generated at the measurement point where the film thickness is the thinnest. Therefore, the thickness of the gate insulating film 104 of the MOS transistor at the measurement point where the voltage Vg is 30V and the leak current is generated is approximately 50 nm, and the measurement is such that the leak current is generated when the voltage Vg is 36V. The film thickness of the gate insulating film 104 of the point MOS transistor can be estimated to be approximately 60 nm.

  In FIG. 6 described above, when the thickness of the silicon insulating film 104 is 15 to 25 nm, a leakage current is generated in the voltage value range of 9V to 11V. As in the case of FIG. 7 described above, it is considered that the voltage value of the voltage Vg at which the lowest leakage current is generated at the measurement point where the film thickness is the thinnest. Therefore, the film thickness of the gate insulating film 104 of the MOS transistor at the measurement point where the voltage Vg is 9V and the leakage current is generated is approximately 15 nm, and the leakage current is generated when the voltage Vg is 11V. The film thickness of the gate insulating film 104 of the point MOS transistor can be estimated to be approximately 25 nm.

From the above measurement results, in the measurement immersed in a pH 9 solution, when the thickness of the gate insulating film 104 is 15 nm, the voltage value Vg of the leakage current is 9 V, and the thickness of the gate insulating film 104 is 25 nm. In this case, when the voltage value of the voltage Vg at which the leakage current is generated is 11V and the film thickness of the gate insulating film 104 is 30 nm, the voltage value of the voltage Vg at which the leakage current is generated is 17V. When the film thickness is 40 nm, the voltage value of the leakage current generating voltage Vg is 24V, and when the gate insulating film 104 film thickness is 50 nm, the leakage current generating voltage Vg is 30V. It can be seen that when the thickness of the insulating film 104 is 60 nm, the voltage value of the voltage Vg at which the leakage current is generated is 36V.
Therefore, since the semiconductor sensor chip for measuring a solution according to the present embodiment uses the voltage value of the voltage Vg normally at 15 V or less, the sensitivity of the sensing is maximum, and the film thickness is such that the leakage current does not flow through the gate insulating film 104. It can be seen from the above experiment that the thickness of about 30 nm is the lower limit. The upper limit of the film thickness may be set in a timely manner when the voltage applied to the solution is increased or when the sensitivity may be low.
Further, since the outermost layer only needs to be a silicon oxide film, even in a three-layer structure with a silicon nitride film sandwiched in the center, only the surface portion of the silicon nitride film formed on the surface of the semiconductor substrate N-SUB is formed into an oxide film. Such a structure may be used as the gate insulating film 104.

Further, since the passivation film 122 has a three-layer structure in which the silicon oxide film 109, the silicon nitride film 110, and the silicon oxide film 111 are sequentially stacked, the silicon nitride film 110 is interposed between the silicon oxides 109 and 111, and the silicon oxide film The tensile stress of the silicon nitride film 110 is introduced with respect to the compressive stress of 109 and 111, and the compressive stress of the silicon oxide films 109 and 111 is offset by the tensile stress of the silicon nitride film 110, whereby the overall stress of the passivation film 122 is obtained. Is reduced, the occurrence of cracks is suppressed, and the reliability of the passivation film 122 is improved. Further, by overlapping three layers of silicon oxide film 109 / silicon nitride film 110 / silicon oxide film 111, the probability of occurrence of pinholes is dispersed, and the reliability of the passivation film 122 is further improved.
Further, the wiring width of the wirings 108D and 108S in the region immersed in the solution is made narrower than the wiring width of the wirings 108D and 108S in the region not immersed in the solution, so that the passivation film 122 in the region immersed in the solution is obtained. The probability that the cracks and pinholes that have occurred in the wiring 108D and 108S are present directly on the wirings 108D and 108S can be reduced, and the solution can reach the wirings 108D and 108S from the generated cracks and pinholes, thereby reducing the probability of occurrence of leakage current. The reliability of the semiconductor sensor chip for solution measurement can be improved.

<Manufacturing Process of N-Channel MOS Transistor N1>
The manufacturing process of the MOS transistor described above will be described with reference to FIGS. 9 to 15 by taking the manufacturing process of the N-channel type MOS transistor N1 as an example. 9 to 15 correspond to the cross-sectional structure of the manufacturing process of the MOS transistor N1 of FIG. Also in the P-channel MOS transistor P1 shown in FIG. 2, the conductivity type of the impurity is reversed, that is, the P-type is only N-type or the N-type is only P-type. The manufacturing process of the transistor is the same.

As shown in FIG. 9, after an oxide film 500 is formed on a semiconductor substrate P-SUB to which a P-type impurity is added by thermal oxidation or the like, a P-type conductivity type is formed on the entire surface at a set depth. Impurities, for example, BF ²⁺ ions are ion-implanted to form a P-type impurity layer for forming the well PW.
Further, in order to form a channel stopper NF that is a P-type impurity layer of a channel stopper in a region where the element isolation film 100 is formed in a later process, a resist pattern opened only at a portion where the element isolation film 100 is formed is formed by photolithography. Then, using this resist pattern as a mask for ion implantation, BF ²⁺ ions having a concentration higher than the impurity concentration when the well PW is formed are ion implanted. The resist pattern is removed.

  Next, as shown in FIG. 10, an element isolation film 100 that electrically isolates the MOS transistor formation region is directly oxidized directly on the channel stopper NF, which is a P-type impurity layer, or a groove is formed in the groove. It is formed by depositing an insulating material (insulator).

In FIG. 11, in order to form the MOS transistor N1 in the region of the well PW where the element isolation film 100 is not formed (transistor formation region), a resist pattern in which regions serving as the source and drain are opened by photolithography is formed. Using this resist pattern as a mask, P ⁺ (phosphorus ions) as N-type impurities are ion-implanted to a depth in the process design and at a set concentration to form diffusion layers 102 and 103. The resist pattern is removed.
Then, on the side surface of the source diffusion layer 102, a potential is applied to the well PW in a region adjacent to the channel formation region 120 of the MOS transistor N1 (a region where a channel between the source and the drain is opposed to each other). A well contact 101 formed of a diffusion layer is formed by photolithography to form a resist pattern in which a region serving as a well contact is opened. Using this resist pattern as a mask, BF ²⁺ is formed as a P-type impurity in a process design depth. Are formed by ion implantation at a concentration set to 1. The resist pattern is removed, and the oxide film 500 is removed.

A gate insulating film 104 is formed by thermal oxidation on the surface of the well PW where the element isolation film 100 is not formed.
Here, the gate insulating film 104 is formed to a thickness of 30 nm or more by thermal oxidation heated to 950 ° C. in an oxygen (O ₂ ) atmosphere. Here, the concentration of the impurity (P: phosphorus) in the semiconductor substrate N-SUB is 1 × 10 ¹⁷ / cm ³ , and the concentration of the impurity (B: boron) in the well PW is 5 × 10 ¹⁸ / cm ³ .

  Next, as shown in FIG. 12, a polycrystalline silicon film is deposited on the entire surface, and only the mask portion that covers a portion exposed as a sense region in a later process is left in plan view. The resist pattern is formed by photolithography, and using this resist pattern as a mask, the polycrystalline silicon film is etched (dry etching, anisotropic etching if necessary) to form a polycrystalline silicon film mask 501. The resist pattern is removed.

Then, as shown in FIG. 13, an oxide film is deposited as an interlayer insulating film 106 on the entire surface by CVD (Chemical Vapor Deposition) or the like.
Next, as a step of exposing the surfaces of the diffusion layers 102, 103, and 101 in a set area in order to form a conductor wiring and a contact to be formed later, a portion where contact holes 107D and 107S are formed by photolithography Only a resist pattern having an opening is formed. Using this resist pattern as a mask, dry etching is performed to remove the interlayer insulating film 106 and the gate insulating film 104 in the contact hole forming portion, and a contact hole 107D for the diffusion layer 103 and a contact hole 107S for the diffusion layers 101 and 102 are formed. . The resist pattern is removed.

Then, a conductor film (for example, an Al—Cu—Si multilayer film) is deposited to a thickness set by sputtering. At this time, it is also deposited in the contact holes 107D and 107S, and a contact is formed by electrical contact between the conductor film and each diffusion layer. Here, the diffusion layer 102 and the diffusion layer 101 are electrically connected by a contact portion of the wiring pattern (wiring 108S) of the conductor film.
In order to form the wirings 108S and 108D as the wiring pattern, a resist pattern having openings other than the portions where the wirings 108S and 108D are formed is formed by photolithography. Then, etching is performed using this resist pattern as a mask to form wirings 108S and 108D. The resist pattern is removed.
Here, the wirings 108S and 108D have a wiring pattern in which the wiring width (for example, 50 μm) of the region immersed in the solution is narrower than the wiring width (for example, 1000 μm) of the region not immersed in the solution. By reducing the probability that the positions of the wirings 108S and 108D coincide with the positions of pinholes and cracks generated in the passivation film 122, which will be described later, the tolerance of the semiconductor sensor chip for solution measurement immersed in the solution is improved. Let

Next, as shown in FIG. 14, TEOS (normal tetraethyl silicate: Si (OC ₂ H ₅ ) ₄ ) is applied to the entire surface, and a silicon oxide film 109 is formed to a thickness of 200 nm.
Further, a silicon nitride film 110 is formed to a thickness of 1200 nm on the entire surface of the silicon oxide film 109 by plasma CVD or the like.
Then, TEOS is applied on the entire surface of the silicon nitride film 110 to form a silicon oxide film 111 with a thickness of 200 nm.

As a result, a passivation film 122 comprising the silicon oxide film 111 / silicon nitride film 110 / silicon oxide film 109 is formed.
Next, an opening (SE opening) 121 is formed for exposing the gate insulating film 104 in the channel formation portion of the MOS transistor N1 serving as the detection portion in the sensor. That is, a resist pattern having an opening only in the opening 121 is formed by photolithography, the formed resist pattern is used as a mask, and the polycrystalline silicon film mask 501 is used as an etching stopper to perform selective etching on the oxide film. Then, the opening 121 is formed, and the resist pattern is removed.

Next, as shown in FIG. 15, the polycrystalline silicon is selectively etched using the resist pattern to remove the polycrystalline silicon film mask 501 exposed from the opened opening 121, and the MOS transistor N1. The surface of the gate insulating film 104 including the channel region is exposed through the opening 121, and the resist pattern is removed.
Then, again, TEOS is applied to the entire surface to form an oxide film, and the oxide film formed by TEOS is etched on the entire surface, whereby the oxide film spacer 112 is formed. Thereby, since the inner peripheral surface of the hole in the opening 121 immersed in the solution is covered with the oxide film spacer 112 as a silicon oxide film, the end surface of the passivation film 122 is not directly in contact with the solution. The resistance of the passivation film 122 can be improved.
Finally, by forming a monomolecular layer film on the surface of the gate insulating film 104, a sensor configured to detect a chemical substance in the solution by a current detection method, which is composed of the MOS transistor N1, is formed.

  That is, the semiconductor sensor chip for solution measurement according to the present embodiment forms a MOS transistor (an exposed organic monomolecular film is formed on the gate insulating film 104 by forming an organic monomolecular film as a detection unit). The chemical substance in the solution in which the gate insulating film 104) is immersed adheres to the organic monomolecular film by adsorption or biochemical reaction, so that the potential of the organic monomolecular film on the gate insulating film 104 is increased. By measuring the change in the current that flows through the MOS transistor due to this change in potential, the concentration of the chemical substance in the solution and the presence or absence of a chemical substance that reacts with the organic monomolecular film in the solution are detected. Can do.

As described above, in the semiconductor sensor chip for solution measurement of this embodiment, the outermost layer of the gate insulating film 104 is formed of a silicon oxide film, and the pH concentration in the solution, DNA, protein, etc. present in the solution A chemical material for detecting a biological sample is formed as an organic monomolecular film on the gate insulating film 104 by silane coupling, and the chemical material for detecting a chemical substance in the solution is fixed to the organic monomolecular film. Can be easily done.
Further, in the semiconductor sensor chip for solution measurement according to the present embodiment, since the gate insulating film 104 maintains detection sensitivity, the voltage Vg between the solution and the source extracted in the above-described experiment is 15 V (necessary for measurement). The minimum film thickness that suppresses the occurrence of leakage current when applied as a "high range", or higher than this film thickness, because it is formed with a thickness corresponding to the sensitivity required for detection of chemical substances. In addition, chemical substances in the solution can be detected.

1 is a cross-sectional view illustrating an example of the structure of an N-channel MOS transistor according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of the structure of a P-channel MOS transistor according to an embodiment of the present invention. It is a conceptual diagram which shows the wafer surface explaining the measurement point of the leakage current measurement of the gate insulating film 104 in the said MOS transistor. It is a graph which shows the voltage value of leak current generation in case the film thickness of the gate insulating film 104 is 20 nm and the solution is pH 4 at the measurement point. It is a graph which shows the voltage value of leak current generation in case the film thickness of the gate insulating film 104 is 20 nm and the solution is pH 7 at the measurement point. It is a graph which shows the voltage value of leak current generation in case the film thickness of the gate insulating film 104 is 20 nm and the solution is pH 9 at the measurement point. It is a graph which shows the voltage value of leak current generation in case the film thickness of the gate insulating film 104 is 35 nm and the solution is pH 9 at the measurement point. It is a graph which shows the voltage value of leak current generation in case the film thickness of the gate insulating film 104 is 55 nm and the solution is pH 9 at the measurement point. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG. It is a conceptual diagram which shows the cross-sectional structure for every process of forming the MOS transistor of this embodiment shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Element isolation film 101,102,103,201,202,203 ... Diffusion layer 104 ... Gate insulating film 106 ... Interlayer insulating film 107D, 107S ... Contact hole 108D, 108S ... Wiring 109,111 ... Silicon oxide film 110 ... Silicon Nitride film 112 ... Oxide film spacer 120 ... Channel formation region 121 ... Opening 501 ... Polycrystalline silicon film mask N1, P1 ... MOS transistor NF, PF ... Channel stopper N-SUB, P-SUB ... Semiconductor substrate NW, PW ... Well

Claims (3)

A semiconductor sensor for solution measurement, comprising a MOS transistor with an exposed gate insulating film, and detecting a chemical substance in the solution by immersing it in a solution to which a potential is applied, by detecting a change in current flowing in the MOS transistor Chip,
A semiconductor substrate;
An organic monomolecular layer fixed on the gate insulating film of the MOS transistor formed on the semiconductor substrate;
Wiring connected to the source and drain of the MOS transistor;
A passivation film having an opening through which the organic monomolecular layer portion is exposed,
The outermost layer of the gate insulating film is formed of a silicon oxide film, the gate insulating film is formed with a thickness of 30 nm or more, and is wired in a region immersed in the solution in the solution measuring semiconductor sensor chip. The semiconductor sensor chip for solution measurement, wherein the width of the wiring is formed narrower than the width of the wiring wired in a region not immersed in the solution in the semiconductor sensor chip for solution measurement. 2. The semiconductor sensor chip for solution measurement according to claim 1 , wherein the passivation film on the wiring is formed in a multilayer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film .   3. The semiconductor sensor chip for measuring a solution according to claim 1, wherein an inner peripheral surface of a hole in the opening immersed in the solution is covered with a silicon oxide film.

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