JP5272323B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is capable of lowering the rise voltage without lowering the reverse withstand voltage, and to provide a manufacturing method thereof. <P>SOLUTION: As semiconductor regions in contact with a first principal surface of a semiconductor base 100 composed by forming an N- silicon carbide epitaxial layer 2 on, for example, an N+ silicon carbide substrate 1 connected to a cathode electrode 6, both of, for example, an N+ polycrystalline silicon layer 4 of a conductivity type same as the conductivity type of the semiconductor base 100 and, for example, a P+ polycrystalline silicon layer 3 of a conductivity type different from the conductivity type of the semiconductor base 100 are provided. Both of the N+ polycrystalline silicon layer 4 and the P+ polycrystalline silicon layer 3 are hetero-joined to the semiconductor base 100, and are ohmically connected to an anode electrode 5. Moreover, the N+ polycrystalline silicon layer 4 of the conductivity type same as the conductivity type of the semiconductor base 100 is formed so as to be in contact with the first principal surface of the semiconductor base 100, and the P+ polycrystalline silicon layer 3 of the conductivity type different from the conductivity type of the semiconductor base 100 is formed in trenches dug in the first principal surface of the semiconductor base 100. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a background art of the present invention, there is a technique described in Japanese Patent Application Laid-Open No. 2003-318413 “High-voltage silicon carbide diode and manufacturing method thereof” of Patent Document 1 filed by the present applicant.

  In the conventional technique described in Patent Document 1, a first main surface of a semiconductor substrate in which an N− type silicon carbide epitaxial layer is formed on an N + type silicon carbide substrate has a band gap different from that of the semiconductor substrate, and P + type polycrystalline silicon layers having different conductivity types are formed, and the N− type silicon carbide epitaxial layer and the P + type polycrystalline silicon layer form a heterojunction. Here, the P + type polycrystalline silicon layer is connected to the anode electrode, and a cathode electrode is formed on the back surface of the N + type silicon carbide substrate. The symbols + and-mean high density and low density.

The conventional semiconductor device having the above-described configuration functions as a diode. That is, when the potential of the anode electrode is higher than the potential of the cathode electrode, a forward current flows, and in the opposite case, the current is prevented from flowing.
JP 2003-318413 A

  In the prior art described in Patent Document 1, the forward voltage rise is determined by the work function of the P + type polycrystalline silicon layer and the N− type silicon carbide epitaxial layer. Here, for example, in addition to the P + type polycrystalline silicon layer of the second conductivity type different from the N− type semiconductor substrate, an N + type polycrystalline silicon layer having a low rising voltage is formed on the heterojunction surface with the P + type polycrystalline silicon layer. If formed in parallel, diodes having two types of rising voltages are connected in parallel, and the entire rising voltage can be lowered.

  However, since the N + type polycrystalline silicon layer has a low reverse breakdown voltage, the reverse breakdown voltage of the entire diode also decreases. Thus, the rising voltage and the reverse breakdown voltage are in a proportional relationship, and it is difficult to lower the rising voltage without reducing the reverse breakdown voltage.

  The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a semiconductor device capable of lowering a rising voltage without lowering a reverse breakdown voltage and a manufacturing method thereof. .

In order to solve the above-mentioned problems, the present invention forms a first hetero semiconductor region of the same conductivity type as the semiconductor substrate to which the second electrode is connected on the first main surface of the semiconductor substrate. different conductivity type second hetero semiconductor region is formed on the first major surface to drilled the groove of the semiconductor substrate, with parallel connection of the first and second hetero semiconductor regions to the first electrode and, second The first and second hetero semiconductor regions are in contact with each other .

  According to the semiconductor device and the method of manufacturing the same according to the present invention, the first semiconductor type hetero semiconductor region having the same conductivity type as that of the semiconductor substrate is formed on the first main surface of the semiconductor substrate, which is different from the conductivity type of the semiconductor substrate. The second conductive type hetero semiconductor region is formed in a groove drilled in the first main surface of the semiconductor substrate, and both the hetero semiconductor regions are connected in parallel to the first electrode, so that the first electrodes are connected in parallel. The rising voltage can be reduced by the conductive hetero semiconductor region, and the decrease in breakdown voltage can be suppressed by the second conductive hetero semiconductor region formed in the groove of the first main surface of the semiconductor substrate.

  Hereinafter, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, a semiconductor device using silicon carbide (SiC) as a substrate material and a hetero semiconductor as polycrystalline silicon will be described as an example. In the present invention, the substrate material is not limited to silicon carbide, and may be made of gallium nitride or diamond.

  Also, the material of the hetero semiconductor is not limited to polycrystalline silicon as long as it is a material that forms a hetero semiconductor region made of a semiconductor material having a band gap different from that of a semiconductor substrate made of an epitaxial layer stacked on a substrate, It may consist of single crystal silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, amorphous silicon germanium, etc., and further, single crystal germanium, polycrystalline germanium, amorphous germanium, single crystal gallium arsenide, polycrystalline It may be made of gallium arsenide, amorphous gallium arsenide, or the like.

  FIG. 1 is a cross-sectional view showing a cross-sectional structure of an element portion in a first embodiment of a semiconductor device according to the present invention.

  As shown in semiconductor device 200 in FIG. 1, N− type silicon carbide epitaxial layer 2 is laminated by epitaxially growing an N− type silicon carbide semiconductor on N + type silicon carbide substrate 1, and silicon carbide semiconductor substrate 100 is formed. Is formed. The first main surface of the N− type silicon carbide epitaxial layer 2 opposite to the N + type silicon carbide substrate 1 is provided with one or a plurality of grooves at predetermined positions. In the portion where the upper groove is present, the inside of the groove is filled with a P + type polycrystalline silicon layer 3 as a second semiconductor type hetero semiconductor region different from the conductive type of the first conductive type N-type semiconductor substrate 100. It is formed in a state.

  Further, on the first main surface where the groove of N − type silicon carbide epitaxial layer 2 does not exist, an N + type polycrystalline silicon layer 4 is formed as a hetero semiconductor region of the same first conductivity type as that of semiconductor substrate 100. Is formed. Here, the polycrystalline silicon layers of both the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 and the N− type silicon carbide epitaxial layer 2 constituting the semiconductor substrate 100 have different band gaps. Thus, a heterojunction interface is formed. Here, the symbols + and − mean high density and low density of the introduced impurity density as described above.

  Further, a predetermined region in silicon carbide epitaxial layer 2 is formed at a junction between silicon carbide semiconductor substrate 100 and the polycrystalline silicon layers of P + type polycrystalline silicon layer 3 and N + type polycrystalline silicon layer 4. A P-type electric field relaxation region 7 that relaxes the electric field from the applied cathode electrode 6 is formed. On the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4, an anode electrode 5 ohmically connected to both the polycrystalline silicon layers is formed as a first electrode. On the other hand, a cathode electrode 6 is formed as a second electrode on the back surface of the N + type silicon carbide substrate 1.

  According to the present embodiment, P + type polycrystalline silicon layer 3 having a large built-in voltage with N− type silicon carbide epitaxial layer 2 and a high reverse breakdown voltage is formed inside the groove of N− type silicon carbide epitaxial layer 2. In other words, the position of the bottom surface of the second conductivity type P + type polycrystalline silicon layer 3 different from the conductivity type of the first conductivity type N-type silicon carbide semiconductor substrate 100 is set to the position of the N-type silicon carbide semiconductor substrate 100. By forming in the groove formed on one main surface and deeper than the bottom surface of the first conductivity type N + type polycrystalline silicon layer 4 having the same conductivity type as that of the N-type silicon carbide semiconductor substrate 100, the reverse When the directional voltage is applied, the depletion layer in N-type silicon carbide epitaxial layer 2 can be expanded more deeply.

  As a result, the distance 52 from the depletion layer end 50 to the N + type polycrystalline silicon layer 4 becomes longer than the distance 51 from the depletion layer end 50 to the P + type polycrystalline silicon layer 3, and the N + type polycrystalline silicon layer 4 The electric field applied to the heterojunction interface with N-type silicon carbide epitaxial layer 2 is reduced, and the electric field can be relaxed. As a result, the withstand voltage when the reverse voltage is applied can be almost equal to that of the P + type polycrystalline silicon layer 3 alone.

  Further, if the impurity density of P + type polycrystalline silicon layer 3 and N + type polycrystalline silicon layer 4 is sufficiently higher than that of silicon carbide epitaxial layer 2, when a reverse voltage is applied, P + type polycrystal silicon layer 3 and N + type polycrystalline silicon layer 4 are formed. It is possible to prevent the depletion layer from extending to the polycrystalline silicon layer side of the crystalline silicon layer 3 and the N + type polycrystalline silicon layer 4. As a result, breakdown can be prevented from occurring in the polycrystalline silicon layer having a low electric field strength causing dielectric breakdown as compared with silicon carbide, and the reverse breakdown voltage can be improved.

  On the other hand, when a voltage is applied in the forward direction, since the N + type polycrystalline silicon layer 4 having a low rising voltage is formed, the rising voltage of the entire heterojunction diode in this embodiment can be lowered. Further, since the P + type polycrystalline silicon layer 3 is also ohmically connected to the anode electrode 5, it acts as a current path when a forward voltage is applied. Here, the heterojunction surface of the P + type polycrystalline silicon layer 3 is in contact with the semiconductor substrate 100 not only at the groove bottom but also at least at a part of the groove side surface, and both the groove bottom and groove side surface. Therefore, a lower on-resistance can be obtained than in the case where the heterojunction surface is formed planarly.

  Further, since P + type polycrystalline silicon layer 3 and N + type polycrystalline silicon layer 4 are in contact with each other, the entire heterojunction interface between both polycrystalline silicon layers and N− type silicon carbide epitaxial layer 2 is the active region. It becomes. Therefore, the current flow is averaged in the heterojunction interface, and a highly reliable semiconductor device can be obtained.

  In the present embodiment, an example in which cathode electrode 6 is formed on the back surface of silicon carbide semiconductor substrate 100 has been described. However, so-called lateral in which cathode electrode 6 is formed on the surface of silicon carbide semiconductor substrate 100 is shown. It may be a type diode.

  In the present embodiment, the case where the number of grooves filled with the P + type polycrystalline silicon layer 3 is five including the peripheral portion as shown in FIG. 1 is shown, but depending on the area of the diode. The number of grooves may be increased or decreased to a desired number of one or more.

  Next, a method for manufacturing the semiconductor device 200 of FIG. 1, that is, the heterojunction diode in the present embodiment will be described with reference to FIGS. Here, FIGS. 2 to 11 are element part cross-sectional structure diagrams illustrating the first to tenth steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

  First, in the first step (semiconductor substrate forming step) in FIG. 2, for example, the semiconductor substrate 100 in which the N− type silicon carbide epitaxial layer 2 is laminated on the N + type silicon carbide substrate 1 is formed. A predetermined mask film 8 and a resist 9 are laminated on the N-type silicon carbide epitaxial layer 2, and then a predetermined pattern for forming one or a plurality of grooves is formed using photolithography or the like. The resist 9 is patterned. As the mask film 8, for example, a silicon nitride film or the like is used.

  Next, in the second step (groove forming step) of FIG. 3, using the resist 9 as a mask, one or more grooves are formed on the first main surface of the N-type silicon carbide epitaxial layer 2. Mask film 8 and N-type silicon carbide epitaxial layer 2 are dry etched. After dry etching, the resist 9 is removed.

  In the next third step of FIG. 4 (the first half step of the electric field relaxation region forming step), in the N− type silicon carbide epitaxial layer 2 that becomes a bonding surface in contact with the peripheral portion of the P + type polycrystalline silicon layer 3 to be formed later. Electric field relaxation region 7 is formed in the region (that is, the region at the bottom of the groove formed in the peripheral portion of N − -type silicon carbide epitaxial layer 2). That is, after the ion implantation mask 11 is formed in the groove of the mask film 8 and the N− type silicon carbide epitaxial layer 2 except for the region where the electric field relaxation region 7 is formed, P type impurity ions 10 such as aluminum and boron are introduced. By implantation, a P-type electric field relaxation region 7 is formed.

  When ion implantation is performed at room temperature, a resist can be used as the ion implantation mask 11. However, when ion implantation is performed while heating the substrate to about 600 ° C. to prevent surface roughness of the substrate, the resist is not a resist. A mask such as a silicon oxide film can be used. In this case, the ion implantation mask 11 needs to enable selective etching with the previously formed mask film 8.

  In the next fourth step of FIG. 5 (second half step of the electric field relaxation region forming step), after removing the ion implantation mask 11, annealing is performed at a high temperature of about 1700 ° C. to activate the introduced impurities. The electric field relaxation region 7 is not limited to the case where a semiconductor having a conductivity type different from that of the semiconductor substrate 100 as described above is used, and a high resistance body or an insulator may be formed. In some cases, the electric field relaxation region 7 may not be formed. In such a case, the steps shown in FIGS. 4 and 5 are omitted.

  Thereafter, in the fifth step of FIG. 6 (the first half step of the second hetero semiconductor region forming step), P + type polycrystalline silicon layer 3 is deposited on the entire surface of mask film 8 and N− type silicon carbide epitaxial layer 2.

In the next sixth step of FIG. 7 (second half step of the second hetero semiconductor region forming step), the P + type polycrystalline silicon layer 3 is etched to form a second hetero semiconductor region until the mask film 8 is exposed. Etching back by dry etching can be used as an etching method, or CMP (Chemical)
A planarization method such as Mechanical Polishing can also be used. As a result, the P + type polycrystalline silicon layer 3 of the second hetero semiconductor region having a different band gap from that of the N − type silicon carbide epitaxial layer 2 of the semiconductor substrate and having a different conductivity type has a bottom surface portion and an N − type carbonized carbon. Not only the bottom surface portion of the groove in silicon epitaxial layer 2 is in contact, but also the side surface portion is formed in contact with at least a part of the side surface portion of the groove in N-type silicon carbide epitaxial layer 2. It will be in the state.

  In the next seventh step of FIG. 8 (first half step of the first hetero semiconductor region forming step), the mask film 8 is removed to expose the first main surface of the N-type silicon carbide epitaxial layer 2 and then exposed. N + type polycrystalline silicon layer 4 is deposited on first main surface of N− type silicon carbide epitaxial layer 2 and P + type polycrystalline silicon layer 3.

  In the next eighth step of FIG. 9 (the second half step of the first hetero semiconductor region forming step), the N + type polycrystalline silicon layer 4 is etched until the P + type polycrystalline silicon layer 3 is exposed, so that the first hetero semiconductor region is etched. Form as. As an etching method, etch back by dry etching can be used, and a planarization method by CMP or the like can also be used. Here, the N + type polycrystalline silicon layer 4, which has a band gap different from that of the N− type silicon carbide epitaxial layer 2 of the semiconductor substrate, but becomes the same conductivity type first hetero semiconductor region, is a P + type polycrystalline silicon layer. 3 may be in a state of covering a part of the groove formed in the first main surface of the N-type silicon carbide epitaxial layer 2 as long as at least a part of the region 3 is exposed.

Furthermore, in the next ninth step (first half step of the first electrode forming step, second electrode forming step) in FIG. 10, the cathode electrode 6 is formed as the second electrode on the back surface of the silicon carbide semiconductor substrate 100. Here, if necessary, the RTA (Rapid) of about 1000 ° C. is used so that the silicon carbide semiconductor substrate 100 and the cathode electrode 6 are in ohmic contact.
Thermal Anneal) is applied.

  Next, the anode electrode 5 is deposited on the polycrystalline silicon layers of both the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4. In addition, as an electrode material of the anode electrode 5 and the cathode electrode 6, titanium, aluminum, or the like is used. At this time, since both the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 are doped with impurities at high density, the polycrystalline silicon layer and the anode electrode 5 are in ohmic contact. It becomes.

  In the last tenth step of FIG. 11 (second half step of the first electrode forming step), a resist pattern is formed on the anode electrode 5 by photolithography. Further, by patterning the anode electrode 5 and the polycrystalline silicon layers of the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 by dry etching using the formed resist as a mask, a semiconductor device as shown in FIG. 200 is finally produced.

  As described in detail above, according to the semiconductor device 200 and the method for manufacturing the same according to the present embodiment, the N + type hetero semiconductor region 4 of the first conductivity type that is the same as the conductivity type of the semiconductor substrate 100 is formed on the semiconductor substrate. For example, a P + type hetero semiconductor region 3 of a second conductivity type different from the conductivity type of the semiconductor substrate 100 is formed in a groove formed in the first major surface of the semiconductor substrate 100. As a result, the rising voltage can be reduced, and the decrease in breakdown voltage can be suppressed. The reason is as follows.

  A groove is formed in the first main surface of the N− type silicon carbide epitaxial layer 2 forming the semiconductor substrate 100, and, for example, P + type polycrystal is formed in the groove as a hetero semiconductor region having a conductivity type different from that of the semiconductor substrate 100. For example, an N + type polycrystalline silicon layer 4 is formed as a hetero semiconductor region having the same conductivity type as that of the semiconductor substrate 100 in a portion where the silicon layer 3 is filled but no groove is formed. In this way, by forming the P + type polycrystalline silicon layer 3 in the groove at a position deeper than the N + type polycrystalline silicon layer 4, the N− type silicon carbide epitaxial layer 2 is formed when a reverse voltage is applied. The depletion layer can be extended deeper. Therefore, the electric field applied to the heterojunction interface between N + type polycrystalline silicon layer 4 and N− type silicon carbide epitaxial layer 2 having a low breakdown voltage is reduced, and the reduction in breakdown voltage at this portion can be suppressed.

  Further, when forward voltage is applied, the anode electrode 5 is connected in parallel to both the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4, so that the N + type polycrystalline silicon layer 4 having a low rising voltage is used. Therefore, the rising voltage of the entire heterojunction diode can be lowered. Further, at the heterojunction interface between the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2 in the groove, not only the groove bottom but also at least a part of the groove side surface is turned on. Therefore, the effective area can be increased and the on-resistance can be reduced.

(Second Embodiment)
Next, a second embodiment of the semiconductor device and the manufacturing method thereof according to the present invention will be described with reference to FIG. FIG. 12 is a cross-sectional view showing a cross-sectional structure of the element portion in the second embodiment of the semiconductor device according to the present invention. As in the first embodiment, the semiconductor device 300 in the present embodiment shown in FIG. 12 uses silicon carbide (SiC) as a substrate material and the hetero semiconductor as polycrystalline silicon. As shown, the connection method between the P + type polycrystalline silicon layer 3 and the anode electrode 5 is different from the semiconductor device 200 of the first embodiment shown in FIG.

  That is, in the semiconductor device 300 of FIG. 12, by forming a contact hole to the P + type polycrystalline silicon layer 3 in the N + type polycrystalline silicon layer 4, the P + type polycrystalline silicon layer 3 and the P + type polycrystalline silicon layer 3 are formed through the contact holes. The anode electrode 5 is connected.

  In the present embodiment, after the steps up to the fourth step in FIG. 5 (the second half step of the electric field relaxation region forming step) in the first embodiment, the fifth and sixth steps in FIG. 6 and FIG. Instead of performing the second hetero semiconductor region forming step), the mask film 8 is removed, and then the P + -type polycrystalline silicon layer 3 is formed so as to fill the groove formed in the N − -type silicon carbide epitaxial layer 2. . Thereafter, instead of the seventh and eighth steps (first hetero semiconductor region forming step) of FIGS. 8 and 9 in the first embodiment, the N + type polycrystalline silicon layer 4 is replaced with the P + type polycrystalline silicon layer 3. And N− type silicon carbide epitaxial layer 2 are stacked on the entire surface, and then a contact hole to P + type polycrystalline silicon layer 3 is formed in N + type polycrystalline silicon layer 4 by photolithography and dry etching.

  That is, in the present embodiment, for example, the N + type polycrystalline silicon layer 4 of the first conductivity type first hetero semiconductor region is only at a position where the groove formed in the N− type silicon carbide epitaxial layer 2 does not exist. It is formed so as to cover the entire surface of N− type silicon carbide epitaxial layer 2 and P + type polycrystalline silicon layer 3 including the position where the groove exists. For this reason, the P + type polycrystalline silicon layer 3 and the anode electrode 5 in the second conductivity type second hetero semiconductor region which are not exposed on the surface and are embedded in the N + type polycrystalline silicon layer 4 are connected. A contact hole is formed in the N + type polycrystalline silicon layer 4.

  The next electrode forming step is substantially the same as the ninth and tenth steps (first electrode forming step, second electrode forming step) of FIGS. 10 and 11 in the first embodiment, but P + type polycrystalline In this embodiment, instead of depositing the anode electrode 5 so as to be in contact with both the silicon layer 3 and the N + type polycrystalline silicon layer 4 and making ohmic contact, the N + type polycrystalline silicon layer 4 is different from the anode electrode 5 in the present embodiment. The anode electrode 5 and the P + type polycrystalline silicon layer 3 are brought into ohmic contact through the contact hole while being deposited so as to be in contact and in ohmic contact.

  By adopting the configuration of the semiconductor device 300 as shown in FIG. 12, it is possible to avoid the entire etch back of the N + type polycrystalline silicon layer 4 as performed in the eighth step of FIG. 9 of the first embodiment. Occurrence of a problem that the N + type polycrystalline silicon layer 4 disappears due to over-etching can be eliminated.

(Third embodiment)
Next, a third embodiment of the semiconductor device and the manufacturing method thereof according to the present invention will be described with reference to FIG. FIG. 13 is a cross-sectional view showing an element section cross-sectional structure in the third embodiment of the semiconductor device according to the present invention. Similarly to the first embodiment and the second embodiment, the semiconductor device 400 in the present embodiment shown in FIG. 13 also uses silicon carbide (SiC) as the substrate material and the hetero semiconductor as polycrystalline silicon. However, as shown in FIG. 13, the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 are formed by ion implantation into the semiconductor region. There is a difference between the form and the second embodiment.

  That is, as a manufacturing method for manufacturing the semiconductor device 400 of FIG. 13, a semiconductor is used instead of the second hetero semiconductor region forming step and the first hetero semiconductor region forming step in the first embodiment and the second embodiment. The semiconductor substrate 100 has a hetero semiconductor region forming step for forming a semiconductor region having a band gap different from that of the semiconductor substrate 100 over the entire first main surface of the substrate 100. Among the semiconductor regions formed on the entire surface, the first main surface of the semiconductor substrate 100 is formed. For example, a P + type polycrystalline silicon layer 3 serving as a second hetero semiconductor region is formed by ion-implanting, for example, a P + type impurity having a conductivity type different from that of the semiconductor substrate in the region where the groove is formed in the surface. Further, for example, an N + type impurity having the same conductivity type as that of the semiconductor substrate is ion-implanted in a region where the groove is not formed in the first main surface, so that the first hetero semiconductor is implanted. It has an ion implantation process for forming the N + -type polycrystalline silicon layer 4 to be a body region.

  FIG. 13 shows that the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 are formed by ion implantation in the case of the layer structure in the semiconductor device 200 of the first embodiment shown in FIG. Although the case is shown, the same can be applied to the case where a contact hole as shown in the semiconductor device 300 of FIG. 12 in the second embodiment is formed in a subsequent process.

  In the configuration of the semiconductor device 400 as shown in FIG. 13, as described above, first, after depositing the polycrystalline silicon layer, the resist patterning by photolithography is performed, so that the P + type and Since the P + type polycrystalline silicon layer 3 and the N + type polycrystalline silicon layer 4 can be formed by ion implantation of N + type impurities separately, the polycrystalline silicon layer can be deposited at a time. And the process can be simplified.

(Fourth embodiment)
Next, a semiconductor device according to a fourth embodiment of the present invention and a manufacturing method thereof will be described. In any of the first to third embodiments described above, the bottom surface at a position where the bottom surface of the groove formed in the first main surface of the semiconductor substrate 100 and the side surface of the groove are in contact with each other. The case where the angle formed by the side surface is a right angle (90 °) has been described. However, the semiconductor device and the manufacturing method thereof according to the present invention are not limited to such a case. For example, as shown in FIG. 14, the angle formed by the bottom surface and the side surface is an obtuse angle (an angle larger than 90 °). The angle may be any angle as long as it is an angle of 90 ° or more, and as shown in FIG. 15, the portion where the bottom surface and the side surface are in contact has an appropriate radius of curvature. It may have a curved surface shape.

  As described above, the shape of the portion where the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2 filled in the groove are in contact with each other is as shown in FIG. By adopting a simple curved surface shape, a leakage current is generated from a position where the bottom surface and the side surface of the groove are in contact with each other when a reverse voltage is applied, and a problem that a desired withstand voltage cannot be obtained is caused. It can be safely avoided.

  FIG. 14 is a cross-sectional view showing an example of a cross-sectional structure of the element portion in the fourth embodiment of the semiconductor device according to the present invention. The bottom surface of the groove formed in the first main surface of the semiconductor substrate 100 and the groove The case where the angle which the said bottom face and the said side surface make in the location which a side surface contacts is an obtuse angle (angle larger than 90 degrees) is shown. That is, as shown in the semiconductor device 500 in FIG. 14, the shape of the portion where the bottom surface and the side surface of the groove are in contact is the angle formed by the bottom surface and the side surface of the groove formed in the first main surface of the semiconductor substrate 100. θ has an inclined surface shape with an obtuse angle (an angle larger than 90 °).

  FIG. 15 is a cross-sectional view showing another example of the cross-sectional structure of the element portion in the fourth embodiment of the semiconductor device according to the present invention. The bottom surface of the groove drilled in the first main surface of the semiconductor substrate 100 This shows a case where the portion where the groove and the side surface of the groove are in contact with each other is a curved surface having an appropriate radius of curvature. That is, as shown in the semiconductor device 600 of FIG. 15, the shape of the portion where the bottom surface and the side surface of the groove formed in the first main surface of the semiconductor substrate 100 are in contact with each other is a curved surface shape having an appropriate curvature radius α. ing. Here, the radius of curvature α in the semiconductor device 600 of FIG. 15 is different from that of the N− type silicon carbide epitaxial layer 2 constituting the semiconductor substrate 100 and the semiconductor substrate 100 at least at the portion where the bottom surface and the side surface of the groove are in contact. Any radius may be used as long as it is larger than the width of electrons tunneling at the heterojunction interface formed by the P + type polycrystalline silicon layer 3 constituting the conductive type second hetero semiconductor region.

  14 and 15, the semiconductor devices 500 and 600 in the present embodiment are both made of silicon carbide (SiC) as the substrate material, as in the first to third embodiments. The inside of the groove formed in the first main surface opposite to the N + type silicon carbide substrate 1 side of the N− type silicon carbide epitaxial layer 2 constituting the semiconductor substrate 100, wherein the hetero semiconductor is polycrystalline silicon. Is filled with the P + type polycrystalline silicon layer 3 as a second hetero semiconductor region having a conductivity type different from that of the semiconductor substrate 100, and is the same as the semiconductor substrate 100 on the first main surface where the groove does not exist. Although the N + type polycrystalline silicon layer 4 is formed as the conductive first hetero semiconductor region, in this embodiment, the shape of the groove filled with the P + type polycrystalline silicon layer 3 is the first shape. Implementation form of It shows a case where different from the groove shape to the third embodiment.

  Hereinafter, the operational effects of the semiconductor devices 500 and 600 having the groove shape as shown in FIGS. 14 and 15 will be described in detail with reference to energy band diagrams.

  FIG. 16 is an energy band diagram showing the energy band state of the heterojunction interface formed between the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2 applied to the semiconductor device according to the present invention. A general energy band state of a heterojunction interface formed between the P + type polycrystalline silicon layer 3 filled in the groove and the N− type silicon carbide epitaxial layer 2 is shown on the bottom surface or side surface of the groove. ing. FIG. 17 is an energy band diagram showing the energy band state of the heterojunction interface formed between the N + type polycrystalline silicon layer 4 and the N− type silicon carbide epitaxial layer 2 applied to the semiconductor device according to the present invention. A general energy band state of a heterojunction interface formed between the N + type polycrystalline silicon layer 4 and the N− type silicon carbide epitaxial layer 2 on the first main surface of the N− type silicon carbide epitaxial layer 2. Show.

  As shown in FIG. 16, the built-in voltage between P + type polycrystalline silicon layer 3 and N− type silicon carbide epitaxial layer 2 forming heterojunction interfaces of different conductivity types is large, and energy barrier height 60 is high. When the reverse voltage is applied, the width 61 of the built-in depletion layer formed in the N-type silicon carbide epitaxial layer 2 is large, and the reverse breakdown voltage can be increased as described above. On the other hand, as shown in FIG. 17, the built-in voltage between the N + type polycrystalline silicon layer 4 and the N− type silicon carbide epitaxial layer 2 forming the heterojunction interface of the same conductivity type is small, and the energy barrier height 62 On the other hand, when the forward voltage is applied, the on-resistance can be kept low. On the other hand, when the reverse voltage is applied, the width 63 of the built-in depletion layer formed in the N-type silicon carbide epitaxial layer 2 is It becomes small and the reverse breakdown voltage is low.

  FIG. 18 is an energy band diagram showing an example of the energy band state of the heterojunction interface in the first to third embodiments of the semiconductor device according to the present invention. As in the first to third embodiments, FIG. An example of the energy band state of the heterojunction at a position where the bottom surface and the side surface of the groove are in contact with each other when the angle between the bottom surface and the side surface of the groove is a right angle (90 °) is shown.

  That is, as shown in FIG. 18, when the angle formed between the bottom surface and the side surface of the groove filled with the P + type polycrystalline silicon layer 3 is a right angle (90 °), the portion where the bottom surface contacts the side surface Depending on the combination of the impurity density of the P + type polycrystalline silicon layer 3 and the impurity density of the N + type polycrystalline silicon layer 4, there is a difference between the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2. Although the height 64 of the energy barrier formed at the heterojunction interface can maintain the same height as the height 60 of the energy barrier in the case of FIG. 16, when a reverse voltage is applied, N The width 65 of the built-in depletion layer formed in the -type silicon carbide epitaxial layer 2 becomes narrow, and there is a possibility that the reverse breakdown voltage when applying the reverse voltage is lowered.

  Therefore, as shown in the semiconductor device 500 of FIG. 15 and the semiconductor device 600 of FIG. 16, is the groove structure adopted a structure having an inclined surface with an angle θ formed by the bottom surface and the side surface of at least 90 ° or more? Alternatively, at least at a location where the bottom surface and the side surface of the groove are in contact with each other, a radius of curvature α that is larger than the width at which electrons tunnel through the heterojunction interface formed by the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2. 18 is adopted as the height of the energy barrier formed at the heterojunction interface between the P + type polycrystalline silicon layer 3 and the N− type silicon carbide epitaxial layer 2. The width of the built-in depletion layer is suppressed from becoming as narrow as the width 65 of the built-in depletion layer shown in FIG. 18 while maintaining the energy barrier height 64 shown in FIG. It becomes possible. Thus, when a reverse voltage is applied, a phenomenon in which a leak current is generated from a position where the bottom surface and the side surface of the groove are in contact with each other and a desired breakdown voltage cannot be obtained can be prevented more reliably.

It is sectional drawing which shows the element part sectional structure in 1st Embodiment of the semiconductor device by this invention. It is an element part section structure figure explaining the 1st process of the manufacturing method of the semiconductor device in a 1st embodiment of the present invention. It is element part sectional structure drawing explaining the 2nd process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is an element part section structure figure explaining the 3rd process of the manufacturing method of the semiconductor device in a 1st embodiment of the present invention. It is element | device part cross-section figure explaining the 4th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element part sectional structure drawing explaining the 5th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element part sectional structure drawing explaining the 6th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element | device part cross-section figure explaining the 7th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element | device part cross-section figure explaining the 8th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element part cross-section figure explaining the 9th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is element | device part cross-section figure explaining the 10th process of the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the element part sectional structure in 2nd Embodiment of the semiconductor device by this invention. It is sectional drawing which shows the element part sectional structure in 3rd Embodiment of the semiconductor device by this invention. It is sectional drawing which shows an example of the element part sectional structure in 4th Embodiment of the semiconductor device by this invention. It is sectional drawing which shows the other example of element part sectional structure in 4th Embodiment of the semiconductor device by this invention. It is an energy band figure which shows the energy band state of the heterojunction interface formed between the P + type polycrystalline silicon layer and N-type silicon carbide epitaxial layer which are applied to the semiconductor device by this invention. It is an energy band figure which shows the energy band state of the heterojunction interface formed between the N + type polycrystalline silicon layer and N- type silicon carbide epitaxial layer which are applied to the semiconductor device by this invention. It is an energy band figure which shows an example of the energy band state of the heterojunction interface in the 1st thru | or 3rd embodiment of the semiconductor device by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... N + type silicon carbide substrate, 2 ... N- type silicon carbide epitaxial layer, 3 ... P + type polycrystalline silicon layer, 4 ... N + type polycrystalline silicon layer, 5 ... Anode electrode, 6 ... Cathode electrode, 7 ... Electric field relaxation Area 8 ... Mask film 9 ... Resist 10 ... Impurity ion 11 ... Ion implantation mask 50 ... Depletion layer edge 51 ... Distance between P + type polycrystalline silicon layer and depletion layer edge 52 ... N + type polycrystalline silicon Distance between layer and depletion layer edge, 60, 62, 64 ... energy barrier height, 61, 63, 65 ... built-in depletion layer width, 100 ... silicon carbide semiconductor substrate, 200, 300, 400, 500, 600 ... semiconductor apparatus.

Claims (23)

A semiconductor substrate of a predetermined conductivity type, a hetero semiconductor region that is in contact with the first main surface of the semiconductor substrate and has a band gap different from that of the semiconductor substrate, and a first semiconductor connected to the hetero semiconductor region And a second electrode connected to the semiconductor substrate, the hetero semiconductor region includes a first hetero semiconductor region having the same conductivity type as the semiconductor substrate, and the semiconductor substrate. The first hetero semiconductor region and the second hetero semiconductor region are both ohmically connected to the first electrode and heterogeneous to the semiconductor substrate. And the first hetero semiconductor region is formed on the first main surface of the semiconductor substrate, and the second hetero semiconductor region is formed in front of the semiconductor substrate. Formed in the drilled groove on the first main surface, further, a semiconductor device which is characterized in that in contact with each other and the said first hetero semiconductor region second hetero semiconductor regions.   2. The semiconductor device according to claim 1, wherein a conductivity type of the semiconductor substrate is an N-type conductivity type. The second hetero semiconductor region formed in the groove formed in the first main surface of the semiconductor substrate is not only the bottom surface of the second hetero semiconductor region, but also the side surfaces of the second hetero semiconductor region. at least also in part, the semiconductor device according to claim 1 or 2, characterized in that in contact with the semiconductor substrate. Wherein said groove is formed in said first major surface of the semiconductor substrate is, according to any one of claims 1 to 3, characterized in that it is present in one or a plurality of positions of the first major surface Semiconductor device. Bottom and the bottom surface and the angle and forms a side of the portion where the side surface is in contact of the groove of the groove, the semiconductor device according to any one of 4 to claims 1, characterized in that at least 90 ° or more. The shape of the portion where the bottom surface of the groove and the side surface of the groove are in contact is at least greater than the width at which charge tunnels through the energy barrier at the heterojunction interface formed by the second hetero semiconductor region and the semiconductor substrate at the portion. the semiconductor device according to any one of 5 claims 1, characterized in that a curved surface having a large radius of curvature. The first electrode is formed so as to be in contact with both the first hetero semiconductor region and the second hetero semiconductor region, thereby providing an ohmic connection to the first hetero semiconductor region and the second hetero semiconductor region. the semiconductor device according to any one of claims 1 to 6, characterized in that it is. The first electrode is formed so as to be in contact with the first hetero semiconductor region and is ohmically connected to the first hetero semiconductor region, and via a contact hole formed in the first hetero semiconductor region. Te, semiconductor device according to any one of claims 1 to 6, characterized in that it is the second hetero semiconductor region and the ohmic contact. The impurity density of the first hetero semiconductor region and the second hetero semiconductor region are both semiconductor device according to any one of claims 1 to 8, wherein the higher than the impurity density of the semiconductor substrate. The electric field of the second electrode applied to the junction between the semiconductor substrate and the hetero semiconductor region is applied to at least a part of the lower layer of the groove formed in the first main surface of the semiconductor substrate. the semiconductor device according to any one of claims 1, characterized in that the electric field relaxation region to relax is formed 9. The semiconductor device according to claim 10 , wherein the electric field relaxation region is formed of any one of a semiconductor having a conductivity type different from that of the semiconductor substrate, a high resistance body, and an insulator. The material of the semiconductor substrate, silicon carbide, gallium nitride or semiconductor device according to any one of claims 1 to 11, characterized in that it consists of one of the diamond. The material of the first hetero semiconductor region and / or the second hetero semiconductor region is any one of single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, or amorphous silicon germanium. claims 1, wherein the semiconductor device according to any one 12 of the. The material of the first hetero semiconductor region and / or the second hetero semiconductor region is any one of single crystal germanium, polycrystalline germanium, amorphous germanium, single crystal gallium arsenide, polycrystalline gallium arsenide, or amorphous gallium arsenide. claims 1, wherein the semiconductor device according to any one 12 of the.   A semiconductor substrate forming step for forming a semiconductor substrate by epitaxially growing a semiconductor region on the substrate, and one or more grooves are formed by etching the first main surface of the semiconductor substrate using a predetermined mask film. Forming a second hetero semiconductor region having a band gap different from that of the semiconductor substrate and having a conductivity type different from that of the semiconductor substrate, in the groove of the semiconductor substrate. And forming a first hetero semiconductor region having a band gap different from that of the semiconductor substrate and having the same conductivity type as that of the semiconductor substrate on the first main surface of the semiconductor substrate on which the groove is not formed. A first hetero semiconductor region forming step, a second electrode forming step of forming a second electrode connected to the semiconductor substrate, the first hetero semiconductor region and the The method of manufacturing a semiconductor device characterized by having a first electrode forming step of forming a first electrode connected to a two hetero semiconductor region.   A semiconductor substrate forming step for forming a semiconductor substrate by epitaxially growing a semiconductor region on the substrate, and one or more grooves are formed by etching the first main surface of the semiconductor substrate using a predetermined mask film. Forming a second hetero semiconductor region having a band gap different from that of the semiconductor substrate and having a conductivity type different from that of the semiconductor substrate, in the groove of the semiconductor substrate. A band gap different from that of the semiconductor substrate, not only on the first main surface where the groove of the semiconductor substrate is not formed, but also on the second hetero semiconductor region, and After forming the first hetero semiconductor region of the same conductivity type, a contact hole for connecting the first electrode to the second hetero semiconductor region is formed on the first hetero semiconductor region. (B) forming a first hetero semiconductor region in the semiconductor region; forming a second electrode to form a second electrode connected to the semiconductor substrate; and forming an ohmic connection on the first hetero semiconductor region. And a first electrode forming step of forming a first electrode in ohmic contact with the second hetero semiconductor region through the contact hole formed in the first hetero semiconductor region. Device manufacturing method.   A semiconductor substrate forming step for forming a semiconductor substrate by epitaxially growing a semiconductor region on the substrate, and one or more grooves are formed by etching the first main surface of the semiconductor substrate using a predetermined mask film. A groove forming step, a hetero semiconductor region forming step in which a semiconductor region having a band gap different from that of the semiconductor substrate is formed on the entire surface of the first main surface of the semiconductor substrate, and among the semiconductor regions formed on the entire surface, In the region where the groove is formed in the first main surface, an impurity having a conductivity type different from that of the semiconductor substrate is ion-implanted to form the second hetero semiconductor region, and in the first main surface, An ion implantation step for forming the first hetero semiconductor region by ion-implanting an impurity having the same conductivity type as that of the semiconductor substrate in the region where the groove is not formed, A second electrode forming step of forming a second electrode connected to the semiconductor substrate; a first electrode forming step of forming a first electrode connected to the first hetero semiconductor region and the second hetero semiconductor region; A method for manufacturing a semiconductor device, comprising: 18. The impurity density of the second hetero semiconductor region and the impurity density of the first hetero semiconductor region are both higher than the impurity density of the semiconductor substrate. 18 . A method for manufacturing a semiconductor device. The electric field of the second electrode applied to the junction between the semiconductor substrate and the hetero semiconductor region is applied to at least a part of the lower layer of the groove formed in the first main surface of the semiconductor substrate. 19. The method of manufacturing a semiconductor device according to claim 15 , further comprising an electric field relaxation region forming step of forming an electric field relaxation region to be relaxed. The method of manufacturing a semiconductor device according to claim 19 , wherein the electric field relaxation region is formed of any one of a semiconductor having a conductivity type different from that of the semiconductor substrate, a high resistance body, or an insulator. 21. The method of manufacturing a semiconductor device according to claim 15 , wherein any one of silicon carbide, gallium nitride, and diamond is used as a material for the semiconductor substrate. As the material of the second hetero semiconductor region and / or the first hetero semiconductor region, any of single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, or amorphous silicon germanium is used. The method for manufacturing a semiconductor device according to claim 15 , wherein the method is a semiconductor device manufacturing method. The material of the second hetero semiconductor region and / or the first hetero semiconductor region is any one of single crystal germanium, polycrystalline germanium, amorphous germanium, single crystal gallium arsenide, polycrystalline gallium arsenide, and amorphous gallium arsenide. The method for manufacturing a semiconductor device according to claim 15 , wherein the method is a semiconductor device manufacturing method.

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