JP5257110B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to a semiconductor test apparatus that performs a test involving destruction of an object when a defect occurs.

In a semiconductor device test, a screening test involving the destruction of an object is performed when a defect occurs.
Examples of screening tests involving the destruction of an object include a switching test, an RBSOA (Reverse Biased Safe Operating Area) test, an L load (inductive load) avalanche test, and a load short circuit test.

In such a screening test, in order to reduce the amount of damage to the subject when a defect occurs, the following semiconductor test apparatus has been conventionally used.
FIG. 6 is a diagram showing a circuit configuration of a conventional semiconductor test apparatus.

Here, a circuit configuration when performing an inductive load switching test on the subject 50 is shown.
The subject 50 is, for example, a semiconductor module including a transistor such as an IGBT (Insulator Gate Bipolar Transistor), a semiconductor package, a wafer, or a chip.

  The semiconductor test apparatus includes a power supply unit 61, an interruption switch unit 62, a charge / discharge snubber circuit 63, a load coil 64, protective freewheeling diodes (FWD) 65 and 66, a gate resistor 67, and a gate driver 68. Have. FIG. 6 further shows the floating inductances 69a and 69b of the circuit caused by wiring and the like.

The power supply unit 61 includes a DC power supply 61a that supplies a power supply voltage Vcc and a power supply stabilization capacitor 61b.
The cutoff switch unit 62 includes a semiconductor switch 62a such as an IGBT, a gate resistor 62b, and a gate driver 62c.

  The charge / discharge type snubber circuit 63 includes a diode 63a and a capacitor 63b connected in series between the collector and emitter of the semiconductor switch 62a. A snubber resistor 63c is connected between the anode and cathode of the diode 63a.

  In the inductive load switching test, a DC voltage is applied to the circuit by the power supply unit 61, a rectangular wave switching pulse is input to the gate electrode of the subject 50 via the gate resistor 67 by the gate driver 68, and the subject 50 is switched. (On / off).

  Here, when the subject 50 is destroyed, in order to prevent the subsequent destruction of the subject 50, the gate driver 62c of the blocking switch unit 62 turns off the semiconductor switch 62a immediately after the destruction is detected or at a predetermined timing. Then, the power source 61 and the subject 50 are separated.

However, at this time, a surge voltage is generated by the load coil 64 and the floating inductances 69a and 69b of the circuit, but the destruction of the subject 50 is prevented by the protective FWDs 65 and 66 and the surge absorbing snubber circuit 63. . As a prior art relating to a semiconductor test apparatus using such a snubber circuit, for example, the one described in Patent Document 2 is known.

  In addition, in order to suppress the surge voltage at the time of turn-off of switching elements, such as IGBT, the semiconductor module which incorporated the discharge prevention snubber circuit is known (for example, refer patent document 1, nonpatent literature 1).

  However, in a conventional semiconductor test apparatus that tests a semiconductor module as the subject 50, a charge / discharge type snubber circuit 63 having a high surge absorption effect as shown in FIG. 6 is used.

Japanese Patent Laid-Open No. 10-136637 JP-A-5-333089

Fuji Electric Device Technology Co., Ltd., “Fuji IGBT Module Application Manual”, p. 5-8-5-11, [online], February 2004, [Search September 17, 2008], Internet <URL: http://www.fujielectric.co.jp/fdt/scd/pdf/ RH984 / RH984.pdf>

However, in the conventional semiconductor test apparatus using the charge / discharge type snubber circuit 63, the following continuous current flows through the circuit after the semiconductor switch 62a is turned off.
FIG. 7 is an example of a continuous current flowing through the semiconductor test apparatus of FIG.

  The solid line arrow indicates the charging current Ia that flows through the circuit until the capacitor 63b of the charge / discharge snubber circuit 63 is charged after the semiconductor switch 62a is turned off. A dotted arrow indicates the regenerative current Ib due to the floating inductance 69a.

  If the voltage across the capacitor 63b immediately before the turn-off is Vs1, the voltage across the capacitor 63b after the turn-off is completed is Vs2, and the capacitance is Cs, the charge amount Q that flows as the charging current Ia is Q = Cs (Vs2-Vs1). )

  Vs2 is substantially equal to the power supply voltage Vcc. Vs1 is Von when the ON voltage of the semiconductor switch 62a is Von and the forward voltage of the diode is VF, but the voltage Vs1 = Von−VF, but Von and VF are usually several V or less. Compared with the power supply voltage Vcc (usually several tens of volts to several thousand volts) at the time of the test, it is very small. Therefore, the amount of charge flowing as the charging current Ia is Q≈Cs × Vcc.

FIG. 8 is a diagram showing a change in the collector current Ic of the subject before and after the subject destruction.
The vertical axis is the collector current Ic [A], and the horizontal axis is the time t [μs]. When destruction of the subject 50 occurs at time tb, the semiconductor switch 62a is turned off, but the collector current Ic does not immediately become zero due to the continuous current such as the charging current Ia and the regenerative current Ib in FIG.

Due to such a continuous current, there is a problem that damage to the subject 50 is enlarged and test electrodes such as probes and stages of the test circuit are damaged.
Similar problems occur in screening tests that require the provision of a semiconductor switch for interruption, such as the RBSOA test, the L load avalanche test, and the load short circuit test in addition to the inductive load switching test described above.

  In view of the above points, the present inventors have an object to provide a semiconductor test apparatus capable of suppressing damage to a subject due to continuous current and damage to a test circuit after destruction of the subject.

  In order to achieve the above object, a semiconductor test apparatus having the following configuration is provided. The semiconductor test apparatus is provided between a power supply unit and a subject, and absorbs a surge voltage generated when the semiconductor switch is turned off, and a semiconductor switch that cuts off a current flowing through the subject when the subject is destroyed. A discharge-preventing snubber circuit.

  It is possible to reduce the damage to the subject due to the continuous current after the destruction of the subject and the damage to the test circuit.

It is a figure which shows the circuit structure of the semiconductor test apparatus of 1st Embodiment. It is a figure which shows the modification of the semiconductor test apparatus of 1st Embodiment. It is a figure which shows the change by the resistance value of the resistor 29 of test condition dVce / dt. It is a figure which shows the effect of attenuation | damping of the continuous current by having applied the semiconductor test apparatus of 1st Embodiment. It is a figure which shows the circuit structure of 2nd Embodiment semiconductor test equipment. It is a figure which shows the circuit structure of the conventional semiconductor test apparatus. It is an example of the continuous current which flows into the semiconductor test apparatus of FIG. It is a figure which shows the change of the collector current Ic of the test object before and after a test object destruction.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a circuit configuration of the semiconductor test apparatus according to the first embodiment.
Here, a circuit configuration when performing an inductive load switching test on the subject 10 is shown.

The subject 10 is, for example, a semiconductor chip such as an IGBT, a wafer that is an assembly thereof, a semiconductor module, or a semiconductor package.
The semiconductor test apparatus according to the first embodiment is configured to flow a current induced by a power supply unit 21, a cutoff switch unit 22, a discharge blocking snubber circuit 23, a load coil 24, a load coil 24, and a floating inductance. And a protective FWD 25 and a protective FWD 26 for regenerating and attenuating energy stored in the load coil 24 and stray inductance, a gate resistor 27, a gate driver 28, and a resistor 29.

Note that FIG. 1 further illustrates the floating inductances 30a and 30b of the circuit, which are caused by wiring and the like.
The power supply unit 21 has a DC power supply 21a and a capacitor 21b for stabilizing the power supply.

  The blocking switch unit 22 is between the subject 10 and the positive electrode of the power supply unit 21 and blocks the current flowing through the subject 10 when the subject 10 is destroyed. The cutoff switch unit 22 includes a semiconductor switch 22a, a gate resistor 22b, and a gate driver 22c. The semiconductor switch 22a is an IGBT, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), or the like. Below, it demonstrates as IGBT. The gate driver 22c is connected to the emitter of the semiconductor switch 22a, and is connected to the gate of the semiconductor switch 22a via the gate resistor 22b. 22a is turned off.

  The discharge preventing snubber circuit 23 has a capacitor 23a and a diode 23b connected in series, and these are connected between the collector and emitter of the semiconductor switch 22a. Further, a node between the capacitor 23a and the anode of the diode 23b is connected to the negative electrode side of the DC power supply 21a via the snubber resistor 23c. According to such a discharge prevention snubber circuit 23, the surge voltage generated at the time of turn-off is absorbed, and the continuous current after the turn-off can be reduced as will be described later.

The load coil 24 is connected between the emitter of the semiconductor switch 22 a and the subject 10. Used as load for inductive load switching test.
The protective FWD 25 is connected in parallel to the load coil 24 and prevents back electromotive force caused by the load coil 24 when the semiconductor switch 22a is turned off.

  The protective FWD 26 is connected in parallel with the series circuit of the load coil 24 and the subject 10, the cathode is connected between the emitter of the semiconductor switch 22 a and the load coil 24, and the subject 10 and the DC power source 21 a are connected. An anode is connected to the negative electrode side. The protective FWD 26 suppresses a surge voltage due to the floating inductance 30a of the circuit.

  The resistor 29 is inserted at an arbitrary position on the path connecting the protective FWD 26, the load coil 24, and the subject 10. In the semiconductor test circuit of FIG. 1, the case where it is connected in series to the protective FWD 26 is shown. The role of the resistor 29 will be described later.

The gate driver 28 controls the gate voltage supplied to the subject 10 through the gate resistor 27 to turn on or off the subject 10.
The operation of the semiconductor test apparatus according to the first embodiment will be described below.

  In the inductive load switching test, a DC voltage is applied to the circuit by the DC power source 21a, a rectangular wave switching pulse is input to the subject 10 via the gate resistor 27 by the gate driver 28, and the subject 10 is switched (ON / OFF). Off).

  During the test (before destruction of the subject 10), the semiconductor switch 22a is in an on state. At this time, the negative electrode of the capacitor 23a of the snubber circuit 23 is connected to the negative electrode of the DC power supply 21a via the snubber resistor 23c. Assuming that the power supply voltage in a steady state is Vcc and the voltage across the capacitor 23a is Vs, the capacitor 23a and the snubber resistor 23c constitute a time constant circuit. Immediately after the start, Vs = Vcc. Usually, the power supply voltage Vcc at the time of the test is several tens of volts to several thousand volts, and both ends of the capacitor 23a are charged with this power supply voltage.

  Next, when the gate driver 22c of the cutoff switch unit 22 detects the end of the test of the subject 10 or the destruction of the subject 10, the semiconductor switch 22a is turned off. At this time, a surge voltage in which the voltage induced by the floating inductances 30a and 30b of the circuit is superimposed on the power supply voltage Vcc is applied to both ends of the semiconductor switch 22a. However, since the power supply voltage is almost charged in the capacitor 23a of the snubber circuit 23, the current flowing through the snubber circuit 23 is suppressed.

  If the capacitance of the capacitor 23a is Cs and the surge voltage generated at both ends of the semiconductor switch 22a is Vce, only a current having a charge amount determined by Q = Cs × (Vce−Vcc) flows to the snubber circuit 23.

This charge amount is significantly smaller than the charge amount Q≈Cs × Vcc flowing after turn-off in the case where the charge / discharge type snubber circuit 63 shown in FIG. 6 is used.
For example, if Vcc = 800V and the peak value of the surge voltage generated at both ends of the semiconductor switch 22a is Vce = 900V, the charge-type snubber circuit 63 is used when the discharge-blocking snubber circuit 23 is used. It is possible to reduce the amount of charge to about 1/8 compared with the case where the

  That is, the amount of charge transfer until the completion of charging can be greatly reduced, and the continuous current can be reduced. That is, the current can be interrupted at high speed. In the case where the subject 10 is a bare chip, it is particularly useful because high-speed current interruption is required.

On the other hand, the continuous current (regenerative current) due to the floating inductances 30a and 30b due to circuit wiring and the like is determined by the energy E = 1/2 × Ls × Ic ² accumulated in the floating inductances 30a and 30b. Here, Ls is an inductance value of the floating inductances 30a and 30b, and Ic is a test current flowing in the circuit before the semiconductor switch 22a is turned off.

  With this energy, a continuous current flows when the semiconductor switch 22a is turned off after the subject 10 is destroyed or at the end of the test. In the semiconductor test apparatus of the present embodiment, the resistor 29, the protective FWD 26, the load coil 24, and the subject 10 are connected in order to prevent damage to the subject 10 or destruction of the test electrode due to the continuous current. It is inserted at an arbitrary position on the connecting path. Thereby, a continuation current can be attenuate | damped rapidly and the damage expansion of the subject 10 and the damage of a test electrode can be suppressed.

  In the inductive load switching circuit, the L load avalanche test circuit, and the load short circuit test circuit, depending on the connection position of the resistor 29, the test conditions and test quality may be affected.

FIG. 2 is a diagram illustrating a modification of the semiconductor test apparatus according to the first embodiment.
FIG. 3 is a diagram showing a change in the test condition dVce / dt depending on the resistance value of the resistor 29 in the semiconductor test apparatus of FIG. The vertical axis represents dVce / dt [kV / μs], and the horizontal axis represents the resistance value [Ω].

  In the semiconductor test apparatus of FIG. 2, a resistor 29 for attenuating the continuous current due to the floating inductances 30 a and 30 b is connected to a path connecting the load coil 24, the subject 10, and the positive electrode of the power supply unit 21. Assuming that the voltage on both sides of the subject 10 is Vce, dVce / dt when the subject 10 is turned off, which is one of the test conditions, varies depending on the resistance value of the resistor 29 as shown in FIG. Therefore, when it is not desired to change the test conditions, the resistor 29 is connected in series with the protective FWD 26 connected in parallel with the subject 10 as shown in FIG. Can be avoided.

FIG. 4 is a diagram illustrating the effect of attenuation of the continuous current due to the application of the semiconductor test apparatus according to the first embodiment.
The horizontal axis represents the resistance value [Ω] of the resistor 29, and the vertical axis represents the value obtained by integrating the square of the continuous current I with time.

  A black square plot shows the characteristics of the semiconductor test apparatus according to the first embodiment using the discharge-blocking snubber circuit 23. For comparison, the characteristics in the case of using a charge / discharge type snubber circuit are indicated by circles, and the characteristics in the case of using only the resistor 29 without using the snubber circuit are indicated by white square plots.

  Multiplying the value on the vertical axis by the resistance value of the subject 10 after destruction yields energy. Assuming that this resistance value is constant, the energy flowing to the subject 10 by the continuous current can be significantly reduced by using the discharge-blocking snubber circuit 23 as compared with the case of using the charge / discharge snubber circuit.

  For example, in the case where a discharge blocking snubber circuit 23 is used and a 5Ω resistor 29 is used rather than a 0.1Ω resistor 29 using a charge / discharge type snubber circuit, FIG. As described above, the energy flowing to the subject 10 after the subject 10 is destroyed can be reduced to about 1/5.

Thereby, the damage expansion of the subject 10 and the damage of the test electrode can be suppressed.
Next, a semiconductor test apparatus according to a second embodiment will be described.
FIG. 5 is a diagram illustrating a circuit configuration of the semiconductor test apparatus according to the second embodiment.

The same components as those in the first embodiment shown in FIG.
In the semiconductor test apparatus of the second embodiment, the snubber circuit 23 is not provided, and the bidirectional Zener diode in which the Zener diodes 31a and 31b are connected in the reverse direction is connected to the gate of the semiconductor switch 22a and the terminal on the high potential side (for example, In the case of N-channel IGBT, the collector is connected, and in the case of N-channel MOSFET, the drain is connected.

  In such a semiconductor test apparatus, the gate driver 22c of the cutoff switch unit 22 turns off the semiconductor switch 22a when detecting the end of the test of the subject 10 or the destruction of the subject 10. At this time, a surge voltage is generated at both ends of the semiconductor switch 22a, but when the surge voltage exceeds the Zener voltage of the connected Zener diodes 31a and 31b, the semiconductor switch 22a is turned on and the surge is absorbed.

  In the semiconductor test apparatus of the second embodiment, by using the bidirectional Zener diode, the charging current does not flow to the capacitor after the destruction of the subject 10 as in the case of using the snubber circuit 23. The current can be reduced. Also, the continuous current caused by the floating inductance 30a can be quickly attenuated by inserting the resistor 29 at an arbitrary position on the path connecting the protective FWD 26, the load coil 24, and the subject 10.

Thereby, the expansion of the destruction of the subject 10 and the destruction of the test electrode can be suppressed.
As described above, the semiconductor test apparatus according to the first and second embodiments has been described by taking the case of performing an inductive load switching test as an example, but also when performing a screening test such as an L load avalanche test and a load short circuit test. The same applies.

  Further, if the influence of the surge voltage can be suppressed by applying the protective FWD 26 or the semiconductor switch 22a having a sufficient withstand voltage against the generated surge voltage, the snubber circuit 23 and the bidirectional Zener diode are not provided. Only the resistor 29 may be provided. When only the resistor 29 is used, as shown by the white square plot in FIG. 4, the energy flowing to the subject 10 after the semiconductor switch 22a is turned off can be greatly reduced. Can prevent damage.

10, 50 Test object 21, 61 Power supply unit 21a, 61a DC power supply 21b, 61b Capacitor 22, 62 Shut-off switch unit 22a, 62a Semiconductor switch 22b, 27, 62b, 67 Gate resistance 22c, 28, 62c, 68 Gate driver 23 , 63 Snubber circuit 23a, 63b Capacitor 23b, 63a Diode 23c, 63c Snubber resistance 24, 64 Load coil 25, 65 Protection freewheeling diode (FWD) that regenerates and attenuates the energy of the load coil
26,66 Protection freewheeling diode (FWD) that regenerates and attenuates the energy of stray inductance
29 Resistor 30a, 30b, 69a, 69b Floating inductance

Claims (2)

In semiconductor test equipment that performs tests involving the destruction of an object,
A semiconductor switch provided between a power supply unit and the subject, and shuts off a current flowing through the subject when the subject is destroyed;
A discharge-blocking snubber circuit that absorbs a surge voltage generated when the semiconductor switch is turned off;
A semiconductor test apparatus characterized by comprising: A load connected between the subject and the semiconductor switch;
A freewheeling diode connected in parallel to the load and the subject;
The semiconductor test apparatus according to claim 1, further comprising a resistor inserted in a path connecting the subject, the load, and the freewheeling diode.

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