JP5245225B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A plasma display device using a typical plasma display panel (hereinafter simply abbreviated as “panel”) as an image display panel has a wide viewing angle, is easy to enlarge, is self-luminous, and has an image display quality. Is becoming the mainstream of large-screen image display devices.

  In the panel, a large number of discharge cells are formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged to face each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed, and a discharge gas containing, for example, xenon is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  The plasma display device displays an image by controlling each of these discharge cells independently and selectively discharging and emitting light. These discharges are stably controlled by applying drive voltage waveforms having many voltage values to the scan electrodes, sustain electrodes, and data electrodes.

  The plasma display device includes an image signal processing circuit, various control circuits, an electrode drive circuit for driving each electrode of the panel, and a power supply circuit for supplying power to these circuit blocks. This power supply circuit supplies a number of power supplies such as an image signal processing circuit, a power supply for driving various control circuits, and a power supply having various voltage values for generating discharge to supply power to each circuit block. Yes.

Such a power supply circuit is usually provided with various protection circuits for safely stopping the operation of the apparatus when any abnormality occurs during the operation of the plasma display apparatus. For example, Patent Document 1 describes an example of a protection circuit that detects the destruction of a component and turns off the power, and Patent Document 2 can destroy the control circuit even if a part of the power circuit fails. No power supply is disclosed.
JP 2004-45816 A JP 2005-143155 A

  Any of these power supply circuits described above detects an abnormality, stops the output of the power supply, and stops the operation of the image display device when any trouble occurs in the plasma display device. However, depending on the type of defect, it is not always necessary to stop the operation, and even if there is a problem such as a slight decrease in image display quality, it may be desirable to be able to display an image if safety can be ensured.

  The plasma display device of the present invention has been made in view of the above problems, and an object of the present invention is to provide a plasma display device capable of ensuring safety even when an image is displayed for a minor defect. .

The present invention relates to a panel having scan electrodes, sustain electrodes, and data electrodes, a scan electrode drive circuit that applies a drive voltage waveform to the scan electrodes, a sustain electrode drive circuit that applies a drive voltage waveform to the sustain electrodes, and a scan electrode A plasma display device including a power supply circuit that supplies power to each of a drive circuit and a sustain electrode drive circuit, wherein a ramp waveform voltage that increases in voltage is applied to a scan electrode and 0V is maintained in an initialization period After that, a ramp waveform voltage whose voltage drops is applied to the scan electrode and the first voltage is applied to the sustain electrode, and the voltage in which the second voltage is superimposed on the first voltage is maintained in the address period The power supply circuit is configured to generate a plurality of voltages to be supplied to the scan electrode drive circuit or the sustain electrode drive circuit, and one end of the sustain electrode drive circuit is first It is connected to the sustain electrode through the first switching element is connected to a power supply unit for generating a voltage, with the other end connected to a power supply unit for generating a second voltage via a second switching element A capacitor grounded via a third switching element; in the initialization period, the capacitor is charged with the first voltage while the first voltage is applied to the sustain electrode; By applying a second voltage to the first electrode, a voltage obtained by superimposing the second voltage on the first voltage is applied to the sustain electrode, and the power supply circuit applies the second voltage to the sustain electrode via a thermistor having a positive temperature characteristic. It is characterized by being configured to supply to the driving circuit. With this configuration, it is possible to provide a plasma display device that can ensure safety even when an image is displayed for a minor problem.

  According to the present invention, it is possible to provide a plasma display device capable of ensuring safety even when an image is displayed for a minor problem.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a structure of panel 10 according to the embodiment of the present invention. On the front substrate 21 made of glass, a plurality of display electrode pairs 28 made up of the scan electrodes 22 and the sustain electrodes 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 cross each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 28 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of plasma display device 100 using panel 10 in accordance with the exemplary embodiment of the present invention. The plasma display device 100 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit that supplies necessary power to each circuit block. 60.

  The image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each circuit block. Scan electrode drive circuit 53 applies drive voltage waveforms having a plurality of voltage values to each of scan electrodes SC1 to SCn based on the timing signal to drive each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 54 applies drive voltage waveforms having a plurality of voltage values to sustain electrodes SU1 to SUn based on the timing signal to drive sustain electrodes SU1 to SUn.

  The power supply circuit 60 supplies several low voltage voltages to the image signal processing circuit 51 and the timing generation circuit 55, in this embodiment, 5V, 15V, and -15V. The data electrode driving circuit 52 is supplied with a voltage Vd (approximately 70 V) for generating an address pulse. The scan electrode drive circuit 53 and the sustain electrode drive circuit 54 are supplied with a plurality of voltages having various voltage values as will be described in detail later. In the present embodiment, the scan electrode drive circuit 53 includes a voltage Vs (approximately 180V), a voltage Vi2 (approximately 400V), a voltage Va (approximately −100V), a voltage Vi4 (approximately voltage Va + 5V), and a voltage Vc (approximately voltage Va + 100V). ), And the sustain electrode drive circuit 54 is supplied with a voltage Vs (approximately 180 V), a voltage Ve1 (approximately 120 V), and a voltage ΔVe (approximately 5 V).

  Next, a driving voltage waveform for driving the panel and its operation will be described. The subfield method is used as a method for driving the panel. In this method, one field period is divided into a plurality of subfields, and gradation display is performed by controlling light emission / non-light emission of each discharge cell in each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent address operation are formed. In the address period, a scan pulse is sequentially applied to the scan electrodes and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes to perform address discharge, thereby selectively forming wall charges. In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the display luminance to be emitted is applied between the scan electrode and the sustain electrode, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged and emitted. .

  FIG. 4 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the exemplary embodiment of the present invention. FIG. 4 shows driving voltage waveforms in two subfields, but driving voltage waveforms in other subfields are substantially the same.

  In the first half of the initializing period of the first subfield, 0 V is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the scan electrodes SC1 to SCn have a discharge start voltage lower than the sustain electrodes SU1 to SUn. A ramp waveform voltage that gradually rises from the voltage Vi1 toward the voltage Vi2 exceeding the discharge start voltage is applied. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like. In the present embodiment, voltage Vi1 is equal to voltage Vs described later.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn receive a discharge start voltage from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. A ramp waveform voltage that gently falls toward the exceeding voltage Vi4 is applied. During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The In the present embodiment, the voltage Vi3 is also equal to the voltage Vs described later.

  As the drive voltage waveform in the initialization period, as shown in the initialization period of the second subfield in FIG. 4, only the voltage waveform in the latter half of the initialization period may be applied. Initializing discharge is selectively generated in the discharge cells that have undergone sustain discharge in the sustain period of the subfield.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Here, the voltage Ve2 is a voltage obtained by superimposing the voltage ΔVe on the voltage Ve1.

  Next, the voltage Va is applied as a negative scan pulse to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm. A voltage Vd is applied as a positive write pulse. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (Vd−Va). Addition exceeds the discharge start voltage, and discharge occurs between the data electrode Dk and the scan electrode SC1. This discharge triggers the discharge between sustain electrode SU1 and scan electrode SC1. Thus, address discharge occurs, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk.

  Here, the reason why the voltage Ve2 higher by ΔVe than the voltage Ve1 applied to the sustain electrodes SU1 to SUn in the latter half of the initialization period is applied to the sustain electrodes SU1 to SUn is generated between the data electrode Dk and the scan electrode SC1. This is to help the discharged discharge progress to the discharge between scan electrode SC1 and sustain electrode SU1. As a result, the writing operation can be more reliably generated and the image display quality can be improved.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row of scan electrode SCn, and the address period ends.

  In the subsequent sustain period, first, voltage Vs is applied as a positive sustain pulse to scan electrodes SC1 to SCn, and 0 V is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. And the discharge start voltage is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 V is applied to scan electrodes SC1 to SCn, and voltage Vs is applied to sustain electrodes SU1 to SUn as a sustain pulse. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a potential difference is applied between the electrodes of the display electrode pair, so that the address discharge is performed in the address period. The sustain discharge is continuously performed in the discharge cell that has caused the failure.

  At the end of the sustain period, a so-called narrow pulse-like potential difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on the electrode SCi and the sustain electrode SUi is erased. Thus, the maintenance operation in the maintenance period is completed.

  The operation of the subsequent subfield is substantially the same as the operation of the first subfield, and thus description thereof is omitted.

  Next, power supply circuit 60 and sustain electrode drive circuit 54 will be described. FIG. 5 is a circuit block diagram of power supply circuit 60 in the embodiment of the present invention. The power supply circuit 60 includes a primary side rectification unit 62, a low voltage power supply unit 64, a high voltage power supply unit 66, and a sub power supply unit 72. The primary side rectifier 62 rectifies and smoothes the commercial AC 100V power supply. The low-voltage power supply unit 64 has a multi-output switching regulator configuration, and generates 5V, 15V, and -15V voltages mainly supplied to the image signal processing circuit 51, the timing generation circuit 55, and the control circuit portions of other circuit blocks. Each of the circuits that generate these voltages is provided with a normal protection circuit that detects an overcurrent and limits the output current. The high-voltage power supply unit 66 also has a multi-output switching regulator configuration, and generates various types of voltages to be supplied to the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54. Specifically, in this embodiment, the voltages Vd, Vs, voltage Vi2, voltage Va, voltage Vi4, voltage Vc, and voltage Ve1 are generated. Each of the circuits that generate these voltages is also provided with a normal protection circuit that detects an overcurrent and limits the current. The sub power supply unit 72 generates a new voltage based on some of the voltages generated by the low voltage power supply unit 64 and the high voltage power supply unit 66. In the present embodiment, sub power supply unit 72 generates voltage ΔVe based on voltage 15 V generated by low voltage power supply unit 64.

  Sustain electrode drive circuit 54 includes sustain pulse generator 59 for generating a sustain pulse in the sustain period, and Ve voltage generator 74 for generating voltage Ve1 and voltage Ve2 applied in the initialization period and the address period. I have.

  FIG. 6 is a circuit diagram of sub power supply unit 72 of power supply circuit 60 and Ve voltage generation unit 74 of sustain electrode drive circuit 54 in the embodiment of the present invention. The sub power supply unit 72 includes a thermistor (hereinafter abbreviated as “positive characteristic thermistor”) R721 connected to the 15V line generated by the low voltage power supply unit 64, and two transistors Q721 and Q722. Current buffer B 721, variable resistor R 722 connected to the input of current buffer B 721 for determining the voltage value of voltage ΔVe, and capacitor C 721 connected to the output of current buffer B 721 for stabilizing the voltage.

  With such a configuration, the variable resistor R722 divides the voltage 15V to generate the voltage ΔVe, and the current is amplified by the current buffer B721. Therefore, the sub power supply unit 72 operates as a power supply of the voltage ΔVe. A regulator IC or the like that generates a reference voltage may be used instead of the variable resistor R722.

  The Ve voltage generation unit 74 includes a backflow prevention diode D741 connected to the voltage Ve1 generated by the high voltage power supply unit 66, a switching element Q741 and a switching element Q742 that output the voltage Ve1 via the diode D741, and a first terminal. Capacitor C741 connected to the cathode side of diode D741, switching element Q743 that grounds the second terminal of capacitor C741, and switching element Q744 that connects voltage ΔVe to the second terminal of capacitor C741.

  In this configuration, in the latter half of the initialization period, the switching elements Q741 and Q742 are turned on, whereby the voltage Ve1 is applied to the sustain electrodes SU1 to SUn via the diode D741 and the switching elements Q741 and Q742. At this time, switching element Q743 is turned on, and voltage Ve1 is charged in capacitor C741. Next, in the writing period, the switching element Q743 is turned off and the switching element Q744 is turned on. Then, the voltage ΔVe is applied to the second terminal of the capacitor C741. At this time, since the voltage Ve1 is charged in the capacitor C741, the voltage at the first terminal of the capacitor C741 becomes the voltage Ve2 in which the voltage ΔVe is superimposed on the voltage Ve1, and this voltage Ve2 is switched to the sustain electrodes SU1 to SUn. The voltage is applied via elements Q741 and Q742.

  As described above, the sustain electrode drive circuit 54 applies the voltage Ve1 that is the first voltage to the sustain electrodes SU1 to SUn in the initialization period, and also applies the voltage ΔVe that is the second voltage to the first voltage in the address period. The superimposed voltage Ve2 is applied to the sustain electrodes SU1 to SUn.

  In this configuration, it is assumed that an overcurrent flows for some reason when the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. Then, the current flowing through the positive temperature coefficient thermistor R721 of the sub power supply unit 72 increases. Since the power consumed by the positive temperature coefficient thermistor R721 increases in proportion to the square of the current, the temperature of the positive temperature coefficient thermistor R721 suddenly rises, and the resistance value of the positive temperature coefficient thermistor R721 increases and the positive temperature coefficient thermistor The current flowing through R721 is limited. Therefore, since the 15V power supply itself does not become an overcurrent, the voltage of the 15V power supply does not decrease, and there is no fear that the control circuit or the like that operates using this power supply will malfunction. Of course, the voltage applied to the sustain electrodes SU1 to SUn is lower than the voltage Ve2, but when the voltage drops to the voltage Ve1, the diode D741 becomes conductive and the voltage Ve1 is supplied. In this state, since the voltage Ve1 is applied to the sustain electrodes SU1 to SUn instead of the voltage Ve2, the address discharge becomes somewhat unstable, but the plasma display device can continuously display images. . When the overcurrent is large and the voltage Ve1 also decreases, the protection circuit of the power supply circuit 60 detects the overcurrent of the voltage Ve1 and safely stops the output of the power supply.

  As described above, according to the plasma display device in the present embodiment, even if an overcurrent flows for some reason when the voltage Ve2 is applied to the sustain electrodes SU1 to SUn during the address period, images are continuously displayed. It can be displayed and safety can be ensured.

  In the present embodiment, as the positive temperature coefficient thermistor R721, a thermistor having a resistance value of about 10Ω during normal operation and about 500Ω during overcurrent is used. However, the specification of the positive temperature coefficient thermistor is not limited to this, and it is desirable to select a thermistor having an optimal characteristic according to the current value to be limited in consideration of the panel characteristics and the circuit configuration.

  Note that a circuit for monitoring the voltage Ve2 may be further added to detect a decrease in the voltage Ve2 and notify the abnormality.

  In the present embodiment, the sub power supply unit 72 has been described as generating the voltage ΔVe. However, for example, the sub power supply unit 72 may be configured to generate a voltage (Vi4−Va) in addition to the voltage ΔVe.

  The plasma display device of the present invention is useful as an image display device using a panel because it can ensure safety even when an image is displayed for a minor defect.

The disassembled perspective view which shows the structure of the panel in embodiment of this invention Electrode arrangement of the panel Circuit block diagram of plasma display device using the panel Drive voltage waveform diagram applied to each electrode of the panel Circuit block diagram of the power supply circuit of the plasma display device Circuit diagram of sub power supply unit and Ve voltage generation unit of same plasma display device

Explanation of symbols

10 Panel (Plasma Display Panel)
DESCRIPTION OF SYMBOLS 21 Front substrate 22 Scan electrode 23 Sustain electrode 28 Display electrode pair 31 Back substrate 32 Data electrode 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 59 Sustain pulse generation part 60 Power supply Circuit 62 Primary side rectification unit 64 Low voltage power supply unit 66 High voltage power supply unit 72 Sub power supply unit 74 Ve voltage generation unit 100 Plasma display device SC1 to SCn Scan electrode SU1 to SUn Sustain electrode D1 to Dm Data electrode R721 (positive characteristic) thermistor R722 Variable resistor B721 Current buffer D741 Diode C721, C741 Capacitor Q741, Q742, Q743, Q744 Switching element

Claims (1)

A plasma display panel having scan and sustain electrodes and data electrodes;
A scan electrode drive circuit for applying a drive voltage waveform to the scan electrode;
A sustain electrode drive circuit for applying a drive voltage waveform to the sustain electrode;
A plasma display device comprising a power supply circuit for supplying power to each of the scan electrode drive circuit and the sustain electrode drive circuit,
In the initialization period, a ramp waveform voltage that increases in voltage is applied to the scan electrode and 0 V is applied to the sustain electrode, and then a ramp waveform voltage that decreases in voltage is applied to the scan electrode and the first voltage is applied. Is applied to the sustain electrode, and in the address period, a voltage obtained by superimposing a second voltage on the first voltage is applied to the sustain electrode,
The power supply circuit is configured to generate a plurality of voltages to be supplied to the scan electrode drive circuit or the sustain electrode drive circuit,
The sustain electrode driving circuit has one end connected to the power supply unit that generates the first voltage and is connected to the sustain electrode via a first switching element, and the other end connected to the second switching element. A capacitor connected to a power supply unit that generates the second voltage and grounded via a third switching element; and during the initialization period, while applying the first voltage to the sustain electrode The capacitor is charged with the first voltage, and a voltage obtained by superimposing the second voltage on the first voltage is applied to the other end of the capacitor during the writing period. Applied to the sustain electrode,
The plasma display apparatus, wherein the power supply circuit is configured to supply the second voltage to the sustain electrode driving circuit via a thermistor having a positive temperature characteristic.

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