JP5229474B2 - Image processing system and program - Google Patents

Description

  The present invention relates to an image processing system and a program.

  Japanese Patent Application Laid-Open No. 2004-228561 describes a configuration for detecting a transmission error by preparing a mode for transmitting a test signal in a configuration for transmitting a digital image signal.

Japanese Patent Laid-Open No. 2002-237853

  An object of the present invention is to provide a technique for inspecting whether or not there is an abnormality in all paths during transmission of image data in transmission of image data using a plurality of paths.

  The invention according to claim 1 is a data generation means for generating a plurality of transmission data including image data and detection data for detecting abnormal transmission of the image data, and a plurality of the transmission data. Conversion processing means for performing a conversion process for transmitting in parallel divided into paths, and in the plurality of generations, the data generation means determines the position of the detection data on the data array in the transmission data. According to another aspect of the present invention, there is provided an image processing system that performs a process of setting different positions according to the output timing of the transmission data.

The invention according to claim 2 is a program that is read and executed by a computer, and the computer has a plurality of transmission data including image data and detection data for detecting abnormal transmission of the image data. When generating the data once, a process of changing the position of the detection data on the data array of the transmission data to a different position according to the generation timing of the transmission data, and dividing the transmission data into a plurality of paths in parallel And a process for transmitting data to the program.

  According to the first aspect of the present invention, in the transmission of image data using a plurality of paths, there is provided a technique for inspecting whether or not there is an abnormality in all the paths when transmitting the image data.

According to the second aspect of the present invention, in the transmission of image data using a plurality of paths, there is provided a program for inspecting whether or not there is an abnormality in all the paths when transmitting the image data.

(1) First embodiment
(Constitution)
FIG. 1 is a block diagram showing an example of an image processing system using the invention. FIG. 1 shows an image processing system 1. The image processing system 1 has a configuration in which the image processing apparatus 100 and the image forming apparatus 200 are connected by an 8ch transmission line 300.

(Configuration of image processing apparatus)
The image processing apparatus 100 includes an image processing circuit 101, a transmission data generation circuit 102, and a serialization driver 103. The image processing circuit 101 converts image data received via a line such as a LAN (for example, document data created by document creation software) into a data format handled by the image forming apparatus 200 and various corrections. Process. In this example, the image processing circuit 101, based on the received image data, image data of four colors Y (yellow), M (magenta), C (cyan), and K (black) (8 bits × 4 = 32 bits). The tag data (3 bits × 4 = 12 bits) of the image data of each basic color, VCLK (1 bit) which is a basic clock, and Vlid (Lsync (line synchronization signal)) (1 bit) for ensuring the synchronization of the line data. , 46-bit data is output. The image processing circuit 101 includes a buffer memory that buffers image data during and after processing.

  The transmission data generation circuit 102 adds 2-bit data to the 46-bit data output from the image processing circuit 101. The 2-bit data is test data for detecting a transmission error of 1ch included in the 8ch transmission line 300. As this test data, a predetermined test pattern is used. As a result, the transmission data generation circuit 102 outputs 48-bit data. The transmission data generation circuit 102 has a function of rearranging the position of the 48-bit data. This example has a function of rearranging 48-bit data every cycle (one clock). This rearrangement method is determined in advance. The transmission data generation circuit 102 includes a buffer memory that buffers image data.

  The serialization driver 103 is a dedicated integrated circuit that converts the 48-bit data output from the transmission data generation circuit 102 into a data format suitable for transmission on the 8ch transmission line 300.

  The image processing apparatus 100 includes a control computer 104. The control computer 104 controls the overall operation of the image processing apparatus 100 and each unit. The control computer 104 includes a CPU, a RAM, a ROM, and an interface function for executing operations described later.

(Configuration of 8ch transmission line)
The 8ch transmission line is a connection wiring having an 8ch signal transmission line. The 8ch transmission line is composed of a parallel transmission cable, a serial transmission cable, an optical cable, or the like.

(Image forming device)
The image forming apparatus 200 has a function of forming an image on a recording material such as paper and outputting the recording material as an image output form. The image forming apparatus 200 includes a deserialization receiver 201, a check circuit 202, and an image forming apparatus 203.

  The deserialization receiver 201 is a dedicated integrated circuit having a function opposite to that of the serialization driver 103. The deserialized receiver 201 and the serialized driver 103 are manufactured as a set.

  The check circuit 202 separates 46-bit data related to image data and 2-bit data for error detection from the 48-bit data output from the deserialization driver 201, and further separates the separated 2-bit data for error detection. Error determination processing based on The check circuit 202 stores data relating to how data is rearranged in the transmission data generation circuit 102, separates test data from the 48-bit data output from the deserialization driver 201, and inputs the data to the transmission data generation circuit 102. The 46-bit data of the previous stage is reproduced. In addition, when an error is determined, the check circuit 202 returns a signal requesting the image processing apparatus 100 to retransmit the line data in which the error is detected, to the image processing apparatus 100 again.

  The image forming apparatus 200 includes a control computer 204. The control computer 204 controls the overall operation of the image forming apparatus 200 and each unit. The control computer 204 includes a CPU, a RAM, a ROM, and an interface function for executing operations described later.

(Example of operation)
Hereinafter, an example of an operation for detecting a transmission abnormality in the 8ch transmission line in the system of FIG. 1 will be described. FIG. 2 is a flowchart illustrating an example of a processing procedure. In FIG. 2, the left flow is a process executed in the image processing apparatus 100, and the right flow is a process executed in the image forming apparatus 200. Here, the program for executing the flow on the left side is stored in the control computer 104 and executed by the control computer 104. A program for executing the flow on the right side is stored in the control computer 204 and executed by the control computer 204. The processing in each step is performed in each corresponding circuit.

  Here, an example of the operation will be described by taking as an example the case of transmitting image data of one page. When the image processing is performed in the image processing apparatus 100 and image data to be stored in the image forming apparatus 100 is prepared in the buffer memory of the image processing circuit 101, the transmission process shown in FIG. 2 is started (step S201). When the processing is started, image data for one page processed by the image processing circuit 101 is prepared (step S202). This data consists of 8 bits for each basic color image data of YMCK, 3 bits for each tag data, such as attributes of the image data for each basic color, CLK and Valid. The basic unit is a total of 46 bits of data.

  The 46-bit data is sent to the transmission data generation circuit 102. In the transmission data generation circuit 102, 2-bit test data is added to obtain 48-bit data (step S203). Next, a process of rearranging the 48-bit position input to the serialization driver 103 is performed (step S204).

  This rearrangement is performed as follows. First, for the first 48-bit data input to the serialization driver 103, 46-bit image data is arranged at positions 1 to 46 in the data string, and test data is arranged at the remaining positions on the 47-48 data. Then, in the next 48-bit data, 46-bit image data is arranged at positions on data 2 to 47, and test data is arranged at positions on the remaining 48 to 1 data. Further, in the next 48-bit data, 46-bit image data is arranged at positions on the 3-48 data, and test data is arranged at the remaining positions on the 1-2 data.

  By sequentially performing this processing procedure, the position of the test data in the 48-bit data string input to the serialization driver 103 is sequentially shifted. That is, the position of the test data on the data string is not fixed and is shifted for each data string.

  The serialization driver 103 converts the data in which the positions of the test data are sequentially shifted to a data format for transmitting the 8ch transmission line 300 (step S205). That is, a data format conversion process for allocating 48-bit data to an 8-channel transmission path is performed. The converted data is buffered in the buffer memory as data for each page (step S206) and output to the 8ch transmission line 300 (step S207).

  Here, since the data transmitted through the 8-channel transmission line 300 has the test data position on the 48-bit data string sequentially shifted for each data string, the test data is determined according to the time position difference of the clock. The channel for transmitting is different. For this reason, by continuing the data transmission, it is possible to transmit the test data to all 8 channels, although not simultaneously.

  Data transmitted from the image processing apparatus 100 via the 8ch transmission line 300 is received by the derealization receiver 201 of the image forming apparatus 200 (step S208). The received data is deserialized (that is, converted into a state output from the transmission data generation circuit 102) in the deserialization receiver 201 (step S209).

  The deserialized data is sent to the check circuit 202, and the reverse process of the rearrangement process performed in the transmission data generation circuit 102 is performed. As a result of this processing, 48-bit data obtained by adding the test data 2 bits to the 46-bit data output from the image processing circuit 101 is reproduced (step S210). Since the check circuit 202 performs processing on the premise of the processing in the transmission data generation circuit 102, the position of the test data on the data string is known in the check circuit 202. Based on this information, 2-bit test data is separated from the 48-bit data (step S211). One page of the image data from which the test data is separated is buffered in the buffer memory (step S212).

  The check circuit 202 stores the test data pattern as reference data, and the reference data is compared with the test data sent from the image processing apparatus 100 (step S213). If the two data match, it is determined that there is no error in data transmission, and the image data is output to the image forming apparatus 203 (step S214). In this case, the image data transmission process according to the process shown in FIG. 2 ends (step S215). If there is image data for the next page and after, the same processing is repeated.

  If it is determined in step S213 that the two data do not match, the process advances to step S216 to determine whether or not the data retransmission request is the third time. If the request for data retransmission is the third time, it is determined that a transmission error has occurred, and an error notification is performed (step S218). When the error notification is executed, an error notification output is output from the check circuit 202, an error message is displayed on a display unit (not shown) of the image forming apparatus 200, and the image forming process in the image forming apparatus 203 is stopped. The process is performed, and the transmission process ends (step S215). In step S216, if the data transmission request is the first or second time, the data is requested to be retransmitted (step S217), and the process returns to the previous stage of step S206 and is buffered on the image processing apparatus 100 side. Data (page data) is retransmitted.

  FIG. 3 is a conceptual diagram showing an example of the state of the data array in the above-described example. FIG. 3 conceptually shows an arrangement state of 48-bit data transmitted in one cycle (one clock). FIG. 3 conceptually shows an arrangement state of transmission data in the 3rd cycle from the Nth cycle to the N + 2th cycle. Here, the dot pattern portion is test data, and the other portion is 46-bit image data. In this example, as shown in the figure, the position of the test data on the data string is shifted every cycle.

  Data at positions indicated by numerals 1 to 48 is distributed to each transmission line of the 8ch transmission line in the serialization driver 103. At this time, as shown in FIG. 3, since the position of the test data is different according to the clock, when viewed in a range of a plurality of cycles, the test data is transmitted through the first transmission line in a certain cycle, In another cycle, test data is transmitted through the second transmission line, and so on, the transmission line through which the test data is transmitted is switched. Thereby, it is possible to transmit test data on all the transmission lines of 8ch and to check whether there is an abnormality in the transmission state.

  According to the example described above, a certain amount of data can be obtained by transmitting test data and changing the position of the test data using the 2-bit free capacity secured in the transmission capacity per pixel. When transmission is performed, all transmission paths are checked. That is, not only a specific transmission channel but also the transmission state of all transmission channels is checked. Also, the transmission of the test signal for checking is performed at the same timing as the transmission of the image data, not in the dedicated mode for the checking operation. For this reason, it is not necessary to perform a test-dedicated operation.

(2) Second Embodiment In this embodiment, checksum data is transmitted using the empty 2 bits in the first embodiment. However, since the data capacity for the checksum is insufficient in 2 bits, the checksum of the image data (46 bits × N) for N cycles / clock is calculated in advance on the sending side, and each 2 bits of data for N cycles. The chuck sum data is transmitted. On the receiver side, 2 bits × N checksum data is acquired from N cycles of data, and error detection of N cycles of image data is performed.

  A specific example will be described below. In this case, the transmission data generation circuit 102 of FIG. 1 includes a four-stage buffer, and calculates a checksum for data of image data (46 bits × 4) of data transmission 4 cycles / VCLK. Then, the checksum value (data) is composed of 2 bits × 4 data, and the 2 bits × 4 checksum data is distributed 2 bits at a time to 48 bits data of each cycle. In other words, when the 2-bit chuck sum data pieces of each cycle are collected for 4 cycles and arranged in order, a checksum for the data of 4 data transmission / VCLK image data (46 bits × 4) is obtained.

  The check circuit 202 on the image forming apparatus 200 side also includes a four-stage buffer similar to the transmission data generation circuit 102. The check circuit 202 separates the chuck sum data (2 bits in each cycle) from the data of 4 cycles / VCLK, and obtains the check sum value obtained by the transmission data generation circuit 102 of the image data of 4 cycles / VCLK. Then, the chuck sum value is calculated from the received image data (4 × 46 bits) of 4 cycles / VCLK and compared with the transmitted check sum value.

  By this processing, data corruption (transmission error) is detected. In this example, if a transmission error occurs in any of the 8ch transmission lines, it affects the checksum value, so that it is possible to monitor abnormalities in all transmission paths. In this embodiment, when an error is detected, the image processing apparatus 100 may be requested to retransmit data in units of lines or pages. In this case, a buffer memory having a necessary capacity is arranged in the image processing apparatus 100 and the image forming apparatus 200.

  FIG. 4 is a conceptual diagram showing an example of the state of the data array in the above-described example. FIG. 4 conceptually shows an arrangement state of 48-bit data transmitted in one cycle (one clock). FIG. 4 conceptually shows the arrangement state of transmission data in the 4th cycle from the Nth cycle to the N + 3th cycle. Here, the dot pattern portion is checksum data, and the other portion is 46-bit image data.

  In this example, the checksum value of the image data for 4 cycles is divided into 4 times using the data transfer of 4 cycles using the capacity of 2 bits of the last part of the data string of each cycle. Divided and transmitted. In FIG. 3, the check circuit 202 separates the test data allocated to each 2-bit capacity from the transmission data of the Nth cycle, the N + 1th cycle, the N + 2th cycle, and the N + 3th cycle, and the 8-bit checksum from them. An example of calculating the value data of is conceptually shown.

  The concept of this embodiment can also be applied to a parity check method or a CRC method. In this case, the number of cycles to be prefetched (the number N described above) is selected according to the capacity of the necessary test data (check code). For example, in the CRC system, N = 8 is selected.

(3) Third Embodiment In this embodiment, an example will be described in which a transmission error is detected when there is no empty transmission data. In this case, in the transmission data generation circuit of FIG. 1, a check pattern is added for each line data (data for one row constituting an image). At this time, test data is transmitted by using a data capacity for Valid (for 1 bit per cycle) for ensuring line synchronization. However, since the capacity as test data cannot be secured in one cycle, N-bit data capacity for N cycles (for example, 4 cycles) is secured, and test data relating to one line data is added to the line data using the data capacity.

  On the image forming apparatus 200 side, the check circuit 202 reproduces the test data from the valid data for N cycles and compares it with the test data stored in advance. Based on the result of this comparison, the presence / absence of an error in the line data is determined. Various processes associated with the error determination are the same as those in the first embodiment.

(4) Fourth Embodiment In this embodiment, the transmission data generation circuit of FIG. 1 calculates a checksum for each line data (one line of data constituting an image), and calculates the result of the line data. Finally, it is added in a data capacity of one cycle (48 bits = 6 bytes). On the image forming apparatus 200 side, the check circuit 202 calculates the checksum value of the image data, and compares the result with the added checksum value. As a result, error determination is performed to determine whether there is a transmission error. Various processes associated with the error determination are the same as those in the first embodiment.

(Other)
The transmission line is not limited to 8ch, but may be a plurality of channels. The program for the operation may be stored in an external server or the like and supplied from there through a line, or may be supplied through an appropriate storage medium.

  The present invention can be used in a system for forming an image such as printing.

It is a conceptual diagram which shows an example of the image processing system using invention. 3 is a flowchart showing an example of a processing procedure in data transmission in the image processing system of FIG. 1. It is a conceptual diagram which shows notionally the arrangement | sequence state of the data transmitted. It is a conceptual diagram which shows notionally the arrangement | sequence state of the data transmitted.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus, 200 ... Image forming apparatus, 300 ... 8ch transmission line.

Claims (2)

Data generating means for generating a plurality of transmission data including image data and detection data for detecting abnormal transmission of the image data;
Conversion processing means for performing a conversion process for dividing the transmission data into a plurality of paths and transmitting them in parallel;
In the plurality of generations, the data generation means
An image processing system that performs processing for changing the position of the detection data on the data array in the transmission data according to the output timing of the transmission data. A program that is read and executed by a computer,
On the computer,
When generating transmission data including image data and detection data for detecting an abnormality in transmission of the image data a plurality of times, the position of the detection data on the data array of the transmission data is determined as the transmission data. Processing to be different positions according to the generation timing of
A program for dividing the transmission data into a plurality of paths and transmitting the data in parallel.

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