JP5228553B2 - Clock signal divider circuit and method - Google Patents

Description

  The present invention relates to a circuit technique, and more particularly to a frequency dividing circuit technique for dividing a clock signal by an arbitrary rational division ratio.

  In a clock signal dividing circuit that divides and divides a clock signal having a lower frequency from a clock signal having an arbitrary frequency, the division ratio, that is, the frequency of the clock signal before dividing and the frequency of the clock signal after dividing is divided. A frequency dividing circuit (integer frequency dividing circuit) having a frequency ratio of 1 / M (M is an integer) can be easily realized by using a counter.

  On the other hand, there has been proposed a frequency dividing circuit capable of frequency division even if the frequency dividing ratio is a rational number consisting of N / M (N is a positive integer and M is a positive integer larger than N) (for example, Patent Document 1, (See Patent Document 2). According to these related techniques, the value N that sets the numerator of the division ratio is cumulatively added for each cycle of the input clock signal, and the addition result becomes larger than the value M that sets the denominator of the division ratio. In such a case, rational number division is realized by performing an operation of subtracting M from the addition result and appropriately masking (thinning out) clock pulses of the input clock signal with reference to the addition result.

  As a related technique, a clock generation circuit using a phase interpolator has been proposed (see, for example, Patent Document 3). According to the technique described in Patent Document 3, a rational frequency divided clock signal having a constant cycle time can be generated by generating an edge at a timing other than the edge of the input clock signal by the phase interpolation circuit.

Japanese Patent Laying-Open No. 2005-45507 JP 2006-148807 A JP 2002-57578 A

  Since the clock signal frequency dividing circuits described in Patent Document 1 and Patent Document 2 realize frequency division by selectively masking the pulses of the input clock signal, the timing of pulse output of the frequency-divided clock signal is The pulse timing of the input clock signal is limited. As a result, there is a problem that the cycle time of the divided clock signal changes greatly from cycle to cycle. Further, since the minimum value of the cycle time does not decrease in proportion to the frequency division ratio, there is a problem that the restriction on the maximum delay of the circuit driven by the frequency-divided clock signal cannot be relaxed according to the frequency. In particular, since the cycle time does not increase when the frequency division ratio is 1 to 1/2, for dynamic frequency voltage control (DVFS: Dynamic Voltage Frequency Scaling) that controls the voltage according to the cycle time to reduce power However, there is a problem that it cannot be applied to the clock generation.

With reference to FIG. 17, a specific example of a problem in rational frequency division according to the related technique will be described. FIG. 17 is a timing chart showing the rational number division result according to the related art. Here, an output clock signal obtained by dividing the input clock signal (8/8) by a frequency division ratio of 7/8 to 1/8 is shown.
As can be seen from FIG. 17, in the division ratio 7/8 to 5/8 corresponding to the division ratio of 1 to 1/2, the minimum value of the cycle time of the divided clock signal is one cycle of the input clock signal. There is a problem that it does not increase according to the frequency division ratio. Further, when the division ratio is 3/8, the minimum value of the cycle time of the divided clock signal is two cycles of the input clock signal, and there is a problem that it does not increase according to the division ratio.

  Further, for example, when the division ratio is 5/8, the maximum value of the cycle time of the divided clock signal is two cycles of the input clock signal. Therefore, there is a problem that the cycle time of the divided clock signal varies for each cycle between 1 and 2 cycles of the input clock signal. For example, when the frequency division ratio is 3/8, the maximum value of the cycle time of the divided clock signal is three cycles of the input clock signal. Therefore, there is a problem that the cycle time of the divided clock signal fluctuates every cycle for 2 to 3 cycles of the input clock signal.

  In addition, since the clock signal frequency dividing circuits described in Patent Literature 1 and Patent Literature 2 do not have a function of adjusting the phase of the frequency-divided clock signal, the clock signal is compensated when the clock skew with other clock signals is compensated. It is necessary to insert a buffer circuit for skew compensation in the distribution circuit. However, when the amount of clock skew is large, many buffer circuits for skew adjustment are required, which increases the area and power cost. In addition, since the delay amount of the buffer circuit cannot be adjusted during operation, when using Dynamic Voltage and Frequency Scaling (DVFS) technology that controls the voltage according to the cycle time to reduce power For example, there is a problem that it is not possible to change the power supply voltage during operation.

  On the other hand, the clock signal frequency dividing circuit described in Patent Document 3 can generate a rational frequency divided clock signal having a constant cycle time by the phase interpolation circuit, and the phase interpolation circuit is a relatively low frequency input clock signal. For example, when an input clock signal having a frequency of 500 MHz or less is frequency-divided, a large capacity is required. Therefore, there is a problem that power consumption and layout area are large and noise is weak. Further, there is a problem that a dedicated design is required for the analog circuit and the design / verification cost is high.

  The present invention is for solving such a problem, and can suppress variation in the cycle time of the output clock signal divided by a rational number without requiring a large circuit scale, and can also reduce the phase of the output clock signal at the time of frequency division. An object of the present invention is to provide a clock signal frequency dividing circuit and method capable of adjusting the frequency.

  In order to achieve such an object, the clock signal frequency dividing circuit according to the present invention is based on a frequency dividing ratio defined by N / M (N is a positive integer, M is a positive integer larger than N). A clock signal frequency dividing circuit that generates an output clock signal obtained by dividing an input clock signal by N / M, and outputs the clock pulse of the input clock signal as it is without being inverted or inverted based on the input control signal Output and masked output, and select and execute an output operation to generate an output clock signal, and a division ratio for each cycle of the input clock signal The phase calculation value indicating the phase relationship between the reference frequency-divided clock signal and the input clock signal having a constant cycle time corresponding to the input clock signal is calculated. A clock selection control circuit that generates a control signal for instructing an output operation for generating a clock signal close to the phase of the lock signal and outputs the control signal to the clock selection circuit. The clock selection control circuit is provided for each cycle of the input clock signal. The phase calculation value indicating the phase relationship between the reference clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and the phase is determined according to the phase adjustment signal indicating the phase control for the output clock signal. A phase calculation circuit that increases or decreases the value of the calculated value, and determines whether or not to output the clock pulse of the input clock signal to the output clock signal based on the phase calculated value, and selects the control signal according to the determination result as the clock Based on the clock output determination circuit that outputs to the circuit and the phase calculation value, the clock pulse of the input clock signal is output as it is without being inverted. Either, to determine whether to output the inverted, and a clock phase determination circuit for outputting a control signal corresponding to the determination result to the clock selection circuit.

  In addition, another clock signal frequency dividing circuit according to the present invention is configured to convert the input clock signal to N / M based on a frequency division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N). A clock signal frequency dividing circuit for generating an output clock signal divided by M, based on the input control signal, whether the clock pulse of the input clock signal is output as it is non-inverted or inverted and output; A clock selection circuit that generates an output clock signal by selecting and executing one of the output operations of masking and not outputting, and a constant cycle time corresponding to the division ratio for each cycle of the input clock signal The phase calculation value indicating the phase relationship between the reference frequency-divided clock signal having the input frequency and the input clock signal is calculated. Based on the phase calculation value, the phase of the reference frequency-divided clock signal in the output operation is approximated. A clock selection control circuit that generates a control signal instructing an output operation for generating a clock signal and outputs the control signal to the clock selection circuit. The clock selection control circuit repeatedly counts the input clock signal for M cycles. A counter circuit that outputs a count value corresponding to the cycle, and a table circuit that holds in advance at least a phase calculation value corresponding to the count value and outputs table data corresponding to the input count value as a phase calculation value .

  Also, the clock signal dividing method according to the present invention is based on a division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N). This is a clock signal dividing method for generating a rounded output clock signal. Based on the input control signal, the clock pulse of the input clock signal is output as it is non-inverted, inverted or output, or masked. A clock selection step for generating an output clock signal by selecting and executing any one of the output operations, and a constant cycle time corresponding to the division ratio for each cycle of the input clock signal A phase calculation value indicating the phase relationship between the reference frequency-divided clock signal and the input clock signal is calculated. Based on this phase calculation value, the phase of the reference frequency-divided clock signal in the output operation is approximated. A clock selection control step for generating a control signal for instructing an output operation for generating a clock signal and outputting the control signal to the clock selection step. The clock selection control step is configured to have a frequency dividing ratio for each cycle of the input clock signal. Calculate the phase calculation value indicating the phase relationship between the reference divided clock signal and the input clock signal having a constant cycle time, and increase or decrease the phase calculation value according to the phase adjustment signal indicating phase control for the output clock signal. A clock output for determining whether to output a clock pulse of the input clock signal to the output clock signal based on the phase calculation value and outputting a control signal according to the determination result to the clock selection step Based on the judgment step and the phase calculation value, the clock pulse of the input clock signal is not inverted as it is. Or force, to determine whether to output the inverted, and a clock phase determination step of outputting a control signal corresponding to the determination result to the clock selecting step.

  Further, another clock signal dividing method according to the present invention is based on a division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N). A clock signal dividing method for generating an output clock signal divided by M, whether the clock pulse of the input clock signal is output as it is non-inverted or inverted based on the input control signal, A clock selection step for generating an output clock signal by selecting and executing one of the output operations of masking and not outputting, and a constant cycle time corresponding to the division ratio for each cycle of the input clock signal The phase calculation value indicating the phase relationship between the reference frequency-divided clock signal having the input clock signal and the input clock signal is calculated. A clock selection control step for generating a control signal for instructing an output operation for generating a near clock signal and outputting the control signal to the clock selection step. The clock selection control step repeatedly counts the input clock signal for M cycles. The counter step for outputting the count value corresponding to the cycle, and the table step for holding at least the phase calculation value corresponding to the count value in advance and outputting the table data corresponding to the input count value as the phase calculation value. Including.

  According to the present invention, in the arithmetic processing of integer values indicating the frequency division ratio denominator M and the frequency division numerator N, the reference frequency division clock signal having a constant cycle time corresponding to the frequency division ratio for each cycle of the input clock signal; The phase calculation value indicating the phase relationship with the input clock signal can be calculated, and based on this phase calculation value, the clock pulse of the input clock signal is output as it is non-inverted, inverted or output, masked and output The output clock signal can be generated by selecting one of the two or not and performing output control on the clock pulse of the input clock signal.

As a result, the minimum cycle time of the output clock signal can be suppressed to an error of half a cycle or less with respect to the constant cycle time of the reference frequency-divided clock signal, and an output clock signal with a small cycle time variation can be generated. Is possible.
In addition, since the phase adjustment can be performed simultaneously with the generation of the divided clock signal by increasing / decreasing the phase calculation value, a special circuit for phase adjustment becomes unnecessary. Further, the arithmetic processing can be configured with only a digital logic circuit, and can be realized with a small circuit scale. For this reason, power consumption and layout area can be reduced, and furthermore, since an analog circuit or a circuit that requires a dedicated design is not used, design / verification costs can be suppressed.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a clock signal frequency dividing circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a clock signal frequency dividing circuit according to the first embodiment of the present invention.

  The clock signal frequency dividing circuit 10 outputs an input clock signal based on a frequency dividing ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) in the frequency dividing ratio setting information 20. This is a circuit that generates an output clock signal obtained by frequency-dividing the clock S by a rational number by an N / M division ratio by selectively controlling stop, phase inversion output, and phase non-inversion output.

The clock signal frequency dividing circuit 10 includes a clock selection control circuit 100 and a clock selection circuit 101 as main circuits.
The clock selection control circuit 100 operates at the timing of the input clock signal, calculates a phase calculation value 111 indicating the phase relationship between the reference divided clock signal having a constant cycle time corresponding to the division ratio and the input clock signal, Based on this phase calculation value 111, among the output operations in the clock selection circuit 101, a control signal for instructing an output operation for generating a clock signal close to the phase of the reference divided clock signal, that is, the clock output control signal 102 And a clock phase control signal 103 are generated every cycle of the input clock signal.

The clock selection control circuit 100 includes a phase calculation circuit 110, a clock output determination circuit 112, and a clock phase determination circuit 113 as main circuit units.
The phase calculation circuit 110 inputs a phase of a reference frequency-divided clock signal having a frequency division ratio of N / M and a constant cycle time corresponding to the frequency-divided ratio, that is, a reference frequency-divided clock signal with respect to an input clock signal It has a function of calculating every cycle of the clock signal.
The clock output determination circuit 112 refers to the phase calculation value 111 calculated by the phase calculation circuit 110 and determines whether or not to output the clock pulse of the input clock signal to the output clock signal for each cycle of the input clock signal. The determination result is output as the clock output control signal 102.

More specifically, the clock output determination circuit 112 causes the clock selection circuit 101 to output the clock pulse of the input clock signal to the output clock signal when the phase calculation value 111 indicates less than one cycle of the input clock signal. A control value for non-mask control is output to the clock output control signal 102.
In addition, when the phase calculation value 111 indicates one cycle or more of the input clock signal, the clock output determination circuit 112 performs mask control so that the clock selection circuit 101 does not output the clock pulse of the input clock signal to the output clock signal. The control value is output to the clock output control signal 102.

  The clock phase determination circuit 113 refers to the phase of the reference frequency-divided clock signal with respect to the input clock signal calculated by the phase calculation circuit 110, and the phase of the output clock signal when the clock pulse of the input clock signal is output as it is, and the input clock Select the phase closer to the reference divided clock signal for each cycle of the input clock signal, out of the phase of the output clock signal when the signal clock pulse is inverted and output, and then perform the reference division The clock selection circuit 101 has a function of outputting, to the clock phase control signal 103, a control value for selecting and controlling the one closer to the phase of the clock signal.

More specifically, when the phase calculation value 111 indicates less than a half cycle of the input clock signal, the clock phase determination circuit 113 causes the clock selection circuit 101 to output the clock pulse of the input clock signal as it is to the output clock signal. A control value for non-inverted output control is output to the clock phase control signal 103.
In addition, the clock phase determination circuit 113 causes the clock selection circuit 101 to invert the clock pulse of the input clock signal and output it to the output clock signal when the phase calculation value 111 indicates a half cycle or more of the input clock signal. A control value to be subjected to inversion output control is output to the clock phase control signal 103.

Whether the clock selection circuit 101 outputs the clock pulse of the input clock signal as it is non-inverted based on the output clock control signal given by the clock phase control signal 103 and the clock output control signal 102 for each cycle of the input clock signal The output clock signal is generated by selecting and executing one of the output operations of inverting the input clock signal for output or masking the input clock signal for output.
The clock selection circuit 101 includes an AND circuit 115, an inverter circuit 116, and a selector circuit 117.

The AND circuit 115 has a function of masking clock pulses of the input clock signal based on the clock output control signal 102. Specifically, the AND circuit 115 masks the clock pulse of the input clock signal when the value of the clock output control signal 102 is “0”, and the input clock when the value of the clock output control signal 102 is “1”. Do not mask signal clock pulses.
The inverter circuit 116 has a function of inverting and outputting the clock pulse of the input clock signal.

  The selector circuit 117 determines whether to output the clock pulse of the input clock signal as it is to the output clock signal without being inverted, or to invert the clock pulse of the input clock signal and output it as the output clock signal. It has a function to select based on. Specifically, when the value of the clock phase control signal 103 is “0”, the selector circuit 117 outputs the clock pulse of the input clock signal as it is to the non-inverted output clock signal, and the value of the clock phase control signal 103 is “ In the case of “1”, an inverted signal of the clock pulse of the input clock signal is output to the output clock signal.

Therefore, when the value of the clock phase control signal 103 is “0” and the value of the clock output control signal 102 is “1”, the clock selection circuit 101 does not invert the clock pulse of the input clock signal and outputs the output clock signal. Output as.
Further, when the value of the clock phase control signal 103 is “1” and the value of the clock output control signal 102 is “1”, the clock selection circuit 101 inverts the clock pulse of the input clock signal to generate an output clock signal. Output.
Further, when the value of the clock output control signal 102 is “0”, the clock selection circuit 101 does not output a clock signal as an output clock signal by masking the clock pulse of the input clock signal.

[Clock selection control circuit]
Next, a clock selection control circuit used in the clock signal frequency dividing circuit according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of the clock selection control circuit.

  In the clock selection control circuit 100, as the division ratio setting signal 20, MN information indicating a value obtained by subtracting the division ratio numerator N from the division ratio denominator M, and −N indicating the negative value of the division ratio numerator N. Information and N information indicating a positive value of the frequency division ratio numerator N are input. These consist of parallel data of several bits, and the value of the frequency division ratio setting information 20 does not change unless the frequency division ratio is changed.

The phase calculation circuit 110 of the clock selection control circuit 100 includes an adder 120, flip-flop circuits 121 and 122, a selector circuit 123, a clock phase control circuit 130, a selector circuit 132, a decrementer 133, and an incrementer 134.
The clock output determination circuit 112 of the clock selection control circuit 100 includes a magnitude comparator 140.
The clock phase determination circuit 113 of the clock selection control circuit 100 includes a double multiplier 150 and a magnitude comparator 151.

  The flip-flop circuits 121 and 122 of the phase calculation circuit 110 operate based on the timing of the rising edge of the input clock signal. In FIG. 2, the input clock signal is not shown.

[Operation of First Embodiment]
Next, the operation of the clock signal frequency dividing circuit according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is an explanatory diagram illustrating an application example of the clock signal frequency dividing circuit according to the first embodiment of the present invention.
Here, the operation when a phase adjustment request for an output clock signal is input to the phase adjustment signal 30 will be described.

FIG. 3 shows an example of a semiconductor integrated circuit including the circuit A and the circuit B. The circuit A operates with a clock A ′ obtained by distributing the clock A by the tree-like clock distribution circuit 41. The circuit B operates with a clock B ′ generated by dividing the clock A by a rational number by the clock signal divider circuit 10 of the present invention and distributed by the tree-like clock distribution circuit 42.
The phase comparison circuit 40 periodically compares the phases of the clock A ′ and the clock B ′, and based on the comparison result, the phase difference between the clock A ′ and the clock B ′ is periodically within a half cycle of the clock A ′. Thus, the clock signal frequency dividing circuit 10 is requested through the phase adjustment signal 30 to adjust the phase of the clock B.

The clock signal dividing circuit 10 according to the present embodiment inputs the clock A as an input clock signal, and outputs an output clock signal generated by dividing the clock A as a clock B as a clock B. Further, the phase adjustment signal 30 is input, and the phase of the clock B is adjusted based on the phase adjustment signal 30.
With this operation, even when the distribution delay of the clock B changes during the operation of the LSI, for example, when the voltage of the circuit B is changed, the phase difference between the clock A ′ and the clock B ′ is periodically followed by the clock A. 'Can be within half a cycle. When the phase difference between the clock A ′ and the clock B ′ is periodically within a small range (for example, within a half cycle of the clock A ′), synchronous high-speed communication between the circuit A and the circuit B becomes possible. There are advantages, such as.

  First, the operation of the clock selection control circuit when there is no phase adjustment will be described with reference to FIG. FIG. 4 is a timing chart showing an operation example (without phase adjustment) of the clock selection control circuit. Here, it is assumed that the frequency division ratio N / M is 3/8. Further, the distribution delay of the clock A, that is, the delay of the clock distribution circuit 41, and the distribution delay of the clock B, that is, the delay of the clock distribution circuit 42 are the same, and therefore the phases of the clock A ′ and the clock B ′ are cycled in the cycle C0. Are consistent with each other.

  The phase comparison circuit 40 compares the phases of the clock A 'and the clock B' in the cycle C0 in which the phases are periodically matched, and outputs a phase adjustment request by the phase adjustment signal 30 based on the comparison result. In this case, since the phases of the clock A ′ and the clock B ′ coincide with each other in the cycle C <b> 0, a value “0” indicating that there is no phase adjustment request is output to the phase adjustment signal 30. In response to this, the clock phase control circuit 130 that receives the phase adjustment signal 30 outputs a value “0” to the phase control signal 131 so that the phase adjustment operation is not performed, and the selector circuit 132 receives the input MN. Control to select.

  In FIG. 4, it is assumed that the value of the phase calculation value 111 is “0” in the cycle C0. The double multiplier 150 doubles the phase calculation value 111 and outputs the result to the magnitude comparator 151. The magnitude comparator 151 refers to the value obtained by doubling the value of the phase calculation value 111 and the comparison result of N, and if the value twice the phase calculation value 111 is N or more, the value “1” is obtained. If the value twice the phase calculation value 111 is less than N, a value “0” is output to the clock phase control signal 103. In the cycle C0, the value of the clock phase control signal 103 is “0”.

  The magnitude comparator 140 refers to the phase calculation value 111 and the comparison result of N. If the phase calculation value 111 is equal to or greater than N, the magnitude comparator 140 sets the value “0”. Is output to the clock output control signal 102. In the cycle C0, the value of the clock output control signal 102 is “1”.

  Therefore, the clock selection circuit 101 outputs the clock pulse of the input clock signal as it is as an output clock signal without being inverted. This corresponds to the fact that the clock pulse of the input clock signal is not inverted and output as an output clock signal is closer to the phase of the reference divided clock signal than the output clock signal of the input clock signal is inverted. To do.

Next, in the cycle C1, the flip-flop circuit 122 holds that the result of the magnitude comparator 140 in the cycle C0, that is, the phase calculation value 111 is less than N.
The selector circuit 123 refers to the result of the magnitude comparator 140 of the previous cycle held in the flip-flop circuit 122, selects the input −N if the phase calculation value 111 is N or more, and calculates the phase calculation value. If 111 is less than N, input MN is selected. Accordingly, in cycle C1, the selector circuit 123 selects the input MN (= 8-3 = 5).
The flip-flop circuit 121 holds the value “0” of the phase calculation value 111 in the cycle C0. Accordingly, the value of the phase calculation value 111 is the output “0 + 5 = 5” of the adder 120.

  The magnitude comparator 151 refers to the value “10” obtained by doubling the value “5” of the phase calculation value 111 and the comparison result of N (= 3), and the value twice the phase calculation value 111 is N As described above, the value “1” is output to the clock phase control signal 103. The magnitude comparator 140 refers to the phase calculation value 111 and the comparison result of N. Since the value “5” of the phase calculation value 111 is N (= 3) or more, the value “0” is input to the clock output control signal 102. Is output. Therefore, the clock selection circuit 101 masks the clock pulse of the input clock signal and does not output it as the output clock signal.

Next, in the cycle C2, the flip-flop circuit 122 holds that the phase calculation value 111 is N or more in the cycle C1. Therefore, the selector circuit 123 selects and outputs the input −N (= −3).
The flip-flop circuit 121 holds the value “5” of the phase calculation value 111 in the cycle C1. Therefore, the value of the phase calculation value 111 is the output “5-3 = 2” of the adder 120.

  The magnitude comparator 151 refers to the value “4” obtained by doubling the value of the phase calculation value 111 and the comparison result of N (= 3), and the value twice the phase calculation value 111 is N or more. Therefore, the value “1” is output to the clock phase control signal 103. The magnitude comparator 140 refers to the phase calculation value 111 and the comparison result of N, and since the value “2” of the phase calculation value 111 is less than N (= 3), the value “1” is added to the clock output control signal 102. Is output. Therefore, the clock selection circuit 101 inverts the clock pulse of the input clock signal and outputs it as an output clock signal. This corresponds to the fact that the clock pulse of the input clock signal is inverted and output is closer to the phase of the reference divided clock signal than the clock pulse of the input clock signal is directly output to the output clock signal.

Next, in the cycle C3, the flip-flop circuit 122 holds that the value of the phase calculation value 111 is less than N in the cycle C2. Therefore, the selector circuit 123 selects and outputs the input MN (= 5).
The flip-flop circuit 121 holds the value 2 of the phase calculation value 111 in the cycle C2. Therefore, the value of the phase calculation value 111 is the output “2 + 5 = 7” of the adder 120.

  The magnitude comparator 151 refers to the value “14” obtained by doubling the value of the phase calculation value 111 and the comparison result of N (= 3), and the double value of the phase calculation value 111 is N or more. Therefore, the value “1” is output to the clock phase control signal 103. The magnitude comparator 140 refers to the phase calculation value 111 and the comparison result of N, and since the value “7” of the phase calculation value 111 is N (= 3) or more, the value “0” is input to the clock output control signal 102. Is output. Therefore, the clock selection circuit 101 masks the clock pulse of the input clock signal and does not output it as the output clock signal.

  Similarly, in cycle C4, the value of the phase calculation value 111 is “7-3 = 4”, the value of the clock phase control signal 103 is “1”, and the value of the clock output control signal 102 is “0”. Therefore, the clock selection circuit 101 does not output the clock pulse of the input clock signal as the output clock signal.

  Similarly, in cycle C5, the value of the phase calculation value 111 is “4-3 = 1”, the value of the clock phase control signal 103 is “0”, and the value of the clock output control signal 102 is “1”. Therefore, the clock selection circuit 101 outputs the clock pulse of the input clock signal as it is as an output clock signal without being inverted. This corresponds to the fact that the clock pulse of the input clock signal is not inverted and output to the output clock signal is closer to the phase of the reference divided clock signal than the clock pulse of the input clock signal is inverted and output. To do.

Similarly, in cycle C6, the value of the phase calculation value 111 is “1 + 5 = 6”, the value of the clock phase control signal 103 is “1”, and the value of the clock output control signal 102 is “0”. Therefore, the clock selection circuit 101 does not output the clock pulse of the input clock signal as the output clock signal.
Similarly, in cycle C7, the value of the phase calculation value 111 is “6-3 = 3”, the value of the clock phase control signal 103 is “1”, and the value of the clock output control signal 102 is “0”. Therefore, the clock selection circuit 101 does not output the clock pulse of the input clock signal as the output clock signal.

Next, in the cycle C0 ′ next to the cycle C7, the flip-flop circuit 122 holds that the phase calculation value 111 is N or more in the cycle C7. Therefore, the selector circuit 123 selects and outputs the input −N (= −3).
Further, the flip-flop circuit 121 holds the value “3” of the phase calculation value 111 in the cycle C7. Therefore, the value of the phase calculation value 111 is the output “3-3 = 0” of the adder 120.

The magnitude comparator 151 refers to the value “0” obtained by doubling the value of the phase calculation value 111 and the comparison result of N, and since the double value of the phase calculation value 111 is less than N, the clock phase The value of the control signal 103 is “0”. The magnitude comparator 140 refers to the phase calculation value 111 and the comparison result of N, and since the value of the phase calculation value 111 is less than N, the value of the clock output control signal 102 is “1”.
Therefore, the clock selection circuit 101 outputs the input clock signal as it is as the output clock signal. This situation is the same as the situation of the cycle C0 described above. Therefore, thereafter, the operations from cycle C0 to cycle C7 are repeated.

  As described above, in the example of FIG. 4, in the cycle C2, the clock pulse of the input clock signal is inverted and output as the output clock signal. For this reason, for example, the cycle time from the rise of the output clock signal in cycle C0 to the rise of the output clock signal in cycle C2 is expanded to 2.5 cycles of the input clock signal. Similarly, the cycle time from the rise of the output clock signal in cycle C2 to the rise of the output clock signal in cycle C5 is expanded to 2.5 cycles of the input clock signal.

  Therefore, the minimum cycle time of the output clock signal can be extended to 2.5 cycles of the input clock signal according to the frequency division ratio. The maximum value of the cycle time of the divided clock signal is three cycles of the input clock signal from the rise of the output clock signal in cycle C5 to the rise of the output clock signal in cycle C0 '. For this reason, the minimum cycle time fluctuation of the divided clock signal can be maintained at 2.5 to 3 cycles of the input clock signal, and the cycle time fluctuation of each cycle can be suppressed.

  In addition, since the selection control operates so as to approximate the phase of the reference frequency-divided clock signal with a constant cycle time, there are many opportunities to expand the minimum cycle time of the frequency-divided clock signal according to the frequency division ratio. It is possible to generate a rational frequency divided clock signal with a small variation in cycle time.

Next, the operation of the clock selection control circuit when adjusting the phase delay will be described with reference to FIGS. FIG. 5 is a timing chart showing another operation example (phase delay adjustment) of the clock selection control circuit. FIG. 6 is a timing chart showing another operation example (after FIG. 5) of the clock selection control circuit.
Here, for example, when the voltage of the circuit B is lowered, the operation when the distribution delay of the clock B, that is, the delay of the clock distribution circuit 42 is larger than the delay of the clock A, that is, the delay of the clock distribution circuit 41 is performed. It is shown.

In the example of FIG. 5, in the cycle C0, the phase of the clock B ′ is delayed from the clock A ′ by a half cycle or more of the clock A ′.
The phase comparison circuit 40 compares the phase of the clock A ′ and the phase of the clock B ′ in the cycle C0, and the result of this comparison is that the phase of the clock B ′ is delayed by more than a half cycle of the clock A ′ from the phase of the clock A ′. In order to adjust the phase delay, the phase adjustment signal 30 is output with a value “−1” requesting that the phase be advanced.

  In response to this, the clock phase control circuit 130 outputs the value “−1” to the phase control signal 131 for one cycle so as to perform the adjustment operation for advancing the phase. In the cycle of outputting the value “−1” to the phase control signal 131, the flip-flop circuit 122 of the clock selection control circuit 100 holds that the phase calculation value 111 is less than N, and the selector circuit 123 Any cycle may be used as long as it selects and outputs the output of the selector circuit 132. Here, it is assumed that the value “−1” is output to the phase control signal 131 in the cycle C6.

  When the phase control signal 131 has the value “−1”, the selector circuit 132 selects the output “MN−1 = 5-1 = 4” of the decrementer 133 obtained by subtracting the value “1” from the input “MN”. To do. Thereby, in the cycle C6, the value of the phase calculation value 111 is adjusted from “1 + 5 = 6” to “1 + 4 = 5”. Therefore, the phase calculation value 111 in the cycle C7 is the value “2”, and the cycle C0 ′ is the value “7”.

  As a result, as apparent from comparison between FIG. 4 and FIG. 5, the clock pulse of the input clock signal whose phase is advanced by half a cycle from the cycle C7 to the cycle C0 'is output as the output clock signal. Therefore, in spite of the distribution delay of clock B being larger than the distribution delay of clock A, the phase difference between clock A ′ and clock B ′ is half a cycle of clock A ′ in cycle C0 ′ following cycle C7. Adjusted within.

  Thereafter, the clock phase control circuit 130 continues the operation shown in FIG. Here, an operation is shown after the phase adjustment is performed in cycle C6 and the phase difference between clock A 'and clock B' is adjusted within half a cycle of clock A 'in cycle C0'.

  The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ again in the cycle C0 ′, and based on the comparison result, the phase adjustment signal 30 has a value “0” indicating that there is no phase adjustment request. Is output. The phase calculation value 111 adjusted in the cycle C6 is held in the flip-flop circuit 121 of the clock selection control circuit 100, and the phase calculation value 111 of the subsequent cycle is calculated based on this. Accordingly, even in the next cycle C0 ″, the phase difference between the clock A ′ and the clock B ′ is within a half cycle of the clock A ′.

Next, the operation of the clock selection control circuit when adjusting the phase delay will be described with reference to FIGS. FIG. 7 is a timing chart showing another operation example (phase advance adjustment) of the clock selection control circuit. FIG. 8 is a timing chart showing another operation example (after FIG. 7) of the clock selection control circuit. FIG. 9 is a timing chart showing another operation example (after FIG. 8) of the clock selection control circuit.
Here, for example, when the voltage of the circuit B is increased, the operation when the distribution delay of the clock B, that is, the delay of the clock distribution circuit 42 is smaller than the delay of the distribution of the clock A, that is, the delay of the clock distribution circuit 41 is performed. It is shown.

In the example of FIG. 7, in the cycle C0, the phase of the clock B ′ is advanced by more than a half cycle of the clock A ′ from the phase of the clock A ′.
The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ in the cycle C0, and the result of this comparison is that the phase of the clock B ′ is more than a half cycle of the clock A ′ than the phase of the clock A ′. In order to adjust the phase advance, a value “+1” requesting that the phase be delayed is output to the phase adjustment signal 30.

  In response to this, the clock phase control circuit 130 outputs the value “+1” to the phase control signal 131 for only one cycle so as to perform the adjustment operation for delaying the phase. In the cycle of outputting the value “+1” to the phase control signal 131, the flip-flop circuit 122 of the clock selection control circuit 100 holds that the phase calculation value 111 is less than N, and the selector circuit 123 Any cycle may be used as long as it selects and outputs the output of the circuit 132. Here, it is assumed that the value “+1” is output to the phase control signal 131 in the cycle C6.

  When the phase control signal 131 has the value “+1”, the selector circuit 132 selects the output “M−N + 1 = 5 + 1 = 6” of the incrementer 134 obtained by adding the value “1” to the input “MN”. Thereby, in cycle C6, the value of phase calculation value 111 is adjusted from “1 + 5 = 6” to “1 + 6 = 7”, phase calculation value 111 in cycle C7 is value “4”, and value “1” in cycle C0 ′. become. At this stage, the input clock signal is output as it is as the output clock signal in the cycle C0 'as before. Therefore, also in the cycle C0 ', the phase of the clock B' is more than half a cycle of the clock A 'than the phase of the clock A'.

After the cycle C0 ′, the clock phase control circuit 130 continues the operation shown in FIG.
In this case, also in the cycle C0 ′, the phase of the clock B ′ has advanced by more than a half cycle of the clock A ′ from the phase of the clock A ′. Therefore, the phase comparison circuit 40 continues to delay the phase to the phase adjustment signal 30. A value “+1” requesting that is output.

  In response to this, the clock phase control circuit 130 outputs a value “+1” to the phase control signal 131 in the cycle C6 ′ so as to perform an adjustment operation for delaying the phase. When the phase control signal 131 has the value “+1”, the selector circuit 132 selects the output “M−N + 1 = 5 + 1 = 6” of the incrementer 134 obtained by adding the value “1” to the input “MN”. As a result, the value of the phase calculation value 111 is adjusted from “2 + 5 = 7” to “2 + 6 = 8” in the cycle C6, the phase calculation value 111 in the cycle C7 ′ is the value “5”, and the value “2” in the cycle C0 ”. "become.

  As a result, in the cycle C0 ″, the clock pulse of the input clock signal whose phase is delayed by a half cycle is output as the output clock signal. Therefore, the distribution delay of the clock B is smaller than the distribution delay of the clock A. Nevertheless, in the cycle C0 ″, the phase difference between the clock A ′ and the clock B ′ is adjusted within a half cycle of the clock A ′.

  Thereafter, the clock phase control circuit 130 continues the operation shown in FIG. Here, the operation is shown after phase adjustment is performed in cycle C6 'and the phase difference between clock A' and clock B 'is adjusted within half a cycle of clock A' in cycle C0 ".

  The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ again in the cycle C0 ′, and based on the comparison result, the phase adjustment signal 30 has a value “0” indicating that there is no phase adjustment request. Is output. The phase calculation value 111 adjusted in the cycle C6 'is held in the flip-flop circuit 121 of the clock selection control circuit 100, and the phase calculation value 111 of the subsequent cycle is calculated based on this. Accordingly, even in the next cycle C0 ′ ″, the phase difference between the clock A ′ and the clock B ′ is within a half cycle of the clock A ′.

[Effect of the first embodiment]
As described above, according to the present embodiment, the clock selection control circuit 100 generates a reference divided clock signal having a constant cycle time corresponding to the division ratio and the input clock signal based on the division ratio setting signal 30. The phase calculation value 111 indicating the phase relationship is calculated, and the value of the phase calculation value 111 is increased or decreased according to the phase adjustment signal. Based on this phase calculation value 111, the input clock signal The clock pulse is selected as either non-inverted output, inverted output, or masked output, and the clock selection circuit 101 selects the clock of the input clock signal based on the selection result. An output clock signal is generated by performing pulse output control.

  As a result, the minimum cycle time of the output clock signal can be suppressed to an error of half a cycle or less with respect to the constant cycle time of the reference frequency-divided clock signal, and an output clock signal with a small cycle time variation can be generated. Is possible.

  Further, the clock selection control circuit 100 and the clock selection circuit 101 can be configured by only a digital logic circuit that performs arithmetic processing on integer values related to the frequency division ratio, and can be realized with a small circuit scale. For this reason, power consumption and layout area can be reduced, and furthermore, since an analog circuit or a circuit that requires a dedicated design is not used, design / verification costs can be suppressed.

  In the present embodiment, the case where the clock selection control circuit 100 inputs and uses the division ratio setting signals MN, -N, and N has been described as an example. However, the present invention is not limited to this. For example, M and N may be input to generate and use MN and -N internally.

In the present embodiment, the clock selection control circuit 100 increases or decreases the phase calculation value 111 according to the phase adjustment signal 30 indicating phase control for the output clock signal.
Specifically, “1” is subtracted from the phase calculation value 111 according to the phase adjustment signal 30 indicating that the phase of the output clock signal is advanced, and according to the phase adjustment signal 30 indicating that the phase of the output clock signal is delayed. Thus, “1” is added to the phase calculation value 111.
Thus, the phase calculation value 111 for the output clock signal can be calculated for each cycle of the input clock signal by an integer value calculation process related to the frequency division ratio.

  Since the clock signal dividing circuits described in Patent Document 1 and Patent Document 2 do not have a function of adjusting the phase of the divided clock signal, the clock signal is compensated for clock skew with other clock signals. It is necessary to insert a buffer circuit for skew compensation in the signal distribution circuit. However, when the amount of clock skew is large, many buffer circuits for skew adjustment are required, which increases the area and power cost. In addition, since the delay amount of the buffer circuit cannot be adjusted during operation, the power supply voltage can be changed during operation, such as when using dynamic frequency voltage control technology that controls the voltage according to the cycle time to reduce power. If you do, there is a problem that you can not cope.

  According to the present embodiment, it is not necessary to provide a delay circuit or the like specifically for phase adjustment, and the phase of the output clock signal can be adjusted while dividing the input clock signal by a rational number. Therefore, it is possible to realize a rational frequency divider circuit with a phase adjustment function with low design / verification costs without significantly increasing the layout area and power consumption.

[Second Embodiment]
Next, a clock signal frequency dividing circuit according to the second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing another configuration of the clock selection control circuit.
In the first embodiment, the case where the clock selection control circuit 100 calculates and outputs the phase calculation value 111 during the frequency division operation has been described. In the present embodiment, a case will be described in which the phase calculation value 111 is output using a table circuit that holds values calculated in advance.

As shown in FIG. 10, the phase calculation circuit 110 of the clock selection control circuit 100 according to the present embodiment includes a counter circuit 160 and a table circuit 161.
As the frequency division ratio setting signal 20, the phase calculation circuit 110 includes MN information indicating a value obtained by subtracting the frequency division ratio numerator N from the frequency division ratio denominator M, M information indicating the frequency division ratio denominator M, and frequency division. N information indicating a positive value of the specific numerator N is input. These consist of parallel data of several bits, and the value of the frequency division ratio setting information 20 does not change unless the frequency division ratio is changed.

  The counter circuit 160 operates at the timing of the input clock signal, and refers to the inputs “M” and “MN” of the division ratio setting information 20 and the phase adjustment signal 30 to input and output clock signals. The value M, which is the number of cycles in which the phase relationship of the circuit circulates, is counted repeatedly, and the value is output to the count value 162.

  The table circuit 161 has a function of holding and selecting and outputting a plurality of table data 164, and phase calculation is performed for each combination 163 of the input “M” and “N” of the division ratio setting information 20 and the count value 162. The value 111 is stored in advance in a table format, more specifically, the phase calculation value 111 calculated by the phase calculation circuit 110 of the first embodiment for each cycle of the input clock signal is stored in a table. The table circuit 161 reads the table data 164 corresponding to the combination 163 of the inputs “M”, “N”, and the count value 162 for each cycle of the input clock signal, and outputs it as the phase calculation value 111. , Output as it is.

  In the clock signal frequency dividing circuit 10 according to the present embodiment, the configuration other than the phase calculation circuit 110 is the same as that in the first embodiment, and a detailed description thereof is omitted here.

[Operation of Second Embodiment]
Next, the operation of the clock signal frequency dividing circuit according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a timing chart showing the operation (without phase adjustment) of the clock selection control circuit. FIG. 12 is a timing chart showing another operation (adjusting phase delay) of the clock selection control circuit. FIG. 13 is a timing chart showing another operation of the clock selection control circuit (after FIG. 13). FIG. 14 is a timing chart showing another operation (adjusting phase advance) of the clock selection control circuit. FIG. 15 is a timing chart showing another operation of the clock selection control circuit (after FIG. 14). FIG. 16 is a timing chart showing another operation of the clock selection control circuit (after FIG. 15). Here, the operation of the clock selection control circuit 100 when the frequency division ratio N / M = 3/8 will be described.

  First, the operation of the clock selection control circuit 100 when the phases of the clock A and the clock B are the same and there is no phase adjustment will be described with reference to FIG. Here, the distribution delay of the clock A, that is, the delay of the clock distribution circuit 41, and the distribution delay of the clock B, that is, the delay of the clock distribution circuit 42, are the same, so that the phases of the clock A ′ and the clock B ′ are cycle C0. Assume that they match periodically.

  The phase comparison circuit 40 compares the phases of the clock A 'and the clock B' in the cycle C0 in which the phases are periodically matched, and outputs a phase adjustment request by the phase adjustment signal 30 based on the comparison result. In this case, since the phases of the clock A ′ and the clock B ′ coincide with each other in the cycle C <b> 0, a value “0” indicating that there is no phase adjustment request is output to the phase adjustment signal 30.

In the clock selection control circuit 100, the counter circuit 160 of the phase calculation circuit 110 becomes 0 in cycle C0, and then repeats counting for M = 8 cycles. In FIG. 11, “0” to “7” are illustrated as the count value 162 and correspond to cycles C0 to C7.
The table circuit 161 holds the value of the phase calculation value 111 when the frequency division ratio N / M = 3/8 as the table data 164, and the combination of the inputs “M”, “N”, and the count value 162 The table data 164 corresponding to 163 is read, and this value is output as the phase calculation value 111.

  Specifically, the table circuit 161 has a value “0” when the count value 162 is “0”, a value “5” when the count value 162 is “1”, and a value “2” when the count value 162 is “2”. The value “2”, the value “7” when the count value 162 is the value “3”, the value “4” when the count value 162 is the value “4”, the value “1” when the count value 162 is the value “5”, The value “6” is output as the phase calculation value 111 when the count value 162 is the value “6” and the value “3” is output when the count value 162 is the value “7”.

  This phase calculation value 111 is the same as the phase calculation value 111 in the first embodiment shown in FIG. Therefore, the clock signal frequency dividing circuit of this example can also realize frequency division with a frequency division ratio N / M = 3/8, as in the first embodiment.

Next, the operation of the clock selection control circuit 100 when adjusting the phase delay will be described with reference to FIG.
In FIG. 12, the distribution delay of the clock B is larger than the distribution delay of the clock A, and the phase of the clock B ′ is delayed from the phase of the clock A ′ by half a cycle or more of the clock A ′ in the cycle C0. To do.
The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ in the cycle C0, and the result of this comparison is that the phase of the clock B ′ is delayed by more than a half cycle of the clock A ′ from the phase of the clock A ′. In order to adjust the phase delay, a value “−1” requesting that the phase is advanced is output to the phase adjustment signal 30.

  In response to the phase adjustment signal 30, the counter circuit 160 corrects the counted value so as to perform an adjustment operation for advancing the phase in any cycle. Specifically, in cycle C 6, “MN = 8−3 = 5” is subtracted from the counted value “6”, the value is corrected to “1”, and the value is output as the count value 162. Thereby, the value of the phase calculation value 111 is adjusted to the value “5” in the cycle C6 and to the value “2” in the next cycle C7. These phase calculation values 111 are the same as the phase calculation values 111 in the first embodiment shown in FIG. Therefore, an output clock signal similar to that in the first embodiment shown in FIG. 5 is output.

  As a result, as apparent from a comparison between FIG. 11 and FIG. 12, an output clock signal whose phase is advanced by half a cycle of the input clock signal is output from cycle C7 to cycle C0 '. Therefore, in spite of the distribution delay of clock B being larger than the distribution delay of clock A, the phase difference between clock A ′ and clock B ′ is half a cycle of clock A ′ in cycle C0 ′ following cycle C7. Adjusted within.

  Thereafter, the clock selection control circuit 100 continues the operation shown in FIG. Here, the phase adjustment is performed in cycle C6, and the operation after the phase difference between clock A 'and clock B' is adjusted within half a cycle of clock A 'in cycle C0' is shown.

The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ again in the cycle C0 ′, and based on the comparison result, the phase adjustment signal 30 has a value “0” indicating that there is no phase adjustment request. Is output.
In response to this, the counter circuit 160 performs a counting operation based on the value adjusted in the cycle C6. Therefore, even in the next cycle C0 ″, the phase difference between the clock A ′ and the clock B ′ is a half cycle of the clock A ′. Within.

Next, the operation of the clock selection control circuit 100 when adjusting the phase advance will be described with reference to FIG.
In FIG. 14, it is assumed that the distribution delay of the clock B is smaller than the distribution delay of the clock A, and the phase of the clock B ′ is advanced more than half a cycle of the clock A ′ in the cycle C0.
The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ in the cycle C0, and the result of this comparison is that the phase of the clock B ′ is more than a half cycle of the clock A ′ than the phase of the clock A ′. In order to adjust the phase advance, a value “+1” requesting that the phase be delayed is output to the phase adjustment signal 30.

  In response to the phase adjustment signal 30, the counter circuit 160 corrects the counted value so as to perform an adjustment operation for delaying the phase in any cycle. Specifically, in cycle C6, “MN = 8−3 = 5” is added to the counted value “6” to correct the value to “11”. In this case, since the range of values to be counted exceeds “0” to “7”, M = 8 is further subtracted to correct the value “3”, and the value is output as the count value 162.

  Thereby, the value of the phase calculation value 111 is adjusted to the value “7” in the cycle C6, the value “4” in the next cycle C7, and the value “1” in the next cycle C0 ′. At this stage, the input clock signal is output as it is as the output clock signal in the cycle C0 'as before. Therefore, also in the cycle C0 ', the phase of the clock B' is more than half a cycle of the clock A 'than the phase of the clock A'.

After the cycle C0 ′, the clock selection control circuit 100 continues the operation shown in FIG.
In this case, also in the cycle C0 ′, the phase of the clock B ′ has advanced by more than a half cycle of the clock A ′ from the phase of the clock A ′. Therefore, the phase comparison circuit 40 continues to delay the phase to the phase adjustment signal 30. A value “+1” requesting that is output.

  In response to this, the counter circuit 160 corrects the value counted in the cycle C6 'so as to perform the adjustment operation for advancing the phase. Specifically, in cycle C <b> 6 ′, “M−N = 8−3 = 5” is added to the counted value “3” and the value is corrected to “8”. Since the range of values to be counted exceeds “0” to “7”, M = 8 is further subtracted to correct the value “0”, and the value is output as the count value 162. Therefore, the value of the phase calculation value 111 is adjusted to the value “0” in the cycle C6, the value “5” in the next cycle C7, and the value “2” in the next cycle C0 ”.

  As a result, in the cycle C0 ″, the clock pulse of the input clock signal whose phase is delayed by a half cycle is output as the output clock signal. Therefore, the distribution delay of the clock B is smaller than the distribution delay of the clock A. Nevertheless, in the cycle C0 ″, the phase difference between the clock A ′ and the clock B ′ is adjusted within a half cycle of the clock A ′.

  Thereafter, the clock selection control circuit 100 continues the operation shown in FIG. Here, the phase adjustment is performed in cycle C6 ', and the operation after the phase difference between clock A' and clock B 'is adjusted within half a cycle of clock A' in cycle C0 "is shown.

The phase comparison circuit 40 compares the phases of the clock A ′ and the clock B ′ again in the cycle C0 ′, and based on the comparison result, the phase adjustment signal 30 has a value “0” indicating that there is no phase adjustment request. Is output.
In response to this, the counter circuit 160 performs a counting operation based on the value adjusted in the cycle C6 ′. Therefore, even in the next cycle C0 ″ ′, the phase difference between the clock A ′ and the clock B ′ is the clock A ′. Within half a cycle.

[Effects of Second Embodiment]
As described above, according to the present embodiment, in the phase calculation circuit 110, the counter circuit 160 repeatedly counts the input clock signal for M cycles, thereby outputting the count value 162 corresponding to the cycle, and at least reaching the count value 162. The corresponding phase calculation value 111 is held in the table circuit 161 in advance, and the table data 164 corresponding to the input count value 162 is output to the clock output determination circuit 112 and the clock phase determination circuit 113 as the phase calculation value 111.

  As a result, the phase calculation value 111 corresponding to the phase relationship between the reference divided clock signal having a constant cycle time corresponding to the division ratio and the input clock signal can be easily obtained with a very simple circuit configuration of the counter circuit and the table circuit. Can be calculated.

In this embodiment, the clock selection control circuit 100 increases or decreases “M−N” to the count value of the counter circuit 160 in accordance with the phase adjustment signal 30 indicating phase control with respect to the output clock signal, thereby calculating the phase. The value 111 is increased or decreased.
Specifically, “MN” is subtracted from the phase calculation value 111 in accordance with the phase adjustment signal 30 indicating that the phase of the output clock signal is advanced, and the phase adjustment signal 30 indicating that the phase of the output clock signal is delayed. Accordingly, “MN” is added to the phase calculation value 111.

Thus, the phase calculation value 111 for the output clock signal can be calculated for each cycle of the input clock signal by an integer value calculation process related to the frequency division ratio.
Therefore, it is not necessary to provide a delay circuit or the like specifically for phase adjustment, and the phase of the output clock signal can be adjusted while dividing the input clock signal by a rational number. Therefore, it is possible to realize a rational frequency divider circuit with a phase adjustment function with low design / verification costs without significantly increasing the layout area and power consumption.

  In this embodiment, the table circuit 161 holds the phase calculation value 111 in a table format for each combination 163 of the inputs “M” and “N” as the frequency division ratio setting information 20 and the count value 162. However, when the frequency division ratio N / M is fixed, the inputs “M” and “N” can be omitted, and the phase calculation value 111 can be calculated by the table circuit 161 having a very small scale. It becomes possible.

  In the present embodiment, the case where the phase calculation value 111 is held as the table data 164 for each combination 163 in the table circuit 161 has been described as an example. However, instead of the phase calculation value 111, the phase calculation value 111 is The values of the clock phase control signal 103 and the clock output control signal 102 generated by reference may be directly held as the table data 164. As a result, the clock output determination circuit 112 and the clock phase determination circuit 113 can be omitted, and the circuit scale can be further reduced.

1 is a block diagram showing a configuration of a clock signal frequency divider circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of a clock selection control circuit. It is explanatory drawing which shows the example of application of the clock signal frequency divider circuit concerning the 1st Embodiment of this invention. It is a timing chart which shows the operation example (no phase adjustment) of a clock selection control circuit. It is a timing chart which shows the other operation example (phase lag adjustment) of a clock selection control circuit. 10 is a timing chart showing another example of operation of the clock selection control circuit (after FIG. 5). 12 is a timing chart showing another operation example (phase advance adjustment) of the clock selection control circuit. 10 is a timing chart showing another operation example (after FIG. 7) of the clock selection control circuit. FIG. 10 is a timing chart showing another example of the operation of the clock selection control circuit (after FIG. 8). FIG. It is a circuit diagram which shows the other structure of a clock selection control circuit. 6 is a timing chart showing an operation (without phase adjustment) of the clock selection control circuit. 12 is a timing chart showing another operation (adjusting phase delay) of the clock selection control circuit. 14 is a timing chart showing another operation of the clock selection control circuit (after FIG. 13). 12 is a timing chart showing another operation (adjustment of phase advance) of the clock selection control circuit. FIG. 15 is a timing chart showing another operation of the clock selection control circuit (after FIG. 14). FIG. 16 is a timing chart showing another operation of the clock selection control circuit (after FIG. 15). It is a timing chart which shows the rational number division result by related technology.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Clock signal dividing circuit, 100 ... Clock selection control circuit, 101 ... Clock selection circuit, 102 ... Clock output control signal, 103 ... Clock phase control signal, 110 ... Phase calculation circuit, 111 ... Phase calculation value, 112 ... Clock Output judgment circuit 113 ... Clock phase judgment circuit 115 ... AND circuit 116 ... Inverter circuit 117 ... Selector circuit 120 ... Adder 121, 122 ... Flip-flop circuit 123 ... Selector circuit 130 ... Phase control circuit 131: Phase control signal, 132: Selector circuit, 133 ... Decrementer, 134 ... Incrementer, 140 ... Large / small comparator, 150 ... Double multiplier, 151 ... Large / small comparator, 160 ... Counter circuit, 161 ... Table circuit, 162 ... count value, 163 ... combination, 164 ... table data.

Claims (7)

A clock signal frequency dividing circuit that generates an output clock signal obtained by dividing the input clock signal by N / M based on a frequency division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) Because
Based on the input control signal, select and execute either the non-inverted, uninverted, or masked output of the clock pulse of the input clock signal. A clock selection circuit for generating the output clock signal;
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and based on the phase calculation value A clock selection control circuit for generating a control signal for instructing an output operation for generating a clock signal close to the phase of the reference divided clock signal among the output operations and outputting the control signal to the clock selection circuit. ,
The clock selection control circuit includes:
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and a phase with respect to the output clock signal is calculated. A phase calculation circuit that increases or decreases the value of the phase calculation value in accordance with a phase adjustment signal indicating control;
Based on the phase calculation value, it is determined whether to output a clock pulse of the input clock signal to the output clock signal, a clock output determination circuit that outputs a control signal according to the determination result to the clock selection circuit;
Based on the phase calculation value, it is determined whether to output the clock pulse of the input clock signal as non-inverted or inverted and output a control signal corresponding to the determination result to the clock selection circuit. A clock signal divider circuit comprising: a phase determination circuit; The clock signal divider circuit according to claim 1,
The phase calculation circuit subtracts 1 from the phase calculation value according to a phase adjustment signal indicating that the phase of the output clock signal is advanced, and according to a phase adjustment signal indicating that the phase of the output clock signal is delayed. A clock signal frequency dividing circuit, wherein 1 is added to the phase calculation value. A clock signal frequency dividing circuit that generates an output clock signal obtained by dividing the input clock signal by N / M based on a frequency division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) Because
Based on the input control signal, select and execute either the non-inverted, uninverted, or masked output of the clock pulse of the input clock signal. A clock selection circuit for generating the output clock signal;
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and based on the phase calculation value A clock selection control circuit for generating a control signal for instructing an output operation for generating a clock signal close to the phase of the reference divided clock signal among the output operations and outputting the control signal to the clock selection circuit. ,
The clock selection control circuit includes:
A counter circuit that outputs a count value corresponding to the cycle by repeatedly counting the input clock signal for M cycles;
And a table circuit that holds in advance a phase calculation value corresponding to at least the count value and outputs table data corresponding to the input count value as a phase calculation value. The clock signal divider circuit according to claim 3,
The clock signal frequency dividing circuit, wherein the counter circuit adjusts the phase of the output clock signal by changing the count value in accordance with a phase adjustment signal instructing phase adjustment of the output clock signal. The clock signal divider circuit according to claim 4,
The counter circuit subtracts MN from the count value according to a phase adjustment signal indicating that the phase of the output clock signal is advanced, and according to a phase adjustment signal indicating that the phase of the output clock signal is delayed. A clock signal dividing circuit, wherein the phase of the output clock signal is adjusted by adding MN to the count value. Clock signal dividing method for generating an output clock signal obtained by dividing the input clock signal by N / M based on a division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) Because
Based on the input control signal, select and execute either the non-inverted, uninverted, or masked output of the clock pulse of the input clock signal. A clock selection step for generating the output clock signal; and
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and based on the phase calculation value A clock selection control step for generating a control signal for instructing an output operation for generating a clock signal close to the phase of the reference divided clock signal among the output operations and outputting the control signal to the clock selection step. ,
The clock selection control step includes:
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and a phase with respect to the output clock signal is calculated. A phase calculation step of increasing or decreasing the value of the phase calculation value according to a phase adjustment signal indicating control;
Based on the phase calculation value, it is determined whether to output a clock pulse of the input clock signal to the output clock signal, a clock output determination step of outputting a control signal according to the determination result to the clock selection step;
Based on the phase calculation value, it is determined whether to output the clock pulse of the input clock signal as it is without being inverted or inverted and output the control signal according to the determination result to the clock selection step A clock signal frequency dividing method comprising: a phase determination step. Clock signal dividing method for generating an output clock signal obtained by dividing the input clock signal by N / M based on a division ratio defined by N / M (N is a positive integer, M is a positive integer larger than N) Because
Based on the input control signal, select and execute either the non-inverted, uninverted, or masked output of the clock pulse of the input clock signal. A clock selection step for generating the output clock signal; and
For each cycle of the input clock signal, a phase calculation value indicating a phase relationship between a reference frequency-divided clock signal having a constant cycle time corresponding to the frequency division ratio and the input clock signal is calculated, and based on the phase calculation value A clock selection control step for generating a control signal for instructing an output operation for generating a clock signal close to the phase of the reference divided clock signal among the output operations and outputting the control signal to the clock selection step. ,
The clock selection control step includes:
A counter step of outputting a count value corresponding to the cycle by repeatedly counting the input clock signal for M cycles;
A clock signal dividing method comprising: a table step of holding in advance a phase calculation value corresponding to at least the count value and outputting table data corresponding to the input count value as a phase calculation value.

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