JP5215087B2 - Electronic circuit - Google Patents

Description

  The present invention relates to an electronic circuit and, more particularly, to an electronic circuit that includes a differential amplifier circuit having an input terminal and a reference signal terminal and generates an averaged signal as a reference signal.

  In recent years, FTTH (Fiber to the home) of the PON (Passive Optical Network) method has become widespread. This system is required to receive optical signals of various amplitudes transmitted from each home and amplify them as electrical signals.

For example, Patent Document 1 discloses a receiving circuit used for PON optical communication. In such a receiving circuit, a light receiving element such as a photodiode (PD) receives an optical signal and outputs a current. A transimpedance amplifier (TIA) converts the current signal output from the PD into a voltage signal. The differential amplifier circuit differentially amplifies the TIA output signal and the reference signal related to the average value of the TIA output signal, and outputs a high level if the TIA output signal is higher than the reference signal, and outputs a low level if it is lower To do. Here, for example, in a receiving circuit used for PON optical communication, the amplitude of an optical signal varies depending on the distance from the communication partner. For this reason, a signal related to the average value of the input signal is generated as a reference signal for each communication partner, and this is compared with the input signal to output a high level and a low level.
JP 2005-223638 A

  In the conventional receiving circuit, since a stable period is required until the reference signal reaches the average value of the input signal, a predetermined time after the input signal is input is defined as a communication preparation period (also referred to as a preamble period), and a dummy signal Receive. However, the reference signal generated in this way is different from the original value under the influence of the fluctuation of the level of the input optical signal in the subsequent communication period.

  The present invention has been made in view of the above problems, and an object thereof is to suppress a reference signal from fluctuating due to an influence of an input signal.

The present invention provides a differential amplifier circuit having an input terminal to which an input signal is input and a reference signal terminal, an averaging circuit that averages the input signal to generate an averaged signal, the reference signal terminal, and the averaged signal A first holding circuit provided between the first holding circuit and the averaging circuit; and a first switch provided between the first holding circuit and the averaging circuit. And a second switch for selectively connecting one of an output of the first holding circuit and an output node between the output of the averaging circuit and the first switch to the reference signal terminal, and the output An electronic circuit comprising: a second holding circuit connected between a node and the second switch, holding the averaged signal and outputting the averaged signal to the second switch . According to the present invention, since the first switch cuts off the first holding circuit and the averaging circuit, it is possible to suppress the reference signal from fluctuating due to the influence of the input signal.

  In the above configuration, the first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit The circuit and the averaging circuit can be cut off. According to this configuration, the average signal of the input signal can be used as the reference signal in the communication preparation period, and the reference signal can be prevented from changing due to the influence of the input signal after the communication preparation period. .

  In the above configuration, the first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit The circuit is disconnected from the averaging circuit, and the second switch selects the output node and connects to the reference signal terminal in the communication preparation period, and outputs the first holding circuit after the communication preparation period. Can be selected and connected to the reference signal terminal. According to this configuration, the average signal of the input signal can be used as the reference signal in the communication preparation period, and the reference signal can be prevented from changing due to the influence of the input signal after the communication preparation period. .

The present invention provides a differential amplifier circuit having an input terminal to which an input signal is input and a reference signal terminal, an averaging circuit that averages the input signal to generate an averaged signal, the reference signal terminal, and the averaged signal A first holding circuit provided between the first holding circuit and the averaging circuit; and a first switch provided between the first holding circuit and the averaging circuit. If, comprising a, the output of the first holding circuit is input to the averaging circuit, the output of the first holding circuit through the averaging circuit is characterized in that it is output to the reference signal terminal It is an electronic circuit .

  In the above configuration, the averaging circuit may generate the average signal by selecting and averaging either the input signal or the output of the first holding circuit. According to this configuration, when the averaging circuit selects the output of the first holding circuit, the reference signal can be prevented from fluctuating due to the influence of the input signal.

  In the above configuration, the first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit And the averaging circuit generates the average signal by selecting and averaging the input signal in the communication preparation period, and after the communication preparation period, the averaging signal is generated. The average signal can be generated by selecting the output of one holding circuit. According to this configuration, the averaged signal can be used as the reference signal during the communication preparation period, and the reference signal can be prevented from fluctuating due to the influence of the input signal after the communication preparation period.

  In the above configuration, the averaged signal is held between the output of the averaging circuit and the first switch, and the output is connected to the reference signal terminal after the communication preparation period, and in the communication preparation period A second holding circuit whose output is connected to the first switch is provided, and the first holding circuit holds the averaged signal held by the second holding circuit. According to this configuration, the reference signal can be stabilized early by the second holding circuit.

  In the above configuration, the first holding circuit may be a peak hold circuit or a low-pass filter that holds the peak of the input signal.

  In the above configuration, the first holding circuit may be configured such that the output can be set to a constant value.

  According to the present invention, since the first switch cuts off the first holding circuit and the averaging circuit, it is possible to suppress the reference signal from fluctuating due to the influence of the input signal.

  First, a PON communication system will be described. FIG. 1A is a block diagram of the PON system. The station side communication device 82 in the station building 80 is connected to each home side communication device 72 in the plurality of homes 70a to 70c via communication paths L1 and L2 which are optical fibers. The station side communication device 82 and the optical splitter 74 are connected by a single communication path L1. The optical splitter 74 and each home-side communication device 72 are connected via each communication path L2. The optical splitter 74 couples a signal input / output from each home-side communication device 72 via each communication path L2 to the communication path L1. The signal of the communication path L1 is input / output to / from the station side communication device 82. The station side communication device 82 has a control circuit 84, a transmission unit 86 and a reception unit 88. The transmission unit 86 is a transmission circuit that transmits an optical signal to each home-side communication device 72. The receiving unit 88 is a receiving circuit that receives an optical signal from each home-side communication device 72. The control circuit 84 is a circuit that controls the transmission unit 86 and the reception unit 88, and outputs a reset signal to the reception unit 88, for example.

  FIG. 1B is a schematic diagram showing an optical signal input to the light receiving element (see the photodiode 42 in FIG. 2) of the receiving unit 88 with respect to time. During the period Ton1, an optical signal is input from the home communication device 72 of the home 70a. During the period Toff1, no optical signal is input, and during the period Ton2, an optical signal from a home side communication device (not shown) of the home 70b is input. Further, no optical signal is input during the period Toff2, and an optical signal is input from the home side communication device (not shown) of the home 70c in the period Ton3. The amplitude of the output signal of each home-side communication device 72 and the loss of the optical signal in each communication path L2 are different. For this reason, the amplitudes of the optical signals in the periods Ton1, Ton2, and Ton3 are different from the amplitudes A1, A2, and A3, respectively. In this manner, optical signals from different homes are input irregularly with different amplitudes to the PON PD 12. Periods Toff1 and Toff2 are periods for switching the communication path L2.

  Next, a comparative example will be described. FIG. 2 is a block diagram of an electronic circuit according to a comparative example. Referring to FIG. 2, the output voltage signal of TIA 40 obtained by amplifying the output current of photodiode (PD) 42 is input to electronic circuit 90 as digital input signal VA. The electronic circuit 90 has a differential amplifier circuit 30 and a reference signal generation circuit 11. The differential amplifier circuit 30 has an input terminal for receiving an input signal VA and a reference signal terminal for receiving a reference signal Vref. The differential amplifier circuit 30 differentially amplifies the input signal VA and the reference signal Vref, and outputs differential output signals Vout and VoutB. As described above, the differential amplifier circuit 30 is a pulse conversion circuit that converts a digital input signal VA, which is a high-frequency signal including digital information, into a pulse signal by comparing it with the reference signal Vref.

  The reference signal generation circuit 11 includes an averaging circuit 10 and a first holding circuit 20. The averaging circuit 10 averages the input signal VA and outputs an average signal Vsm. The averaging circuit 10 includes differential amplifier circuits 12 and 14, resistors R1 and R2, and a capacitor C1. The differential amplifier circuit 12 receives the input signal VA and the average signal Vsm of the output node Nsm of the differential amplifier circuit 14. The differential amplifier circuit 12 differentially amplifies the input signal VA and the averaged signal Vsm, and outputs the differential signal to the differential amplifier circuit 14 via the resistors R1 and R2. The two inputs of the differential amplifier circuit 14 are connected to each other by a capacitor C1. The averaging circuit 10 averages the input signal VA with a time constant defined by the resistors R1 and R2 and the capacitor C1, and outputs the average signal Vsm to the output node Nsm.

  The first holding circuit 20 is connected between the reference signal terminal of the differential amplifier circuit 30 and the averaging circuit 10. The first holding circuit 20 is, for example, a peak hold circuit, holds the average signal Vsm, and outputs the holding signal Vph to the reference signal terminal of the differential amplifier circuit 30. For example, the first holding circuit 20 holds a signal near the peak of the average signal Vsm and outputs it as the holding signal Vph. The holding signal Vph is input to the differential amplifier circuit 30 as the reference signal Vref.

  The functions of the averaging circuit 10 and the first holding circuit 20 will be described. FIGS. 3A and 3B are diagrams showing the input signal VA and the reference signal Vref with respect to time. Referring to FIGS. 3A and 3B, no optical signal is input to the PD 42 in the period Toff. Therefore, the input signal VA is an initial value. In the period Ton, an optical signal is input to the PD 42, and the input signal VA varies. During a certain period (communication preparation period Tpre), ON and OFF signals (0, 1 signal) are alternately input. The communication preparation period Tpre is a preparation period for the averaging circuit 10 to average the input signal VA. After the communication preparation period Tpre is a communication period Tcom in which data is actually transmitted. In the communication period Tcom, as the input signal VA, the on and off signals are not always input alternately, but the following figures describe the case where the on and off signals are input alternately.

  The differential amplifier circuit 30 outputs a high level or a low level as the output signals Vout and VoutB depending on whether the input signal VA is larger or smaller than the reference signal Vref. For this reason, it is preferable that the reference signal Vref becomes the average value Vm of the input signal VA early. However, as shown in FIG. 3A, if the time constant of the averaging circuit 10 is long, the reference signal Vref does not reach the average value Vm early. Thus, the reference signal Vref is not stabilized within the communication preparation period Tpre. On the other hand, as shown in FIG. 3B, if the time constant of the averaging circuit 10 is short, the reference signal Vref quickly reaches the average value Vm within the communication preparation period Tpre, but then synchronizes with the fluctuation of the input signal VA. The reference signal Vref also fluctuates.

  FIG. 4 is a diagram showing the input signal VA and the reference signal Vref of the comparative example. Referring to FIG. 4, the time constant of the averaging circuit 10 is shortened as shown in FIG. Also, the holding time constant of the first holding circuit 20 is made sufficiently longer than the time constant of the averaging circuit 10. Thereby, the reference signal Vref follows the input signal VA and rises early. Even when the input signal VA is at a low level, the first holding circuit 20 outputs the holding signal Vph near the peak of the averaged signal Vsm, so that the variation of the reference signal Vref with respect to time as shown in FIG. Within the communication preparation period Tpre, the reference signal Vref quickly reaches the average value Vm of the input signal VA and stabilizes.

  However, in the reference signal generation circuit 11 of the comparative example, if there is a level fluctuation of the input optical signal in the communication period Tcom after the reference signal Vref is stabilized, it is input to the first holding circuit 20 due to the influence thereof. When the averaged signal Vsm to be changed fluctuates, the first holding circuit 20 holds the peak of the averaged signal Vsm. Further, the holding signal Vph varies due to the discharge from the first holding circuit 20 to the averaging circuit 10 side, and the reference signal Vref also varies. For example, when the output level of the input signal VA increases during the communication period Tcom, the average signal Vsm increases accordingly, and the holding signal Vph also increases.

Table 1 shows the principle of the present invention. According to the present invention, the reference signal generation circuit 11 uses the averaged signal Vsm obtained by averaging the input signal VA as the reference signal Vref, and then refers to the holding signal Vph that holds the averaged signal Vsm regardless of the input signal VA. It is assumed that the signal Vref. For example, the average signal Vsm is used as the reference signal Vref in the communication preparation period Tpre. Thereby, the reference signal Vref can be set to the average value of the input signal VA. On the other hand, during the communication period Tcom (after the communication preparation period), the holding signal Vph that holds the averaged signal Vsm is used as the reference signal Vref regardless of the input signal VA. That is, the holding signal Vph does not depend on the input signal VA during the communication period. As a result, the reference signal Vref can be kept at the average value of the input signal VA, and the reference signal Vref can be prevented from fluctuating due to the influence of the input signal VA.

  In the communication preparation period Tpre, the reference signal generation circuit 11 averages the input signal VA to obtain an average signal Vsm. Therefore, it is preferable that the reference signal generation circuit 11 holds the peak of the averaged signal Vsm when the input signal VA is averaged to obtain an averaged signal, which is used as the reference signal Vref.

  In Table 1, the reference signal Vref is switched between the communication preparation period Tpre and the communication period Tcom. The reference signal Vref may be switched after the reference signal Vref is stabilized to the average value of the input signal VA or close to the average value of the input signal VA, and before the communication period Tcom, Vref during the communication period is Stabilize. Hereinafter, an embodiment for realizing the reference signal generation circuit 11 shown in Table 1 will be described.

  FIG. 5 is a block diagram of an electronic circuit according to the first embodiment. Referring to FIG. 5, in the reference signal generation circuit 11 a according to the first embodiment, a first switch SW <b> 1 is provided between the output node Nsm of the averaging circuit 10 and the first holding circuit 20. That is, the first switch SW1 connects or blocks the average signal Vsm to the first holding circuit 20a. Other configurations are the same as those of the comparative example shown in FIG.

  FIG. 6A is a diagram illustrating an example in which a low-pass filter is used as the first holding circuit 20. Referring to FIG. 6A, the first holding circuit 20a includes a resistor R between the input and the output, and a capacitor C between the output and the ground. As described above, a low-pass filter having a time constant sufficiently larger than the time constant of the averaging circuit 10 can be used as the first holding circuit 20a.

  FIG. 6B is a diagram illustrating an example in which a peak hold circuit is used as the first holding circuit 20. Referring to FIG. 6B, the first holding circuit 20 includes differential amplifier circuits 22 and 24, a diode D1, a capacitor C2, and a reset circuit 25. The differential amplifier circuit 22 differentially amplifies the averaged signal Vsm and the holding signal Vph. The output of the differential amplifier circuit 22 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the input of the differential amplifier circuit 24. The differential amplifier circuit 24 differentially amplifies the signal Vp and the holding signal Vph and outputs the holding signal Vph. A capacitor C2 and a reset circuit 25 are connected in parallel between the cathode of the diode D1 and the ground. The reset circuit 25 is an NPN bipolar transistor 26. The collector of the transistor 26 is connected to the cathode of the diode D1, the emitter is connected to the ground, and the reset signal Reset is input to the base. When the reset signal Reset becomes high level, the first holding circuit 20 sets the holding signal Vph to a constant value (for example, ground). As a result, the first holding circuit 20 is reset.

  When the average signal Vsm is larger than the hold signal Vph, the differential amplifier circuit 22 outputs a positive signal, charges the capacitor C2 via the diode D1, and determines the potential of the signal Vp. The differential amplifier circuit 24 differentially amplifies the signal Vsm and the holding signal Vph. Therefore, the holding signal Vph becomes the signal Vp. When the signal Vsm is smaller than the hold signal Vph, the differential amplifier circuit 22 outputs a negative signal, but the signal Vp does not change because the diode D1 is in the reverse direction. As described above, the first holding circuit 20 which is a peak hold circuit holds the holding signal Vph at the maximum value (peak) of the averaged signal Vsm.

  FIG. 7 is a time chart illustrating the operation of the electronic circuit according to the first embodiment. The operation of the input signal VA and the reference signal Vref with respect to time and the first switch SW1 is shown. Referring to FIG. 7, at time t0 when the input signal VA is input, the first switch SW1 is in the on state. Therefore, at the beginning of the communication preparation period Tpre, the reference signal Vref becomes an average value of the input signal VA at an early stage and becomes stable, similarly to the operation described in the comparative example of FIG. After time t1 when the reference signal Vref is stabilized, the first switch SW1 is turned off at time t2. Thus, after the communication preparation period Tpre ends, the holding signal Vph held by the first holding circuit 20 before the first switch SW1 is turned off becomes the reference signal Vref, so that the average signal Vsm becomes the reference signal Vref. It is possible to suppress the influence. Even if the switch SW1 is turned off before the time t1, it is possible to suppress the average signal Vsm from affecting the reference signal Vref as long as the reference signal Vref is approaching a stable level.

  According to the first embodiment, as illustrated in FIG. 7, the first switch SW1 holds the average signal Tsm for the first time in the period up to the time t2 (that is, in at least a part of the communication preparation period Tpre). Connect to circuit 20. As a result, as shown in Table 1, the reference signal generation circuit 11a holds the averaged signal Vsm obtained by averaging the input signal VA and sets it as the reference signal Vref. In addition, since the first holding circuit 20 uses the holding signal Vph, which holds the averaged signal Vsm, as the reference signal Vref, as described with reference to FIG. 4, the reference signal Vref is quickly stabilized near the average value of the input signal VA. Can be made. On the other hand, as shown in FIG. 7, the first switch SW1 cuts off the average signal Vsm and the first holding circuit 20 during the period after the time t2 (that is, the communication period Tcom after the communication preparation period Tpre). As a result, as shown in Table 1, the holding signal Vph that holds the averaged signal Vsm regardless of the input signal VA is set as the reference signal Vref. Therefore, it is possible to suppress the reference signal Vref from fluctuating due to the influence of the input signal VA.

  Further, since the first holding circuit 20 can be reset, the first holding circuit 20 can be reset during the periods Toff1 and Toff2 of FIG. 1B, and the reference signal Vref can be set to the minimum value.

  The second embodiment is an example having the second switch SW2. FIG. 8 is a block diagram of the second embodiment. Referring to FIG. 8, the reference signal generation circuit 11b according to the second embodiment includes a second switch SW2 that selects either the average signal Vsm or the hold signal Vph and sets it as the reference signal Vref. That is, the second switch SW2 selectively selects one of the output of the first holding circuit 20 and the output node Nsm between the output of the averaging circuit 10 and the first switch SW1 as a reference signal of the differential amplifier circuit 30. Connect to the terminal. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 9 is a time chart illustrating the operation of the electronic circuit according to the second embodiment. The operations of the input signal VA and the reference signal Vref with respect to time, and the first switch SW1 and the second switch SW2 are shown. Referring to FIG. 9, before time t2, second switch SW2 selects averaged signal Vsm as reference signal Vref. After time t2, the switch SW2 selects the holding signal Vph and sets it as the reference signal Vref.

  According to the second embodiment, as illustrated in FIG. 9, the second switch SW2 selects the averaged signal Vsm before time t2 (initial stage of the communication preparation period Tpre). That is, the output node Nsm is selected and connected to the reference signal terminal of the differential amplifier circuit 30. Thereby, as shown in Table 1, the reference signal generation circuit 11b can use the averaged signal Vsm obtained by averaging the input signal VA as the reference signal Vref. At this time, the first switch SW1 is in an on state, and the average signal Vsm is input to the first holding circuit 20. On the other hand, the second switch SW2 selects the holding signal Vph after time t2 (after the communication preparation period Tpre). That is, the output of the first holding circuit 20 is selected and connected to the reference signal terminal of the differential amplifier circuit 30. After the time t2, the first switch SW1 is turned off, and the first holding circuit 20 holds, for example, the peak value of the averaged signal Vsm up to the time t2. As a result, as shown in Table 1, the holding signal Vph that holds the averaged signal Vsm can be used as the reference signal Vref regardless of the input signal VA. Therefore, it is possible to suppress the reference signal Vref from fluctuating due to the influence of the input signal VA.

  The third embodiment is an example in which the reference signal generation circuit includes a second holding circuit. FIG. 10 is a block diagram of the third embodiment. Referring to FIG. 10, the reference signal generation circuit 11c according to the third embodiment includes a second holding circuit 32 that holds the averaged signal Vsm. That is, the second holding circuit 32 is connected between the output node Nsm and the second switch SW2. The second switch SW2 selects either the average signal Vsm2 held by the second holding circuit 32 or the holding signal Vph, and sets the selected signal as the reference signal Vref. Other configurations are the same as those of the second embodiment shown in FIG.

  The operations of the first switch SW1 and the second switch SW2 of the third embodiment are the same as those in FIG. 9 of the second embodiment. According to the third embodiment, in the communication preparation period Tpre, the second switch SW2 uses the average signal Vsm2 held by the second holding circuit 32 as the reference signal Vref. Thereby, the reference signal Vref can be stabilized more quickly in the communication preparation period Tpre. Note that the time constant of the second holding circuit 32 is preferably smaller than the time constant of the first holding circuit 20 because the average signal Vsm may be held while the communication holding period Tpre is off. Thus, the holding time of the communication preparation period Tpre and the communication period Tcom can be set independently. As the second holding circuit 32, a low-pass filter as shown in FIG. 6A or a peak hold circuit as shown in FIG. 6B can be used.

  FIG. 11 is a block diagram of an electronic circuit according to the fourth embodiment. Referring to FIG. 11, the reference signal generation circuit 11 d includes an averaging circuit 10 a, a first holding circuit 36, a first switch SW1, and a second holding circuit 34. The averaging circuit 10a includes differential amplifier circuits 12a and 14, resistors R1 and R2, and a capacitor C1. There are two positive side inputs of the differential amplifier 23a, +1 and +2, and the input +1 or +2 can be selected by the second switch signal Vsw2. The configurations of the other differential amplifier circuits 12a and 14, resistors R1 and R2, and capacitor C1 are the same as those of the averaging circuit 10 of the first to third embodiments, and a description thereof is omitted. The output Vsm (average signal) of the averaging circuit 10a is input to the second holding circuit 34. The second holding circuit 34 holds the average signal Vsm (for example, holds the peak of the average signal Vsm), and outputs the holding signal Vph to the first holding circuit 36 via the first switch SW1. The second holding circuit 34 outputs Vph to the reference signal terminal of the differential amplifier circuit 30. The input signal VA is input to the input +1 of the averaging circuit 10a, and the output Vph2 of the first holding circuit 36 is input to the input +2. Therefore, the averaging circuit 10a can generate the average signal Vsm by selecting and averaging either the input signal VA or the output Vph2 of the first holding circuit 36.

  FIG. 12 is a circuit diagram of the differential amplifier circuit 12a. Referring to FIG. 12, the differential amplifier circuit 12a includes NPN transistors T1 to T6, resistors R8 and R9, and a current source 110. The second switch signals Vsw2 and Vsw2B are complementary signals. When the second switch signal Vsw2 is high, the differential circuit including the transistors T1 and T2 and the resistors R8 and R9 is activated, and the reference signal Vref and the input +1 differential signals Out and OutB are output. When the second switch signal Vsw2 is low, the differential circuit including the transistors T3 and T4 and the resistors R8 and R9 is activated, and the reference signal Vref and the input +2 differential signals Out and OutB are output. Thus, the transistors T5 and T6 function as the second switch SW2 that selects the inputs +1 and +2.

  FIG. 13 is a time chart illustrating the operation of the electronic circuit according to the fourth embodiment. The operations of the input signal VA and the reference signal Vref with respect to time, and the first switch SW1 and the second switch SW2 are shown. Referring to FIG. 13, at time t0, the second switch SW2 selects the input signal VA, and the first switch SW1 is on. The reference signal Vref can be stabilized early by the second holding circuit 34. Further, since the first switch SW1 is on, the holding signal Vph is held in the first holding circuit 36. At time t1, the first switch SW1 is turned off at time t2 after the reference signal Vref is stabilized. The second switch SW2 is switched from the input signal VA to the output Vph2 of the first holding circuit 36. In other words, the differential amplifier circuit 12a switches the input from +1 to +2. Thereby, the averaging circuit 10a averages the output Vph2.

  According to the fourth embodiment, when the second switch SW2 selects the input signal VA, the averaging circuit 10a generates the average signal Vsm by averaging the input signal VA. At this time, since the first switch SW1 is on, the first holding circuit 36 holds the average signal Vsm and outputs Vph2. The output Vph2 of the first holding circuit 36 is input to the averaging circuit 10a. When the second switch SW2 selects the output Vph2 of the first holding circuit 36, the output Vph2 of the first holding circuit 36 via the averaging circuit 10a is output to the reference signal terminal of the differential amplifier circuit 30.

  According to the fourth embodiment, in the communication preparation period Tpre, the first switch SW1 is turned on to connect the first holding circuit 36 and the averaging circuit 10a. The averaging circuit 10a generates the average signal Vsm by selecting and averaging the input signal VA. As a result, as shown in Table 1, the reference signal Vref, which is the output of the reference signal generation circuit 11d, is a signal obtained by averaging the input signal VA. On the other hand, after the communication preparation period Tpre, the first switch SW1 is turned off to cut off the first holding circuit 36 and the averaging circuit 10a. The averaging circuit 10a generates an average signal Vsm by selecting and averaging the output Vph2 of the first holding circuit 36. As a result, the reference signal Vref becomes a signal obtained by averaging the output Vph2 of the first holding circuit 36. That is, as shown in Table 1, the reference signal Vref becomes a holding signal (output Vph2) in which the first holding circuit 36 holds the averaged signal Vsm regardless of the input signal VA. Therefore, it is possible to suppress the reference signal Vref from fluctuating due to the influence of the input signal VA.

  Further, a second holding circuit 34 is connected between the output of the averaging circuit 10a and the first switch SW1. The second holding circuit 34 holds the average signal Vsm and outputs it to the reference signal terminal and the first switch SW1. That is, the node (holding node) between the second holding circuit 34 and the first switch SW1 is connected to the reference signal terminal of the differential amplifier circuit 30. The first holding circuit 36 holds the average signal held in the second holding circuit 34. Accordingly, since the second holding circuit 34 holds the averaged signal of the input signal VA as a reference signal even in the communication preparation period Tpre, the reference signal Vref can be stabilized at an early stage. The time constant in the communication preparation period Tpre may be a longer time than the on / off period of the input signal VA, and the time constant in the communication period Tcom is preferably a longer time than the period Ton. Therefore, the time constant of the first holding circuit 36 is preferably longer than the time constant of the second holding circuit 34. As in the comparative example, the averaging time constant of the averaging circuit 10 a is preferably shorter than the time constant of the second holding circuit 34. Thus, the time constant for stabilizing the reference signal Vref in the communication preparation period Tpre and the time constant for keeping the reference signal stable in the communication period Tcom can be set independently.

  The first holding circuit 36 and the second holding circuit 34 can be, for example, the low-pass filter shown in FIG. Further, for example, the peak hold circuit of FIG.

  FIG. 14 is a block diagram of the fifth embodiment. Referring to FIG. 14, as compared with FIG. 11 of the fourth embodiment, differential amplifier circuits 92 and 94 are provided in the subsequent stage of the differential amplifier circuit 30. Thereby, a larger output than Example 4 can be performed. Further, by using the differential amplifier circuit 92 or 94 as a limit amplifier, the differential output signals Vout and VoutB can be made into rectangular waves. The first holding circuit 36 and the second holding circuit 34 use the peak hold circuit of FIG.

  The control circuit 102 includes resistors R5 and R6, a peak hold circuit 56, a hysteresis comparator 54, AND circuits 58 and 62, a timer 60, and an amplifier circuit 64. Resistors R5 and R6 are connected between the output signals A3 + and A3- of the differential amplifier circuit 30. The peak hold circuit 56 holds the peak of the signal A3 + and outputs it to the hysteresis comparator 54. A signal divided by the resistors R5 and R6 is input to the other input of the hysteresis comparator 54. The hysteresis comparator 54 outputs a low level as the signal SD when the signal A3 + falls below a certain ratio of the maximum value of the signal A3 +. The amplifier circuit 64 amplifies the signal SD.

  The AND circuit 58 receives the reset signal Reset and the signal SD. Therefore, the AND circuit 58 outputs a high level as the signal SEL when the reset signal Reset is at a low level (not reset) and the signal SD is at a high level. The AND circuit 62 receives the signal SEL and a signal obtained by delaying the signal SEL by the timer 60. The AND circuit 62 outputs a low level after a predetermined time after the signal SEL becomes a low level. As a result, a low level is output as the first switch signal Vsw1 and the second switch signal Vsw2. The amplifier circuit 64 amplifies the first switch signal Vsw1. The second switch SW2 selects VA when the second switch signal Vsw2 is at a high level, and selects Vph2 when the second switch signal Vsw2 is at a low level. The first switch SW1 is turned on when the first switch signal Vsw1 is at a high level and turned off when the first switch signal Vsw1 is at a low level.

  The amplifier circuit 52 amplifies the reset signal Reset. The reset signal Reset is a signal for resetting the corresponding circuit when it becomes high level. The output of the amplifier circuit 52 is input to the peak hold circuit 56, the first holding circuit 36, and the second holding circuit 34. When the reset signal Reset becomes a high level, the peak hold circuit 56, the first holding circuit 36, and the second holding circuit 34 are reset, and the peak hold circuit 56, the first holding circuit 36, and the second holding circuit 34 respectively hold. The hold signal is reset.

  FIG. 15 is a time chart illustrating the operation of the electronic circuit according to the fifth embodiment. An input signal VA, a Reset signal, switch signals Vsw1, Vsw2, operation of the first switch SW1, operation of the second switch SW2, and reference signal Vref with respect to time are shown. In the period Ton2 in which the previous input signal VA is input, the Reset signal is low and the switch signals Vsw1 and Vsw2 are low. The second switch SW2 selects Vph2, and the reference signal Vref has a peak of the average value of Vph2. The first switch SW1 is off. In a period Toff2 in which the input signal VA is not input, the reset signal Reset is at a high level. The first holding circuit 36, the second holding circuit 34, and the peak hold circuit 56 are reset. As a result, A3 + becomes equal to or greater than a certain ratio of the maximum value of A3 +, so that the signal SD becomes high level. Accordingly, the signal SEL is also at a high level, and the switch signals Vsw1 and Vsw2 are at a high level. Accordingly, the first switch SW1 is turned on, the second switch SW2 selects VA, and the reference signal Vref becomes a peak of the average value of the input signal VA.

  At time t0, the period Ton3 is reached and the input signal VA starts to be input. Since the reference signal Vref is 0 (minimum value) at time t0, A3 + becomes a maximum value. As the reference signal Vref increases, the ratio of A3 + to the maximum value of A3 + decreases. At time t4, when the ratio of A3 + to the maximum value of A3 + becomes equal to or less than a certain value, the signal SD becomes low level. Here, by making the time constant of the hysteresis comparator 54 longer than the period of the input signal VA, the signal SA is not affected by the period of the input signal VA. At time t4, the signal SEL becomes low level. At time t2 after the delay time Tdel by the timer 60, the switch signals Vsw1 and Vsw2 are at a low level. Accordingly, the first switch SW1 is turned off, the second switch SW2 selects Vph2, and the reference signal Vref becomes a peak of the average value of Vph2.

  As described above, the operation described with reference to FIG. The resistors R5 and R6 are preferably set so that the signal SD becomes high level immediately before the reference signal Vref becomes the average value Vm. The delay time of the timer 60 is preferably set so that the switch signals Vsw2 and Vsw1 are turned off after the reference signal Vref is stabilized and before the communication preparation period Tpre ends.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIG. 1A is a block diagram of the PON system, and FIG. 1B is a schematic diagram of an optical signal with respect to the time of optical communication of the PON system. FIG. 2 is a circuit diagram of an electronic circuit according to a comparative example. FIGS. 3A and 3B are timing charts in the case where the holding circuit is not provided and the time constant is large and small. FIG. 4 is a timing chart of the electronic circuit according to the comparative example. FIG. 5 is a circuit diagram of an electronic circuit according to the first embodiment. FIG. 6A shows an example of a holding circuit using a low-pass filter, and FIG. 6B shows an example of using a peak hold circuit for the holding circuit. FIG. 7 is a timing chart of the electronic circuit according to the first embodiment. FIG. 8 is a circuit diagram of an electronic circuit according to the second embodiment. FIG. 9 is a timing chart of the electronic circuit according to the second embodiment. FIG. 10 is a circuit diagram of an electronic circuit according to the third embodiment. FIG. 11 is a circuit diagram of an electronic circuit according to the fourth embodiment. FIG. 12 is a circuit diagram of the differential amplifier circuit. FIG. 13 is a timing chart of the electronic circuit according to the fourth embodiment. FIG. 14 is a circuit diagram of an electronic circuit according to the fifth embodiment. FIG. 15 is a timing chart of the electronic circuit according to the fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Average circuit 11 Reference signal generation circuit 20, 34 1st holding circuit 30 Differential amplifier circuit 32, 36 2nd holding circuit 40 Transimpedance amplifier 42 Photodiode SW1 1st switch SW2 2nd switch

Claims (9)

A differential amplifier circuit having an input terminal to which an input signal is input and a reference signal terminal;
An averaging circuit that averages the input signal to generate an averaged signal;
A first holding circuit which is provided between the reference signal terminal and the output of the averaging circuit, holds the averaged signal and outputs the averaged signal to the reference signal terminal;
A first switch provided between the first holding circuit and the averaging circuit;
A second switch for selectively connecting one of the output of the first holding circuit and the output node between the output of the averaging circuit and the first switch to the reference signal terminal;
A second holding circuit connected between the output node and the second switch, holding the averaged signal and outputting it to the second switch;
An electronic circuit comprising:   The first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit and the average The electronic circuit according to claim 1, wherein the electronic circuit is interrupted. The first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit and the average Shut off the circuit
The second switch selects the output node in the communication preparation period and connects it to the reference signal terminal, and after the communication preparation period, selects the output of the first holding circuit and connects it to the reference signal terminal. The electronic circuit according to claim 1 . A differential amplifier circuit having an input terminal to which an input signal is input and a reference signal terminal;
An averaging circuit that averages the input signal to generate an averaged signal;
A first holding circuit which is provided between the reference signal terminal and the output of the averaging circuit, holds the averaged signal and outputs the averaged signal to the reference signal terminal;
A first switch provided between the first holding circuit and the averaging circuit;
Comprising
The output of the first holding circuit is input to the averaging circuit, an electronic circuit which the output of the first holding circuit through the averaging circuit is characterized in that it is output to the reference signal terminal. 5. The electronic circuit according to claim 4, wherein the averaging circuit generates the average signal by selecting and averaging either the input signal or the output of the first holding circuit. The first switch connects the first holding circuit and the averaging circuit in a communication preparation period for averaging the input signals, and after the communication preparation period, the first holding circuit and the average Shut off the circuit
The averaging circuit generates the averaged signal by selecting and averaging the input signal in the communication preparation period, and selecting the output of the first holding circuit after the communication preparation period 6. The electronic circuit according to claim 5 , wherein an averaged signal is generated. The average signal is held between the output of the averaging circuit and the first switch, and the output is connected to the reference signal terminal after the communication preparation period, and the output is connected during the communication preparation period. A second holding circuit connected to the first switch is provided;
The electronic circuit according to claim 6, wherein the first holding circuit holds the average signal held by the second holding circuit. Said first holding circuit, the electronic circuit according to any one of claims 1 to 7, characterized in that the peak-hold circuit or low-pass filter holds a peak of the input signal. Said first holding circuit, the electronic circuit according to any one of claims 1 8, characterized in that it is possible to set the output to a constant value.

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