JP5214002B2 - Nonvolatile memory device - Google Patents

Description

  The present invention relates to a non-volatile memory device, and more particularly to the setup of a power supply voltage supplied to drive the device.

  In recent years, nonvolatile storage devices capable of storing nonvolatile data have become mainstream. For example, a flash memory that can be highly integrated can be cited. Furthermore, MRAM (Magnetic Random Access Memory) devices that perform nonvolatile data storage using a thin film magnetic material are attracting particular attention as a new generation nonvolatile storage device.

  Unlike a volatile SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory), a non-volatile device that performs non-volatile data storage has a standby current by turning off the power supply in a non-operating standby state. Can be reduced to 0, and there is an advantage that the battery life of the system can be extended.

  On the other hand, a nonvolatile storage device such as a flash memory or an MRAM device can store nonvolatile data, and therefore generally stores a program or data relating to the initial setting of the device, and stores information stored in the storage device. Based on the above, a device setup operation has been executed.

  Although the background art of the present invention has been described based on general technical information obtained by the applicant, information to be disclosed as prior art document information before filing within the scope stored by the applicant. The applicant does not have

  However, when the power is turned off and then turned on again to start up, it is necessary to read from the memory a program or data related to the initial settings for executing the device setup operation. The setup speed varies, and a certain period of time is required until all the circuit elements constituting the memory are normally started.

  Furthermore, when driving the power supply line connected to each circuit element, the wiring capacity and decoupling capacity of the power supply line of the device are large, so the operation of turning on / off the power becomes the operation of charging / discharging the large capacity. Therefore, there is a drawback that it takes a long time and power consumption is large.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory device that can be set up at a high speed after the power is turned on.

  According to one embodiment of the present invention, a nonvolatile memory device is connected to first and second memory modules having memory cells that store data in a nonvolatile manner, and the first and second memory modules, respectively. , And first and second external power supply lines that supply external power for driving the first and second memory modules, and the power capacity of the first external power supply line is the second external power supply. Less than the line power capacity.

  According to one embodiment of the present invention, the first external power supply line is charged before the second memory module by dividing the external power supply line into separate power supply lines and reducing the power supply capacity compared to the other. Thus, the setup for the first memory module is completed early.

It is a schematic block diagram of the chip | tip 1 according to embodiment of this invention. It is a figure explaining the power system circuit of the MRAM module according to Embodiment 1 of this invention. It is a diagram illustrating an internal circuit block of the MRAM module according to the first embodiment of the present invention. 2 is a diagram illustrating a configuration of a memory cell array 30. FIG. 2 is a schematic diagram showing a configuration of a memory cell MC. FIG. FIG. 6 is a conceptual diagram illustrating a data read operation from memory cell MC. It is a conceptual diagram explaining the data write-in operation | movement with respect to a memory cell. It is a conceptual diagram explaining the relationship between the data write current at the time of data writing and the magnetization direction of a tunnel magnetoresistive element. It is a figure explaining the relationship between the element and voltage which comprise each circuit block of a memory module. It is a figure explaining an example at the time of comparing standby current Istby, power supply capacity, power supply setup speed, and circuit setup speed about each circuit block. It is a figure explaining the circuit block inside an MRAM module according to the modification of Embodiment 1 of this invention. It is a figure explaining the connection relation of the power source line of the circuit block inside the mat | matte peripheral circuit group MCGa according to the modification of Embodiment 1 of this invention. It is a figure explaining the power system circuit of the MRAM module according to Embodiment 2 of this invention. It is a figure explaining the circuit block inside the MRAM module according to Embodiment 2 of this invention. It is a figure explaining the power supply system circuit of the MRAM module according to the modification of Embodiment 2 of this invention. It is a figure explaining the operation timing of a switch in the case of performing a high-speed power supply setup with respect to MRAM module 16-1 according to the modification of Embodiment 2 of this invention. It is a figure explaining the power system circuit of the MRAM module according to Embodiment 3 of this invention. It is a figure explaining the power system circuit of the MRAM module according to the modification 1 of Embodiment 3 of this invention. It is a figure explaining the power system circuit according to the modification 2 of Embodiment 3 of this invention. It is a figure explaining the power system circuit of the MRAM module according to Embodiment 4 of this invention. It is a figure explaining the power supply system circuit of the MRAM module according to the modification of Embodiment 4 of this invention. It is a figure explaining the supply timing of an external power supply voltage in the case of performing high-speed power supply setup with respect to MRAM module 16-1 according to the modification of Embodiment 4 of this invention, and the operation timing of a switch. It is a figure explaining the circuit structure of the switch according to Embodiment 5 of this invention. It is a figure explaining the structure of the switch according to the modification of Embodiment 5 of this invention. It is a timing chart explaining the switch operation of the high-speed power supply setup according to Embodiment 6 of the present invention. It is a timing chart figure explaining the switch operation of the high-speed power supply setup according to the modification of Embodiment 6 of this invention.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic configuration diagram of a chip 1 according to an embodiment of the present invention.

  Referring to FIG. 1, a chip 1 according to an embodiment of the present invention includes a CPU 5 for controlling the entire chip, a random access memory (RAM) and a read only ROM (Read Only ROM). And a controller unit 20 that is a peripheral circuit for generating a clock signal, a control signal, or the like. Further, a pad PD is formed in the peripheral region of the chip 1, and for example, a power supply voltage or an external instruction signal is input through the pad PD. Here, as an example, a power supply line VL1 to which a low-voltage external power supply voltage Vcc1 (hereinafter also simply referred to as a power supply voltage Vcc1) used for driving in a low voltage operation, such as a logic circuit, is supplied, and a high voltage operation is used. A power supply line VL2 to which a high-voltage external power supply voltage Vcc2 (hereinafter simply referred to as power supply voltage Vcc2) is used is shown.

  Here, although not shown, an interface unit (also referred to as an IF circuit) that exchanges signals with the outside is also provided. In this example, an MRAM module having a thin film magnetic element is taken as an example of the configuration of the storage unit 15, and a connection configuration of power lines for supplying an external power supply voltage to the MRAM module (hereinafter also referred to as a power system circuit) will be described. .

  FIG. 2 is a diagram illustrating a power system circuit of the MRAM module according to the first embodiment of the present invention.

  Referring to FIG. 2, the power supply system circuit of the MRAM module according to the embodiment of the present invention includes internal power supply lines IVL1 and IVL1 # electrically coupled to two power supply lines VL1 and VL2, respectively.

  Internal power supply line IVL1 is electrically coupled to power supply line VL1, and supplies power supply voltage Vcc1 to the power supply node on the power supply side of MRAM module 16. On the other hand, internal power supply line IVL1 # is electrically coupled to power supply line VL2, and supplies power supply voltage Vcc2 to the power supply node on the power supply side of MRAM module 16. Assume that a capacitor 21 having a capacity C0 is provided as a load as the power supply capacity of the power supply line VL1. Similarly, it is assumed that a capacitor 21 # having a capacity C0 # is provided as a load as the power supply capacity of the power supply line VL2. Further, it is assumed that capacitors 23 and 23 # having capacitors C1 and C1 # are provided as loads as power supply capacities of the internal power supply lines IVL1 and IVL1 #. On the other hand, the ground side of the MRAM module is electrically coupled to the ground voltage GND. Further, it is assumed that a capacitor 22 having a capacity C0g is loaded as the ground capacity of the ground line IGL on the ground side of the MRAM module.

  FIG. 3 is a diagram illustrating an internal circuit block of the MRAM module according to the first embodiment of the present invention. Here, one MRAM module will be described.

  Referring to FIG. 3, the MRAM module according to the first embodiment of the present invention includes a plurality of circuit blocks. Typically, it includes a memory cell array 30, an address decoder for performing row or column selection of the memory cell array in response to an input of an address ADD, and a write current driver for supplying a write current at the time of data writing. Here, the address decoder and the write current driver are collectively referred to as an address decoder / write current driver 31. Also included is a data read system circuit for controlling data read and a sense amplifier for performing an amplification operation on the read data. The data read system circuit and the sense amplifier are collectively referred to as a data read system circuit / sense amplifier 32. The MRAM module 16 also includes a data I / O system circuit 33 that controls the input / output of input data or output data (collectively referred to as data I / O) by exchanging data with the IF circuit, and a clock signal. Control system peripheral circuit 34 for outputting various control signals for operating each circuit based on the input of CLK or control signal CT, etc., and an external power supply voltage to adjust the voltage level and output it as an internal voltage Voltage generation circuit 35. Here, as an example of the voltage generation circuit 35, for example, a case where a reference voltage Vref used as a comparison target at the time of data reading is generated is shown.

  In this example, the power supply voltages Vcc1 and / or Vcc2 are supplied from the internal power supply lines IVL1 and IVL1 # to each circuit block as required. For example, the address decoder / write current driver 31 is shown. Data read system circuit / sense amplifier 32, data I / O system circuit 33, control system peripheral circuit 34 and voltage generation circuit 35 are electrically coupled to internal power supply line IVL1 and supplied with power supply voltage Vcc1. Address decoder / write current driver 31, data read system circuit / sense amplifier 32, data I / O system circuit 33, and voltage generation circuit 35 are electrically coupled to internal power supply line IVL1 #, and power supply voltage Vcc2 is applied. Supplied.

  In this configuration, a switch is provided between the supplied internal power supply lines IVL1 and IVL1 # and each circuit block. Specifically, address decoder / write current driver 31 is electrically coupled to internal power supply lines IVL1 and IVL1 # via switches SWa and SWa #. Data read system circuit / sense amplifier 32 is electrically coupled to internal power supply lines IVL1, IVL1 # via switches SWb, SWb #. Data I / O system circuit 33 is electrically coupled to internal power supply lines IVL1 and IVL1 # via switches SWc and SWc #. Control system peripheral circuit 34 is electrically coupled to internal power supply line IVL1 through switch SWd. Voltage generation circuit 35 is electrically coupled to internal power supply lines IVL1 and IVL1 # via switches SWe and SWe #.

Here, the configuration of the memory cell array will be described.
FIG. 4 is a diagram for explaining the configuration of the memory cell array 30.

  Referring to FIG. 4, here, memory cells MC arranged in a matrix are shown, and correspond to a word line WL and a digit line DL provided corresponding to each memory cell row, and a memory cell column. The bit lines BL1 to BLm provided respectively are shown. Memory cell MC includes a tunneling magneto-resistance element TMR and an access transistor ATR. Tunneling magneto-resistance element TMR is electrically coupled between bit line BL1 and ground voltage GND via access transistor ATR. Access transistor ATR has its gate electrically coupled to word line WL.

Here, the operation principle of the memory cell MC will be described.
FIG. 5 is a schematic diagram showing the configuration of the memory cell MC.

  Referring to FIG. 5, memory cell MC forms a tunnel magnetoresistive element TMR whose electrical resistance changes according to the stored data level and a path of sense current Is passing through tunnel magnetoresistive element TMR during data reading. Access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR.

  A digit line DL for instructing data writing to the memory cell, a word line WL for executing data reading, and an electric power corresponding to the data level of stored data in data reading and data writing A bit line BL which is a data line for transmitting a signal is arranged.

FIG. 6 is a conceptual diagram illustrating a data read operation from memory cell MC.
Referring to FIG. 6, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB and free magnetic layer VL.

  In data reading, access transistor ATR is turned on in response to activation of word line WL, and tunneling magneto-resistance element TMR is connected between bit line BL and ground voltage GND. As a result, a bias voltage corresponding to the bit line voltage is applied to both ends of the tunnel magnetoresistive element TMR, and a tunnel current flows through the tunnel film. By using such a tunnel current, it is possible to cause a sense current to flow through the current path from bit line BL to tunnel magnetoresistive element TMR to access transistor ATR to ground voltage GND during data reading.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance value of the tunnel magnetoresistive element TMR becomes the minimum value Rmin when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are parallel, and the magnetization directions of both are opposite ( The maximum value Rmax is obtained when the direction is anti-parallel.

  Therefore, if the free magnetic layer VL is magnetized in the direction corresponding to the stored data, the voltage change caused in the tunnel magnetoresistive element TMR by the sense current Is differs depending on the stored data level. Therefore, for example, if the sense current Is is supplied to the tunnel magnetoresistive element TMR after the bit line BL is precharged to a constant voltage, the data stored in the memory cell can be read by detecting the voltage of the bit line BL. .

FIG. 7 is a conceptual diagram illustrating a data write operation for a memory cell.
Referring to FIG. 7, at the time of data writing, word line WL is deactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in the direction corresponding to the write data is supplied to digit line DL and bit line BL.

  FIG. 8 is a conceptual diagram illustrating the relationship between the data write current and the magnetization direction of the tunnel magnetoresistive element at the time of data writing.

  Referring to FIG. 8, the horizontal axis indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and digit line DL, respectively.

  In the memory cell, the fixed magnetization direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL, and free magnetic layer VL is at the level of stored data (“1” and “0”). Accordingly, it is magnetized in the direction parallel to the fixed magnetization layer FL or in the antiparallel (opposite) direction along the easy axis direction. The memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in the figure. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to.

When the operating point at the time of data writing is designed as in the example shown in FIG. 8, the strength of the data write magnetic field in the easy axis direction in the memory cell that is the data write target is H _WR . Designed to be That is, the value of the data write current that flows through bit line BL or digit line DL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

In order to rewrite the data stored in the memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass a data write current of a predetermined level or more to both digit line DL and bit line BL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the memory cell is held in a nonvolatile manner until new data writing is executed.

  Thus, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, so that electric resistance values Rmax and Rmin of tunneling magnetoresistive element TMR, and stored data Non-volatile data storage can be executed by associating them with the respective levels (“1” and “0”).

  FIG. 9 is a diagram illustrating the relationship between the elements constituting each circuit block of the memory module and the supplied voltage.

  Referring to FIG. 9, memory cell array 30 includes an MOS transistor and a tunnel magnetoresistive element TMR as an analog circuit. The address decoder / write current driver 31 and the data read circuit / sense amplifier 32 are constituted by CMOS transistors as digital / analog circuits. Further, the control system peripheral circuit 34 and the data I / O system circuit 33 are constituted by CMOS transistors as digital circuits. The voltage generation circuit 35 is configured by a MOS transistor as an analog circuit.

  Here, as an example, the address decoder / write current driver 31, the data read system circuit / sense amplifier 32, the data I / O system circuit 33, and the voltage generation circuit 35 are either one of the power supply voltage Vcc1 or the power supply voltage Vcc2. Driven. Control system peripheral circuit 34 is driven by power supply voltage Vcc1. As described above, it is assumed that the power supply voltage Vcc1 is a low voltage and the power supply voltage Vcc2 is a high voltage.

  FIG. 10 is a diagram illustrating an example when the standby current Istby, the power supply capacity, the power supply setup speed, and the circuit setup speed are compared for each circuit block.

  As described with reference to FIG. 3, the memory cell array 30 is configured not to be directly connected to the power supply line because it receives power supply from, for example, a write current driver. Therefore, the standby current Istby becomes 0. The power capacity is also 0 (none) because it is not configured to receive power directly.

  On the other hand, comparing the other circuits, the control peripheral circuit 34 is driven by the low power supply voltage Vcc1 as described above, and the standby current Istby and the power supply capacity are smaller than those of the other circuit blocks. Designed to. Similarly, data read system circuit / sense amplifier 32 is driven by one of power supply voltage Vcc1 or power supply voltage Vcc2, but is used at the time of data read. Regarding standby current Istby and power supply capacity, Designed to be smaller than the circuit block.

  In the data I / O system circuit 33, a certain amount of standby current Istby flows to exchange data with the IF circuit during data input / output. As will be described later, the standby current Istby does not flow from the address decoder / write current driver 31, but flows from the control peripheral circuit. That is, since it flows moderately in the meantime, it is marked as “medium” here. Since the power supply capacity is configured to drive the high-voltage power supply voltage Vcc2 during data input / output and execute data transfer, the power supply capacity is large when compared with the power supply capacity of the control system peripheral circuit 34.

  Further, since the voltage generation circuit 35 steadily generates and outputs, for example, the reference voltage Vref, the standby current Istby is larger than the address decoder / write current driver 31 as in the data I / O system circuit 33. Although Istby does not flow, it flows more than the control system peripheral circuit. That is, it will flow moderately during that time.

  Since the address decoder / write current driver 31 needs to drive the power supply voltage Vcc2 to supply the data write current and the like at the time of data writing, the standby current Istby has a larger value than other circuit blocks. . Since the power supply capacity is configured to supply the data write current by driving the high power supply voltage Vcc2 at the time of data writing as described above, it has a large value when compared with the control peripheral circuit 34. .

Next, consider the power supply setup speed and the circuit setup speed.
As described above, since the address decoder / write current driver 31 has a larger power supply capacity than other circuit blocks including the control system peripheral circuit 34, the power supply set-up speed is other circuit including the control system peripheral circuit 34. Slower than block.

  On the other hand, the circuit setup speed depends on the relationship between the load driving capability of the circuit and the load capacity of the output node of the circuit. Basically, high-speed operation is required, so that other circuit blocks other than the voltage generation circuit 35 are required. The voltage generator 35 is set to be set up at a high speed, but the power supply voltage is stabilized to some extent in the voltage generation circuit 35 because the internal voltage including the high voltage or the low voltage reference voltage is generated using the power supply voltage. Until then, an appropriate internal voltage cannot be generated. Therefore, it is necessary to wait until the power supply voltage is stabilized, and the setup speed is set slower than that of other circuit blocks.

  In the above, for example, in the MRAM module, the comparison of the standby current of the circuit block, the power supply capacity, the power supply setup and the circuit setup speed has been described. However, as shown in FIG. On the other hand, the address decoder / write current driver 34, the data I / O system circuit 33, and the voltage generation circuit 35 are slower than the other circuit blocks.

  Here, since each circuit block is electrically coupled to the internal power supply lines IVL1 and IVL1 # and receives power supply, all the circuit blocks are supplied with power through the internal power supply lines IVL1 and IVL1 # at a time. Since a large load capacity is applied, the charging time of the internal power supply line becomes long. If it takes time to charge the power supply line, it takes more time to set up a circuit block with a slow power supply setup speed, and it takes time to set up the circuit block as a whole.

  On the other hand, according to the present invention, a switch is provided between each circuit block and the internal power supply lines IVL1 and IVL1 # so that each circuit block and the power supply line are electrically separated. Therefore, it is possible to charge the internal power supply lines IVL1 and IVL1 # and further the power supply lines VL1 and VL2 at a high speed by reducing the load capacity of the internal power supply lines IVL1 and IVL1 # as a whole and thereby reducing the time constant. Become.

  In this configuration, after power-on, power supply is not started simultaneously to all circuit blocks included in the MRAM module in order to execute power supply setup at high speed. For example, an address decoder / write included in the MRAM module First, power is supplied to the current driver 34 and the data I / O system circuit 33.

  Specifically, the switches SWa and SWa # and the switches SWc and SWc # corresponding to the address decoder / write current driver 31 and the data I / O system circuit 33, which are circuit blocks with a slow power supply setup, are first operated to Power supply of power supply voltages Vcc1 and Vcc2 from power supply lines IVL1 and IVL1 # is first executed. Further, for the voltage generation circuit 35 which is a circuit block with a slow circuit setup, the corresponding switches SWd and SWd # are first operated to execute the power supply of the power supply voltages Vcc1 and Vcc2 from the internal power supply lines IVL1 and IVL1 #.

  Next, the switches SWb, SWb #, SWc, SWc #, SWd, which are other circuit blocks with a fast power supply setup, are operated to supply power from the internal power lines IVL1, IVL1 #. Thereby, the power supply setup can be executed at high speed for the address decoder / write current driver 31 and the data I / O system circuit 33 having a low power supply setup speed. The voltage generator 35 also has a high power supply setup, but the circuit setup is slow, so that the setup can be executed at a high speed by operating from the beginning.

  As a result, it is possible to charge the power supply line at high speed, and in some circuit blocks of the plurality of circuit blocks, the power supply is executed earlier than the other circuit blocks, thereby setting up the circuit block having a slow power supply setup. Can be executed at high speed. In addition, a circuit block with a slow circuit setup can be set up at a high speed by quickly supplying power, and the entire circuit block can be set up at a high speed. Note that the switch connection control can be operated in response to an instruction from the outside, for example, an instruction from the CPU.

(Modification of Embodiment 1)
In the first embodiment, the configuration in which a switch is provided between each circuit block and the internal power supply line to enable high-speed setup in FIG. 3 has been described, but here, it corresponds to a memory mat described later. A configuration for executing high-speed setup by providing a switch will be described.

  FIG. 11 is a diagram illustrating an internal circuit block of the MRAM module according to the modification of the first embodiment of the present invention. Here, a case where the memory array is divided into a plurality of memory mats MAT is shown. As an example, a case will be described in which the memory array 30 is divided into four memory mats MAT1 to MAT4 (also collectively referred to as memory mats MAT).

  It is assumed that the peripheral circuit described in FIG. 3 is provided corresponding to each memory mat MAT. Specifically, an address decoder / write current driver 31a, a data read system circuit / sense amplifier 32a, and a data I / O system circuit 33a are provided corresponding to the memory mat MAT1. Similarly, address decoders / write current drivers 31b to 31d, data read system circuits / sense amplifiers 32b to 32d, and data I / O system circuits 33b to 32d are provided corresponding to the memory mats MAT2 to MAT4, respectively. Note that the control system peripheral circuit 34 and the voltage generation circuit 35 described with reference to FIG. 3 are provided in common to the memory mats MAT1 to MAT4, although not shown. The address decoder / write current driver 31a, the data read system circuit / sense amplifier 32a, and the data I / O system circuit 33a constitute a mat peripheral circuit group MCGa provided corresponding to the memory mat MAT1. . Similarly, address decoder / write current drivers 31b to 31d, data read system circuits / sense amplifiers 32b to 32d, and data I / O system circuits 33b to 33d are provided corresponding to memory mats MAT2 to MAT4, respectively. The mat peripheral circuit groups MCGb to MCGd thus formed are configured.

  Further, internal power supply lines are provided corresponding to the respective mat peripheral circuit groups MCGa to MCGd, and switches for electrically coupling the power supply lines VL1 and VL2 and the internal power supply lines are provided. For example, switches SWma and SWma # for electrically coupling to power supply lines VL1 and VL2 are provided corresponding to mat peripheral circuit group MCGa. Similarly, switches SWmb and SWmb # are provided corresponding to the mat peripheral circuit group MCGb. Switches SWmc and SWmc # are provided corresponding to the mat peripheral circuit group MCGc. Switches SWmd and SWmd # are provided corresponding to the mat peripheral circuit group MCGd.

  FIG. 12 is a diagram illustrating a connection relationship between power supply lines of circuit blocks in the mat peripheral circuit group MCGa according to the modification of the first embodiment of the present invention. Here, the mat peripheral circuit group MCGa is representatively described here, but the same is true for the other mat peripheral circuit groups, and the detailed description thereof will not be repeated.

  Referring to FIG. 12, here, each circuit block described in FIG. 3 is provided corresponding to memory mat MAT1.

  Here, internal power supply lines IVL1a and IVL1 # are provided corresponding to memory mat MAT1. The power supply line VL1 supplies the power supply voltage Vcc1 to the internal power supply line IVL1a through the switch SWma. Power supply line VL2 supplies power supply voltage Vcc2 to internal power supply line IVL1 # a through switch SWma #. Then, power supply voltages Vcc1 and Vcc2 are supplied to each circuit block in accordance with the same connection relationship as described in FIG. As described above, the control system peripheral circuit 34 and the voltage generation circuit 35 are provided in common corresponding to each memory mat MAT, and are mutually connected to the internal power supply lines provided corresponding to each memory mat MAT. It shall be electrically coupled. Further, in the configuration of FIG. 3, a switch is provided between each circuit block and the internal power supply line. However, in this configuration, the internal power supply lines IVL1a and IVL1 # a and the power supply lines VL1 and VL2 are connected. The difference is that the switches SWma and SWma # are provided between them, but the other points are the same, and the detailed description thereof will not be repeated.

  Here, a specific memory mat among the plurality of memory mats MAT1 to MAT4, for example, the memory mat MAT1, is used for initial setting as a program related to initial setting as a so-called boot area, that is, as an initialization program at power-on. It is assumed that adjustment data such as DC tuning or memory redundancy repair information is stored. In addition, for the memory mat MAT2, CPU instruction information is stored as a so-called instruction area. It is assumed that other memory mats MAT are allocated for another purpose, for example, for storing CPU data as a so-called data area.

  When the power is turned on, the CPU executes the initial operation related to the initial setting by accessing the boot area or the instruction area described above among the storage information generally stored in the storage unit 15. On the other hand, other data areas and the like are usually accessed after the initial operation is executed.

  Therefore, in the modification of the first embodiment of the present invention, the memory cell array 30 is divided into a plurality of memory mats MAT, and an initial operation is performed on a specific memory mat among the plurality of memory mats MAT. Is stored, that is, assigned as a boot area or an instruction area, power is not supplied to all memory mats MAT, but power is supplied only to the specific memory mat. Execute. Here, as an example, it is assumed that memory mats MAT1 and MAT2 are allocated as a boot area and an instruction area as described above.

  Specifically, the switches SWma, SWma #, SWmb, SWmb # provided corresponding to the mat peripheral circuit groups MCGa, MCGb are operated to supply the power supply voltages Vcc1, Vcc2 to the corresponding internal power supply lines IVL1a, IVL1 # a, etc. Execute power supply.

  Thus, after the power is turned on, the power supply is not started to all the memory mats MAT at the same time, but the power supply setup or the like is executed only for the specific memory mats MAT1 and MAT2 to be accessed at high speed. The mats MAT1 and MAT2 can be set up at high speed and can be accessed at high speed.

  In addition, a switch is provided between the power supply lines VL1 and VL2 in order to supply the power supply voltages Vcc1 and Vcc2 to each mat peripheral circuit group, and electrical connection is made between the internal power supply line and the power supply line of each mat peripheral circuit group. It has a structure separated from each other. Therefore, as described above, it is possible to charge the power supply lines VL1 and VL2 at high speed by reducing the load capacity applied to the power supply line and thereby lowering the time constant, thereby enabling high-speed setup. Note that the switch connection control can be operated in response to an instruction from the outside, for example, an instruction from the CPU.

  In this configuration, the switch that is electrically coupled to the power supply line corresponding to the memory mat MAT is provided to realize a high-speed setup. However, as described with reference to FIG. It is also possible to adopt a configuration in which a switch is provided between the power supply line and the internal power supply line. In the case of the configuration and method described with reference to FIG. 3, a high-speed setup can be executed for a specific memory mat MAT.

  In this configuration, as an example, the case where specific memory mats MAT1 and MAT2 are allocated as the boot area and the instruction area has been described, but the boot area and the instruction area are allocated in the memory mat MAT1. It is also possible to perform power supply setup or the like by operating only the switch corresponding to the memory mat MAT1 at high speed. In addition, here, the memory array is divided into four memory mats as an example, and a configuration in which a switch electrically coupled to the power supply line is provided corresponding to each memory mat MAT has been described. It is not limited to mat units. For example, when the memory mat is divided into a plurality of memory blocks, a switch that is electrically coupled to the power supply line is provided according to the method described above corresponding to each memory block, for example, the boot area and the instruction area are specified. Of course, it is possible to execute power supply setup or the like by operating only the switch corresponding to the specific memory block at high speed.

(Embodiment 2)
In the first embodiment, one MRAM module has been described. In the second embodiment, a configuration in which a plurality of MRAM modules are provided in the storage unit 15 will be described.

  FIG. 13 is a diagram illustrating a power system circuit of the MRAM module according to the second embodiment of the present invention.

  Referring to FIG. 13, a plurality of MRAM modules 16-1 to 16-N are provided here. Corresponding to each MRAM module, internal power supply lines IVL1 to IVLN electrically connected to common power supply line VL1 are provided. In addition, switches SW1 to SWN that electrically couple internal power supply lines IVL1 to IVLN and power supply line VL1 are provided, respectively.

  Here, as an example, switches SW1 and SWN for electrically coupling internal power supply lines IVL1 and IVLN and power supply line VL1 are provided corresponding to MRAM modules 16-1 and 16-N, respectively. The same applies to other MRAM modules. The power supply node on the power supply side of MRAM module 16-1 is electrically coupled to internal power supply line IVL1. Further, it is assumed that a capacitor 21 having a capacity C0 is provided as a load as the power supply capacity of the power supply line VL1. Further, it is assumed that a capacitor 23-1 having a capacity C1 is provided as a load as a power supply capacity of the power supply line IVL1. The power supply node on the ground side of MRAM module 16-1 is electrically coupled to ground voltage GND. Further, it is assumed that a capacitor 22-1 having a capacitance C1g is loaded as the ground capacitance of the ground line IGL1 on the ground side of the MRAM module 16-1. The same applies to other MRAM modules. Although only the power supply line VL1 supplying the power supply voltage Vcc1 is described here, the same applies to the power supply line VL2 supplying the power supply voltage Vcc2 in the same manner as described above. In the following description, the power supply line VL1 that supplies the power supply voltage Vcc1 will be mainly described for the sake of simplicity.

  FIG. 14 is a diagram illustrating an internal circuit block of the MRAM module according to the second embodiment of the present invention.

  Referring to FIG. 14, the difference from the configuration of FIG. 12 is that memory mat MAT1 is replaced with memory cell array 30, but the other connection relationships are the same. Specifically, internal power supply lines IVL1 and IVL1 # are provided here. The power supply line VL1 supplies the power supply voltage Vcc1 to the internal power supply line IVL1 via the switch SW1. Power supply line VL2 supplies power supply voltage Vcc2 to internal power supply line IVL1 # via switch SW1 #. Then, power supply voltages Vcc1 and Vcc2 are supplied to each circuit block in accordance with the same connection relationship as described in FIG.

  In the modification of the first embodiment described above, the case where the program related to the initial setting is stored in the specific memory mat MAT has been described. However, in this example, a specific MRAM module is necessary for high-speed startup. It is assumed that a program related to the initial setting is stored.

  In the conventional configuration, the power supply lines VL1 and VL2 and the internal power supply lines IVL1 and IVL1 # are always electrically coupled to all the MRAM modules. In other words, since it is not electrically isolated and no switch element or the like is provided in particular, an excessively large load capacity such as a power supply capacity, a wiring capacity, and a stray capacity as a whole is generated at the time of starting up the power supply. It will take. Since the charging time of the power line is caused by a time constant based on the load capacity, a certain period is required until the power line is charged. In this regard, for example, even when the CPU 5 wants to access only a specific MRAM module from among a plurality of MRAM modules, a common power supply line is provided corresponding to all the MRAM modules. It takes time to charge due to the load capacity of the line, and it is difficult to access a specific MRAM module at high speed.

  In the present application, since a switch is provided for each MRAM module, the internal power supply lines VL1 and VL2 are electrically disconnected from each other. In the configuration of the present application, in particular, switches SW1 and SW1 # for controlling the electrical connection between the power supply lines VL1 and VL2 and the internal power supply lines IVL1 and IVL1 # are provided for a specific MRAM module, respectively. Since the power supply lines VL1 and VL2 as a whole are reduced, the load capacity of the power supply lines VL1 and VL2 is reduced, and thereby the time constant is lowered, whereby the power supply lines VL1 and VL2 can be charged at high speed.

  By turning on the switches SW1 and SW1 #, the internal power supply lines IVL1 and IVL1 # can be charged at high speed, so that power supply setup for a specific MRAM module among a plurality of MRAM modules can be performed early. Can be completed.

  In addition, the peak current at the time of power-on can be suppressed by the resistance component of the switch SW.

  Here, the configuration in which an internal power supply line is provided corresponding to each MRAM module has been described. However, the present invention is not limited to this, and an MRAM module group is configured by at least one MRAM module, and an internal corresponding to this MRAM module group is configured. A configuration in which a power supply line and a switch SW are provided is also possible. Further, here, the switch for electrically coupling the internal power supply line IVL and the power supply line VL1 electrically coupled to each MRAM module has been described. However, the switch is directly used without providing the internal power supply line IVL. Needless to say, the power supply line VL1 can be electrically coupled. The same applies to the following.

(Modification of Embodiment 2)
FIG. 15 is a diagram illustrating a power system circuit of an MRAM module according to a modification of the second embodiment of the present invention.

  Referring to FIG. 15, the configuration of the power supply system circuit according to the modification of the second embodiment of the present invention is different from the configuration of FIG. 13 in that switch SW12 is provided between internal power supply line IVL1 and internal power supply line IVL2. Furthermore, the point provided is different. Here, a case where switches SW1 and SW2 are respectively provided corresponding to the MRAM modules 16-1 and 16-2 is shown.

  FIG. 16 is a diagram illustrating switch operation timings when high-speed power supply setup is executed for the MRAM module 16-1 according to the modification of the second embodiment of the present invention.

  First, as shown in FIG. 16, the switch SW1 is first turned on. Thereby, the internal power supply line IVL1 is charged. Thereafter, the switch SW2 is turned on. Then, charging of internal power supply line IVL2 is executed this time. When the switch SW12 is turned on, the power supply capacity C2 of the internal power supply line IVL2 acts as a coupling capacity with respect to the internal power supply line IVL1 of the MRAM module 16-1, so that the power supply voltage of the MRAM module 16-1 can be stabilized more stably. It becomes possible to drive.

(Embodiment 3)
FIG. 17 is a diagram illustrating a power system circuit of the MRAM module according to the third embodiment of the present invention.

  Referring to FIG. 17, here, internal ground lines IGL1 to IGLN are provided corresponding to a plurality of MRAM modules, respectively, and switches SW1g to SWNg are provided between internal ground line IGL and ground voltage GND, respectively.

  In the configuration of the present application, internal ground lines IGL1 to IGLN are provided corresponding to the MRAM modules 16-1 to 16-N, respectively, and switches SW1g to SW1g to connect between the internal ground lines IGL1 to IGLN and the ground voltage GND, respectively. Since the SWNg is provided and electrically connected between them, the load capacity applied to the entire internal ground line IGL is reduced, thereby reducing the time constant to shorten the discharge time of the internal ground line IGL at high speed. Can do. Then, as described above, only the MRAM module specifically selected from the plurality of MRAM modules is switched on. By turning on the switch, the internal ground line IGL can also be discharged at high speed, so that power supply setup for a specific MRAM module can be completed early. Accordingly, for example, if a program related to initial settings is stored in a specific MRAM module as described above, the operation related to initial settings can be completed early by completing power supply setup early. . Further, since the switch has a resistance component, it is possible to prevent an excessive peak current from being supplied to the MRAM module.

  Although not shown, for example, as described above with reference to FIG. 15, a switch SW is provided between the internal ground line IGL1 and the internal ground line IGL2, and the switch SW is turned on at the timing according to FIG. Similarly, since the circuit capacity of the non-selected MRAM module works as a decoupling capacity of the internal ground line IGL1, there is an effect that the decoupling capacity can be reduced.

(Modification 1 of Embodiment 3)
FIG. 18 is a diagram illustrating a power system circuit of the MRAM module according to the first modification of the third embodiment of the present invention.

  Referring to FIG. 18, here, MRAM modules 16-1 and 16-2 are shown as an example. A switch SW1 is provided on the power supply side corresponding to the MRAM module 16-1, and a switch SW2g is provided on the ground side corresponding to the MRAM module 16-2. The power supply node on the power supply side of MRAM module 16-1 is electrically coupled to internal power supply line IVL1. The power supply node on the ground side of MRAM module 16-1 is electrically coupled to ground voltage GND. A power supply node on the power supply side of MRAM module 16-2 is electrically coupled to power supply line VL1. The power supply node on the ground side of MRAM module 16-2 is electrically coupled to internal ground line IGL2.

  In this case, the power source capacity and the ground capacity are set so that the capacity C1g = C2 >> C1 = C2g.

  As a result, the power supply lines IVL1 and IVL2 and the ground lines IGL1 and IGL2 effectively contribute as decoupling capacitors, and charge / discharge capacities at the time of power supply selection are reduced, so that power supply setup can be executed at higher speed.

(Modification 2 of Embodiment 3)
FIG. 19 is a diagram illustrating a power supply system circuit according to the second modification of the third embodiment of the present invention.

  Referring to FIG. 19, the configuration of the power system circuit according to the second modification of the third embodiment of the present invention includes switches SW1, SW1 on the power supply side and the ground side of MRAM modules 16-1, 16-2,. SW1g, SW2 and SW2g are provided, respectively.

  When each MRAM module 16-1, 16-2,... Stores, for example, a program that can be properly used by an OS (Operating System) program, etc., high-speed power supply setup is performed only for the selected MRAM module It is also possible to make it.

(Embodiment 4)
In the first to third embodiments described above, a configuration in which an internal power supply line is provided for a common power supply line and a switch that is electrically connected between the common power supply line and the internal power supply line has been described. However, in the fourth embodiment, a method for speeding up the power supply setup of the MRAM module when the power supply lines are provided independently will be described.

  FIG. 20 is a diagram illustrating a power system circuit of the MRAM module according to the fourth embodiment of the present invention.

  Referring to FIG. 20, in this example, a power supply line is provided independently for each MRAM module. Specifically, power supply lines VL11 and VL12 are provided corresponding to the MRAM modules 16-1 and 16-2, respectively. The power supply voltage ext. Is applied to the power supply lines VL11 and VL12. Vcc11 and ext. Vcc12 is supplied.

  That is, when the external power supply line corresponding to the MRAM module required for high-speed startup is divided into separate power supply lines and the power supply capacity C2 (>> C1) of the power supply line VL11 is set, the load capacity is small, so the ext. Vcc11 rises at a high speed with respect to the MRAM module 16-1.

  Alternatively, ext. Vcc11 is set to Ext. It is also possible to realize power supply setup at high speed by externally controlling the power supply so that the power supply is turned on and supplied before Vcc12.

(Modification of Embodiment 4)
FIG. 21 is a diagram illustrating a power system circuit of an MRAM module according to a modification of the fourth embodiment of the present invention.

  Referring to FIG. 21, the configuration according to the modification of the fourth embodiment of the present invention is different from the configuration according to FIG. 20 in that a switch SW10 is further provided between power supply line VL11 and power supply line VL12. .

  FIG. 22 is a diagram illustrating external power supply voltage supply timing and switch operation timing when executing high-speed power supply setup for MRAM module 16-1 according to the modification of the fourth embodiment of the present invention.

  In the configuration of this example, first, the power supply voltage Vcc11 is raised before the power supply voltage Vcc12 by external control. Along with this, the potential level of the power supply line VL11 is initially raised by the supply of the power supply voltage Vcc11. Thereafter, by supplying the power supply voltage Vcc12, the potential level of the power supply line VL12 increases. Next, the switch SW10 is turned on. As a result, the power supply line VL11 and the power supply line VL12 are electrically coupled, so that the capacitor C2 of the power supply line VL12 is added to the power supply line VL11 as a decoupling capacitor. It becomes possible, that is, power supply setup is completed at high speed.

(Embodiment 5)
In the fifth embodiment, a circuit configuration of a switch used in a power supply system circuit will be described.

FIG. 23 is a diagram illustrating a circuit configuration of the switch according to the fifth embodiment of the present invention.
Referring to FIG. 23, a P-channel MOS transistor is used here as switch SW1 for electrically coupling power supply line VL1 and internal power supply line IVL1. N channel MOS transistor SW1g is used as switch SW1g for electrically coupling ground voltage GND and internal ground line IGL1. Similarly, similar MOS transistors can be provided for other power supply lines or ground lines.

  As the switch on the power source side or ground side in the above embodiment, a MOS-FET having a small source-drain leak and a gate leak at the time of OFF is desirable. For example, a MOS-FET or a gate insulating film having a relatively large threshold is used. Thick MOS-FETs can be used. These correspond to transistors used in a relatively high voltage portion in the chip in the embedded memory. Specifically, a transistor used in an interface unit (also referred to as an IF circuit) or the like is possible. For example, as an application example in the case of a mixed memory, a transistor that operates with 1.5 volt drive is used in the internal logic, and a transistor that operates with 3.3 volt drive with a high threshold voltage is used in the IF section or the like. Used. Alternatively, as the MOS-FET having a thick gate insulating film, a transistor having a gate insulating film of 20 mm is used in the internal logic, and a transistor having a thick gate insulating film is used in the IF section or the like. In the configuration of the present application, a transistor having a high threshold voltage or a thick gate insulating film can be used.

  In the single memory, it is possible to use a transistor used at a relatively high voltage portion in the chip such as an interface portion.

(Modification of Embodiment 5)
FIG. 24 is a diagram illustrating a configuration of a switch according to the modification of the fifth embodiment of the present invention.

  Referring to FIG. 24, here, a voltage step-down circuit VDC included in the voltage generation circuit is shown. Here, a configuration in which the external power supply line VL1 driven by 3.3V is supplied to the internal power supply line IVL driven by 1.5V will be described. Voltage step-down circuit VDC includes a switch transistor PSW1, a comparator CP, and resistors R1 and R2. Switch transistor PSW1 is a P-channel MOS transistor, and is provided between power supply line VL1 and internal power supply line IVL, and its gate receives an output signal of comparator CP. Comparator CP compares the voltage of internal node Nd with reference voltage Vref and outputs a comparison result. Specifically, if the voltage of internal node Nd is higher than reference voltage Vref (1.5 V), “H” level is output. Along with this, the switch transistor PSW1 is turned off. On the other hand, if the voltage of the internal node Nd is lower than the reference voltage Vref (1.5 V), the “L” level is output. Along with this, the switch transistor PSW1 is turned on. Resistors R1 and R2 are connected in series between power supply line VL1 and the ground voltage via internal node Nd. The resistance division based on the resistors R1 and R2 is adjusted so that the voltage of the internal node Nd becomes about 1.5V when the voltage of the power supply line VL1 is 3.3V.

  By using the configuration according to the modification of the fifth embodiment, that is, the switch transistor PSW1 at the final stage of the voltage step-down circuit VDC as the switch SW1, the number of circuit components is reduced as a whole, which is advantageous in terms of cost.

(Embodiment 6)
FIG. 25 is a timing chart illustrating the switch operation of the high-speed power supply setup according to the sixth embodiment of the present invention.

  Here, as an example, the configuration shown in FIG. 23 will be described as an example. That is, a configuration in which a P-channel MOS transistor and an N-channel MOS transistor are respectively provided on the power supply side and the ground side will be described. In this example, power is supplied to the jth MRAM module 16-j (specific MRAM module) at a high speed, and the other nth MRAM modules 16-n are later than that. Power supply shall be executed.

  First, the power supply voltage Vcc1 is turned on at time T0 (power on). At time T1, “H” level signals are input to the gates of the switches SWTj and SWTjg, respectively. In this case, an “L” level signal is input to the gates of the switches SWTn and SWTng. Accordingly, switch SWTj is off, but switch SWTjg is turned on, and internal ground line IGLj is electrically coupled to ground voltage GND. The switch SWTn is on, but the switch SWTng is off. Therefore, the relationship between the j-th MRAM module 16-j and the n-th MRAM module 16-n has the configuration described in FIG.

  Next, at time T2, an “L” level signal is input to the gate of the switch SWTj. Accordingly, the switch SWTj is turned on, the internal power supply line IVLj and the power supply line VL1 are electrically coupled, and power supply is executed at high speed to the MRAM module 16-j. Thereafter, at time T3, an “H” level signal is input to the gate of the switch SWTng, and power is supplied to the nth MRAM module 16-n. Although not shown, the MRAM module 16-n is not shown. Is the active period.

  Note that the control signal Enable is input to the MRAM module 16-j during the active period up to time T4 when the "H" level signal is input to the gate of the switch SWTj. After time T4, the sleep period is once again set until the “L” level signal is input to the gate of the switch SWTj. After the input, the active period is set again.

  Although not shown in FIG. 21, it is assumed that a power supply capacity or a ground capacity is added to the internal power supply line IVL and the internal ground line IGL, respectively. Then, in the same way as the capacity C1g = C2 >> C1 = C2g described in FIG. 18, the power capacity and the ground capacity of the jth and nth MRAM modules are set to have the same relationship. Can perform high-speed power supply by operating the switch at the predetermined timing. That is, the power supply lines IVLj and IVLn and the ground lines IGLj and IGLn effectively contribute as decoupling capacities, and the charge / discharge capacities at the time of power supply selection are reduced, so that the power supply setup can be executed at high speed.

  Here, the j-th MRAM module has been described as being given the highest priority. However, this information stores, for example, an initialization program at power-on, adjustment data such as DC tuning, or memory redundancy relief information. It is assumed that the information is stored in the boot area. When the power is turned on, first, information on the highest priority MRAM module is read from the boot area and stored in the register. When the information is read next time, the information stored in the register is used. This makes it possible to specify the MRAM module having the highest priority.

(Modification of Embodiment 6)
In the sixth embodiment, the configuration in which the j-th MRAM module is given the highest priority for the switching operation of the high-speed power supply setup has been described. Here, a case where the MRAM module having the highest priority is changed will be described.

  FIG. 26 is a timing chart illustrating the switch operation of the high-speed power supply setup according to the modification of the sixth embodiment of the present invention. Here, it is assumed that the jth MRAM module 16-j is accessed with the highest priority first, and the kth MRAM module 16-k is accessed with the highest priority during the next cycle.

  Referring to FIG. 26, time T0 to T4 is the same as FIG. Specifically, the power supply voltage Vcc1 is turned on at time T0 (power on). At time T1, “H” level signals are input to the gates of the switches SWTj and SWTjg, respectively. In this case, “L” level signals are respectively input to the gates of the switches SWTn, SWTng and SWTk, SWTkg. Accordingly, switch SWTj is off, but switch SWTjg is turned on, and internal ground line IGLj is electrically coupled to ground voltage GND. The switches SWTn and SWTk are on, but the switches SWTng and SWTkg are off. Therefore, the relationship between the j-th MRAM module 16-j and the n-th MRAM module 16-n or the k-th MRAM module 16-k has the configuration described in FIG.

  Next, at time T2, an “L” level signal is input to the gate of the switch SWTj. Accordingly, the switch SWTj is turned on, the internal power supply line IVLj and the power supply line VL1 are electrically coupled, and power supply is executed at high speed to the MRAM module 16-j. Then, at time T3, an “H” level signal is input to the gates of the switches SWTng and SWTkg, and power is supplied to the nth and kth MRAM modules 16-n and 16-k. Although not shown, the MRAM modules 16-n and 16-k are in an active period.

  Note that the control signal Enable is input to the MRAM module 16-j during the active period up to time T4 when the "H" level signal is input to the gate of the switch SWTj. In addition, after time T4, it becomes a sleep period. Then, power supply is executed with priority given to the k-th MRAM module 16-k. Specifically, at time T5 after time T4, an “L” level signal is input to the gates of switches SWTjg and SWTj. An “H” level signal is input to the gates of the switches SWTkg and SWTk. Further, an “L” level signal is input to the gates of the switches SWTng and SWTn.

  Accordingly, the switch SWTjg is turned off and the SWTj is turned on. Further, the switch SWTkg is on and the SWTk is off. Further, the switch SWTng is off and SWTn is on. Therefore, the relationship between the k-th MRAM module 16-j and the j-th MRAM module 16-j or the n-th MRAM module 16-n has the configuration described in FIG.

  At time T6, an “L” level signal is input to the gate of the switch SWTk. Along with this, the switch SWTk is turned on, the internal power supply line IVLk and the power supply line VL1 are electrically coupled, and power supply is executed at high speed to the MRAM module 16-k. Then, at time T7, an “H” level signal is input to the gates of the switches SWTjg and SWTng, and power is supplied to the j and nth MRAM modules 16-j and 16-n. Although not shown, the MRAM modules 16-n and 16-k are in an active period.

  As for the change of the priority MRAM module, information on the highest priority MRAM module is read into the boot area and stored in the register. Further, information on the MRAM module having the next highest priority is read from the boot area, and the information stored in the register is updated. Then, based on the updated information stored in the register, the highest priority MRAM module is identified, and the signal input given to the corresponding switch SWT is controlled. The input timing of the signal is executed by the CPU.

  In the above embodiment, the MRAM module using the TMR element has been described as an example. However, the present invention is not limited to this and can be similarly applied to other nonvolatile memories.

  Further, the memory cell of the MRAM module is not limited to the tunnel magnetoresistive element TMR conforming to the above data writing method, and a memory cell conforming to another data writing method such as a spin torque switching cell may be employed.

  In the above configuration, the embedded memory with a built-in processor has been described.

  In the above-described embodiment, the case where one MRAM module to which power supply is preferentially executed has been described. However, the present invention is not limited to this, and priority is given to an MRAM module group including a plurality of MRAM modules. It is also possible to adopt a configuration in which power supply is executed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 chip, 5 CPU, 10 RAM, 15 ROM, 16 MRAM module, 20 controller unit, 21, 23 power supply capacity, 22 ground capacity, 30 memory cell array, 31 address decoder / write current driver, 32 data read system circuit / sense Amplifier, 33 Data I / O system circuit, 34 Control system peripheral circuit, 35 Voltage generation circuit.

Claims (1)

A memory array having memory cells for storing data in a nonvolatile manner ;
A plurality of circuit blocks for performing data reading and data writing of data stored in the memory array;
A power line provided corresponding to the plurality of circuit blocks and supplying a driving voltage of the corresponding circuit block;
A plurality of switches provided corresponding to the plurality of circuit blocks, respectively, for controlling an electrical connection with the power supply line to supply the driving voltage;
At least one circuit block of the plurality of circuit blocks has a power supply capacity larger than other circuit blocks,
A nonvolatile memory device that turns on a switch corresponding to the at least one circuit block before a switch corresponding to another circuit block when power is turned on .

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