JP5205803B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a plurality of circuits are formed on a semiconductor substrate.

Conventionally, a level shift circuit that shifts the amplitude center of a signal is known (see, for example, Patent Document 1). This level shift circuit receives an input signal from the first operational amplifier, and generates an output signal in which the amplitude center is shifted by the subsequent operational amplifier.
In this case, the dynamic range required for the first operational amplifier is different from the dynamic range required for the subsequent operational amplifier.
JP 2002-344258 A

By the way, when the level shift circuit described above is configured by a semiconductor device such as an integrated circuit, the breakdown voltage of the semiconductor device is set to exceed a voltage between the maximum value and the minimum value of the dynamic range in at least the first-stage and subsequent-stage operational amplifiers. There is a need to.
That is, when a plurality of circuits having different dynamic ranges are formed in one integrated circuit, it is necessary to set a withstand voltage so that all the circuits can operate. For this reason, when the dynamic range of each circuit is greatly different, there is a problem that it cannot be incorporated into one integrated circuit due to restrictions on the semiconductor process. Alternatively, an integrated circuit has to be formed using a semiconductor process having a higher breakdown voltage.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for forming a plurality of circuits that operate at different power supply voltages on the same semiconductor substrate.

In order to solve the above-described problem, a semiconductor device according to the first aspect of the present invention includes one of a P-type conductivity and an N-type conductivity type as a first conductivity type (for example, P-type) and the other as a second conductivity type ( For example, N type), a first region and a second region are formed on the first conductivity type semiconductor substrate, and the first semiconductor element formed in the first region ( For example, 22, 32, and 42 shown in FIG. 2, the first well of the first conductivity type formed in the second region (for example, 50 shown in FIG. 2), and formed in the second region. A second well of the second conductivity type for electrically separating the first well and the semiconductor substrate (for example, 60 shown in FIG. 2), a second semiconductor element formed in the first well ( For example, 52 shown in FIG. 2), a first circuit formed of the first semiconductor element (for example, the circuit shown in FIG. 2). In A), but the first semiconductor element and the second semiconductor element, and the second circuit formed by the second semiconductor element (e.g., comprising a circuit B) and shown in FIG. 2, the said second well semiconductor The potential of the semiconductor substrate and the potential of the second well are set so that the substrate is reverse-biased. The power supply voltage of the first circuit is composed of a first power supply potential and a second power supply potential. The power supply voltage of the two circuits is composed of a third power supply potential and a fourth power supply potential, supplies the second power supply potential to the semiconductor substrate, supplies the third power supply potential to the second well, The power supply voltage of the circuit and the power supply voltage of the second circuit overlap in the range from the third power supply potential to the second power supply potential, and the signal transmitted between the first circuit and the second circuit The level is from the third power supply potential to the second power supply potential. Characterized in that it is set to be enclosed.

  According to the present invention, since the semiconductor substrate and the first well can be electrically separated by the second well, the breakdown voltage of the second semiconductor element can be set independently of the first semiconductor element. As a result, even if the withstand voltage of the first semiconductor element is defined by the power supply voltage of the first circuit, it does not affect the withstand voltage of the second semiconductor element, so the power supply voltages of the first circuit and the second circuit can be made different. it can. That is, when the voltage from the maximum value to the minimum value of the power supply voltage of the first circuit and the second circuit is the applied voltage, the withstand voltage of the first semiconductor element is larger than the power supply voltage of the first circuit and smaller than the applied voltage. The breakdown voltage of the second semiconductor element is larger than the power supply voltage of the second circuit and smaller than the applied voltage. Accordingly, a plurality of circuits having different power supply voltages can be incorporated into the semiconductor device with a low withstand voltage process. The first semiconductor element may be formed of only P-type semiconductor elements, only N-type semiconductor elements, and P-type and N-type semiconductor elements.

Further, in this invention, the second well and said semiconductor substrate to set the potential of the potential of the semiconductor substrate and the second well to be reverse biased. Thereby, since no current flows between the semiconductor substrate and the second well, both can be electrically separated.

The power supply voltage of the first circuit includes a first power supply potential and a second power supply potential, and the power supply voltage of the second circuit includes a third power supply potential and a fourth power supply potential. supplying said second power supply potential, for supplying the third power supply potential to the second well. As a result , the second well and the semiconductor substrate are reverse-biased with the power supply potential supplied to the first circuit and the second circuit, so that no special power supply is required.

Further , the power supply voltage of the first circuit and the power supply voltage of the second circuit overlap in a range from the third power supply potential to the second power supply potential, and between the first circuit and the second circuit. level of the transmitted signal, Ru is set to be in the range from the third power supply potential to the second power supply potential.
Since the signal level to be transmitted is set in a range where the power supply voltages overlap, the signal can be transferred within the range of withstand voltage allowed for the transistors constituting the first circuit and the transistors constituting the second circuit.

  In the semiconductor device described above, the first semiconductor element includes the first transistor of the first conductivity type and the second transistor of the second conductivity type, and the second semiconductor element includes the second conductivity type. The transistors included in the first circuit are the first transistor and the second transistor, and the transistors included in the second circuit are the first transistor and the third transistor. Is preferred. In this case, the first circuit and the second circuit can be composed of CMOS.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an example of a circuit configuration to which the present invention is applied. FIG. 1A shows an outline of a circuit, and FIG. 1B shows an example of generation of a voltage supplied to the circuit. This circuit functions as a level shift circuit of a headphone amplifier, for example.

  As shown in FIG. 1A, the level shift circuit includes a signal input terminal In, a signal output terminal Out, an operational amplifier OpAmp, an inverting amplifier InvAmp, and resistors R1 to R4. That is, this circuit includes two amplifiers, an operational amplifier OpAmp and an inverting amplifier InvAmp. The operational amplifier OpAmp is supplied with + Vs and −Vs as driving power supplies. The inverting amplifier InvAmp is supplied with Vd as a driving power supply, and the other power supply terminal is grounded to GND. That is, the power supply voltage range of the operational amplifier OpAmp is −Vs to + Vs, and the power supply voltage range of the inverting amplifier InvAmp is 0 to Vd. These power supply voltages have the following relationship. Vd> + Vs> GND> −Vs.

  Here, the positive polarity + Vs supplied to the operational amplifier OpAmp is a voltage value smaller than Vd supplied to the inverting amplifier InvAmp, and the negative polarity −Vs supplied to the operational amplifier OpAmp is supplied to the operational amplifier OpAmp. It is assumed that the positive polarity is equal to + Vs. These power supply voltages can be supplied, for example, in a configuration as shown in FIG. That is, Vd is used as the external power supply voltage, and this voltage is supplied to the inverting amplifier InvAmp. Also, Vd is stepped down to + Vs using the step-down regulator 100 or the like, and used as the positive power supply voltage of the operational amplifier OpAmp. Furthermore, −Vs having the opposite polarity is generated from + Vs using the charge pump 110 or the like, and is used as the negative power supply voltage of the operational amplifier OpAmp. However, another external power source may be used without generating + Vs from Vd.

In this level shift circuit, it is assumed that an input AC signal Vin having an amplitude center at the voltage Vref is applied to the input terminal In. In this case, assuming that the amplitude center of the output AC signal Vout of the operational amplifier OpAmp is Vx, the voltage V1 of the positive input terminal of the operational amplifier OpAmp is given by the following equation (1), and the negative input terminal of the operational amplifier OpAmp is The voltage V2 is given by the following equation (2).
V1 = (Vref−Vin) R3 / (R3 + R4) (1)
V2 = (Vref + Vin- (Vout + Vx)) R2 / (R1 + R2) + (Vout + Vx)
...... Formula (2)
Here, if R1 = R2 = R3 = R4, the amplification factor of the level shift circuit is -2, and an imaginary short circuit is established in the operational amplifier OpAmp. Therefore, Vout + Vx is expressed by Equation (1) and Equation (2) as follows: It is given by the following equation (3).
Vout + Vx = -2Vin ... Formula (3)
That is, Vx = 0, and the AC output signal Vout becomes a signal centered on the ground potential GND (= 0V) by level-shifting the input AC signal Vin. As a result, the AC input signal Vin can be level shifted without using a coupling capacitor. By this level shift, even if the output signal of the operational amplifier OpAmp is directly connected to the speaker, no DC voltage is applied to the speaker, so that the speaker can be protected.

Moreover, V1 and + Vs have the relationship of the following formula (4).
+ Vs>V1> 0 ...... Formula (4)
That is, signal transmission is performed in a range where the power supply voltage range (Vd to GND) of the inverting amplifier InvAmp and the power supply voltage range (+ Vs to −Vs) of the operational amplifier OpAmp overlap.

  The level shift circuit described above includes circuit portions that operate in different power supply voltage ranges, and is particularly applied to circuits formed on the same substrate. The present invention will be described in detail with a more specific configuration. The semiconductor device described below can be used as a circuit that forms part of the amplifier shown in FIG. In this embodiment, a CMOS (Complementary-Metal-Oxide-Semiconductor) widely used as a basic circuit of a semiconductor device is taken as an example, but the present invention can also be applied to other circuits.

  FIG. 2 is a cross-sectional view schematically showing the structure of the semiconductor device of this embodiment. The semiconductor device shown in FIG. 2 includes a first region AA and a second region BB on a P-type semiconductor substrate 10. A circuit A and a part of the circuit B are formed in the first area AA, and the other part of the circuit B is formed in the second area BB. The circuit A is a part of the inverting amplifier InvAmp shown in FIG. 1, and the circuit B is a part of the operational amplifier OpAmp shown in FIG. Further, Vd = 5.5V, + Vs = + 2.75V, and -Vs = -2.75V. The circuit A operates with a power supply voltage of 5.5V-GND, and the circuit B operates with a power supply voltage of ± 2.75V. Thus, the circuit A and the circuit B operate with different power supply voltages. Each circuit is composed of CMOS, and an equivalent circuit is as shown in FIG.

  That is, in the circuit A, a P-type MOS 22 whose source and substrate are connected to a 5.5 V power source and an N-type MOS 32 whose source and substrate are grounded to GND are connected in series. A common gate signal IN_A is input, and the drain voltages of the P-type MOS 22 and the N-type MOS 32 are output as OUT_A.

  In the circuit B, a P-type MOS 42 whose source and substrate are connected to a 2.75V power source and an N-type MOS 52 whose source and substrate are grounded to a -2.75V power source are connected in series. Yes. The common gate signal IN_B is input, and the drain voltages of the P-type MOS 42 and the N-type MOS 52 are output as OUT_B.

  Returning to FIG. The P-type MOS 22 of the circuit A is formed in an N well 20 formed on the P-type substrate 10. A voltage of 5.5 V is applied to the N well 20 through the well contact layer 24. This voltage is also applied to the source of the P-type MOS 22. The N-type MOS 32 of the circuit A is formed in a P-well 30 formed on the P-type substrate 10. However, the P well 30 may not be formed, or may be formed with an impurity concentration different from the impurity concentration of the P-type substrate 10. The P well 30 is grounded to the GND via the well contact layer 34. Similarly, the source of the N-type MOS 32 is also grounded to GND. As a result, the P-type substrate 10 is grounded to GND. In this case, a parasitic diode is attached between the P-type substrate 10 and the N well 20, but no current flows because it is reverse-biased. It is the gates of the P-type MOS 22 and the N-type MOS 32 that have the greatest problem with the breakdown voltage in the circuit A structure. In this example, the amplitude of the gate signal IN_A is assumed to be 5.5 V-GND which is the power supply voltage of the circuit A. Therefore, the gate oxide film is designed to have a withstand voltage of 5.5V.

  The P-type MOS 42 of the circuit B is formed in an N well 40 formed on the P-type substrate 10. A voltage of 2.75 V is applied to the N well 40 via the well contact layer 44. This voltage is also applied to the source of the P-type MOS 42. A parasitic diode is also attached between the P-type substrate 10 and the N-well 40, but no current flows because it is reverse-biased.

  The N-type MOS 52 of the circuit B is formed in the P-well 50 formed inside the N-well 60 formed on the P-type substrate 10. That is, the N-type MOS 52 of the circuit B has a triple well structure. The N well 60 is composed of the Deep_N well 60a, the N well 60b, and the N well 60c in the cross-sectional view. However, this is a problem in the manufacturing process and may be regarded as a single N well 60.

A voltage of 2.75 V is applied to the N well 60 via the well contact layer 64. A voltage of −2.75 V is applied to the P well 50 via the well contact layer 54. This voltage is also applied to the source of the N-type MOS 52. A parasitic diode is also attached between the P-type substrate 10 and the N-well 60, but no current flows because it is reverse-biased. The N well 60 can electrically isolate the P well 50 biased to −2.75 V and the P type substrate 10 biased to GND.
It is the gates of the P-type MOS 42 and the N-type MOS 52 that have the greatest problem with the breakdown voltage in the structure of the circuit B. In this example, the amplitude of the gate signal IN_B is assumed to be ± 2.75 which is the power supply voltage of the circuit B. Therefore, the gate oxide film is designed to have a withstand voltage of 5.5V.

  In addition, as shown in FIG.1 (b), the voltage applied respectively can be produced | generated as follows, for example. That is, 5.5 V is used as the power supply voltage and applied to the P-type MOS 22 of the circuit A. This power supply voltage 5.5V is stepped down to 2.75V by a step-down regulator such as a series regulator and used as a voltage applied to the P-type MOS 42 of the circuit B. Further, -2.75V is generated from 2.75V using a charge pump or the like and used as a voltage to be applied to the N-type MOS 52 of the circuit B. However, the present invention is not limited to this method. For example, a separate power source may be used for 5.5V and 2.75V.

  As shown in FIG. 2, according to the present embodiment, the P well 50 in which the N type MOS 52 is formed is electrically separated from the P type substrate 10 by the N well 60. Therefore, the substrate potential of the N-type MOS 52 can be set uniquely, and circuits having different power supply voltages can be formed on the same semiconductor substrate. Specifically, the circuit A and the circuit B formed on the same semiconductor substrate can have different power supply voltages, or circuits with different breakdown voltages can be used. Furthermore, a voltage having a polarity opposite to the power supply voltage can be applied to one circuit.

  FIG. 4 is a plan view schematically showing the mask layout of the semiconductor device shown in FIG. The cross-sectional view of FIG. 2 corresponds to a cross section taken along the line A-A ′ of FIG. In this figure, the same reference numerals are given to the same objects as those in FIG. This figure also shows that a P-well 50 is formed in an N-well 60, and further an N-type MOS 52 is formed.

In this embodiment, the Deep_N well is formed on the P-type substrate, and the P-well formed in the Deep_N well is electrically separated from the P-type substrate. However, the Deep_P well is formed on the N-type substrate. The N well formed in the Deep_P well may be electrically separated from the N-type substrate. Moreover, the power supply voltage of this embodiment is an example and this invention is not limited to these.
Note that the inverting amplifier InvAmp including the circuit A and the operational amplifier OpAmp including the circuit B perform signal transmission in a range where the power supply voltages overlap as described above, so that the withstand voltage of the circuit A or the circuit B is increased by signal transmission. Is not exceeded.

It is a block diagram which shows an example of the circuit to which this invention is applied. It is sectional drawing which shows the structure of the semiconductor device which concerns on this embodiment typically. 3 is an equivalent circuit of a circuit formed in a semiconductor device. It is a top view which shows the outline of the mask layout of the semiconductor device which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Substrate, 20 ... N well, 22 ... P type MOS, 24 ... N well contact layer, 30 ... P well, 32 ... N type MOS, 34 ... P well contact layer, 40 ... N well, 42 ... P type MOS 44 ... N well contact layer, 50 ... P well, 52 ... N type MOS, 54 ... P well contact layer, 60 ... N well, 64 ... N well contact layer, 100 ... step-down regulator, 110 ... charge pump

Claims (2)

A semiconductor in which a first region and a second region are formed on a semiconductor substrate of the first conductivity type when one of P-type and N-type conductivity is a first conductivity type and the other is a second conductivity type. A device,
A first semiconductor element formed in the first region;
A first well of the first conductivity type formed in the second region;
A second well of the second conductivity type formed in the second region for electrically separating the first well and the semiconductor substrate;
A second semiconductor element formed in the first well;
A first circuit formed of the first semiconductor element;
The first semiconductor element and the second semiconductor element, or a second circuit formed of the second semiconductor element,
A potential of the semiconductor substrate and a potential of the second well are set so that the second well and the semiconductor substrate are reverse-biased;
The power supply voltage of the first circuit is composed of a first power supply potential and a second power supply potential,
The power supply voltage of the second circuit is composed of a third power supply potential and a fourth power supply potential,
Supplying the second power supply potential to the semiconductor substrate;
Supplying the third power supply potential to the second well;
The power supply voltage of the first circuit and the power supply voltage of the second circuit overlap in a range from the third power supply potential to the second power supply potential,
A level of a signal transmitted between the first circuit and the second circuit is set to be in a range from the third power supply potential to the second power supply potential;
A semiconductor device. The first semiconductor element includes a first transistor of the first conductivity type and a second transistor of the second conductivity type,
The second semiconductor element includes a second transistor of the second conductivity type,
The transistors included in the first circuit are the first transistor and the second transistor,
The transistors included in the second circuit are the first transistor and the third transistor.
The semiconductor device according to claim 1 .

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