JP5203578B2 - Data transfer device - Google Patents

Description

  The present invention relates to a data transfer device, and more particularly to a technique for transferring data without error between a plurality of input / output circuits.

  In a computer having a plurality of processors, data transfer between processors must be performed without error. For this purpose, each processor includes an input / output circuit for processing data signals to be input / output. In such a data transfer apparatus, a plurality of processors are connected to a common transmission line via an input / output circuit. When data is transferred from one processor to another processor, the input / output circuit of the transfer source processor is an output circuit, and the input / output circuit of the transfer destination processor is an input circuit. When the transfer source and transfer destination processors are switched, the input / output circuit is switched to the output circuit or the input circuit accordingly.

  Each input circuit compares the level of the input data signal with a preset reference voltage (threshold), shapes the waveform, and transfers it to a circuit inside the processor. If the setting of the reference voltage at this time is inappropriate, data is erroneously identified and a transfer error occurs. Therefore, the value of the reference voltage should be set so as to obtain a wider margin in consideration of the state of the transmission signal.

  For example, Patent Document 1 discloses a transmission apparatus that aims to make an input signal versatile and automatically set an optimum point for discrimination determination with high accuracy. Here, the voltage threshold level and clock phase are sequentially swept with respect to the input signal, and the identification point with the lowest error occurrence within the effective area of the eye pattern is automatically measured. Is set to control reproduction.

JP 2003-18140 A

  If the data transfer speed is low and the amplitude of the transmission signal is large, the operation margin is wide, and even if the setting of the reference voltage slightly deviates from the optimum value, it does not cause a problem that increases transfer errors. However, in recent processors, the data transfer speed has been increased with the increase in the operating frequency, and the signal amplitude tends to be reduced accordingly. When the operation margin is thus narrowed, unless the setting of the reference voltage is appropriately set with higher accuracy, data identification is erroneous and erroneous data is transferred to the processor.

  In the data transfer apparatus, the input / output characteristics of the plurality of input / output circuits are not necessarily the same. In particular, the optimum value of the reference voltage when operating as an input circuit is not always the same. This is because the input characteristics of each input / output circuit are affected by variations due to manufacturing processes, power supply voltage fluctuations, temperature fluctuations, and the like, and the optimum values of the respective reference voltages may differ.

  Furthermore, since data is transferred between a plurality of processors (a plurality of input / output circuits), there are various combinations of transfer source and input / output circuits, and the distance between the transmission paths. Is not constant. Therefore, the state of signal degradation in the transmission path is not uniform depending on the combination of the input / output circuits, and the optimum value of the reference voltage of each input / output circuit must be set accordingly.

  In Patent Document 1, a technique for setting an optimum point for reproduction control in one transmission system is disclosed, but the problem in the data transfer apparatus including a plurality of input / output circuits as described above is not considered.

  Conventionally, an operation margin test has been performed in order to confirm whether the already set reference voltage is appropriate and whether there is a margin with respect to the upper and lower limits of the reference voltage. As a result of the operation margin test, when it is found that the reference voltage is not properly set, the reference voltage is corrected by replacing circuit components. Such margin testing and parts replacement are manual operations, which are inefficient and require improvement.

  An object of the present invention is to solve the above-described conventional problems and reduce the occurrence of transfer errors in a data transfer apparatus that transfers high-speed data signals between a plurality of input / output circuits. Furthermore, the reference voltage of each input / output circuit is automatically set optimally.

The present invention relates to a data transfer device that connects a plurality of data processing devices to a common transmission line via an input / output circuit and transfers data between the data processing devices. A comparator that receives a test signal from the processing unit and determines whether or not the input / output circuit has received it correctly, and a reference voltage that is used as a reference when the signal is input to the input / output circuit. And a reference voltage control circuit that obtains an optimal reference voltage for correctly receiving and stores the reference voltage in a storage unit according to the result. The reference voltage control circuit is configured to obtain an optimum value of the reference voltage for each data processing device as a data transmission source and store it in the storage unit.

  Here, the reference voltage control circuit changes the reference voltage stepwise with respect to the test signal transmitted from each data processing device, and sets the optimum value of the reference voltage so that the operation margin for correctly receiving the test signal is maximized. Set.

  Each data processing device includes a flag generator that generates a flag signal unique to the device, and the data processing device of the transmission source adds the flag signal from the flag generator to the data and transfers it. The data processing device on the receiving side identifies the transmission source data processing device from the flag signal received by the reference voltage control circuit, and reads and sets the reference voltage optimum value for the transmission source data processing device from the storage unit.

  According to the present invention, when a high-speed data signal is transferred between a plurality of input / output circuits, the reference voltage of each input / output circuit can be automatically set optimally to reduce the occurrence of a transfer error.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration block diagram showing an embodiment of a data transfer apparatus according to the present invention. The data transfer device 1 of this embodiment includes n data processing devices (processors) 10-1, 10-2,..., 10-n, which are respectively input / output circuits 101-1, 101-. 2,... 101-n are connected to a common transmission line (wiring) 130. Each input / output circuit operates as an output circuit that transfers data generated by each data processing device to another data processing device, and also operates as an input circuit that inputs data transferred from the other data processing device. Hereinafter, these operation modes are referred to as an output mode and an input mode, and an input / output circuit in such an operation state is referred to as an output circuit and an input circuit. At the time of data transfer between devices, one data processing device (input / output circuit) among n data processing devices (input / output circuits) is selected as an output mode, and another data processing device (input / output circuit) is selected. ) Is operated as an input mode. In the input mode, the waveform is shaped by comparing the level of the input signal with the reference voltage Vref. At this time, each reference voltage control circuit 102 sets a reference voltage Vref for each input / output circuit (input circuit) 101. The system control circuit 120 performs input / output switching control between devices, and controls switching of operation modes of each circuit in each data processing device 10.

  Each data processing device 10 has the following configuration (in the description of the reference numerals, the suffix for each device is omitted). The input / output control circuit 103 switches and controls whether the input / output circuit 101 is set to the output mode or the input mode.

  In the case of the output mode and the test transmission, the test pattern generator 106 generates a test signal Vtest. The test signal is used to determine the optimum value of the reference voltage Vref of the input / output circuit 101 in each of the other data processing devices 10, and each test pattern that generates a common signal in each data processing device 10. A generator 106 is included. In the case of normal data transmission, data Vdata calculated and generated by the data processing apparatus 10 is output from the normal data path 105. Further, the output flag generator 104 generates a unique flag signal Vflag that identifies the data processing apparatus 10. The selectors 107 and 108 switch the signal source and send it to the input / output circuit 101 depending on whether the transmission is test transmission or normal data transmission.

  When the test mode is received in the input mode, the input / output circuit 101 receives a test signal Vtest from another data processing apparatus. At that time, the reference voltage control circuit 102 receives the reference voltage Vref while changing it. Then, the signal passing through the input / output circuit 101 and the test signal generated by the test pattern generator 106 of the data processing apparatus are compared by the comparator 110 to determine whether the signal patterns match. As a result of the determination, an operation margin of the reference voltage Vref that can be correctly received is obtained, and an optimum value is determined and stored. Note that a time difference occurs between the two signals when making the comparison determination, so the timing is adjusted by the delay circuit 109. If the input mode is normal data reception, the data processor is identified from the received flag signal Vflag, and the reference voltage Vref is optimally set according to the transmission source. Subsequently, the data signal Vdata that has passed through the input / output circuit 101 is sent to the normal data path 111.

  In this embodiment, the test signal Vtest is transmitted from the test pattern generator 106 of one data processing device, and the comparator 110 determines whether or not the other data processing device has received it correctly. At that time, the reference voltage Vref of the input / output circuit (input circuit) 101 is changed to obtain the operation margin of the reference voltage that can correctly receive the test signal, and the optimum value Vropt of the reference voltage is determined for each input circuit on the receiving side. decide. Next, the test signal is transmitted by switching the data processing device on the transmission side to another device, and similarly, the optimum value Vropt of the reference voltage is determined for each input circuit on the reception side. In this manner, the optimum value Vropt of the reference voltage is determined for each data processing device (that is, output circuit) on the transmission side. In actual data reception, the transmission source data processing device (output circuit) is identified from the transmitted flag signal, and the reference voltage is set to the optimum value Vropt accordingly.

  Here, as an example, a case where the test signal Vtest is transmitted from the data processing device 10-1 to the other data processing devices 10-2,..., 10-n and the reference voltage optimum value Vropt of each input circuit is determined. explain.

  First, the input / output control circuit 103-1 sets the input / output circuit 101-1 as an output circuit, and the input / output control circuits 103-2,..., 103-n are input / output circuits 101-2,. 101-n is set as the input circuit. The data processing apparatus 10-1 outputs a test signal Vtest from the test pattern generator 106-1, and the selector 108-1 selects it. The test signal passes through the input / output circuit (output circuit) 101-1 and is transmitted to the transmission line 130. The transmitted test signal is received by input / output circuits (input circuits) 101-2,..., 101-n of each data processing device.

  Here, attention is focused on the data processing apparatus 10-2. The test signal Vtest is received by the input circuit 101-2, waveform shaping is performed based on the set reference voltage Vref, and the test signal Vtest ′ is obtained. The test signal Vtest ′ is sent to the comparator 110-2. The comparator 110-2 compares the received test signal Vtest 'with the test signal Vtest from the test pattern generator 106-2. Here, since the test pattern generator 106-2 outputs the same test signal as the transmission source test pattern generator 106-1, it can be used as a reference for comparison. The delay circuit 109-2 delays the test signal Vtest from the test pattern generator 106-2 and matches the timing of the test signal Vtest 'that has passed through the input circuit 101-2. If the comparator 110-2 confirms that the patterns of the test signals Vtest ′ and Vtest match, the input circuit 101-2 determines that the test signal has been correctly received, and sets the current reference voltage Vref. Judge that there is no problem. Similarly, in the other input circuits 101-3,..., 101-n, it is determined whether there is no problem in setting the reference voltage Vref.

  Thereafter, the reference voltage Vref is changed and set in each input circuit 101 to determine whether or not the test signal is correctly taken. In this way, the operation margin of the reference voltage that can correctly receive the test signal is obtained, and the reference voltage optimum value Vropt of each input circuit is determined. Further, the data processing device that transmits the test signal is switched to another device, and the reference voltage optimum value Vropt is determined for each data processing device on the transmission side.

  Next, after obtaining the reference voltage optimum value Vropt, normal data transfer is executed. As an example, a case where data is transmitted from the data processing device 10-1 to the other data processing devices 10-2,..., 10-n will be described.

  In the data processing device 10-1, the output flag generator 104-1 generates a flag signal Vflag specific to the device 10-1. The data path 105-1 outputs the data signal Vdata generated by the device 10-1. The selector 107-1 combines both signals (for example, adds a flag signal Vflag to the header portion of the data signal Vdata), and sends it to the output circuit 101-1 via the selector 108-1. The output circuit 101-1 adjusts the signal level as necessary and transmits it to the transmission line 130.

  The data signal Vdata transmitted to the transmission line 130 is received by the input circuits 101-2,..., 101-n of the data processing devices 10-2,. For example, the input circuit 101-2 extracts the flag signal Vflag added to the input data signal and sends it to the reference voltage control circuit 102-2. The reference voltage control circuit 102-2 identifies that the transmission source is the data processing device 10-1 from the received flag signal Vflag, and sets a reference voltage optimum value Vropt suitable for the data processing device 10-1. Then, the data signal Vdata is received from the input circuit 101-2 and sent to the normal data path 111-2, which is processed by the data processing device 10-2. The other data processing device 10-n receives the same.

  In this way, each input circuit not only sets the optimum value of the reference voltage according to its input characteristics, but can also set the optimum value of the reference voltage according to the data transmission source device (output circuit). it can. Therefore, even if the characteristics of each input circuit, each output circuit, and the transmission path in the data transfer device are different, it is possible to always receive signals in an optimal state and reduce transfer errors. Further, since the operation margin test for setting the reference voltage and the optimum setting of the reference voltage are automated, the work efficiency can be greatly improved.

  FIG. 2 is a diagram showing an internal configuration of the input circuit and the reference voltage control circuit in the data transfer apparatus of FIG. Input data Vin (test signal Vtest and normal data Vdata) is input to the comparator 207 of the input circuit 206, the level is determined using the reference voltage Vref as a threshold value, the waveform is shaped, and output data Vout is output. The reference voltage Vref is given by dividing the DC voltage 201 by the variable resistors 202 and 203, but the reference voltage control circuit 205 changes the reference voltage Vref by controlling the resistance values of the variable resistors 202 and 203. As the variable resistors 202 and 203, for example, a plurality of resistors may be connected in parallel and switched by a switch connected in series to each resistor. Although the storage unit 208 stores the reference voltage optimum value Vropt for each output circuit of the transmission source, it may be stored as the resistance values of the variable resistors 202 and 203.

  By using the circuit shown in FIG. 2, a margin test of the reference voltage can be performed and set to an optimum value. The test signal Vtest is supplied as the input data Vin, the variable voltage 202, 203 is controlled by the reference voltage control circuit 205 and the reference voltage Vref is changed and set, and the test signal Vtest ′ that has passed through the input circuit 206 is determined. . If the signal Vtest ′ is correct as a result of the determination, the set reference voltage is not a problem. In this way, the optimum value is determined from the allowable operation margin (maximum value and minimum value) of the reference voltage, and stored in the storage unit 208. Thereafter, when receiving normal data, the reference voltage control circuit 205 identifies the device that is the transmission source from the flag signal Vflag, reads the optimum value Vropt stored for each transmission source from the storage unit 208, and sets it as the reference voltage Vref. To do.

  FIG. 3 is a schematic diagram showing a waveform shaping operation in the input circuit. The input voltage Vin is compared with the reference voltage Vref, and the waveform is shaped to obtain the output voltage Vout. If the amplitude of the input voltage Vin is large (in the case of Vin1), the output voltage Vout1 does not shift in data period. However, when the data transfer rate of the input voltage Vin increases and the signal amplitude decreases, the reference voltage Vref for the input voltage deviates from an appropriate value (in the case of Vin2). As a result, the data cycle of the output voltage Vout2 varies, and the probability that an error will occur in the transfer data increases.

  The input characteristics of the input circuit are affected by variations due to manufacturing processes, power supply voltage fluctuations, temperature fluctuations, and the like. Therefore, when a plurality of input circuits are included, an optimum value of the reference voltage suitable for each must be set. Furthermore, the degree of deterioration of the quality of the input signal varies depending on the signal transmission source condition and the transmission path condition (distance). Therefore, when receiving signals from a plurality of transmission sources, an optimum value of the reference voltage must be set for each transmission source.

  FIG. 4 is a flowchart showing a procedure for obtaining an optimum reference voltage in each input circuit. The total number of input / output circuits is n, and a test signal (test pattern) is transmitted from one input / output circuit (output circuit) to another input / output circuit (input circuit). Each input circuit changes the reference voltage Vref step by step to obtain an operation margin of the reference voltage that can correctly receive the test signal, and determines an optimum value Vropt of the reference voltage therefrom. m is the number of the input / output circuit, and m = 1, 2,..., n. The reference voltage Vref is changed by adding V (k) (k is an integer) to the initial value Vro. Here, V (0) = 0,... <V (−2) <V (−1) <V (0) <V (1) <V (2) <.

  In response to a test start command (S401), m = 1 and k = 0 are set as initial values (S402). The input / output control circuit 103 sets the mth input / output circuit as an output circuit, and sets other input / output circuits as input circuits (S403). The reference voltage control circuit 102 (205) of each input circuit sets the reference voltage Vref to Vro + V (k) (S404). Next, a test pattern is transmitted from the output circuit m and received by each input circuit (S405). Each input circuit shapes the waveform of the input test pattern based on the reference voltage Vref. Then, the comparator 110 compares it with the test pattern from the test pattern generator 106, and determines that it has been received correctly if they match (S406).

  If there is an input circuit that has been correctly received (Yes in S407), the maximum value Vrmax of the reference voltage of the input circuit is updated with the current value Vro + V (k) and stored in the storage unit 208 (S408). Thereafter, k is updated to k + 1 (S409), and the process returns to S404. Subsequently, the reference voltage is increased to the next value Vro + V (k + 1) to check whether it can be received correctly in the same manner, and the reference voltage maximum value Vrmax is updated in the input circuit that has been correctly received. In this way, while increasing the reference voltage, the process is repeated until all input circuits cannot receive signals correctly. As a result, the storage unit 208 stores the reference voltage maximum value Vrmax of each input circuit.

  If all input circuits cannot receive correctly (No in S407), k = -1 is set (S410). This time, the reference voltage is set to be decreased from the initial value Vro (S411), a test pattern from the output circuit m is received (S412), and whether or not each input circuit has received correctly is checked (S413).

  If there is an input circuit that has been correctly received (Yes in S414), the minimum value Vrmin of the reference voltage of the input circuit is updated to the current value Vro + V (k) and stored (S415). Thereafter, k is updated to k−1 (S416), and the process returns to S411. Subsequently, the reference voltage is decreased to the next value Vro + V (k−1) to check whether it can be received correctly in the same manner, and the reference voltage minimum value Vrmin is updated in the input circuit that has been correctly received. In this way, while decreasing the reference voltage, it is repeated until all input circuits cannot receive correctly. As a result, the storage unit 208 stores the reference voltage minimum value Vrmin of each input circuit.

  When all the input circuits cannot receive correctly (No in S414), the reception of the test pattern from the output circuit m is terminated. If there is an input circuit for which the maximum value Vrmax and minimum value Vrmin of the reference voltage have not been obtained so far (No in S417), the input circuit is determined to be defective (S418). In each input circuit, the average value of the maximum value Vrmax and the minimum value Vrmin of the reference voltage is set as the reference voltage optimum value Vropt, and this value is stored in the storage unit 208 (S419).

  After completing the above, it is updated to m = m + 1 (S421), and the process returns to S403. Then, the next input / output circuit (m + 1) is used as an output circuit, and the reference voltage optimum value Vropt of each input / output circuit corresponding thereto is obtained. In this way, the test is repeated until all the input / output circuits are output circuits. When m = n, the test is terminated (S420, S422).

  FIG. 5 is a diagram illustrating the reference voltage values of the input circuits obtained as a result of the test signal reception. The storage unit 208 of each input circuit stores a reference voltage maximum value Vrmax, a reference voltage minimum value Vrmin, which is an operation margin, and a reference voltage optimum value Vropt obtained as an average of these for each output circuit of the transmission source. . And the reference voltage optimal value Vropt memorize | stored in the memory | storage part 208 is used as a reference voltage set in the case of normal data reception. The reference voltage optimum value Vropt is an average value of the reference voltage maximum value Vrmax and the minimum value Vrmin for simplicity, but is not limited thereto, and may be calculated as appropriate, such as a weighted average.

  FIG. 6 is a flowchart showing a procedure during normal data transfer. When data transfer is started (S601), a flag signal Vflag is transmitted from a transmission source device (output circuit) to another device (input circuit) among n data processing devices (input / output circuits) (S602). ). Each input circuit identifies which output circuit is the transmission source based on the received flag signal Vflag (S603). Then, the reference voltage optimum value Vropt for the identified output circuit is read and set from the reference voltage value (shown in FIG. 5) stored in the storage unit 208 (S604). Then, the data Vdata is transferred from the output circuit to each input circuit (S605). If there is a next data transfer from a different output circuit after the data transfer (Yes in S606), the process returns to S602 and the above operation is repeated. That is, the flag signal Vflag is transmitted from one of the next output circuits to another input circuit. Each input circuit sets a new reference voltage optimum value Vropt and receives data. According to this procedure, regardless of which input / output circuit becomes the output circuit, the other input circuits automatically set the optimum reference voltage to enable data reception.

  In addition to the above embodiment, by attaching a power supply voltage variable circuit, a frequency variable circuit, and a temperature variable device, it is possible to simultaneously perform an operation margin test on the reference voltage, power supply voltage, frequency, and temperature in the data transfer device. Then, a margin test with high accuracy can be performed by changing the power supply voltage, frequency and temperature.

1 is a configuration block diagram showing an embodiment of a data transfer apparatus according to the present invention. The figure which shows the internal structure of the input circuit and reference voltage control circuit in FIG. The schematic diagram which shows the waveform shaping operation | movement in an input circuit. The flowchart figure which shows the procedure which calculates | requires the optimal reference voltage in each input circuit. The figure which shows the reference voltage value of each input circuit obtained as a result of test signal reception. The flowchart figure which shows the procedure at the time of normal data transfer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data transfer apparatus 10 ... Data processing apparatus 101 ... Input / output circuit 102,205 ... Reference voltage control circuit 120 ... System control circuit 103 ... Input / output control circuit 106 ... Test pattern generator 104 ... Output flag generator 110 ... Comparator DESCRIPTION OF SYMBOLS 130 ... Transmission path 206 ... Input circuit 208 ... Memory | storage part Vref ... Reference voltage Vropt ... Reference voltage optimal value Vtest ... Test signal Vflag ... Flag signal.

Claims (2)

In a data transfer device that connects a plurality of data processing devices to a common transmission line via an input / output circuit and transfers data between the data processing devices,
Each data processing device receives a test signal from another data processing device, and a comparator for determining whether or not the input / output circuit has correctly received it,
A reference voltage control that provides a reference voltage as a reference at the time of signal input to the input / output circuit, and obtains an optimum reference voltage that can be correctly received in accordance with a determination result of the comparator and stores the reference voltage in a storage unit Circuit ,
A flag generator for generating a flag signal specific to each data processing device ;
The reference voltage control circuit obtains an optimum value of the reference voltage for each data processing device as a data transmission source and stores it in the storage unit ,
The data processing device of the transmission source adds the flag signal from the flag generator to the data and transfers it,
The data processing device on the receiving side identifies the transmission source data processing device from the flag signal received by the reference voltage control circuit, and reads and sets the reference voltage optimum value for the transmission source data processing device from the storage unit. A data transfer device. The data transfer device according to claim 1, wherein
The reference voltage control circuit changes the reference voltage stepwise with respect to the test signal transmitted from each of the data processing devices, and optimizes the reference voltage so that the operation margin for correctly receiving the test signal is maximized. A data transfer device characterized by setting a value.

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