JP5202456B2 - Test apparatus and test method - Google Patents

Description

  The present invention relates to a test apparatus, and more particularly to a test apparatus for a device under test that performs source-synchronous transmission.

  In recent years, DDR SDRAM using differential clocks (denoted as CK and CK #) has become widespread. The DDR SDRAM uses two-phase differential clocks CK and CK #, and performs data transfer using respective rising edges (hereinafter also referred to as positive edges). For this reason, compared with a single-data-rate (SDR) SDRAM that uses a single-phase clock CK instead of a differential clock, the rising edge and falling edge (hereinafter also referred to as negative edge) of the single-phase clock CK are apparently seen. Since both edges are used, the actual data transfer rate is doubled.

  Since DDR SDRAM transfers data twice as fast as SDR SDRAM, when using differential clocks CK and CK # as they are, if dynamic jitter is superimposed on them, accurate data transfer is possible. It becomes difficult. Therefore, a data strobe signal DQS that can use both edges when transferring the data signal DQ is added to the DDR SDRAM.

  The level of the data strobe signal DQS transitions at a timing just like the center point of the data signal in the write cycle from the driver to the memory. On the contrary, in the data read cycle from the memory to the driver, the level transitions at the same timing as the data signal DQ. The DDR SDRAM takes in the data signal DQ using the data strobe signal DQS instead of the reference clock, thereby enabling stable data transfer even with a high-speed operation clock. That is, in the DDR SDRAM, the timing of the data strobe signal DQS and the data signal DQ is important.

For example, Patent Document 1 discloses a test method using a multi-strobe signal. In this test method, the following processing is performed.
1. The reference clock is delayed to generate a multi-strobe signal having edges at predetermined intervals.
2. The values of the data signal DQ and the data strobe signal DQS are determined at the timing of each edge of the multi-strobe signal, the change point of the data signal DQ (edge position, hereinafter referred to as the first change point) and the change point of the data strobe signal DQS. The position of (hereinafter, the second change point) is acquired.
3. The phase difference between the first change point and the second change point is calculated. By calculating the phase difference, the influence of common mode jitter that is similarly attached to the data signal DQ and the data strobe signal DQS is removed.
4). It is determined whether the calculated phase difference is included in a predetermined specification.

JP 2004-127455 A

  In the technique described in Patent Document 1, it is necessary to make the phase coverage of the multi-strobe signal wider than the amount of output jitter from the device under test. For example, consider a case where 1 GHz DDR data and a cycle (unit interval) 500 ps width are detected. If the jitter of the data strobe signal DQS is 400 ps p-p, it is necessary to cover a phase range of at least 400 ps with respect to the data strobe signal DQS. For the data signal DQ, it is necessary to cover a phase range obtained by adding the jitter amount of 400 ps of the data strobe signal DQS to the unit interval 500 ps. That is, it is necessary to generate a multi-strobe signal so as to cover a very wide phase range. This causes problems such as an increase in circuit scale and power consumption in hardware that generates a multi-strobe signal. Such a problem is not limited to the DDR SDRAM, and may occur in various devices adopting a similar transmission method.

  The present invention has been made in view of such a situation, and one of the exemplary purposes of an aspect thereof is to be able to evaluate a phase difference between a data signal and a data strobe signal while suppressing an increase in circuit scale and power consumption. Providing test equipment.

  One embodiment of the present invention relates to a test apparatus for testing a device under test that performs source-synchronous transmission. The test apparatus generates a multi-strobe signal having a plurality of edges at predetermined time intervals based on the data strobe signal by giving a multistage delay to the data strobe signal output from the device under test. A strobe signal generation unit; a timing comparison unit that determines a value of a data signal at each of a plurality of edge timings of the multi-strobe signal; and generates timing data indicating a timing at which the value changes; and A logical comparison unit that determines whether the condition is satisfied.

  According to this aspect, since the multi-strobe signal MSTRB is generated based on the data strobe signal DQS, the phase difference between the data signal DQ and the data strobe signal DQS can be directly measured. That is, even when the jitter is large, an increase in circuit scale and power consumption can be suppressed.

  The device under test may be a DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory).

The test apparatus according to an aspect may further include a strobe signal generation unit that generates a reference strobe signal, and a selector that receives the data strobe signal and the strobe signal and selects one in accordance with a control signal. . The multi-strobe signal generation unit may generate the multi-strobe signal with reference to one selected by the selector.
In this mode, it is possible to switch to a mode in which a multi-strobe test is performed using a strobe signal generated inside the test apparatus, and the change timing of the data signal DS and the data strobe signal DQS is measured on the absolute time axis in the test apparatus. it can.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  The test apparatus according to the present invention can measure a device having a large jitter while suppressing an increase in circuit scale and power consumption.

It is a block diagram which shows the structure of the test apparatus which concerns on embodiment. 2 is a time chart showing an operation example in a first mode of the test apparatus of FIG. 1. 3 is a time chart showing an operation example in a second mode of the test apparatus of FIG. 1.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 1 is a block diagram showing a configuration of a test apparatus 2 according to the embodiment. The DUT 1 that is a DDR SRAM outputs m-bit (m is a natural number) data signals DQ _{1 to} DQ _m and a data strobe signal DQS. The test apparatus 2 receives the data signals DQ _{1 to} DQ _m and the data strobe signal DQS, determines whether or not standards such as setup time and hold time are satisfied based on these timings, and determines whether the DUT 1 is good or bad.

  The test apparatus 2 in FIG. 1 can be switched between the first mode and the second mode according to the mode control signal MODE. Here, the first mode is set when MODE = 1, and the second mode is set when MODE = 0.

  The test apparatus 2 includes a plurality of determination circuits 10 provided for each data signal DQ, level comparators 11a and 11b provided corresponding to the data signal DQ and the data strobe signal DQS, a phase adjustment unit 20, A strobe signal generator 30 and a logic comparison controller 40 are provided. Although not shown here, a similar determination circuit 10 may be provided for the data strobe signal DQS.

The high-side level comparator 11a compares the data signal DQ with a predetermined upper threshold voltage VOH. The output signal DQ_SH of the level comparator 11a is high level (1) when DQ> VOH, and low level (0) when DQ <VOH.
Similarly, the level comparator 11b compares the data strobe signal DQS with a predetermined upper threshold voltage VOH. The output signal DQS_SH of the level comparator 11b is high level (1) when DQ> VOH, and low level (0) when DQ <VOH.

The test apparatus 2 further includes a low-side level comparator (not shown) that compares the data signal DQ and the data strobe signal DQS with the lower threshold voltage VOL. On the low side, the output signal DQ_SL of the level comparator for the data signal DQ is high level (1) when DQ <VOL, and low level (0) when DQ> VOL. Similarly, an output signal of the level comparator for the data strobe signal DQS is also provided for the output signals (DQ_SL, DQS_SL) of the low-side level comparator.

  The phase adjustment unit 20 is provided after the level comparator 11. The phase adjustment unit 20 gives a delay to at least one of the output signal DQ_SH corresponding to the data signal DQ and the output signal DQS_SH corresponding to the data strobe signal DQS, so that the relative phase difference between the data signal DQ and the data strobe signal DQS is given. Adjust. By providing the phase adjustment unit 20, the difference between the propagation length of the data signal DQ and the propagation length of the data strobe signal DQS in the path from the DUT 1 to the test apparatus 2 can be calibrated. The phase adjustment unit 20 may be provided before the level comparator 11.

  The strobe signal generator 30 generates a strobe signal STRB. This strobe signal STRB is a reference pulse generated with reference to the test apparatus 2 and has a frequency synchronized with the test rate. The strobe signal STRB generated by the strobe signal generator 30 is used in a second mode to be described later.

  Determination circuits 10_1 to 10_m (hereinafter collectively referred to as determination circuit 10) are ASICs (Application Programmable ICs) having the same configuration. Each of the determination circuits 10_1 to 10_m determines whether the DUT 1 is good or bad, identifies a defective portion, and an error based on the change timing of the corresponding data signal DQ (DQ_SH / SL) and the change timing of the data strobe signal DQS (DQS_SH / SL). Measure the rate.

  Hereinafter, the configuration of the determination circuit 10_1 will be described as an example. The determination circuit 10 includes a multi-strobe signal generation unit 12, a timing comparison unit 14, a phase data conversion unit 16, a logic comparison unit 18, and a selector 32.

The selector 32 is provided to switch between the first mode and the second mode. The data strobe signal DQS that has been skew-adjusted by the phase adjustment unit 20 is input to the first terminal (1) of the selector 32. The strobe signal STRB generated by the strobe signal generator 30 is input to the second terminal (0) of the selector 32. The selector 32 selects the data strobe signal DQS at the first terminal (1) when the mode control signal MODE is 1, and selects the strobe signal STRB at the second terminal (0) when it is 0.
That is, the data strobe signal DQS_SH is supplied to the multi-strobe signal generator 12 in the first mode, and the strobe signal STRB_SH is supplied to the multi-strobe signal generator 12 in the second mode.

Hereinafter, in order to facilitate understanding, the description will be made with the first mode fixed.
The multi-strobe signal generator 12 has a plurality of (n + 1) edges at a predetermined time interval ΔT with reference to the data strobe signal DQS_SH by giving a multistage delay to the data strobe signal DQS selected by the selector 32. Multi-strobe signals MSTRB _{0 to} MSTRB _n (simply referred to simply as MSTRB if necessary) are generated.

The multi-strobe signal generation unit 12 includes a plurality of delay elements D1 to Dn connected in cascade, for example. A tap is provided between adjacent delay elements. Each delay element gives a delay of a predetermined time ΔT to the input signal. From each tap, a multi-strobe signal MRSTRB [0: n] given a different delay time is output. Specifically, the output signal of the i-th delay element Di is an i-th phase multi-strobe signal MSTRB _i . Input signals of the first-stage delay element D1 is a multi-strobe signal MSTRB ₀ of the 0-phase.

The timing comparison unit 14 receives the data signal DQ_SH subjected to skew adjustment by the phase adjustment unit 20 and the (n + 1) -phase multi-strobe signal MSTRB.
The timing comparison unit 14 determines the value of the data signal DQ_SH for each of the timings of a plurality of edges of the multi-strobe signal MSTRB, and generates timing data TD indicating the timing at which the value changes.

For example, the timing comparison unit 14 includes n + 1 latches (flip-flops) L0 to Ln assigned to the n + 1-phase multi-strobe signals MSTRB.
The i-th (0 ≦ i ≦ n) latch Li latches the value of the data signal DQ_SH at the edge timing of the i-phase multi-strobe signal MSTRB, and sets the i-th bit TD [i] of the timing data TD. Output.

  For example, consider a case where the data signal DQ changes from 0 (low level) to 1 (high level). In this case, when the 0th bit to the Kth bit of the timing data TD [0: n] are 0, and the K + 1th bit to the nth bit are 1, the bit position where the value of the timing data TD changes (in this case, K) indicates the changing point. Data in which values 1 and 0 change with a certain bit position as a boundary, such as timing data TD, is also referred to as a thermometer code.

  The phase data converter 16 receives the timing data TD and converts it into a data format suitable for subsequent signal processing including binary data. For example, the phase data converter 16 may be a priority encoder that converts a thermometer code into a binary code. From the phase data converter 16, binary format timing data TDb is output.

  The logic comparison unit 18 determines whether or not the timing data TDb satisfies a predetermined condition. For example, condition data (for example, an upper limit value and a lower limit value) indicating a range in which the timing data TDb is allowed is input to the logical comparison unit 18. The condition data is generated by the logical comparison control unit 40.

  The above is the configuration of the test apparatus 2. Next, the operation of the test apparatus 2 will be described.

(First mode)
FIG. 2 is a time chart showing an operation example in the first mode of the test apparatus 2 of FIG.

  During the test, a data signal DQ having a known pattern and a data strobe signal DQS synchronized therewith are output from the DUT 1. In an ideal situation where there is no jitter, the edge of the data strobe signal DQS is located approximately at the center of the eye opening of the data signal DQ. However, in reality, jitter is superimposed on each of the data signal DQ and the data strobe signal DQS. Due to the influence of the jitter, the timings of the change points of the data signal DQ and the data strobe signal DQS change relatively, and a situation where the setup condition and the hold condition are not satisfied may occur.

  The test apparatus 2 detects the difference between the change timing t1 of the data signal DQ and the change timing t2 of the data strobe signal DQS, and determines whether a predetermined relationship is satisfied.

The multi-strobe signal generator 12 generates (n + 1) -phase multi-strobe signals MSTRB _{0 to} MSTRB _n over one cycle (unit interval UI) of the data signal DQ with reference to the edge of the data strobe signal DQS. FIG. 2 shows the case of n = 8 phases. Considering the case where the data signal DQ transitions from 0 to 1 in the period T, the timing data TD [0] to TD [4] are 0, and the timing data TD [5] to TD [8] are 1.

The bit position (K = 5) where the value of the timing data TD changes indicates the relative phase difference between the data strobe signal DQS and the data signal DQ. The logic comparison unit 18 determines whether or not the value K of the timing data TDb is included in a predetermined range. In the example of the time chart of FIG. 2, when K = 5, it is guaranteed that the data strobe signal DQS is positioned at the center of the data signal DQ. On the other hand, when K is too small apart from 5 or too large, the setup condition and hold condition are not satisfied, and the value of the data signal DQ cannot be determined. The logical comparison control unit 40 is set with an upper limit value UL and a lower limit value LL determined based on the setup condition and the hold condition.
LL <K <UL
It is determined whether or not the above is satisfied. The test apparatus 2 can evaluate DUT 1 based on the determination result by the logic comparison unit 18.

(Second mode)
Next, the second mode will be described. The second mode is a mode for maintaining compatibility with the conventional test apparatus 2. FIG. 3 is a time chart showing an operation example in the second mode of the test apparatus 2 of FIG.

  In the second mode, the selector 32 selects the strobe signal STRB. That is, the multi-strobe signal MSTRB is generated with reference to the strobe signal STRB.

  The decision circuit 10 corresponding to the data signal DQ evaluates the change timing of the data signal DQ using the multi-strobe signal MSTRB. This change timing t1 is an absolute time with the leading strobe signal STRB as a reference (0), and it can be seen from the time chart of FIG. 3 that a change point of the data signal DQ occurs in the eighth phase. That is, the timing data TDb = 8.

  Further, the change timing t2 of the data strobe signal DQS is evaluated by a determination unit for the data strobe signal DQS (not shown). In the time chart of FIG. 3, it can be seen that a change point of the data signal DQS occurs in the fourth phase. That is, the timing data TDb = 4.

In the second mode, the test apparatus 2 calculates the difference between the timing data TDb of the data signal DQ and the timing data TDb of the data strobe signal DQS by an arithmetic circuit (not shown). This calculation process is performed to exclude the influence of the common mode jitter that is superimposed on the data strobe signal DQS and the data signal DQ by the same amount in the same direction, and is unavoidable in the second mode.
The test apparatus 2 determines whether the difference is included in a predetermined range.

  The above is the operation in the second mode.

Next, advantages of the test apparatus 2 shown in FIG. 1 particularly in the first mode will be described. The advantage of the first mode becomes more apparent by comparison with the second mode.
In the second mode, a subtraction process is required to remove the influence of the common mode jitter and evaluate the relative phase fluctuation (jitter) between the data signal DQ and the data strobe signal DQS. On the other hand, in the first mode, subtraction processing is not necessary, so that power consumption of the circuit can be reduced.

  As shown in the time chart of FIG. 3, in the second mode, it is necessary to generate the multi-strobe signal MSTRB over one cycle (unit interval) of each of the data signal DQ and the data strobe signal DQS. A 12-phase multi-strobe signal MSTRB is required in the range of 5 UI. This means that the power consumption of the multi-strobe signal generator 12 increases. On the other hand, in the first mode, it is sufficient to generate the multi-strobe signal MSTRB in the range of 1U, so that power consumption can be reduced.

  Moreover, in the test apparatus 2 of FIG. 1, when the compatibility with the conventional multi-strobe measurement is not required, the test apparatus 2 may be designed to operate only in the first mode. In this case, since the multi-strobe signal generator 12 only needs to generate the multi-strobe signal MSTRB within the range of 1 UI, the circuit scale can be further reduced.

  Further, if only the first mode is used, the subtraction process is unnecessary, so that the circuit unit for performing the arithmetic process becomes unnecessary, so that the circuit scale can be further reduced.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and arrangement changes are possible without departing from the scope.

DQ ... data signal, DQS ... data strobe signal, STRB ... strobe signal, MSTRB ... multi-strobe signal, 1 ... DUT, 2 ... test device, 10 ... determination unit, 11 ... level comparator, 12 ... multi-strobe signal generation unit, 14 ... timing comparison unit, 16 ... phase data conversion unit, 18 ... logic comparison unit, 20 ... phase adjustment unit, 30 ... strobe signal generation unit, 32 ... selector, 40 ... logic comparison control unit.

Claims (6)

A test apparatus for testing a device under test that performs source-synchronous transmission,
A multi-strobe signal generator for generating a multi-strobe signal having a plurality of edges at predetermined time intervals with reference to the data strobe signal by giving a multistage delay to the data strobe signal output from the device under test; ,
A timing comparison unit that determines a value of a data signal for each timing of a plurality of edges of the multi-strobe signal and generates timing data indicating a timing at which the value changes;
A logical comparison unit for determining whether the timing data satisfies a predetermined condition;
A test apparatus comprising: A strobe signal generator for generating a reference strobe signal;
A selector that receives the data strobe signal and the strobe signal and selects one in accordance with a control signal;
Further comprising
The test apparatus according to claim 1, wherein the multi-strobe signal generation unit generates the multi-strobe signal with reference to one selected by the selector.   The test apparatus according to claim 1, further comprising a phase adjustment unit that receives the data signal and the data strobe signal and adjusts a relative phase difference therebetween. A method for testing a device under test that performs source-synchronous transmission,
Generating a multi-strobe signal having a plurality of edges at predetermined time intervals based on the data strobe signal by giving a multistage delay to the data strobe signal output from the device under test;
Determining a value of a data signal for each of a plurality of edge timings of the multi-strobe signal, and generating timing data indicating a timing at which the value changes;
Determining whether the timing data satisfies a predetermined condition;
A method comprising the steps of: Generating a reference strobe signal;
Selecting one of the data strobe signal and the strobe signal according to a control signal;
Further comprising
5. The method of claim 4, wherein the multi-strobe signal is generated based on one selected signal.   The method according to claim 4, further comprising adjusting a relative phase difference between the data signal and the data strobe signal.

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