JP5202084B2 - Timing controller, image signal line drive circuit, and image display device - Google Patents

Description

  The present invention relates to an image signal line driving circuit and a timing controller used in a matrix display device such as a liquid crystal display device, and more particularly to generation of a control signal for outputting an image signal from an image signal line driving circuit to an image signal line. It is.

  In general, a control device called a timing controller is used for operation control of a matrix display device such as a liquid crystal display device. The timing controller generates a control signal for a display panel drive circuit (scanning line drive circuit and image signal line drive circuit) based on various signals input from the outside, and transmits it to the drive circuit together with image data. To do. The drive circuit drives the liquid crystal panel according to the control signal and the image data, thereby displaying an image on the liquid crystal panel.

  The conventional timing controller needs to correctly recognize the resolution of the display panel in order to generate an appropriate control signal. The simplest method is to record resolution information in advance in the memory of the timing controller as a constant. However, if this is done, the resolutions that can be handled for each timing controller are limited, resulting in a decrease in versatility.

  Therefore, the present inventor inputs a start pulse to the image signal line drive circuit at the forefront of the image signal line drive circuit (or scanning line drive circuit) formed by cascading a plurality of unit circuits, and then makes a round of them. A timing controller that can detect the resolution of the display panel by counting the time until the start pulse is output from the last stage (final stage) is proposed (Patent Document 1 below).

JP 2007-41258 A

  A conventional timing controller includes a counter inside so that a control signal of the image signal line driving circuit can be output at a predetermined timing. The counter measures the generation timing of each control signal by increasing (counting up) the count value in accordance with a horizontal clock that defines the operation timing of the image signal line driving circuit. A conventional timing controller generates each control signal based on the count value.

  In particular, since the image signal line driving circuit needs to output the image data to the display panel after reading the image data for one horizontal line, the timing controller uses a pulse signal as a trigger at the end of one horizontal period. (Latch pulse) was output. In the conventional timing controller, when the count value of the counter reaches the horizontal resolution of the display panel (or a value close to it), it is regarded as the end of one horizontal period and a latch pulse is generated. In other words, the conventional timing controller needs to include a counter capable of counting at least up to a resolution in the horizontal direction, which causes an increase in the circuit scale of the timing controller.

  In the timing controller of Patent Document 1 described above, in order to count the time from when the start pulse is input to the front stage until the start pulse is output from the last stage, at least near the horizontal resolution. It is necessary to provide a counter capable of counting up to.

  The present invention has been made to solve the above-described problems, and is a timing controller capable of improving versatility and reducing the circuit scale, an image signal line driving circuit, and a display device equipped with the timing controller. The purpose is to provide.

The timing controller according to the first aspect of the present invention supplies an image signal to each of a plurality of cascade-connected image signal line driving circuits, and sends a start pulse corresponding to the head of one horizontal period in the image signal to the front stage. A timing controller that supplies a latch pulse corresponding to the end of one horizontal period to each of the image signal line drive circuits, and makes a round of the plurality of image signal line drive circuits. A latch pulse generation circuit that receives the start pulse output from the last image signal line drive circuit and generates the latch pulse in response to the start pulse output from the last image signal line drive circuit wherein the latch pulse generation circuit, the start pulse outputted from the image signal line driving circuit of the last stage A delay circuit that delays by a predetermined delay time, a counter that starts counting after receiving the start pulse delayed by the delay circuit, and the count value reaches a predetermined target value after the counter starts counting until it reaches a shall and a comparator for activating the latch pulse.

An image signal line driving circuit according to a second aspect of the present invention sequentially outputs a multi-stage shift register including a plurality of cascaded unit shift registers and a serially input image signal from the plurality of unit shift registers. A data register that sequentially captures the output signal in synchronization with the output signal, a pulse generation circuit that generates a first pulse signal in accordance with the output signal of the last stage of the unit shift register or its vicinity, and the first pulse signal And a second pulse signal input from the outside, a setting terminal for setting which of the first and second signals the selector selects, and the selector The image processing apparatus includes an output circuit that outputs the image signal to the image signal line of the display panel according to the selected signal.

  According to the present invention, since the timing controller does not need to recognize the resolution in advance, the versatility of the timing controller is improved, and a memory for storing the resolution can be omitted. In addition, since it is not necessary to provide a counter having a large circuit scale, it is possible to contribute to the downsizing of the timing controller and the downsizing of the image display device.

<Embodiment 1>
FIG. 1 is a block diagram showing a main part of a liquid crystal display device 1 which is an image display device according to Embodiment 1 of the present invention. The actual image display apparatus includes many elements in addition to those shown in FIG. 1, but in this specification, only main elements that are particularly relevant to the present invention are illustrated, and other elements are shown. Omitted.

  As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal panel 2, scanning line driving circuits 11 to 13, image signal line driving circuits 21 to 28, and a timing controller 30. A plurality of scanning lines 31 and a plurality of image signal lines 32 are arranged on the liquid crystal panel 2 so as to intersect each other, and a pixel is formed at each of the intersections arranged in a matrix.

  Each pixel includes a pixel transistor (TFT) 34 and a liquid crystal element 33. The pixel transistor 34 has a control electrode connected between the image signal line 32 and the liquid crystal element 33 and connected to the scanning line 31. In FIG. 1, only the pixels in the first row and the first column are representatively shown. The scanning line driving circuits 11 to 13 drive the pixel transistor 34 by outputting a driving signal (scanning line driving signal) to the scanning line 31. The image signal line driving circuits 21 to 28 output image data (analog signal) to the image signal line 32 and write the image data to the liquid crystal element 33 through the pixel transistor 34.

  Each of the scanning line driving circuits 11 to 13 is an integrated circuit formed by cascading a plurality of unit circuits (hereinafter referred to as “unit scanning line driving circuits”) for driving one scanning line 31. Three scanning line driving circuits 11 to 13 are also cascade-connected. That is, all the unit scanning line driving circuits integrated in the scanning line driving circuits 11 to 13 are cascade-connected.

  Similarly, each of the image signal line drive circuits 21 to 28 is an integrated circuit formed by cascading a plurality of unit circuits (hereinafter referred to as “unit signal line drive circuits”) that output image data to one image signal line 32. is there. Eight image signal line drive circuits 21 to 28 are also cascade-connected. That is, all the unit signal line drive circuits integrated in the image signal line drive circuits 21 to 28 are all cascade-connected.

  The timing controller 30 includes a data enable signal as a reference signal for control of the image signal line driving circuits 21 to 28 and the scanning line driving circuits 11 to 13 (hereinafter referred to as “control reference signal”) together with the image data (V-DATA). A signal DENA, a horizontal synchronization signal HD, a vertical synchronization signal VD, and a reference clock DCLK are input. The data enable signal DENA is a signal indicating a period during which image data is valid. The horizontal synchronization signal HD is a signal for synchronizing the liquid crystal panel 2 in the horizontal direction (lateral direction), and the vertical synchronization signal VD is a signal for synchronizing in the vertical (vertical direction) direction. The reference clock DCLK is a reference for the operation timing of the timing controller 30.

  The timing controller 30 generates RGB data (RGB-DATA) composed of red, green, and blue data based on the image data (V-DATA), and drives the image signal line based on the control reference signal. Control signals for driving the circuits 21 to 28 and the scanning line driving circuits 11 to 13 are generated. The RGB data (image signal) is a digital signal representing red, green, and blue data, respectively, and the red, green, and blue digital signals are respectively sent to the image signal line drive circuits 21 to 21 using a data bus having a width of several bits. 28.

  The control signals of the scanning line driving circuits 11 to 13 include a clock CLKV (hereinafter referred to as “vertical clock CLKV”) that defines the operation timing of the scanning line driving circuits 11 to 13 and a start pulse STV (hereinafter referred to as “vertical scanning start timing”). “Vertical start pulse STV”), an output enable signal / OE for switching on and off the outputs of the scanning line driving circuits 11 to 13 and the like.

  The vertical start pulse STV is a pulse signal activated corresponding to the head of each frame period in the RGB data output from the timing controller 30. The vertical start pulse STV output from the timing controller 30 is input to the scanning line driving circuit 11 which is the first stage in the cascade connection. The vertical start pulse STV is transferred in the order of the scanning line driving circuits 11, 12, and 13 to make a round. At this time, in the scanning line driving circuits 11 to 13, each of the cascade-connected unit scanning line driving circuits drives the corresponding scanning line 31 in synchronization with the vertical start pulse STV sent from its previous stage. The vertical start pulse STV is sent to the next stage.

  The operation of the unit scanning line driving signal is performed in synchronization with the vertical clock CLKV. As a result, the plurality of scanning lines 31 are sequentially activated in synchronization with the vertical clock CLKV (that is, the liquid crystal panel 2 is scanned), and the pixel transistors 34 connected to each of the scanning lines 31 correspondingly are Turns on in turn in 31 units.

  The output enable signal / OE is for adjusting a period during which RGB data can be written to the liquid crystal element 33, and thereby the output of the scanning line driving circuits 11 to 13 is switched on and off. The output enable signal / OE is a negative logic signal, and the scanning line drive circuits 11 to 13 perform the normal operation (scanning of the scanning line 31) when the output enable signal / OE is at L (Low) level. When the output enable signal / OE becomes the H (High) level, all the scanning lines 31 are set to the L (Low) level (that is, all the pixel transistors 34 are turned off and the writing of the RGB data to the liquid crystal element 33 is prohibited. ).

  On the other hand, the control signals of the image signal line driving circuits 21 to 28 generated by the timing controller 30 include a clock CLKH (hereinafter “horizontal clock CLKH”), a start pulse STH (hereinafter “horizontal start pulse STH”), a latch pulse LP, and the like. Is included. The horizontal clock CLKH defines the operation timing of the image signal line driving circuits 21 to 28.

  The horizontal start pulse STH is a pulse signal that is activated corresponding to the head of each horizontal period in the RGB data output from the timing controller 30, and is used in each of the drive circuits integrated in the image signal line drive circuits 21 to 28. Thereby, the timing of the start of data capture is defined.

  The horizontal start pulse STH output from the timing controller 30 is input to the image signal line drive circuit 21 which is the first stage in the cascade connection. The horizontal start pulse STH is transferred in the order of the image signal line driving circuits 21, 22,. At that time, in the image signal line drive circuits 21 to 28, each of the cascade-connected unit signal line drive circuits is synchronized with the horizontal start pulse STH sent from the preceding stage of the image signal line drive circuits 21 to 28, and the RGB data from the timing controller 30 is obtained. The horizontal start pulse STH is sent to the next stage.

  The operation of the unit signal line driving circuit is performed in synchronization with the horizontal clock CLKH. As a result, the individual unit signal line drive circuits of the image signal line drive circuits 21 to 28 can sequentially capture RGB data transmitted serially in synchronization with the horizontal clock CLKH at predetermined timings. .

  The latch pulse LP is a pulse signal corresponding to the end of one horizontal period of RGB data, and the RGB data for one horizontal line captured and held by the image signal line driving circuits 21 to 28 is output to the liquid crystal panel 2. It is a signal that defines the timing to perform. The latch pulse LP is input to each of the image signal line drive circuits 21 to 28. In addition, the control signal output from the timing controller 30 includes a polarity inversion signal for inverting the polarity of the liquid crystal drive. The timing controller 30 transmits these control signals together with the RGB data to the image signal line driving circuits 21 to 28.

  As described above, in the liquid crystal display device of FIG. 1, the scanning line driving circuits 11 to 13 activate the scanning lines 31 of the liquid crystal panel 2 one horizontal line at a time on the basis of the vertical start pulse STV and the vertical clock CLKV. The signal line driving circuits 21 to 28 sequentially take in RGB data based on the horizontal start pulse STH and the horizontal clock CLKH, and the image signal line 32 receives RGB data for one horizontal line according to the last latch pulse LP in one horizontal period. Output to. As a result, RGB data for one horizontal line is written to pixels in a specific row every horizontal period. By repeating this operation, an image is displayed on the entire liquid crystal panel 2.

Each of the image signal line drive circuits 21 to 28 has an input terminal and an output terminal for the horizontal start pulse STH so that cascade connection is possible. Hereinafter, for convenience of explanation, the horizontal start pulse output from the timing controller 30 is expressed as STH ₀ , and the horizontal start pulse output from the image signal line drive circuits 21 through 28 is expressed as STH ₁ through STH ₈ (see FIG. 1). In the conventional liquid crystal display device, the output terminal of the horizontal start pulse STH ₈ of the last image signal line drive circuit (image signal line drive circuit 28) is normally not connected to anything, but in this embodiment, the horizontal start pulse STH is not connected. ₈ is input to the timing controller 30 (however, in Patent Document 1 described above, a signal corresponding to the horizontal start pulse STH ₈ is input to the timing controller as in the present invention).

  Here, the configuration and operation of each of the image signal line drive circuits 21 to 28 will be described in more detail. FIG. 2 is a block diagram showing the configuration of the image signal line driving circuits 21 to 28, and representatively shows the i-th one of the image signal line driving circuits 21 to 28 connected in cascade.

  As shown in FIG. 2, each of the image signal line drive circuits 21 includes a shift register 201, a data register 202, a latch circuit 203, and an output stage 204. The shift register 201, the data register 202, the latch circuit 203, and the output stage 204 include a plurality (m) of unit circuits corresponding to the image signal lines 32 (each of the above “unit signal line driving circuits”). Is composed of unit circuits of the shift register 201, the data register 202, the latch circuit 203, and the output stage 204).

The shift register 201 has a multistage configuration in which unit circuits (unit shift registers) are cascade-connected. In the image signal line driving circuits 21 to 28, the shift registers 201 are connected in a cascade manner. The horizontal start pulse STH _i input to the shift register 201 is sequentially transferred to the unit shift registers C1, C2,..., Cm at a timing synchronized with the horizontal clock CLKH, and then output to the next image signal line driving circuit. Is done. That is, the horizontal start pulse STH _{i + 1} sent to the next image signal line driving circuit corresponds to the output signal of the last unit shift register Cm in the shift register 201.

  A plurality of unit circuits (unit data registers) of the data register 202 convert RGB data transmitted serially in synchronization with the horizontal clock CLKH into output signals of the unit shift registers C1, C2,. Import at the timing synchronized with. Thus, display data for one pixel is held in each unit data register.

  The latch circuit 203 and the output stage 204 are controlled by a latch pulse LP output from the timing controller 30. The latch circuit 203 takes in the RGB data for one horizontal line held in the data register 202 in response to the rising edge of the latch pulse LP (change from L level to H level, that is, “activation”). (The data held in the data register 202 is shifted to the latch circuit 203). The output stage 204 includes a D / A (digital / analog) converter, and converts each of the RGB data held in the latch circuit 203 into an analog signal. Thereafter, the latch circuit 203 converts the RGB data (voltage) converted into an analog signal into the liquid crystal panel 2 in response to the fall of the latch pulse LP (change from H level to L level, ie, “deactivation”). Output to the image signal line 32.

  FIG. 3 is a timing chart showing the control operation of the image signal line drive circuits 21 to 28 having the structure shown in FIG. Here, the horizontal resolution of the liquid crystal panel 2 is assumed to be n.

The timing controller 30 outputs a horizontal start pulse STH ₀ at a timing corresponding to the head of each horizontal period. Image-signal-line drive circuit 21 through 28 unit shift register C1~Cn Cascaded over is to a horizontal start pulse STH ₀ a trigger, it activates its output signal sequentially in synchronization with the horizontal clock CLKH. In parallel with this, RGB data (d _{1 to} d _n ) for one horizontal line is serially input to the data register 202 in synchronization with the horizontal clock CLKH. As a result, RGB data for one horizontal line is taken into the n unit data registers of the image signal line driving circuits 21 to 28.

At a predetermined timing after the last row of RGB data (d _n ) is taken into the data register 202, the controller 30 sets the latch pulse LP to H level (activates).

  When the latch pulse LP becomes H level, RGB data for one horizontal line held in the data register 202 is taken into the latch circuit 203 and converted into an analog signal by the D / A converter of the output stage 204. Is done. Thereafter, the timing controller 30 returns the latch pulse LP to L level (deactivates). In response to this, the output stage 204 outputs RGB data of the analog signal to the image signal line 32 of the liquid crystal panel 2.

In consideration of the time required for the operation of each circuit, the data register 202 after completing the acquisition of data d _n of the last column, (up to the rise of the latch pulse LP) to incorporating the RGB data to the latch circuit 203 In this case, a predetermined delay time t _DL is secured. Similarly, from the time when the latch circuit 203 takes in the RGB data until the output stage 204 outputs an analog signal to the image signal line 32 (that is, the length of the active period of the latch pulse LP), a certain time interval t. _LP (hereinafter referred to as “pulse width t _LP ”) is secured.

In the conventional timing controller, the internal counter starts counting up in synchronization with the horizontal clock CLKH from the time when it outputs the horizontal start pulse STH ₀ , and when the count value reaches a predetermined value, the latch pulse LP Was activated. That is, the conventional timing controller measures the elapse of time t _C shown in FIG. Therefore, the counter included in the conventional timing controller needs to be capable of counting up to a large value of at least the resolution n in the horizontal direction, and as described above, this contributes to an increase in circuit scale. It was.

FIG. 4 is a diagram for explaining the operation of the timing controller 30 according to the present embodiment. FIG. 4 is the same as FIG. 3 except that the waveform of the horizontal start pulse STH ₈ output from the image signal line driving circuit 28 is added. The control method of the image signal line drive circuits 21 to 28 in the timing controller 30 according to the present embodiment is basically as described with reference to FIG. However, the timing controller 30 does not measure the time t _C shown in FIG.

As shown in FIG. 1, the horizontal start pulse STH ₈ output from the image signal line drive circuit 28 is input to the timing controller 30 of the present embodiment. As shown in FIG. 4, in the example of the horizontal start pulse STH ₈ is activated about the same as the acquisition timing of the data d _n of the last row among the one horizontal line (Fig. 4, the active period of the horizontal start pulse STH ₈ The period for taking in data d _n is equal to each other).

The timing controller 30, the fall timing of the horizontal start pulse STH ₈ uptake period of the data d _n of the last row is completed, the time measurement for ensuring the delay time t _DL and the pulse width t _LP latch pulse LP The latch pulse LP is activated for a certain period based on the passage of time. That is, since the timing controller 30 measures extremely short time (delay time t _DL and pulse width t _LP ) compared to the time t _C in FIG. 3, the counter and the like required by the timing controller 30 are small in scale. Is enough. Therefore, it can contribute to the reduction of the circuit scale of the timing controller.

Further, since the length of the time t _{C in} FIG. 3 measured by the conventional timing controller varies depending on the horizontal resolution of the liquid crystal panel, the conventional timing controller needs to recognize the horizontal resolution in advance. It was.

On the other hand, the length of each of the delay time t _DL and the pulse width t _LP measured by the timing controller 30 of the present embodiment may be constant regardless of the resolution in the horizontal direction. It is not necessary to recognize the horizontal resolution. In other words, it can be applied to the liquid crystal panel 2 of any resolution, and high versatility can be obtained. Further, the need for a memory or the like for retaining resolution information is also contributing to the reduction in circuit scale.

FIG. 5 is a block diagram showing an example of a latch pulse LP generation circuit (latch pulse (LP) generation circuit) included in the timing controller 30 according to the present embodiment. The latch pulse generation circuit includes a delay circuit 301 for securing a delay time t _DL , a counter 302 and a comparator 303 for securing a pulse width t _LP . The delay circuit 301 receives the horizontal start pulse STH ₈ , delays it by the delay time t _DL and transmits it to the counter 302. Although the delay circuit 301 is not a so-called “counter”, the delay time t _DL is substantially measured by setting the transmission delay caused by the delay circuit 301 to the delay time t _DL .

Upon receiving the horizontal start pulse STH ₈ delayed by the delay circuit 301, the counter 302 starts counting in synchronization with the horizontal clock CLKH. The comparator 303 operates to activate the latch pulse LP after the counter 302 starts counting until the count value reaches a predetermined target value. That is, the length of the pulse width t _LP is determined by setting the target value.

  According to the latch pulse generation circuit of FIG. 5, as shown in FIG. 4, it is activated when the delay time tDL has elapsed from the falling timing of the horizontal start pulse STH8, and then the time corresponding to the pulse width tLP has elapsed. A latch pulse LP that is sometimes deactivated is generated.

The counter 302 used in the latch pulse generation circuit of FIG. 5 only needs to be able to count the number of pulses of the horizontal clock CLKH corresponding to the pulse width t _LP , so that a circuit having a small circuit scale can be used. That is, since the configuration of the latch pulse generation circuit is simplified, it is possible to contribute to the downsizing of the timing controller 30.

In the example of FIG. 5, the delay circuit 301 is used to secure the delay time t _DL so that a smaller circuit can be realized. However, a counter can also be used to secure the delay time t _DL . That is, the latch pulse generation circuit according to the present invention is not limited to the configuration shown in FIG. 5, but detects the inactivation of the horizontal start pulse STH ₈ and then the pulse width t when a time corresponding to the delay time t _DL elapses. as long as it can output the latch pulse LP of the _LP may be any configuration.

<Embodiment 2>
In the first embodiment, the timing controller 30 generates the latch pulse LP based on the horizontal start pulse STH ₈ after making a round of the image signal line drive circuits 21 to 28. However, in the second embodiment, The latch pulse LP is generated by the image signal line drive circuits 21 to 28 themselves. That is, in the present embodiment, the timing controller 30 does not need to have a latch pulse LP generation circuit.

FIG. 6 is a block diagram showing a main part of the liquid crystal display device 1 according to the second embodiment. In the figure, elements having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here. In the present embodiment, since a signal corresponding to the latch pulse LP is generated inside each of the image signal line drive circuits 21 to 28, the signal line of the latch pulse LP is not shown in FIG. However, the horizontal start pulse STH ₈ output from the image signal line drive circuit 28 is supplied to each of the image signal line drive circuits 21 to 28.

  FIG. 7 is a diagram showing the configuration of the image signal line drive circuits 21 to 28 according to the present embodiment, and typically shows the i-th one. In FIG. 7, elements having the same functions as those shown in FIG. 2 are denoted by the same reference numerals.

  The configuration of the image signal line driving circuit of FIG. 7 is almost the same as that of FIG. 2, but a signal for controlling the latch circuit 203 and the output stage 204 (a signal corresponding to the latch pulse LP of FIG. 2) is two pulse signals LP1. , LP2 is different. Hereinafter, the pulse LP1 input to the latch circuit 203 is referred to as a “first latch pulse”, and the pulse LP2 input to the output stage 204 is referred to as a “second latch pulse”.

  The first latch pulse LP1 corresponds to the rising edge of the latch pulse LP in FIG. 2, and the latch circuit 203 takes in the RGB data held in the data register 202 in response to the activation of the first latch pulse LP1. To work. The second latch pulse LP2 corresponds to the falling edge of the latch pulse LP of FIG. 2, and the output stage 204 converts the RGB data converted into an analog signal into an image according to the activation of the second latch pulse LP2. It operates to output to the signal line 32.

  In the present embodiment, as shown in FIG. 7, as the first latch pulse LP1, the output signal of the last unit shift register Cm belonging to each image signal line driving circuit (that is, the horizontal start pulse STH transmitted to the unit shift register Cm). Is used.

As the second latch pulse LP2, a horizontal start pulse STH ₈ output from the image signal line drive circuit 28 which is the last stage of the image signal line drive circuits 21 to 28 is used (also in the image signal line drive circuit 28). The horizontal start pulse STH ₈ is re-input as the second latch pulse LP2.

According to this configuration, in each of the image signal line drive circuits 21 to 28, the RGB data held by the data register 202 immediately after the data register 202 fetches the final RGB data of the pixel column to which it corresponds. Is shifted to the latch circuit 203. Then, in response to the activation of the horizontal start pulse STH ₈ from the image signal line driving circuit 28, RGB data converted into analog signals is output to the image signal line 32 from all the output stages 204 of the image signal line driving circuits 21 to 28. Is done.

As described above, in this embodiment, the operation timing of the latch circuit 203 is shifted for each image signal line driver circuit, but from the output stage 204, the specified timing (after the data d _n fetch period of the last row) is reached. Since RGB data (analog signal) is output to the image signal line 32, normal image display is possible.

Here, as described with respect to the delay time t _DL and the pulse width t _{LP in the} first embodiment, considering the time required for the operation of each circuit, the data register 202 completes the acquisition of the RGB data, A certain time interval is secured between the time when the data is shifted to the latch circuit 203 and the time when the output circuit 204 outputs the RGB data to the image signal line 32 after the latch circuit 203 takes in the RGB data. Preferably it is. In this case, as shown in FIG. 7, the first latch pulse LP1 is input to the latch circuit 203 through the flip-flop (FF) 205 as a delay circuit, and the second latch pulse LP2 is similarly input to the output stage through the flip-flop 206. What is necessary is just to input into 204.

  Each of the flip-flops 205 and 206 may be provided in a plurality of stages according to the length of the required delay time. Since this “required delay time” is known at the design stage of the image signal line driving circuits 21 to 28, the number of flip-flops 205 and 206 can be easily determined at the design stage.

  FIG. 7 shows an example in which the output signal of the last unit shift register Cm in the image signal line driving circuit is used as the first latch pulse LP1. In particular, when the flip-flops 205 and 206 are used, the flip-flops 205 and 206 do not necessarily have to be in the last stage. However, if the flip-flops 205 and 206 are close to the last stage, the number of flip-flops 205 and 206 may be small.

  According to this embodiment, since the timing controller 30 does not need to include a latch pulse generation circuit, the circuit scale of the timing controller 30 is reduced. The number of components of each of the image signal line drive circuits 21 to 28 increases. However, since the number of the components is about flip-flops 205 and 206 that can be realized with a simple configuration, the circuit scale of the entire liquid crystal display device 1 can be reduced. it can.

<Embodiment 3>
In the second embodiment, it is not necessary for the timing controller 30 to generate the latch pulse LP. However, since each of the image signal line drive circuits 21 to 28 independently generates the first latch pulse LP1, the respective latch circuits 203 are provided. The operation timing is shifted. That is, the interval from when the RGB data held by the data register 202 is shifted to the latch circuit 203 until the RGB data (analog signal) is output to the image signal line 32 is determined by each of the image signal line driving circuits 21 to 28. It will be different.

  Depending on the configuration of the display device, this phenomenon may cause a problem in the operation of the display device. Therefore, in the third embodiment, the timing controller 30 does not need to generate the latch pulse LP, and the interval from when the RGB data is shifted to the latch circuit 203 until it is output to the image signal line 32 can be made constant. Propose.

  FIG. 8 is a block diagram showing a main part of the liquid crystal display device 1 according to the third embodiment. Also in this figure, elements having the same functions as those shown in FIG. In the present embodiment, each of the image signal line driving circuits 21 to 28 can generate the latch pulse LP, and the image signal line driving circuits 21 to 28 can pass the latch pulse LP. (Therefore, in FIG. 8, a bidirectional arrow is attached to the path of the latch pulse LP). However, in actual use, only one of the image signal line drive circuits 21 to 28 is set so as to generate the latch pulse LP, and the latch pulse LP is distributed to the others (FIG. 11).

  FIG. 9 is a diagram showing the configuration of the image signal line drive circuits 21 to 28 according to the present embodiment, and typically shows the i-th one. In FIG. 9 as well, elements having the same functions as those shown in FIG.

  The image signal line drive circuit of FIG. 9 has a configuration in which a latch pulse generation circuit 206, an input / output buffer 207, and a selector 208 are further added to the configuration of FIG. In response to the activation of the output signal of the last stage unit shift register Cm belonging to the image signal line driving circuit (that is, the horizontal start pulse STH transmitted to the unit shift register Cm), the latch pulse generation circuit 206 latches the LP pulse Can be generated.

FIG. 10 shows a specific example of the latch pulse generation circuit 206. The latch pulse generation circuit 206 is the same as that shown in FIG. That is, the latch pulse generation circuit 206 of FIG. 10 generates the counter 302 and the comparator 303 after the delay time t _DL generated by the delay circuit 301 after the output signal of the last unit shift register Cm falls. A latch pulse LP that is activated only for the pulse width t _LP is output. The counter 302 only needs to be able to count the number of pulses of the horizontal clock CLKH corresponding to the pulse width t _LP of the latch pulse LP, and may have a small circuit scale. Therefore, the image signal by providing this latch pulse generation circuit 206 is sufficient. The increase in circuit scale of the line drive circuits 21 to 28 is not a problem.

  The input / output buffer 207 functions as an output buffer that outputs the latch pulse LP generated by the latch pulse generation circuit 206 of the image signal line driving circuit to another image signal line driving circuit, and the other image signal line driving circuit. And a function as an input buffer for receiving the latch pulse LP generated in step (1) and inputting it to the selector 208. However, the input / output buffer 207 is controlled by the voltage level supplied to the setting terminal MST, and when the setting terminal MST is set to the L level, the output of the latch pulse LP to the outside is cut off (that is, the input buffer). Will only function as).

  The selector 208 includes a latch pulse LP generated by the latch pulse generation circuit 206 of the image signal line driving circuit 21 and a latch pulse LP (generated by another image signal line driving circuit) input from the outside through the input / output buffer 207. Latch pulse LP) is input, one of them is selected according to the voltage level of the setting terminal MST, and the selected signal is supplied to the latch circuit 203 and the output stage 204. Here, the selector 208 supplies the latch pulse LP generated by the latch pulse generation circuit 206 of the image signal line driving circuit to the latch circuit 203 and the output stage 204 if the setting terminal MST is set to the H level. If the setting terminal MST is set to L level, the latch pulse LP generated by another image signal line driving circuit is supplied to the latch circuit 203 and the output stage 204.

  When the setting terminal MST is at the L level, the latch pulse LP generated by the latch pulse generation circuit 206 is blocked by the input / output buffer 207 and the selector 208 and is not sent to other elements. It need not be generated. For this reason, in this embodiment, the latch pulse generation circuit 206 is also controlled by the voltage level of the setting terminal MST, and the latch pulse generation circuit 206 is in a pause state when the setting terminal MST is at the L level.

  As described above, the image signal line driving circuit of FIG. 9 operates the latch circuit 203 and the output stage 204 based on the latch pulse LP generated by itself when the setting terminal MST is set to the H level. The pulse LP is output to another image signal line driving circuit (this state is hereinafter referred to as “master state”). Conversely, when the setting terminal MST is set to the L level, the latch pulse LP is not generated by itself, and the latch circuit 203 and the output stage 204 are set based on the latch pulse LP supplied from another image signal line driving circuit. Operate (this state is hereinafter referred to as “slave state”).

  In actual use of the liquid crystal display device 1 of the present embodiment, only the image signal line drive circuit 28 at the rearmost stage among the cascaded image signal line drive circuits 21 to 28 is set to the master state, and the other image signal line drives are driven. The circuits 21 to 27 are brought into a slave state. That is, as indicated by an arrow in FIG. 11, the image signal line drive circuit 28 generates the latch pulse LP and distributes it to the other image signal line drive circuits 21 to 27 (image signal line drive circuit 21). -27 do not output the latch pulse LP).

  As a result, in all of the image signal line drive circuits 21 to 28, the latch circuit 203 and the output stage 204 operate based on the latch pulse LP generated by the image signal line drive circuit 28. That is, the latch circuit 203 and the output stage 204 of the image signal line drive circuits 21 to 28 all operate based on the same latch pulse LP. Therefore, the interval from when the RGB data is shifted to the latch circuit 203 until it is output to the image signal line 32 is the same in the image signal line drive circuits 21 to 28.

<Modification>
In each of the above embodiments, an example in which a liquid crystal panel is driven using three scanning line driving circuits (integrated circuits) and eight image signal line driving circuits (integrated circuits) has been shown. Optional. Also, the timing controller, the scanning line driving circuit, and the image signal line driving circuit have been described on the assumption that they are individual integrated circuits. However, two or all of them are integrated circuits formed using the same semiconductor substrate. It may be made. For example, the timing controller may be built in the same integrated circuit as the image signal line driving circuit, or may be built in the same integrated circuit as the scanning line driving circuit. Of course, all of the timing controller, the scanning line driving circuit, and the image signal line driving circuit may be incorporated in the same integrated circuit.

  In the example shown above, only the configuration in which the horizontal start pulse is shifted from the left to the right of the liquid crystal panel is shown, but the present invention is also applicable to a configuration in which the horizontal start pulse is shifted in the opposite direction. Is possible. Actually, there are also image signal line drive circuits that shift the horizontal start pulse from the left to the right of the liquid crystal panel, and image signal line drive circuits that can be shifted in either direction.

  For example, in the first embodiment, regardless of the shift direction of the horizontal start pulse, the latch pulse generation circuit of the timing controller 30 generates the latch pulse LP based on the horizontal start pulse output from the last image signal line driving circuit. It only has to be generated. For example, if the shift direction is from right to left, a latch pulse may be generated based on a horizontal start pulse output from the image signal line driving circuit arranged on the leftmost side.

  In the second embodiment, in each image signal line driving circuit, the output signal of the unit shift register at the last stage (or the vicinity thereof) in the multistage shift register (201) is used as the first latch pulse (LP1). The horizontal start pulse output from the last image signal line driving circuit may be used as the second latch pulse (LP2). For example, if the shift direction is from right to left, the output signal of the unit shift register disposed on the leftmost side (or in the vicinity thereof) in each image signal line drive circuit is the first latch pulse, and the most The horizontal start pulse output from the image signal line driving circuit disposed on the left side may be used as the second latch pulse.

  Further, in the case of Embodiment 3, in each image signal line driving circuit, the output signal of the last unit shift register (or the vicinity thereof) in the multi-stage shift register (201) is supplied to the latch pulse generation circuit. It is sufficient that only the last-stage image signal line driving circuit is set to the master state, and the others are set to the slave state. For example, if the shift direction is from right to left, only the image signal line driving circuit disposed on the leftmost side may be set to the master state.

2 is a configuration diagram of a main part of the liquid crystal display device according to Embodiment 1. FIG. 1 is a block diagram illustrating a configuration of an image signal line driving circuit according to a first embodiment. FIG. 3 is a timing chart for explaining a control method of the image signal line driving circuit according to the first embodiment. FIG. 5 is a timing diagram for explaining the operation of the timing controller according to the first embodiment. FIG. 3 is a block diagram illustrating a specific example of a latch pulse generation circuit according to the first embodiment. FIG. 6 is a configuration diagram of a main part of a liquid crystal display device according to a second embodiment. FIG. 6 is a block diagram illustrating a configuration of an image signal line driving circuit according to a second embodiment. FIG. 6 is a configuration diagram of a main part of a liquid crystal display device according to a third embodiment. FIG. 6 is a block diagram illustrating a configuration of an image signal line driving circuit according to a third embodiment. FIG. 10 is a block diagram illustrating a specific example of a latch pulse generation circuit according to a third embodiment. FIG. 10 is a diagram for explaining a latch pulse generation operation when the liquid crystal display device according to the third embodiment is actually used.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Liquid crystal display device, 2 Liquid crystal panel, 11-13 Scan line drive circuit, 21-28 Image signal line drive circuit, 30 Timing controller, 31 Scan line, 32 Image signal line, 33 Liquid crystal element, 34 Pixel transistor, 201 Shift register 202, data register, 203 latch circuit, 204 output stage, 205, 206 flip-flop, 206 latch pulse generation circuit, 207 input / output buffer, 208 selector, 301 delay circuit, 302 counter, 303 comparator.

Claims (5)

An image signal is supplied to each of the plurality of cascade-connected image signal line drive circuits, and a start pulse corresponding to the head of one horizontal period in the image signal is supplied to the image signal line drive circuit in the forefront stage. A timing controller for supplying a latch pulse corresponding to the end of a horizontal period to each of the image signal line driving circuits,
In response to the start pulse output from the last-stage image signal line drive circuit in response to the start pulse output from the last-stage image signal line drive circuit through the plurality of image signal line drive circuits A latch pulse generation circuit for generating the latch pulse ;
The latch pulse generation circuit includes:
A delay circuit that delays the start pulse output from the last-stage image signal line driving circuit by a predetermined delay time;
A counter that starts counting after receiving the start pulse delayed by the delay circuit;
A timing controller comprising: a comparator that activates the latch pulse from when the counter starts counting until the count value reaches a predetermined target value .   An image display device equipped with the timing controller according to claim 1. A multi-stage shift register including a plurality of unit shift registers connected in cascade;
A data register that sequentially captures serially input image signals in synchronization with output signals sequentially output from the plurality of unit shift registers;
A pulse generation circuit for generating a first pulse signal in response to an output signal of the last stage of the unit shift register or its neighboring stage;
A selector for selecting either the first pulse signal or a second pulse signal input from the outside;
A setting terminal for setting whether the selector selects the first signal or the second signal;
An output circuit for outputting the image signal to an image signal line of a display panel according to a signal selected by the selector;
An image signal line driving circuit. The image signal line driving circuit according to claim 3,
The image signal captured in the data register is a digital signal,
Each of the plurality of image signal line drive circuits includes:
A latch circuit that captures and holds the image signal held in the data register in response to activation of the signal selected by the selector;
A D / A converter that converts the image signal held by the latch circuit into an analog signal;
The output circuit is
In response to the deactivation of the signal selected by the selector, the image signal converted into an analog signal is output to the image signal line.
An image signal line driving circuit. A plurality of image signal line drive circuits;
An image display device comprising: a timing controller that supplies an image signal to each of the plurality of image signal line driving circuits and supplies a start pulse corresponding to the head of one horizontal period to the image signal line driving circuit in the foremost stage. There,
Each of the plurality of image signal line drive circuits includes:
An image signal line driving circuit according to claim 3 or 4,
The plurality of image signal line driving circuits are:
Each of the shift registers is connected to be cascaded,
The start pulse output from the timing controller is:
It is input to the shift register of the image signal line drive circuit in the forefront stage,
In the last image signal line drive circuit,
The selector is set to select the first pulse signal;
In the image signal line drive circuit other than the last stage,
As the second pulse signal, the first pulse generated by the last image signal line driving circuit is input,
The selector is set to select the second pulse signal
An image display device characterized by that.

Images