JP5200408B2 - Thin film transistor manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor using a photolithography method.

  In general, in a flat display device, a display medium is formed using elements using liquid crystal, organic EL, electrophoresis, or the like. In such a display medium, in order to ensure uniformity of screen brightness, screen rewriting speed, and the like, a technique using an active drive element composed of a thin film transistor (hereinafter also referred to as TFT) as an image drive element has become mainstream. ing.

  A TFT is usually formed by sequentially forming a semiconductor thin film such as a-Si (amorphous silicon) or p-Si (polysilicon) or a metal thin film such as a source electrode, a drain electrode, or a gate electrode on a glass substrate. It is manufactured by going. In order to manufacture a flat panel display using this TFT, a high-precision photolithography method process is usually required in addition to a vacuum system facility such as a CVD method and a sputtering method and a thin film forming step that requires a high-temperature processing step. The running cost is very heavy. Furthermore, along with the recent needs for larger display screens, their costs have become enormous.

  Therefore, in recent years, development of organic TFTs using organic semiconductor materials has been actively promoted as a technique for compensating for the disadvantages of conventional TFTs. Since organic TFTs can be manufactured by a low-temperature process, it is said that a light and hard-to-break resin substrate can be used, and that a flexible display using a resin film as a substrate can be realized. Further, by using an organic semiconductor material that can be manufactured by a wet process such as printing or coating under atmospheric pressure, a display with excellent productivity and a very low cost can be realized.

  However, organic semiconductor materials are chemically unstable materials compared to inorganic semiconductors such as silicon, and changes in properties due to irradiation with visible light, ultraviolet light, contact with organic solvents, oxygen, moisture, etc. Performance degradation occurs. Therefore, in order to protect the organic TFT from such factors affecting the performance, a protective film having a light shielding property and a gas barrier property (hereinafter also referred to as a passivation film) is formed so as to cover the semiconductor.

For the passivation film, an organic material or an inorganic material is used as a material, but it is preferable to use at least one inorganic material in consideration of oxygen blocking performance and water vapor blocking performance. For the film formation of the inorganic material, a dispersion liquid in which the inorganic material is dispersed or a solution in which the precursor is dissolved can be used, but the thin film performance is inferior to that formed by using the vacuum process. Usually, a film of SiO ₂ or parylene is formed by sputtering or CVD.

  By the way, the passivation film is usually unnecessary in a portion other than the semiconductor. For example, when the pixel electrode is formed on the same surface as the gate electrode, the source electrode, and the drain electrode, the passivation film on the pixel electrode is unnecessary and needs to be removed. In addition, in order to increase the aperture ratio, in the case of a structure in which a pixel electrode is formed on the surface of the uppermost layer of the substrate and a TFT having a flat film is formed in the lower layer, the drain electrode of the TFT and the pixel electrode are connected. A passivation film is not necessary in the opening of the through hole and must be removed.

  As described above, the passivation film is usually unnecessary for portions other than the semiconductor, and needs to be patterned into a predetermined shape.

As a patterning method for the passivation film, a method using a dry process such as a photolithography method or a vacuum evaporation method (for example, refer to Patent Document 1), or a resist film for lift-off is formed before the passivation film is formed. In addition, a method of lifting off and removing a lift-off resist layer after film formation is known.
JP 2004-221562 A

  However, the method disclosed in Patent Document 1 requires a photolithography process for forming a resist pattern in patterning the passivation film in addition to forming the passivation film, which complicates the manufacturing process. There is a problem that the manufacturing equipment is expensive. In addition, when forming a resist pattern by photolithography, it is necessary to highly accurately align the TFT position completed in the previous process, which leads to a further increase in the cost of the manufacturing apparatus. There is. Also, when patterning a passivation film by lift-off, when patterning a resist film for lift-off, as in the case of Patent Document 1, a photolithography process and high-precision alignment are required. There is a problem that the manufacturing process is complicated and the price of the manufacturing apparatus is increased.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a thin film transistor capable of obtaining stable performance in a simple process.

  The above object is achieved by the invention described in any one of 1 to 9 below.

1. A method of manufacturing a thin film transistor using a photolithography method,
A patterning step of processing a photosensitive resin film formed on the substrate on which at least one of the gate electrode layer and the source / drain electrode layer is formed into a predetermined pattern shape by a photolithography method;
A lift-off resist forming step of leaving a predetermined region portion of the photosensitive resin film formed in the predetermined pattern shape without removing, and a lift-off resist used in a later step;
After the lift-off resist forming step, a semiconductor film is formed so as to be bonded to the source electrode and the drain electrode, and a semiconductor protective film is formed so as to cover the semiconductor film and the substrate on which the lift-off resist is formed A film forming process;
And a protective film removing step for removing the semiconductor protective film formed on the lift-off resist.

2. The thin film transistor has a pixel electrode layer formed on the substrate,
2. The method of manufacturing a thin film transistor according to 1 above, wherein the lift-off resist forming step forms the lift-off resist on the pixel electrode layer.

3. In the patterning step, the photosensitive resin film is processed into a predetermined pattern shape by multi-tone exposure and first development,
3. The thin film transistor according to 2 above, wherein the lift-off resist forming step removes the photosensitive resin film in a region excluding the photosensitive resin film formed in the region on the pixel electrode layer by the second development. Manufacturing method.

  4). 4. The method of manufacturing a thin film transistor according to any one of 1 to 3, wherein the photosensitive resin film is a photoresist film.

  5. 3. The method of manufacturing a thin film transistor according to 1 or 2, wherein the photosensitive resin film is a gate insulating film.

  6). 3. The method of manufacturing a thin film transistor according to 1 or 2 above, wherein the photosensitive resin film is made of a bank material used when a droplet material is applied to a predetermined region.

7). A method of manufacturing a thin film transistor using a photolithography method,
A photosensitive resin film formed on a substrate on which a thin film transistor having a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor film is formed is processed into a predetermined pattern shape by photolithography. Patterning process to
A lift-off resist forming step of leaving a predetermined region portion of the photosensitive resin film formed in the predetermined pattern shape without removing, and a lift-off resist used in a later step;
A protective film forming step of forming a semiconductor protective film so as to cover the thin film transistor and the substrate on which the lift-off resist is formed;
And a protective film removing step for removing the semiconductor protective film formed on the lift-off resist.

8). The thin film transistor has a pixel electrode formed on the substrate,
8. The method of manufacturing a thin film transistor according to 7, wherein the lift-off resist forming step forms the lift-off resist on the pixel electrode.

  9. 9. The method of manufacturing a thin film transistor according to 7 or 8, wherein the photosensitive resin film is a PVA film.

  According to the present invention, a predetermined region portion of a photosensitive resin film used in a thin film transistor manufacturing process is left without being removed, and the remaining portion is lifted off when patterning a semiconductor protective film formed in a subsequent process. It was used as a resist. This eliminates the need for a photolithography process for newly forming a lift-off resist in order to pattern the semiconductor protective film, thereby simplifying the manufacturing process.

  Further, by using a predetermined region portion of the photosensitive resin film processed into a predetermined pattern shape by photolithography as a lift-off resist, the relative position between the base member and the lift-off resist in the predetermined region portion is uniquely determined. . For example, when an etching resist for patterning the pixel electrode is used as the lift-off resist, the position of the pixel electrode and the position of the opening of the semiconductor protective film can be matched with high accuracy. That is, high-precision alignment between the lift-off resist and the region where the semiconductor protective film of the base member is to be opened becomes unnecessary, and the manufacturing apparatus can be reduced in price.

  Embodiments of a method for manufacturing a thin film transistor (hereinafter also referred to as TFT) according to the present invention will be described below with reference to the drawings. In addition, although this invention is demonstrated based on embodiment of illustration, this invention is not limited to this embodiment.

Embodiment 1
FIG. 1 shows a manufacturing process of a TFT according to the first embodiment. 1A to 1G are process cross-sectional views. As shown in FIG. 1G, the TFT 1 according to the first embodiment is a bottom gate bottom contact type, and the pixel electrode PX and the gate electrode G are formed in the same process. The first embodiment is a patterning method of a passivation film 107 (semiconductor protective film) using a photoresist film 103 for patterning the gate electrode G and the pixel electrode PX.

  Hereinafter, the patterning method of the passivation film 107 of the TFT 1 according to the first embodiment will be described with reference to FIG.

  First, in order to pattern the gate electrode G and the pixel electrode PX from the electrode layer 102 formed on the substrate 101, a photoresist film (photosensitive resin film; Hereinafter, a resist film 103 is formed (FIG. 1A).

  Next, mask exposure is performed on the resist film 103. By performing halftone exposure (multi-tone exposure) using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A first developing area A1, a second developing area A2, and a lift-off resist area A3 are formed (FIG. 1B).

  In the first development process, the first development region A1 is developed to pattern the resist film 103, and the gate electrode G and the pixel electrode PX are patterned by the subsequent etching process (FIG. 1C); Process).

  In the second development step, the second development region A2 is developed, the resist film 103a on the gate electrode G is removed, and the resist film 103b remains only on the pixel electrode PX. This resist film 103b becomes a lift-off resist (FIG. 1 (d); lift-off resist forming step).

  Next, by forming a gate insulating film 104, a source electrode S, a drain electrode D, a semiconductor film 105, and a PVA film 106 using a known method, a bottom-gate / bottom-contact TFT 10 is manufactured (FIG. 1E )).

Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the resist film 103b, and the like are formed (FIG. 1F; protective film formation step). The film forming method may be performed by a commonly used method, and the means is not limited. The material for the passivation film 107 includes SiO ₂ and SiNx, but the material type is not limited as long as the performance of protecting the TFT is sufficient.

  Finally, the resist film 103b remaining on the pixel electrode PX that has become the lift-off resist region A3 by the halftone exposure is lifted off. The resist film 103b and the passivation film 107b formed on the resist film 103b are removed by lift-off, and the passivation film 107 is patterned to complete the TFT 1 in which the pixel electrode PX is exposed (FIG. 1G; protective film). Removal step).

[Embodiment 2]
FIG. 2 shows a manufacturing process of the TFT according to the second embodiment. 2A to 2H are process cross-sectional views. As shown in FIG. 2H, the TFT 1 according to the second embodiment is a bottom gate bottom contact type as in the first embodiment, and the pixel electrode PX and the gate electrode G are formed in the same process. The second embodiment is a patterning method for the passivation film 107 using the gate insulating film 104.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the second embodiment will be described with reference to FIG.

  First, in order to pattern the gate electrode G and the pixel electrode PX from the electrode layer 102 formed on the substrate 101, a resist film 103 is formed on the substrate 101 on which the electrode layer 102 is formed (FIG. 2 (a)).

  Next, mask exposure is performed on the resist film 103 (FIG. 2B). Thereafter, by performing development processing and etching processing, the electrode layer 102 in the region where the resist film 103 has been removed is etched. By peeling off the resist film 103 remaining on the electrode layer 102 after the etching, the gate electrode G and the pixel electrode PX are patterned (FIG. 2C).

  Next, a gate insulating film 104 (photosensitive resin film) having photosensitivity is formed on the substrate 101 on which the gate electrode G and the pixel electrode PX are patterned (FIG. 2D).

  Next, mask exposure is performed on the gate insulating film 104. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a gate insulating film region A3 are formed (FIG. 2E).

  In the first development step, the first development region A1 is developed to pattern the gate insulation film 104, and the gate insulation film on the gate insulation film 104a and the pixel electrode PX that serves as a lift-off resist to be lifted off in a subsequent process. 104b remains on the substrate 101 (FIG. 2F).

  Next, the source electrode S, the drain electrode D, the semiconductor film 105, and the PVA film 106 are formed by using a known method, whereby the bottom gate / bottom contact type TFT 10 is manufactured.

  Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the gate insulating film 104b, and the like are formed (FIG. 2G).

  Finally, the gate insulating film 104b remaining on the pixel electrode PX which has become the lift-off resist region A2 by halftone exposure is lifted off. The gate insulating film 104b and the passivation film 107b formed on the gate insulating film 104b are removed by lift-off, the passivation film 107 is patterned, and the TFT 1 with the pixel electrode PX exposed is completed (FIG. 2H). .

[Embodiment 3]
FIG. 3 shows a manufacturing process of the TFT according to the third embodiment. 3A to 3G are process cross-sectional views. As shown in FIG. 3G, the TFT 1 according to the third embodiment is a bottom gate bottom contact type as in the first embodiment, and the pixel electrode PX and the gate electrode G are formed in the same process. The third embodiment is a patterning method of the passivation film 107 using the resist film 103 that becomes a bank for forming the source electrode S and the drain electrode D.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the third embodiment will be described with reference to FIG.

  First, as a pre-process of the process shown in FIG. 3A, the gate electrode G and the pixel electrode PX are patterned through the processes of FIGS. 2A to 2C described in the second embodiment. Next, a photosensitive gate insulating film 104 is formed on the substrate 101 on which the gate electrode G and the pixel electrode PX are patterned. Thereafter, by performing mask exposure and development processing on the gate insulating film 104, the gate insulating film 104a is patterned only on the gate electrode G portion.

  Next, a resist film 103 serving as a bank for forming the source electrode S and the drain electrode D is formed on the substrate 101 on which the gate electrode G, the pixel electrode PX, and the gate insulating film 104a are patterned (FIG. 3). (B)).

  Next, mask exposure is performed on the resist film 103. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a source / drain electrode forming bank region A3 are formed (FIG. 3C).

  In the first development process, the first development region A1 is developed to pattern the resist film 103, and the resist film 103a serving as a source / drain electrode formation bank and the pixel electrode PX serving as a lift-off resist to be lifted off in a subsequent process. The resist film 103b on the substrate remains on the substrate 101 (FIG. 3D).

  Next, a source electrode S and a drain electrode D are formed using a source / drain electrode forming bank (resist film 103a) by using a solution process such as an ink jet method, a sputtering method, or a vapor deposition method. -The drain electrode forming bank (resist film 103a) is removed (FIG. 3E).

  Next, the bottom gate / bottom contact type TFT 10 is manufactured by forming the semiconductor film 105 and the PVA film 106 using a known method.

  Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the resist film 103b, and the like are formed (FIG. 3F).

  Finally, the resist film 103b remaining on the pixel electrode PX that has become the lift-off resist region A2 by the halftone exposure is lifted off. The resist film 103b and the passivation film 107b formed on the resist film 103b are removed by lift-off, and the passivation film 107 is patterned to complete the TFT 1 in which the pixel electrode PX is exposed (FIG. 3G).

[Embodiment 4]
FIG. 4 shows a manufacturing process of the TFT according to the fourth embodiment. 4A to 4F are process cross-sectional views. As shown in FIG. 4F, the TFT 1 according to the fourth embodiment is a bottom gate bottom contact type as in the first embodiment, and the pixel electrode PX and the gate electrode G are formed in the same process. The fourth embodiment is a passivation film patterning method using the bank 108 for forming the semiconductor film 105.

  Hereinafter, a method for patterning the passivation film 107 of the TFT 1 according to the fourth embodiment will be described with reference to FIG.

  First, as a pre-process of the process shown in FIG. 4A, the gate electrode G, the gate insulating film 104, the source electrode S, and the like are formed on the substrate 101 in accordance with the method described in the first to third embodiments. A drain electrode D and a pixel electrode PX are formed.

  Next, a bank material 108 (photosensitive resin film) having photosensitivity that becomes a bank 108a for forming the semiconductor film 105 on the substrate 101 on which the source electrode S, the drain electrode D, the pixel electrode PX, and the like are formed. A film is formed (FIG. 4A).

  Next, mask exposure is performed from above the bank 108. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a semiconductor film forming bank region A3 are formed (FIG. 4B).

  The bank 108 is patterned by developing the first development area A1 in the first development process, and the bank 108a serving as a semiconductor film forming bank and the pixel electrode PX serving as a lift-off resist to be lifted off in a subsequent process. The bank 108b remains on the substrate 101 (FIG. 4C).

  Next, a semiconductor film 105 is formed using a semiconductor film forming bank (bank 108a) by using a solution process such as an inkjet method or a dispenser method (FIG. 4D).

  Next, a bottom gate bottom contact type TFT 10 is manufactured by forming a PVA film 106 using a known method.

  Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the bank 108b, and the like are formed (FIG. 4E).

  Finally, the bank 108b remaining on the pixel electrode PX that has become the lift-off resist region A2 by halftone exposure is lifted off. The bank 108b and the passivation film 107b formed on the bank 108b are removed by lift-off, the passivation film 107 is patterned, and the TFT 1 in which the pixel electrode PX is exposed is completed (FIG. 4F).

[Embodiment 5]
FIG. 5 shows a manufacturing process of the TFT according to the fifth embodiment. FIG. 5A to FIG. 5F are process cross-sectional views. As shown in FIG. 5F, the TFT 1 according to the fifth embodiment is a bottom gate bottom contact type as in the first embodiment, and the pixel electrode PX and the gate electrode G are formed in the same process. The fifth embodiment is a patterning method of the passivation film 107 using the PVA film 106.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the fifth embodiment will be described with reference to FIG.

  First, as a pre-process of the process shown in FIG. 5A, the gate electrode G, the gate insulating film 104, the source electrode S, and the like are formed on the substrate 101 in accordance with the method described in the first to fourth embodiments. The TFT 11 in a form in which the drain electrode D, the semiconductor film 105, and the pixel electrode PX are formed is formed.

  Next, a photosensitive PVA film 106 (photosensitive resin film) is formed on the substrate 101 on which the TFT 11 is formed (FIG. 5B).

  Next, mask exposure is performed on the PVA film 106. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a semiconductor film protecting PVA region A3 are formed (FIG. 5C).

  The PVA film 106 is patterned by developing the first development area A1 in the first development process, and the PVA film 106a that protects the semiconductor film 105 and the pixel electrode PX that serves as a lift-off resist that is lifted off in a subsequent process. The PVA film 106b is left on the substrate 101 (FIG. 5D; patterning process, lift-off resist forming process).

  Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the PVA film 106b, etc. are formed (FIG. 5E; protective film formation step).

  Finally, the PVA film 106b remaining on the pixel electrode PX that has become the lift-off resist region A2 by halftone exposure is lifted off. The PVA film 106b and the passivation film 107b formed on the PVA film 106b are removed by lift-off, and the passivation film 107 is patterned to complete the TFT 1 from which the pixel electrode PX is exposed (FIG. 5F; protective film). Removal step).

[Embodiment 6]
FIG. 6 shows a manufacturing process of the TFT according to the sixth embodiment. FIG. 6A to FIG. 6H are process cross-sectional views. As shown in FIG. 6H, the TFT 1 according to Embodiment 6 is a bottom gate bottom contact type, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. The sixth embodiment is a patterning method of the passivation film 107 using the resist film 103 for patterning the pixel electrode PX, the source electrode S, and the drain electrode D.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the first embodiment will be described with reference to FIG.

  First, as a pre-process of the process illustrated in FIG. 6A, the gate electrode G and the gate insulating film 104 are formed on the substrate 101 in accordance with the method described in the first to fifth embodiments. Thereafter, an electrode layer 109 to be a source electrode S, a drain electrode D, and a pixel electrode PX is formed in a subsequent process on the substrate 101 over which the gate insulating film 104 and the like are formed.

  Next, in order to pattern the source electrode S, the drain electrode D, and the pixel electrode PX from the electrode layer 109 formed on the substrate 101, a resist film 103 is formed on the substrate 101 on which the electrode layer 109 is formed. A film is formed (FIG. 6B).

  Next, mask exposure is performed on the resist film 103. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A second developing area A2 and a lift-off resist area A3 are formed (FIG. 6C).

  The resist film 103 is patterned by developing the first developing region A1 in the first developing process, and the source electrode S, the drain electrode D, and the pixel electrode PX are patterned by the subsequent etching process (FIG. 6D). )).

  In the second development step, the second development region A2 is developed, the resist film 103a on the source electrode S and the drain electrode D is removed, and the resist film 103b remains only on the pixel electrode PX. This resist film 103b becomes a lift-off resist (FIG. 6E).

  Next, the semiconductor film 105 and the PVA 106 film are formed by using a known method, thereby manufacturing the bottom gate / bottom contact type TFT 10 (FIG. 6F).

  Next, a passivation film 107 is formed so as to cover the substrate 101 on which the TFT 10, the resist film 103b, and the like are formed (FIG. 6G).

  Finally, the resist film 103b remaining on the pixel electrode PX that has become the lift-off resist region A3 by the halftone exposure is lifted off. The resist film 103b and the passivation film 107b formed on the resist film 103b are removed by lift-off, the passivation film 107 is patterned, and the TFT 1 in which the pixel electrode PX is exposed is completed (FIG. 6H).

[Embodiment 7]
FIG. 7 shows a manufacturing process of the TFT according to the seventh embodiment. FIG. 7A to FIG. 7F are process cross-sectional views. As shown in FIG. 7F, the TFT 1 according to the seventh embodiment is a bottom gate bottom contact type, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. The seventh embodiment is a passivation film patterning method using the bank 108 for forming the semiconductor film 105.

  The manufacturing process of the TFT 1 according to the seventh embodiment is substantially the same as that of the fourth embodiment except that the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. Description is omitted.

[Embodiment 8]
FIG. 8 shows a manufacturing process of the TFT according to the eighth embodiment. FIG. 8A to FIG. 8F are process cross-sectional views. As shown in FIG. 8F, the TFT 1 according to the eighth embodiment is a bottom gate bottom contact type, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. The eighth embodiment is a patterning method for the passivation film 107 using the PVA film 106.

  The manufacturing process of the TFT 1 according to the eighth embodiment is substantially the same as that of the fifth embodiment except that the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. Description is omitted.

[Embodiment 9]
FIG. 9 shows a manufacturing process of the TFT according to the ninth embodiment. FIG. 9A to FIG. 9F are process cross-sectional views. The TFT 1 according to the ninth embodiment is a top gate bottom contact type as shown in FIG. 9F, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. The ninth embodiment is a patterning method of the passivation film 107 using the resist film 103 for patterning the pixel electrode PX, the source electrode S, and the drain electrode D.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the ninth embodiment will be described with reference to FIG.

  First, in order to pattern the source electrode S, the drain electrode D, and the pixel electrode PX from the electrode layer 109 formed on the substrate 101, a resist film 103 is formed on the substrate 101 on which the electrode layer 109 is formed. A film is formed (FIG. 9A).

  Next, mask exposure is performed on the resist film 103. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A second developing area A2 and a lift-off resist area A3 are formed (FIG. 9B).

  The resist film 103 is patterned by developing the first developing region A1 in the first developing step, and the source electrode S, the drain electrode D, and the pixel electrode PX are patterned by the subsequent etching process (FIG. 9C). )).

  In the second development step, the second development region A2 is developed, the resist film 103a on the source electrode S and the drain electrode D is removed, and the resist film 103b remains only on the pixel electrode PX. This resist film 103b becomes a lift-off resist. Thereafter, a semiconductor film 105 is formed in a channel portion between the source electrode S and the drain electrode D by using a known method (FIG. 9D).

  Next, a gate insulating film 104 is formed using a spin coating method or the like so as to cover the substrate 101 over which the semiconductor film 105, the resist film 103b, and the like are formed. Thereafter, a gate electrode G is formed on the gate insulating film 104, thereby producing a top gate / bottom contact TFT 10 (FIG. 9E). In this case, the gate insulating film 104 covers the semiconductor film 105 and also functions as a passivation film.

  Finally, the resist film 103b remaining on the pixel electrode PX that has become the lift-off resist region A3 by the halftone exposure is lifted off. The resist film 103b and the gate insulating film 104b formed on the resist film 103b are removed by lift-off, the gate insulating film 104 functioning as a passivation film is patterned, and the TFT 1 with the pixel electrode PX exposed is completed (FIG. 9 (f)).

[Embodiment 10]
FIG. 10 shows a manufacturing process of the TFT according to the tenth embodiment. FIG. 10A to FIG. 10H are process cross-sectional views. As shown in FIG. 10H, the TFT 1 according to the tenth embodiment is a top gate bottom contact type as in the ninth embodiment, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. Has been. The tenth embodiment is a passivation film patterning method using the bank 108 for forming the semiconductor film 105.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the tenth embodiment will be described with reference to FIG.

  First, as a pre-process of the process illustrated in FIG. 10A, the source electrode S, the drain electrode D, and the pixel electrode PX are formed on the substrate 101 in accordance with the method described in the first to ninth embodiments. To do.

  Next, a photosensitive bank 108 material to be a bank 108a for forming the semiconductor film 105 is formed on the substrate 101 on which the source electrode S, the drain electrode D, and the pixel electrode PX are formed (FIG. 10 (FIG. 10). b)).

  Next, mask exposure is performed from above the bank 108. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a semiconductor film forming bank region A3 are formed (FIG. 10C).

  The bank 108 is patterned by developing the first development area A1 in the first development process, and the bank 108a serving as a semiconductor film forming bank and the pixel electrode PX serving as a lift-off resist to be lifted off in a subsequent process. The bank 108b remains on the substrate 101 (FIG. 10D).

  Next, a semiconductor film 105 is formed using a semiconductor film forming bank (bank 108a) by using a solution process such as an inkjet method or a dispenser method (FIG. 10E).

  Next, a gate insulating film 104 is formed using a spin coating method or the like so as to cover the substrate 101 over which the semiconductor film 105, the bank 108b, and the like are formed (FIG. 10F). Thereafter, a gate electrode G is formed on the gate insulating film 104, thereby producing a top gate / bottom contact type TFT 10 (FIG. 10G). In this case, the gate insulating film 104 covers the semiconductor film 105 and also functions as a passivation film.

  Finally, the bank 108b remaining on the pixel electrode PX that has become the lift-off resist region A2 by halftone exposure is lifted off. The gate insulating film 104b formed on the bank 108b and the bank 108b is removed by lift-off, the gate insulating film 104 functioning as a passivation film is patterned, and the TFT 1 in which the pixel electrode PX is exposed is completed (FIG. 10 ( h)).

[Embodiment 11]
FIG. 11 shows a manufacturing process of the TFT according to the eleventh embodiment. FIG. 11A to FIG. 11J are process cross-sectional views. As shown in FIG. 11H, the TFT 1 according to the eleventh embodiment is a top gate bottom contact type as in the ninth embodiment, and the pixel electrode PX, the source electrode S, and the drain electrode D are formed in the same process. Has been. The eleventh embodiment is a patterning method of the passivation film 107 using the gate insulating film 104.

  Hereinafter, a patterning method of the passivation film 107 of the TFT 1 according to the eleventh embodiment will be described with reference to FIG.

  First, as a pre-process of the process shown in FIG. 11A, the source electrode S, the drain electrode D, and the pixel electrode PX are formed on the substrate 101 in accordance with the method described in the first to tenth embodiments. To do.

  Next, a semiconductor film 105 is formed in a channel portion between the source electrode S and the drain electrode D using a known method (FIG. 11B).

  Next, a photosensitive gate insulating film 104 is formed so as to cover the substrate 101 on which the source electrode S, the drain electrode D, the pixel electrode PX, and the semiconductor film 10 are formed (FIG. 11C). In this case, the gate insulating film 104 covers the semiconductor film 105 and also functions as a passivation film.

  Next, mask exposure is performed on the gate insulating film 104. By performing halftone exposure using the halftone mask 50 at the time of exposure, regions with an exposure amount of 100%, an intermediate value (for example, 50%), and 0% are formed. A lift-off resist region A2 and a gate insulating film region A3 are formed (FIG. 11D).

  In the first development step, the first development region A1 is developed to pattern the gate insulation film 104, and the gate insulation film on the gate insulation film 104a and the pixel electrode PX that serves as a lift-off resist to be lifted off in a subsequent process. 104b remains on the substrate 101 (FIG. 11E).

  Next, in order to pattern the gate electrode G, a resist film 103 is formed on the substrate 101 on which the gate insulating film 104a, the gate insulating film 104b, and the like are formed (FIG. 11F).

  Next, mask exposure and development are performed on the resist film 103 to remove the resist film 103a where the gate electrode G is to be formed.

  Next, the electrode layer 102 is formed on the substrate 101 on which the resist film 103b for forming the gate electrode G is patterned by using a vapor deposition method, a sputtering method, or the like (FIG. 11H). Thereafter, the resist film 103b is peeled off from the substrate 101, whereby the gate electrode G is formed at a desired portion, and the top gate / bottom contact type TFT 10 is manufactured (FIG. 11 (i)).

  Finally, the gate insulating film 104b remaining on the pixel electrode PX which has become the lift-off resist region A2 by halftone exposure is lifted off. The gate insulating film 104b is removed by lift-off, the gate insulating film 104 functioning as a passivation film is patterned, and the TFT 1 with the pixel electrode PX exposed is completed (FIG. 10H).

  As described above, in the manufacturing method of the TFT 1 according to the present invention, the photosensitive resin film (the photoresist film 103, the gate insulating film 104, the bank material 108, the PVA film 106) used in the manufacturing process of the TFT 1 is used. A predetermined region portion is left without being removed, and the remaining portion is used as a lift-off resist when patterning the passivation film 107 and the gate insulating film 104 functioning as a passivation film formed in a subsequent process. This eliminates the need for a photolithography process for newly forming a lift-off resist in order to pattern the passivation film 107 and the gate insulating film 104 functioning as a passivation film, thereby simplifying the manufacturing process.

  Further, by using a predetermined region portion of the photosensitive resin film processed into a predetermined pattern shape by photolithography as a lift-off resist, the relative position between the base member and the lift-off resist in the predetermined region portion is uniquely determined. . For example, when the etching resist film 103 for patterning the pixel electrode PX is used as a lift-off resist, the position of the pixel electrode PX and the position of the opening of the passivation film 107 can be matched with high accuracy. That is, highly accurate alignment between the lift-off resist and the region where the passivation film 107 of the base member is desired to be opened becomes unnecessary, and the manufacturing apparatus can be reduced in price.

It is a figure which shows the manufacturing process of TFT by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 3 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 4 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 5 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 6 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 7 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 8 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 9 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 10 of this invention. It is a figure which shows the manufacturing process of TFT by Embodiment 11 of this invention.

Explanation of symbols

1, 10 TFT
101 Substrate 102, 109 Electrode Layer 103 Resist Film 104 Gate Insulating Film 105 Semiconductor Film 106 PVA Film 107 Passivation Film 108 Bank D Drain Electrode G Gate Electrode PX Pixel Electrode S Source Electrode 50 Halftone Mask

Claims (10)

A method of manufacturing a thin film transistor using a photolithography method,
A patterning step of processing the photosensitive resin film formed on the substrate on which the gate electrode layer is formed into a predetermined pattern shape by a photolithography method;
A lift-off resist forming step of leaving a predetermined region portion of the photosensitive resin film formed in the predetermined pattern shape without removing, and a lift-off resist used in a later step;
Forming a source electrode and a drain electrode on the substrate after the lift-off resist is formed;
Forming a semiconductor film so as to be joined to the source electrode and the drain electrode, and a protective film forming step of forming a semiconductor protective film to cover the substrate in which the semiconductor film and the lift-off resist is formed,
And a protective film removing step for removing the semiconductor protective film formed on the lift-off resist .
The thin film transistor has a pixel electrode layer formed on the substrate,
In the lift-off resist formation step, the lift-off resist is formed on the pixel electrode layer,
In the patterning step, the photosensitive resin film is processed into a predetermined pattern shape including a lift-off resist region on the pixel electrode layer by multi-tone exposure and one-time development. . A method of manufacturing a thin film transistor using a photolithography method,
A patterning step of processing the photosensitive resin film formed on the substrate on which the source electrode and the drain electrode are formed into a predetermined pattern shape by a photolithography method;
A lift-off resist forming step of leaving a predetermined region portion of the photosensitive resin film formed in the predetermined pattern shape without removing, and a lift-off resist used in a later step;
After the lift-off resist is formed, a semiconductor film is formed so as to be bonded to the source electrode and the drain electrode, and a semiconductor protective film is formed so as to cover the semiconductor film and the substrate on which the lift-off resist is formed. A protective film forming step;
And a protective film removing step for removing the semiconductor protective film formed on the lift-off resist.
The thin film transistor has a pixel electrode layer formed on the substrate,
In the lift-off resist formation step, the lift-off resist is formed on the pixel electrode layer ,
In the patterning step, the photosensitive resin film is processed into a predetermined pattern shape including a lift-off resist region on the pixel electrode layer by multi-tone exposure and one-time development. . In the patterning process, after it said photosensitive resin film is a multi-tone exposure, processed into the predetermined pattern by a first development,
In the lift-off resist forming step, to claim 1 or 2, characterized in that the removal of the photosensitive resin film in the region except for the second photosensitive resin layer formed in the area above the pixel electrode layer by development of The manufacturing method of the thin-film transistor of description. 4. The method of manufacturing a thin film transistor according to claim 2, wherein a gate electrode is formed on the substrate on which the photosensitive resin film is formed in the patterning step. 4. The method of manufacturing a thin film transistor according to claim 2, further comprising a step of forming a gate electrode after forming the semiconductor protective film. 6. The method of manufacturing a thin film transistor according to claim 1, wherein the photosensitive resin film is a photoresist film. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the photosensitive resin film is a gate insulating film. In the patterning step, a bank is formed by patterning the photosensitive resin film,
A source electrode, a drain electrode, or a droplet material of a semiconductor film formed on the substrate after the lift-off resist is formed is applied to a predetermined region using the bank, so that the source electrode, the drain electrode, or The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor film is formed. A method of manufacturing a thin film transistor using a photolithography method,
A photosensitive resin film formed on a substrate on which a thin film transistor having a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor film is formed is processed into a predetermined pattern shape by photolithography. Patterning process to
A lift-off resist forming step of leaving a predetermined region portion of the photosensitive resin film formed in the predetermined pattern shape without removing, and a lift-off resist used in a later step;
A protective film forming step of forming a semiconductor protective film so as to cover the thin film transistor and the substrate on which the lift-off resist is formed;
And a protective film removing step for removing the semiconductor protective film formed on the lift-off resist.
The thin film transistor has a pixel electrode formed on the substrate,
In the lift-off resist formation step, the lift-off resist is formed on the pixel electrode,
In the patterning step, the photosensitive resin film is processed into a predetermined pattern shape including a lift-off resist region on the pixel electrode by multi-tone exposure and one development. The method of manufacturing a thin film transistor according to claim 9, wherein the photosensitive resin film is a PVA film.

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