JP5198212B2 - Multi-carrier modulation signal receiver - Google Patents

Description

  The present invention relates to a multi-carrier modulation signal receiving apparatus, and more particularly to a receiving apparatus that can correctly receive transmission data even in a multipath environment that causes problems when receiving radio waves in digital broadcasting, wireless LAN, and the like.

  For example, OFDM (Orthogonal Frequency Division Multiplexing) is a multi-carrier modulation method used for digital broadcasting, wireless LAN, and the like. In OFDM, a period called a guard interval (GI: Guard Interval) or a cyclic prefix (CP) is provided and signal period extension is performed in order to obtain multipath tolerance.

  On the other hand, Non-Patent Document 1 points out that OFDM is a kind of transmultiplexer. FIG. 10 is a block diagram showing a configuration of a general transmultiplexer. The transmultiplexer 100 includes a synthesis bank including M interpolators and M transmission filters, and an analysis bank including M reception filters and M decimators. The synthesis bank and the analysis bank are connected via a channel (transmission path).

  FIG. 11 is a block diagram showing a configuration when OFDM is expressed as a transmultiplexer. As can be seen from FIG. 11, OFDM is a DFT modulation transmultiplexer in which the filter coefficients of the prototype filter are all 1 and the filter length matches the number of subchannels. This is clear from the fact that the OFDM pulse forming filter uses a rectangular window function.

  However, the prototype filter in this OFDM has a first sidelobe level of about −13 dB and poor frequency characteristics. In order to cope with this, it is necessary to perform channel equalization by suppressing the occurrence of intersymbol interference and carrier interference by setting GI. Non-Patent Document 1 points out that the influence of a channel (transmission path) can be further reduced by performing more ideal frequency division multiplexing.

  By the way, a DFT modulation filter bank (a system in which an analysis bank and a synthesis bank of a DFT modulation transmultiplexer are dual) has an FFT (Fast) for analysis and synthesis if the number of subchannels is a power of two. Since it is possible to use a Fourier Transform pair, it is known to be useful in practical use.

  Non-Patent Document 2 shows that a perfect reconstruction condition is satisfied in a pseudo manner by correcting the decimation of the DFT modulation filter bank in two stages. That is, it is shown that the output signal is approximately equal to a constant multiple of the time delay of the input signal.

  FIG. 12 is a block diagram showing the configuration of the modified DFT modulation synthesis bank, and FIG. 13 is a block diagram showing the configuration of the modified DFT modulation analysis bank. In FIG. 12, the modified DFT modulation synthesis bank 101 receives M subchannel signals, extracts the real part component and the imaginary part component of the subchannel signal, performs the first-stage interpolation, and performs the delay. The real part component and the imaginary part component are combined. Then, a second stage of interpolation is performed on the synthesized signal to perform filtering, and all the subchannel signals are synthesized and output as an equivalent baseband signal. In FIG. 13, the modified DFT modulation analysis bank 102 receives an equivalent baseband signal, branches it into M equivalent baseband signals, respectively performs a filtering process to perform a first stage decimation, The second-stage decimation is performed on the delayed imaginary part component, and the real part component and the imaginary part component are combined and output as M subchannel signals, respectively.

  From the viewpoint of the multi-carrier modulation system, the modified DFT modulation synthesis bank 101 shown in FIG. 12 and the modified DFT modulation analysis bank 102 shown in FIG. 102 becomes a demodulator. That is, by using the modified DFT modulation synthesis bank 101 and the modified DFT modulation analysis bank 102 at the transmitting and receiving ends, signal transmission by the multicarrier modulation method can be realized. In this case, since a prototype filter having a filter length longer than the number of subchannels can be used, better frequency characteristics can be realized. However, if there is distortion due to multipath in the channel between transmission and reception, a channel equalizer is required.

Ali N. Akansu, Pierre Dubamel, Xueming Lin, and Marc de Courville. “Orthogonal transmultiplexers in communications: A review.”, IEEE Trans. Signal Process., 46 (4): 979-995, April 1998. Tanja Karp and N.J. Fliege., “Modified DFT filter banks with perfect reconstruction.”, IEEE Trans. Circuits Syst. II, 46 (11): 1404-1414, November 1999.

  In the conventional OFDM transmission / reception apparatus, a GI is added in order to obtain resistance against multipath, and the OFDM signal is periodically extended during that period. Therefore, channel equalization can be performed by a 1-tap filter in a simple frequency domain.

  However, when the delay spread of the channel exceeds the GI length, reception characteristics are significantly impaired due to the occurrence of intersymbol interference and intercarrier interference. Furthermore, since the GI is the same as the end of the OFDM symbol, it is redundant information, and there is a problem that transmission efficiency is sacrificed in order to obtain multipath tolerance.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a multicarrier modulation signal receiving apparatus capable of obtaining resistance against multipath without transmitting redundant information. is there.

In order to solve the above-mentioned problem, a multicarrier modulation signal receiving apparatus according to claim 1 according to the present invention receives a multicarrier modulation signal received by a modified DFT modulation synthesis bank performing two-stage interpolation. A modified DFT modulation analysis bank that performs two-stage decimation and operates at twice the maximum decimation rate, wherein the modified DFT modulation analysis bank receives the multi-carrier modulated signal and is orthogonal A demodulated equivalent baseband signal, a filter and a decimator for generating a subchannel signal by subjecting the delayed equivalent baseband signal to filtering and decimating processing, and a real part component and an imaginary part component from the subchannel signal. Extract and output real subchannel signal vector Characterized in that and a sub-channel processing unit for outputting the imaginary part subchannel signal vector to generate a real component and an imaginary component and a real component becomes imaginary component paired said extracted.

  According to a second aspect of the present invention, there is provided the multicarrier modulation signal receiving apparatus according to the first aspect, wherein the modified DFT modulation analysis bank delays the quadrature demodulated equivalent baseband signal. Decimating a delay device, an analysis filter for filtering the equivalent baseband signal, and an equivalent baseband signal delayed by the delay device, and a subchannel signal filtered by the analysis filter Based on the decimator and the subchannel signal decimated by the decimator, the real part component and the imaginary part component are extracted to output a real part subchannel signal vector, and the imaginary part is obtained based on the real part subchannel signal vector. Subchannel processing that generates and outputs subchannel signal vectors Characterized by comprising a and.

  A multi-carrier modulation signal receiving apparatus according to claim 3 of the present invention is the multi-carrier modulation signal receiving apparatus according to claim 1, which is an analysis bank equivalent to the modified DFT modulation analysis bank. A first polyphase analysis bank for performing a polyphase analysis on the quadrature demodulated equivalent baseband signal to generate a subchannel signal; a delay device for delaying the quadrature demodulated equivalent baseband signal; and the delay device A second polyphase analysis bank that generates a subchannel signal by polyphase analysis of the equivalent baseband signal delayed by the first and second subphase signals generated by the first polyphase analysis bank. And the imaginary part signal are extracted, and the signal generated by the second polyphase analysis bank is extracted. Based on the channel signal, the real part component and the imaginary part component are extracted, the real part subchannel signal vector is generated from the extracted real part component and imaginary part component, and the real part subchannel signal is output. A subchannel processing unit that generates and outputs an imaginary part subchannel signal vector based on the vector.

  A multicarrier modulation signal receiving apparatus according to claim 4 of the present invention is the multicarrier modulation signal receiving apparatus according to any one of claims 1 to 3, wherein the subchannel processing unit includes two real parts. Generate and output a real part subchannel signal vector from the component and two imaginary part components, and multiply the real part subchannel signal vector by a predetermined transformation matrix to generate and output an imaginary part subchannel signal vector. It is characterized by that.

  A multicarrier modulation signal receiving apparatus according to claim 5 of the present invention is the multicarrier modulation signal receiving apparatus according to any one of claims 1 to 4, wherein the modified DFT modulation analysis bank includes subchannel processing. And a linear equalizer that linearly equalizes the real part subchannel signal vector and the imaginary part subchannel signal vector output by the part with an equalization coefficient.

  According to a sixth aspect of the present invention, there is provided the multicarrier modulation signal receiving apparatus according to the fifth aspect, wherein the linear equalizer is a real part subchannel output by a subchannel processing section. A first equalizer that linearly equalizes a signal vector and a second equalizer that linearly equalizes an imaginary part subchannel signal vector, linearly equalized by the first equalizer A complex carrier symbol is output based on the real part subchannel signal and the imaginary part subchannel signal linearly equalized by the second equalizer.

  According to a seventh aspect of the present invention, there is provided the multicarrier modulation signal receiving apparatus according to the fifth aspect, wherein the pilot signal included in the multicarrier modulated signal is a minimum as a reference signal. An equalization coefficient calculation unit that calculates an equalization coefficient for performing linear equalization by the linear equalizer based on a square error criterion is provided.

  The multicarrier modulation signal receiving apparatus according to claim 8 of the present invention is the multicarrier modulation signal receiving apparatus according to claim 7, wherein the equalization coefficient calculation unit includes the real part subchannel signal vector and the imaginary part subchannel. A common equalization coefficient for linear equalization of channel signal vectors is calculated.

  The invention according to claim 9 is the multicarrier modulation signal receiving apparatus according to claim 7, wherein the equalization coefficient calculation unit uses each of the real part component and the imaginary part component of the pilot signal as a reference signal. The equalization coefficient is updated twice with the signal.

  As described above, according to the present invention, the modified DFT modulation analysis bank operates the received signal substantially at twice the maximum thinning rate, and in addition to the original output signal, the output signal is a real part component. In addition, two types of subchannel signal vectors (a real part subchannel signal vector and an imaginary part subchannel signal vector) are output in combination with output signals having opposite (paired) imaginary part components. Then, the linear equalizer linearly equalizes the two types of subchannel signal vectors output by the modified DFT modulation analysis bank and processed at twice the maximum decimation rate, so that redundant information such as GI is obtained. It is possible to obtain resistance against multipath without transmitting.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
[Multi-carrier modulation signal receiver]
FIG. 1 is a block diagram showing a configuration of a multicarrier modulation signal receiving apparatus according to an embodiment of the present invention. The multicarrier modulation signal receiving apparatus 1 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an analysis bank 5, a linear equalizer 6, an equalization coefficient calculation unit 7, a demapping unit 8, and a parallel A serial conversion unit 9 is provided. The analysis bank 5 reflects the configuration of the analysis bank 5-1 shown in FIG. 2 or the analysis bank 5-2 shown in FIG.

  The frequency conversion unit 2 inputs a signal received by the multicarrier modulation signal receiving apparatus 1 and converts the frequency of the input signal into an IF signal. The IF signal output from the frequency converter 2 is input to the A / D converter 3. The A / D converter 3 A / D converts the IF signal (analog IF signal) input from the frequency converter 2 into a digital IF signal. The digital IF signal output from the A / D converter 3 is input to the quadrature demodulator 4. The orthogonal demodulator 4 orthogonally demodulates the digital IF signal input from the A / D converter 3 into an equivalent baseband signal. The equivalent baseband signal output from the quadrature demodulator 4 is input to the analysis bank 5.

  The analysis bank 5 converts the equivalent baseband signal input from the quadrature demodulation unit 4 into a frequency domain signal at a rate twice the maximum decimation rate, and a real part component and an imaginary part component of the output signal in a normal analysis bank In addition, an imaginary part component and a real part component paired with a normal output signal are also output together. That is, the analysis bank 5 includes two real part components and two imaginary part components, a real part subchannel signal vector composed of four real number signals, and two real part components and two imaginary parts. An imaginary part subchannel signal vector composed of four components of the real number signals is output. The real part sub-channel signal vector and the imaginary part sub-channel signal vector (hereinafter collectively referred to as sub-channel signal vectors) output from the analysis bank 5 are divided into two, one being equalized to the linear equalizer 6 and the other being equalized. Input to the coefficient calculation unit 7.

  The linear equalizer 6 linearly equalizes the subchannel signal vector input from the analysis bank 5 using the equalization coefficient input from the equalization coefficient calculation unit 7. The equalized subchannel signal output from the linear equalizer 6 is divided into two, one being input to the demapping unit 8 and the other being input to the equalization coefficient calculation unit 7.

  The equalization coefficient calculator 7 calculates an equalization coefficient using the subchannel signal vector input from the analysis bank 5 and the subchannel signal after equalization input from the linear equalizer 6. The equalization coefficient output from the equalization coefficient calculation unit 7 is input to the linear equalizer 6.

  The demapping unit 8 demaps the equalized subchannel signal input from the linear equalizer 6 and converts it to a parallel signal. The parallel signal output from the demapping unit 8 is input to the parallel-serial conversion unit 9. The parallel-serial conversion unit 9 converts the parallel signal input from the demapping unit 8 into a serial signal. As described above, the multicarrier modulation signal receiving apparatus 1 receives the received signal, performs various processes from the frequency conversion unit 2 to the parallel serial conversion unit 9, and outputs an output bit string signal to the outside.

[Analysis bank (direct structure)]
Next, the first configuration (direct configuration) of the analysis bank 5 shown in FIG. 1 will be described. FIG. 2 is a block diagram showing a first configuration of the analysis bank 5. This analysis bank 5-1 includes delay units 11-1 to 11- (M-1), analysis filters 12-0 to 12- (M-1), decimators 13-0 to 13- (M-1), and sub Channel processing units 14-0 to 14- (M-1) are provided. The analysis bank 5-1 receives the equivalent baseband signal from the quadrature demodulator 4 and generates and outputs real part subchannel signal vectors 0 to M-1 and imaginary part subchannel signal vectors 0 to M-1. Here, M is a natural number indicating the number of subchannels of the transmultiplexer, and a power of 2 is generally used. Hereinafter, an arbitrary subchannel is assumed to be k.

  The equivalent baseband signal input from the quadrature demodulator 4 shown in FIG. 1 is divided into two, one input to the delay unit 11-1 and the other input to the analysis filter 12-0. The delay device 11-1 delays the equivalent baseband signal input from the quadrature demodulation unit 4 by one sample. The equivalent baseband signal output from the delay unit 11-1 is divided into two, one input to the analysis filter 12-1 and the other input to the delay unit 11-2.

  Similarly, the delay device 11-k (2 ≦ k <M−1) delays the equivalent baseband signal input from the preceding delay device 11- (k−1) by one sample. The equivalent baseband signal output from the delay unit 11-k is divided into two, one input to the subsequent delay unit 11- (k + 1) and the other input to the analysis filter 12-k.

  The delay unit 11- (M-1) delays the equivalent baseband signal input from the delay unit 11- (M-2) by one sample. The equivalent baseband signal output from the delay device 11- (M-1) is input to the analysis filter 12- (M-1).

  The analysis filter 12-k (0 ≦ k ≦ M−1) receives the equivalent baseband signal and performs filtering. The filtered equivalent baseband signals output from the analysis filter 12-k are respectively input to the decimator 13-k.

  The decimator 13-k (0 ≦ k ≦ M−1) performs a decimation (decimation) of the ratio M / 2 on the filtered equivalent baseband signal input from the analysis filter 12-k. The decimated equivalent baseband signal (subchannel signal k) output from the decimator 13-k is input to the subchannel processing unit 14-k.

  The subchannel processing unit 14-k (0 ≦ k ≦ M−1) performs processing for each subchannel on the equivalent baseband signal (subchannel signal k) after decimation input from the decimator 13-k. A partial subchannel signal vector k and an imaginary part subchannel signal vector k (subchannel signal vector k) are generated and output.

  In the analysis bank 5-1 shown in FIG. 2, the delay unit 11-k and the analysis filter 12-k provided in the preceding stage of the decimator 13-k are M times the maximum decimation rate (maximum decimation rate). Works with. On the other hand, since the decimation rate is M / 2 in the decimator 13-k, the subchannel processing unit 14-k provided in the subsequent stage of the decimator 13-k operates at twice the maximum decimation rate.

[Sub-channel processing section of analysis bank (direct configuration)]
Next, the subchannel processing unit 14-k illustrated in FIG. 2 will be described. FIG. 3 is a block diagram illustrating a configuration of the subchannel processing unit 14-k. The subchannel processing unit 14-k includes delay units 15-1 to 15-3, decimators 16-1 and 16-2, real part extraction units 17-1 and 17-2, and imaginary part extraction units 18-1 and 18. -2 and multipliers 19-1 and 19-2. The subchannel processing unit 14-k receives the subchannel signal k from the decimator 13-k shown in FIG. 2, and receives the real part subchannel signal vector k composed of four elements and the imaginary part sub composed of four elements. Each channel signal vector k is generated and output.

  The subchannel signal k input from the decimator 13-k shown in FIG. 2 is divided into two, one input to the delay unit 15-1 and the other input to the decimator 16-1. The delay unit 15-1 delays the subchannel signal k input from the decimator 13-k by one sample. Since the delay unit 15-1 operates at twice the maximum thinning rate, one sample here means a time that is ½ times the maximum thinning rate. The subchannel signal output from the delay unit 15-1 is input to the decimator 16-2.

  The decimator 16-1 performs decimation with a ratio of 2 on the subchannel signal k input from the decimator 13-k illustrated in FIG. The subchannel signal after decimation output from the decimator 16-1 is divided into two, one being input to the real part extracting unit 17-1 and the other being input to the imaginary part extracting unit 18-1.

  Decimator 16-2 performs a decimation of ratio 2 on the subchannel signal input from delay device 15-1. The subchannel signal after decimation output from the decimator 16-2 is divided into two, one being input to the imaginary part extracting unit 18-2 and the other being input to the real part extracting unit 17-2.

  The real part extraction unit 17-1 extracts a real part from the subchannel signal input from the decimator 16-1, and generates a real subchannel signal. The real number subchannel signal output from the real part extraction unit 17-1 is divided into two, one is output from the subchannel processing unit 14-k as one element of the real part subchannel signal vector k, and the other is the delay unit 15-3. Is input.

  The imaginary part extraction unit 18-1 extracts an imaginary part from the subchannel signal input from the decimator 16-1, and generates a real number subchannel signal. The real subchannel signal output from the imaginary part extraction unit 18-1 is divided into two, one is output from the subchannel processing unit 14-k as one element of the real subchannel signal vector k, and the other is the delay unit 15-2. Is input.

  The imaginary part extraction unit 18-2 extracts an imaginary part from the subchannel signal input from the decimator 16-2 and generates a real number subchannel signal. The real subchannel signal output from the imaginary part extraction unit 18-2 is divided into two parts, one being one element of the real part subchannel signal vector k and the other being one element of the imaginary part subchannel signal vector k. 14-k.

  The real part extraction unit 17-2 extracts a real part from the subchannel signal input from the decimator 16-2 and generates a real number subchannel signal. The real subchannel signal output from the real part extraction unit 17-2 is divided into two, one is output from the subchannel processing unit 14-k as one element of the real part subchannel signal vector k, and the other is the multiplier 19-1. Is input.

  The multiplier 19-1 multiplies the real subchannel signal input from the real part extraction unit 17-2 by -1, and inverts the sign. The real subchannel signal with the sign inverted output from the multiplier 19-1 is output from the subchannel processing unit 14-k as one element of the imaginary part subchannel signal vector k.

  The delay unit 15-2 delays the real subchannel signal input from the imaginary part extraction unit 18-1 by one sample. The real subchannel signal output from the delay unit 15-2 is output from the subchannel processing unit 14-k as one element of the imaginary subchannel signal vector k.

  The delay unit 15-3 delays the real subchannel signal input from the real part extraction unit 17-1 by one sample. The real subchannel signal output from the delay unit 15-3 is input to the multiplier 19-2. The multiplier 19-2 multiplies the real subchannel signal input from the delay unit 15-3 by -1, and inverts the sign. The real subchannel signal with the inverted sign output from the multiplier 19-2 is output from the subchannel processing unit 14-k as one element of the imaginary part subchannel signal vector k.

  In the subchannel processing unit 14-k shown in FIG. 3, the delay unit 15-1 provided in the preceding stage of the decimator 16-2 operates at twice the maximum thinning rate as described above. On the other hand, since the decimation rate is 2 in the decimators 16-1 and 16-2, the real part extraction units 17-1 and 17-2 and the imaginary part extraction unit 18 provided in the subsequent stage of the decimators 16-1 and 16-2. -1, 18-2, delay units 15-2 and 15-3, and multipliers 19-1 and 19-2 operate at the maximum thinning rate. However, the subchannel signal output from the decimator 16-1 is branched into two signals, and the two branched subchannel signals are processed at the same sampling rate (maximum thinning rate). . Therefore, the subchannel signal output from the decimator 16-1 is processed at twice the maximum thinning rate. The same applies to the subchannel signal output from the decimator 16-2. That is, the entire subchannel processing unit 14-k operates substantially at twice the maximum thinning rate.

In general, paying attention to the real part signal of the signal transmitted by multi-carrier modulation by the transmitter, the influence of the multipath of the channel (transmission path) is applied to the imaginary part component in addition to the real part component. It reaches. Therefore, in the multicarrier modulation signal receiving apparatus 1, the subchannel signal output from the decimator 16-1 is divided into two in the subchannel processing unit 14-k of the analysis bank 5-1, and the real part extracting unit 17-1 The real part component is extracted, and the imaginary part component is extracted by the imaginary part extraction unit 18-1. That is, the real part component and the imaginary part component that are affected by multipath or the like are extracted from the real part component signal. Furthermore, the subchannel signal output from the decimator 16-2 is divided into two, the real part component is extracted by the real part extraction unit 17-2, and the imaginary part component is extracted by the imaginary part extraction unit 18-2. . The real part subchannel signal vector k is constructed so that these four real signals are elements. Similarly, when attention is paid to the imaginary part signal of the signal transmitted by multicarrier modulation by the transmission apparatus, the influence of the multipath of the channel (transmission path) is applied to the real part component in addition to the imaginary part component. It also reaches. Therefore, in the multicarrier modulation signal receiving apparatus 1, the subchannel signal output from the decimator 16-2 is divided into two in the subchannel processing unit 14-k of the analysis bank 5-1, and the imaginary part extracting unit 18-2 The imaginary part component is extracted, and the real part component is extracted by the real part extracting unit 17-2. That is, the imaginary part component and the real part component that are affected by the multipath are extracted from the imaginary part component signal. Furthermore, the output of the imaginary part extracting unit 18-1 is delayed by one sample by the delay unit 15-2, and the output of the real part extracting unit 17-1 is delayed by one sample by the delay unit 15-3 and multiplied. An imaginary part subchannel signal is generated so that a subchannel signal whose sign is inverted by multiplying by -1 by the part 19-2 is generated and four real signals are combined with the real part component and the imaginary part component. A vector k was constructed. On the other hand, the modified DFT modulation analysis bank 102 shown in FIG. 13 extracts only the real part component affected by the multipath or the like from the real part component signal, and outputs the multi-part signal from the imaginary part signal. Only the imaginary part component affected by the path is extracted. In the multicarrier modulation signal receiving device 1 according to the embodiment of the present invention, the real part subchannel signal vector k and the imaginary part subchannel signal vector k that can cancel the interference components in the linear equalizer 6 are analyzed by the analysis bank 5. -1 sub-channel processing unit 14-k so that the orthogonality can be restored in a pseudo manner.

  In this way, the real subchannel signal output from the real part extraction unit 17-1, the real subchannel signal output from the imaginary part extraction unit 18-1, the real subchannel signal output from the imaginary part extraction unit 18-2, and The real number subchannel signal output from the real part extraction unit 17-2 is output from the subchannel processing unit 14-k as a real part subchannel signal vector k having each as an element. Further, the real subchannel signal output from the imaginary part extraction unit 18-2, the real subchannel signal output from the multiplier 19-1, the real subchannel signal output from the delay unit 15-2, and the multiplier 19-2 The output real subchannel signal is output from the subchannel processing unit 14-k as an imaginary part subchannel signal vector k having each element as an element.

とし、虚部抽出部１８−１により抽出される実数サブチャネル信号を

とし、虚部抽出部１８−２により抽出される実数サブチャネル信号を

とし、実部抽出部１７−２により抽出される実数サブチャネル信号を

とすると、実部サブチャネル信号ベクトルｋは、以下のようになる。

ここで、上付きのＴは転置を、下付きのｋはサブチャネルを、上付きのＲおよびＩはそれぞれ実部および虚部を、ｚ^Ｍは最大間引きレートであること、すなわちサンプル間隔がシンボル長の１／Ｍであることを示す。 The real subchannel signal extracted by the real part extraction unit 17-1 is

And the real subchannel signal extracted by the imaginary part extraction unit 18-1 is

And the real subchannel signal extracted by the imaginary part extracting unit 18-2

And the real subchannel signal extracted by the real part extraction unit 17-2 is

Then, the real part subchannel signal vector k is as follows.

Where the superscript T is the transpose, the subscript k is the subchannel, the superscripts R and I are the real and imaginary parts, respectively, and z ^M is the maximum decimation rate, ie the sample interval is a symbol Indicates 1 / M of the length.

On the other hand, the imaginary part subchannel signal vector k is as follows.

  As described above, according to the first configuration (analysis bank 5-1) of the analysis bank 5, the real part subchannel signal vector k is generated, and the imaginary part subchannel is generated based on the real part subchannel signal vector k. A channel signal vector k is generated. Also, as shown in Equation (2), the conversion from the real part subchannel signal vector k to the imaginary part subchannel signal vector k is performed by a conversion matrix that is a constant. As a result, the linear equalizer 6 at the subsequent stage uses a common equalization coefficient for both vectors without using different equalization coefficients for the real subchannel signal vector k and the imaginary subchannel signal vector k. Therefore, it is preferable that linear equalization can be performed.

[Analysis bank (polyphase composition)]
Next, the second configuration (polyphase configuration) of the analysis bank 5 shown in FIG. 1 will be described. FIG. 4 is a block diagram showing a second configuration of the analysis bank 5. The analysis bank 5-2 includes a delay unit 21, polyphase analysis banks 22-1 and 22-2, and subchannel processing units 23-0 to 23- (M-1). The analysis bank 5-2 receives the equivalent baseband signal from the quadrature demodulator 4 and generates and outputs real part subchannel signal vectors 0 to M-1 and imaginary part subchannel signal vectors 0 to M-1.

  The equivalent baseband signal input from the quadrature demodulator 4 shown in FIG. 1 is divided into two, one input to the delay unit 21 and the other input to the polyphase analysis bank 22-1. The delay unit 21 delays the equivalent baseband signal input from the quadrature demodulation unit 4 by M / 2 samples. The equivalent baseband signal output from the delay unit 21 is input to the polyphase analysis bank 22-2.

  The polyphase analysis bank 22-1 performs polyphase analysis on the equivalent baseband signal input from the quadrature demodulation unit 4, and generates subchannel signals 0 to M-1. The subchannel signals 0 to M-1 output from the polyphase analysis bank 22-1 are input to the subchannel processing units 23-0 to 23- (M-1).

  The polyphase analysis bank 22-2 performs polyphase analysis on the equivalent baseband signal input from the delay device 21, and generates subchannel signals 0 to M-1. The subchannel signals 0 to M-1 output from the polyphase analysis bank 22-2 are input to the subchannel processing units 23-0 to 23- (M-1).

  The subchannel processing units 23-0 to 23- (M-1) perform processing for each subchannel on the respective subchannel signals 0 to M-1 input from the polyphase analysis banks 22-1 and 22-2. Real part subchannel signal vectors 0 to M-1 and imaginary part subchannel signal vectors 0 to M-1, that is, real part subchannel signal vector k and imaginary part subchannel signal vector k (subchannel signal vector k). Generate and output.

[Polyphase analysis bank]
Next, the polyphase analysis banks 22-1 and 22-2 shown in FIG. 4 will be described. FIG. 5 is a block diagram showing the configuration of the polyphase analysis banks 22-1 and 22-2. The polyphase analysis bank 22 includes delay units 24-1 to 24- (M-1), decimators 25-0 to 25- (M-1), polyphase filters 26-0 to 26- (M-1), An FFT unit 27 and multiplication units 28-0 to 28- (M-1) are provided. The polyphase analysis bank 22 receives the equivalent baseband signal, generates and outputs subchannel signals 0 to M-1.

  The equivalent baseband signal input to the polyphase analysis bank 22 is divided into two, one input to the delay unit 24-1 and the other input to the decimator 25-0. The delay device 24-1 delays the input equivalent baseband signal by one sample. The equivalent baseband signal output from the delay unit 24-1 is divided into two, one input to the delay unit 24-2, and the other input to the decimator 25-1.

  Similarly, the delay unit 24-k (2 ≦ k <M−1) delays the equivalent baseband signal input from the preceding stage delay unit 24- (k−1) by one sample. The equivalent baseband signal output from the delay unit 24-k is divided into two, one input to the subsequent delay unit 24- (k + 1) and the other input to the decimator 25-k.

  The delay unit 24- (M-1) delays the equivalent baseband signal input from the delay unit 24- (M-2) by one sample. The equivalent baseband signal output from the delay unit 24- (M-1) is input to the decimator 25- (M-1).

  A decimator 25-k (0 ≦ k ≦ M−1) receives an equivalent baseband signal and performs a decimation process with a ratio M on the equivalent baseband signal. The decimated equivalent baseband signal output from the decimator 25-k is input to the polyphase filter 26-k.

  The polyphase filter 26-k (0 ≦ k ≦ M−1) performs polyphase filter processing on the equivalent baseband signal after decimation input from the decimator 25-k. The equivalent baseband signal after the polyphase filter processing output from the polyphase filter 26-k is input to the FFT unit 27.

ここで、Ｎはプロトタイプフィルタのフィルタ長を、Ｍはサブチャネル数を示す自然数を、ｋは任意のサブチャネルをそれぞれ示す。 The polyphase filter E _k (z) is a polyphase component of Type 1 of the prototype filter p (n), and is represented by the following expression.

Here, N is the filter length of the prototype filter, M is a natural number indicating the number of subchannels, and k is an arbitrary subchannel.

  The FFT unit 27 performs FFT processing on each equivalent baseband signal after the polyphase filter processing input from the polyphase filter 26-k. The M subchannel signals output from the FFT unit 27 are respectively input to the multiplication unit 28-k.

Multiplier 28-k (0 ≦ k ≦ M−1) multiplies the subchannel signal input from FFT unit 27 by j ^M−k . However, j is an imaginary unit. The subchannel signal k output from the multiplier 28-k is input to the subchannel processor 23-k shown in FIG.

  As described above, the polyphase analysis bank 22 receives the equivalent baseband signal, generates the subchannel signals 0 to M-1, and outputs the subchannel signals 0 to M-1 to the subchannel processing units 23-0 to 23- (M-1). Hereinafter, the subchannel signal output from the polyphase analysis bank 22-1 is k1, and the subchannel signal output from the polyphase analysis bank 22-2 is k2.

[Subchannel processing section of analysis bank (polyphase configuration)]
Next, the subchannel processing units 23-0 to 23- (M-1) illustrated in FIG. 4 will be described. FIG. 6 is a block diagram illustrating a configuration of the subchannel processing unit 23-k (0 ≦ k ≦ M−1). The subchannel processing unit 23-k includes real part extraction units 29-1 and 29-2, imaginary part extraction units 30-1 and 30-2, delay units 31-1 and 31-2, and a multiplier 32-1. 32-2 is provided. The subchannel processing unit 23-k receives the subchannel signal k1 from the polyphase analysis bank 22-1 shown in FIGS. 4 and 5, and also receives the subchannel signal k2 from the polyphase analysis bank 22-2. A real part subchannel signal vector k and an imaginary part subchannel signal vector k are generated and output.

  When the subchannel processing unit 23-k and the subchannel processing unit 14-k shown in FIG. 3 are compared, the subchannel processing unit 14-k shown in FIG. And the decimators 16-1 and 16-2, the subchannel processing unit 23-k receives the subchannel signals k1 and k2, and the delay unit corresponding to the delay unit 15 and the decimator 16-1, The difference is that a decimator corresponding to 16-2 is not provided.

  Real part extraction units 29-1 and 29-2, imaginary part extraction units 30-1 and 30-2, delay units 31-1 and 31-2, and multipliers 32-1 and 32- 2 are real part extraction units 17-1 and 17-2, imaginary part extraction units 18-1 and 18-2, and delay units 15-2 and 15-3 of the subchannel processing unit 14-k illustrated in FIG. And correspond to the multipliers 19-1 and 19-2. Since these configurations have already been described with reference to FIG. 3, the description thereof is omitted here.

  4, 5, and 6, the delay units 21, 24-1, 24-2 provided in the preceding stage of the decimators 25-0 to 25-(M−1) are M times the maximum thinning rate. Operate. In addition, polyphase filters 26-0 to 26- (M-1), an FFT unit 27, and multipliers 28-0 to 28- (M-) provided at the subsequent stage of the decimators 25-0 to 25- (M-1). 1) Real part extraction units 29-1, 29-2, imaginary part extraction units 30-1, 30-2, delay units 31-1, 31-2 and multipliers 32-1, 32-2 Work at rate. However, since the subchannel signals k1 and k2 having the maximum decimation rate are input from the polyphase analysis banks 22-1 and 22-2, and the subchannel signal vector k is output without performing decimation, the subchannel processing unit The overall 23-k operates substantially at twice the maximum decimation rate.

  As described above, according to the second configuration of the analysis bank 5 (analysis bank 5-2), the real part subchannel signal vector k is generated and the real part subchannel is generated as in the case of the analysis bank 5-1. The imaginary part subchannel signal vector k is generated based on the signal vector k. Also, as shown in Equation (2), the conversion from the real part subchannel signal vector k to the imaginary part subchannel signal vector k is performed by a conversion matrix that is a constant. As a result, the linear equalizer 6 at the subsequent stage uses a common equalization coefficient for both vectors without using different equalization coefficients for the real subchannel signal vector k and the imaginary subchannel signal vector k. Therefore, it is preferable that linear equalization can be performed.

[Linear equalizer]
Next, the linear equalizer 6 shown in FIG. 1 will be described. FIG. 7 is a block diagram showing the configuration of the linear equalizer 6. The linear equalizer 6 includes equalizers 41-1 and 41-2, a multiplier 42 and an adder 43. The linear equalizer 6 receives the real part subchannel signal vector k and the imaginary part subchannel signal vector k from the analysis bank 5 shown in FIG. 1, and the real part subchannel signal vector k and the imaginary part for each subchannel. The subchannel signal vector k is equalized using equalization coefficients by the equalizers 41-1 and 41-2, respectively, and a complex carrier symbol is output.

  The real part subchannel signal vector k output from the analysis bank 5 shown in FIG. 1 is input to the equalizer 41-1, and the imaginary part subchannel signal vector k is input to the equalizer 41-2. Although not shown, the equalization coefficient output from the equalization coefficient calculator 7 shown in FIG. 1 is input to the equalizers 41-1 and 41-2. The equalizer 41-1 equalizes the real part subchannel signal vector k input from the analysis bank 5 with the equalization coefficient input from the equalization coefficient calculation unit 7, and the equalizer 41-2 analyzes The imaginary part subchannel signal vector k input from the bank 5 is equalized with the equalization coefficient input from the equalization coefficient calculation unit 7. The equalized real subchannel signal k (carrier symbol) output from the equalizer 41-1 is input to the adder 43 and the equalized imaginary subchannel signal k output from the equalizer 41-2. (Carrier symbol) is input to the multiplier 42.

  The multiplier 42 multiplies the carrier symbol input from the equalizer 41-2 by 1j. The carrier symbol output by the multiplier 42 and multiplied by 1j is input to the adder 43.

  The adder 43 adds the carrier symbol input from the equalizer 41-1 and the carrier symbol input from the multiplier 42, and generates a complex carrier symbol. The complex carrier symbol output from the adder 43 is input to the equalization coefficient calculator 7 and the demapping unit 8 shown in FIG.

[Equalizer]
Next, the equalizers 41-1 and 41-2 shown in FIG. 7 will be described. FIG. 8 is a block diagram showing the configuration of the equalizers 41-1 and 41-2. The equalizer 41 includes adaptive filters 44-1 to 44-4 and an adder 45. The equalizer 41 equalizes the real part subchannel signal vector k or the imaginary part subchannel signal vector k output from the analysis bank 5 with the equalization coefficient output from the equalization coefficient calculator 7 for each subchannel, Partial subchannel signal k (carrier symbol) or imaginary subchannel signal k (carrier symbol) is output.

の要素、または虚部サブチャネル信号ベクトルｋである

の要素を、図１に示した等化係数算出部７から入力される等化係数によりフィルタ処理する。適応フィルタ４４−１〜４４−４の出力するフィルタ処理後の実部サブチャネル信号ベクトルｋの要素または虚部サブチャネル信号ベクトルｋの要素は加算部４５へ入力される。 The adaptive filters 44-1 to 44-4 are real part subchannel signal vectors k input from the analysis bank 5.

Element or imaginary part subchannel signal vector k

These elements are filtered by the equalization coefficient input from the equalization coefficient calculation unit 7 shown in FIG. The elements of the real part subchannel signal vector k or the elements of the imaginary part subchannel signal vector k after the filtering process output from the adaptive filters 44-1 to 44-4 are input to the adding unit 45.

  The adder 45 adds the elements of the real part subchannel signal vector k or the elements of the imaginary part subchannel signal vector k after the filtering process input from the adaptive filters 44-1 to 44-4. The equalized real subchannel signal (carrier symbol) output from the adder 45 is input to the adder 43 shown in FIG. Further, the equalized imaginary part subchannel signal (carrier symbol) output from the adder 45 is input to the multiplier 42 shown in FIG.

[Equalization coefficient calculator]
Next, the equalization coefficient calculation unit 7 shown in FIG. 1 will be described. FIG. 9 is a block diagram showing a configuration of the equalization coefficient calculation unit 7. The equalization coefficient calculation unit 7 includes a pilot signal extraction unit 51, a pilot signal generation unit 52, a subtraction unit 53, and an equalization coefficient optimization unit 54. The equalization coefficient calculator 7 receives the real part subchannel signal vector k or the imaginary part subchannel signal vector k from the analysis bank 5, and receives the equalized subchannel signal (complex carrier symbol) from the linear equalizer 6. An equalization coefficient is generated and output based on the least square error criterion with the pilot signal as a reference signal. That is, the equalization coefficient calculation unit 7 outputs the real part equalization coefficient generated from the real part subchannel signal vector k to the equalizer 41-1 of the linear equalizer 6, and outputs the imaginary part subchannel signal. The equalization coefficient for the imaginary part generated from k is output to the equalizer 41-2 of the linear equalizer 6.

  The pilot signal extraction unit 51 extracts a pilot signal included in a received signal that is a subchannel signal after equalization input from the linear equalizer 6. The pilot signal output from the pilot signal extraction unit 51 is input to the subtraction unit 53.

  The pilot signal generation unit 52 generates a known pilot signal whose amplitude and phase are determined in advance. The known pilot signal output from the pilot signal generation unit 52 is input to the subtraction unit 53.

  The subtraction unit 53 subtracts the pilot signal input from the pilot signal extraction unit 51 from the known pilot signal input from the pilot signal generation unit 52 to generate an error. The error output from the subtraction unit 53 is input to the equalization coefficient optimization unit 54.

  The equalization coefficient optimizing unit 54 uses the real part subchannel signal vector or the imaginary part subchannel signal vector input from the analysis bank 5 and the error input from the subtractor 53 so that the error is minimized. Then, the equalization coefficient is calculated and updated based on the least square error criterion. As the equalization coefficient update algorithm, LMS, RLS, or the like can be used. Since these algorithms are publicly known, description thereof is omitted here. Note that the equalization coefficient optimization unit 54 performs processing using the real part component of the error input from the subtraction part 53 when optimizing the real part equalization coefficient from the real part subchannel signal vector. . Further, when the equalization coefficient for the imaginary part is optimized from the imaginary part subchannel signal vector, the process is performed using the imaginary part component among the errors input from the subtraction part 53.

  Here, as described above, the real part subchannel signal vector k and the imaginary part subchannel signal vector k generated by the analysis bank 5 have a relationship that can be transformed using a constant transformation matrix according to Equation (2). Thus, the equalizers 41-1 and 41-2 shown in FIGS. 7 and 8 can perform linear equalization using a common equalization coefficient. Therefore, the equalization coefficient calculation unit 7 outputs the real part equalization coefficient generated from the real part subchannel signal vector k to the equalizer 41-1 of the linear equalizer 6, and outputs the imaginary part subchannel signal. Instead of outputting the equalization coefficient for the imaginary part generated from the vector k to the equalizer 41-2 of the linear equalizer 6, the equalization coefficient for the real part is equalized by the equalizers 41-1, 41. -2 may be output. Alternatively, the equalization coefficient for the imaginary part may be output to the equalizers 41-1 and 41-2. In this case, the common equalization coefficient for the real part and the imaginary part can be updated using any one of the real part component and the imaginary part component of one pilot signal. That is, the common equalization coefficients for the real part and the imaginary part can be updated twice by using two components of the real part component and the imaginary part component of one pilot signal.

〔simulation result〕
Next, the results obtained by computer simulation will be described. FIG. 14 shows the MER (Modulation Error Ratio) after equalization with respect to the multipath delay time in the one-wave multipath environment obtained by computer simulation for the multicarrier modulation signal receiver 1 shown in FIG. FIG. (1) shows the characteristics of the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention, and (2) shows the characteristics of the conventional OFDM receiving apparatus. The multipath D / U is 3 dB, the C / N is 40 dB, the vertical axis is MER (dB), and the horizontal axis is the multipath delay time normalized by the symbol length. Further, the conventional OFDM receiving apparatus has a GI ratio of 1/8, and the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention has an overlap coefficient of 4.

  According to (2) which shows the characteristics of the conventional OFDM receiver, when the multipath delay time is within the GI length (when normalized delay time ≦ 0.125), the reception characteristics are good. When the delay time exceeds the GI length (when normalized delay time> 0.125), it can be seen that the MER after equalization is greatly deteriorated. On the other hand, according to (1) showing the characteristics of the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention, multipath equalization is performed even when the multipath delay time is long. It can be seen that the reception characteristics are excellent.

  Further, in the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention, no GI is inserted, and in the conventional OFDM receiving apparatus, the GI ratio is 1/8. Thereby, when the transmission efficiency per unit time is set to 1 in the multicarrier modulation signal receiving apparatus 1, the transmission efficiency per unit time is 8/9 in the conventional OFDM receiving apparatus due to the GI. Therefore, the transmission capacity can be expanded by using the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention.

  As described above, according to the multicarrier modulation signal receiving apparatus 1 according to the embodiment of the present invention, the analysis carrier 5 that is a modified DFT modulation analysis bank that operates the received signal substantially at twice the maximum thinning rate is provided. In addition to the original output signal, this analysis bank 5 is a subchannel signal vector that combines output signals whose real and imaginary components are opposite (paired) from the output signal, that is, the real part sub Two types of signals, that is, a channel signal vector (a signal composed of four components) and an imaginary part subchannel signal vector (a signal composed of four components) are output. That is, two real part components and two imaginary part components are extracted from the subchannel signal, a real subchannel signal vector composed of these four components is output, and two real parts in the real part subchannel signal vector are output. Two imaginary part components are generated from the components, two real part components are generated from the two imaginary part components in the real subchannel signal vector, and an imaginary part subchannel signal vector composed of these four components is output. I made it. The linear equalizer 6 linearly equalizes the two types of signals processed by the analysis bank 5 at twice the maximum thinning rate. As a result, multipath tolerance can be obtained without transmitting redundant information such as GI.

It is a block diagram which shows the structure of the multicarrier modulation signal receiver by embodiment of this invention. It is a block diagram which shows the 1st structure of an analysis bank. FIG. 3 is a block diagram illustrating a configuration of a subchannel processing unit in FIG. 2. It is a block diagram which shows the 2nd structure of an analysis bank. It is a block diagram which shows the structure of the polyphase analysis bank of FIG. FIG. 5 is a block diagram illustrating a configuration of a subchannel processing unit in FIG. 4. It is a block diagram which shows the structure of a linear equalizer. It is a block diagram which shows the structure of the equalizer of FIG. It is a block diagram which shows the structure of an equalization coefficient calculation part. It is a block diagram which shows the structure of a general transmultiplexer. It is a block diagram which shows a structure when OFDM is expressed as a transmultiplexer. It is a block diagram which shows the structure of a correction DFT modulation synthesis bank. It is a block diagram which shows the structure of a correction DFT modulation analysis bank. It is a figure which shows MER after equalization with respect to multipath delay time calculated | required by computer simulation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multicarrier modulation signal receiver 2 Frequency conversion part 3 A / D conversion part 4 Orthogonal demodulation part 5 Analysis bank 6 Linear equalizer 7 Equalization coefficient calculation part 8 Demapping part 9 Parallel serial conversion part 11 Delayer 12 Analysis filter 13 Decimator 14 Subchannel processing unit 15 Delay unit 16 Decimator 17 Real part extraction unit 18 Imaginary part extraction unit 19 Multiplier 21 Delay unit 22 Polyphase analysis bank 23 Subchannel processing unit 24 Delay unit 25 Decimator 26 Polyphase filter 27 FFT unit 28 multiplier 29 real part extractor 30 imaginary part extractor 31 delay 32 multiplier 41 equalizer 42 multiplier 43 adder 44 adaptive filter 45 adder 51 pilot signal extractor 52 pilot signal generator 53 subtractor 54 etc. Coefficient optimization unit 100 Transmultiplexer 101 Modified DFT modulation synthesis Link 102 Modify DFT modulation analysis bank

Claims (9)

A multi-carrier modulation signal receiving apparatus for receiving a multi-carrier modulated signal by a modified DFT modulation synthesis bank performing two-stage interpolation,
Includes a modified DFT modulation analysis bank that performs two-stage decimation and operates at twice the maximum decimation rate,
The modified DFT modulation analysis bank receives the multi-carrier modulated signal and orthogonally demodulated equivalent baseband signal, and delays the equivalent baseband signal to filter and decimate the subchannel signal. A filter and a decimator to be generated, and a real part component and an imaginary part component are extracted from the subchannel signal to output a real part subchannel signal vector, and an imaginary part paired with the extracted real part component and imaginary part component multi-carrier modulation signal receiving apparatus characterized by comprising: a sub-channel processing unit, a which generates a component and real component outputs the imaginary part subchannel signal vector. The modified DFT modulation analysis bank is
A delay unit for delaying the orthogonal demodulated equivalent baseband signal;
An analysis filter that performs filtering on the equivalent baseband signal and the equivalent baseband signal delayed by the delay unit;
A decimator for decimating the subchannel signal filtered by the analysis filter;
Based on the subchannel signal decimated by the decimator, the real part component and the imaginary part component are extracted to output a real part subchannel signal vector, and the imaginary part subchannel signal is output based on the real part subchannel signal vector. The multicarrier modulation signal receiving apparatus according to claim 1, further comprising: a subchannel processing unit that generates and outputs a vector. An analysis bank equivalent to the modified DFT modulation analysis bank, wherein the analysis bank is
A first polyphase analysis bank for polyphase analyzing the quadrature demodulated equivalent baseband signal to generate a subchannel signal;
A delay unit for delaying the orthogonal demodulated equivalent baseband signal;
A second polyphase analysis bank for polyphase analysis of the equivalent baseband signal delayed by the delay unit to generate a subchannel signal;
Based on the subchannel signal generated by the first polyphase analysis bank, the real part signal and the imaginary part signal are extracted, and based on the subchannel signal generated by the second polyphase analysis bank. The real part component and the imaginary part component are extracted, and a real part subchannel signal vector is generated and output from each of the extracted real part component and imaginary part component, and based on the real part subchannel signal vector. The multicarrier modulation signal receiving apparatus according to claim 1, further comprising: a subchannel processing unit that generates and outputs an imaginary part subchannel signal vector.   The subchannel processing unit generates and outputs a real part subchannel signal vector from two real part components and two imaginary part components, and multiplies the real part subchannel signal vector by a predetermined transformation matrix to obtain an imaginary part. The multicarrier modulation signal receiving apparatus according to any one of claims 1 to 3, wherein a partial subchannel signal vector is generated and output.   The modified DFT modulation analysis bank includes a linear equalizer that linearly equalizes the real part subchannel signal vector and the imaginary part subchannel signal vector output by the subchannel processing unit using equalization coefficients. The multicarrier modulation signal receiving apparatus according to any one of claims 1 to 4, wherein the multicarrier modulation signal receiving apparatus is provided. The linear equalizer linearly equalizes the real part subchannel signal vector output by the subchannel processing unit, and the second equalization linearly equalizes the imaginary part subchannel signal vector. And equipped with
Outputting a complex carrier symbol based on the real part subchannel signal linearly equalized by the first equalizer and the imaginary part subchannel signal linearly equalized by the second equalizer. The multicarrier modulation signal receiving apparatus according to claim 5, wherein:   An equalization coefficient calculation unit for calculating an equalization coefficient for performing linear equalization by the linear equalizer based on a least square error standard using a pilot signal included in the multicarrier modulated signal as a reference signal, The multicarrier modulation signal receiving apparatus according to claim 5 or 6, further comprising:   8. The multi-equation according to claim 7, wherein the equalization coefficient calculation unit calculates a common equalization coefficient for linearly equalizing the real part subchannel signal vector and the imaginary part subchannel signal vector. Carrier modulation signal receiver.   8. The multi-factor according to claim 7, wherein the equalization coefficient calculation unit updates the equalization coefficient twice with one pilot signal by using each of the real part component and the imaginary part component of the pilot signal as a reference signal. Carrier modulation signal receiver.

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