JP5194359B2 - Reverse breakdown voltage field stop type semiconductor device for igniter - Google Patents

Description

  The present invention relates to a semiconductor device used in a circuit including an inductive load (L load), and more particularly to a semiconductor device used in an internal combustion engine ignition device (igniter).

  As shown in FIG. 4, in a circuit including inductive loads 101 and 102, as a product having a function of generating an intermittent spark by a high voltage generated in the secondary coil 102 corresponding to the intermittent current flowing in the primary coil 101, There is an internal combustion engine ignition device 100 that uses an intermittent spark generated in an internal combustion engine ignition plug 103 connected to the secondary coil 102. In this internal combustion engine ignition device 100, a bipolar transistor has been conventionally used as the switching means 104 used in a circuit for causing an intermittent current to flow through the primary coil. However, in recent years, an IGBT (insulated gate bipolar transistor) has been used. (See Patent Documents 1 and 2).

  The electrical characteristics required for the IGBT employed as the switching means 104 used in the above-described internal combustion engine ignition device 100 are focused on low on-voltage characteristics and low switching loss characteristics. Conventionally, as shown in the cross-sectional view of FIG. 5, an IGBT as a switching means for an ignition device (igniter) for an internal combustion engine has been used as a punch-through IGBT that is easy to manufacture. Field stop (buffer layer) IGBTs have been studied (see Patent Document 3). The field stop (hereinafter sometimes abbreviated as FS) type IGBT here is a kind of punch-through type IGBT. Usually, the punch-through type IGBT has an epitaxial layer and is expensive. The IGBT is an inexpensive device that can reduce the on-voltage because it uses an inexpensive FZ-n substrate and can reduce the thickness of the high-resistance drift layer.

  On the other hand, in the inductive load circuit for the igniter, in the process in which the current suddenly decreases when the IGBT moves from the on state to the off state, the primary coil corresponds to the coil inductance L and the current change flowing through the coil. The voltage in the direction to suppress the change (IGBT collector side in the positive direction) rises rapidly, and when the switch is turned off, the voltage drops sharply. When this surge voltage (several hundreds V) that occurs abruptly is clamped by the Zener voltage of the Zener diode disposed between the collector and gate of the IGBT, the voltage on the primary coil side is induced in the secondary coil, A reverse voltage is generated in the secondary coil. In the above-described process, the positive surge voltage on the primary side may reach a negative voltage (several tens to 100 V) when it is lowered. When the primary side voltage becomes a reverse voltage, a reverse bias is applied to the collector of the IGBT, and thus the IGBT may be destroyed.

  Generally, the IGBT structure (forward breakdown voltage IGBT structure) includes a punch-through type (PT type) shown in FIG. 6, a non-punch-through type (NPT type) shown in FIG. 7, and a field stop type (FS type) shown in FIG. ) Etc. Here, the case of an n-channel IGBT will be described.

The punch-through IGBT (hereinafter referred to as PT-IGBT) in FIG. 6 includes an n ⁺ buffer layer 112 and an n ⁻ drift layer 113 formed by epitaxial growth on a thick p ⁺ substrate 111 to be a p ⁺ collector layer. The epitaxial silicon substrate 110 is used, and a depletion layer that extends when a reverse bias is applied to the junction between the IGBT p base layer 114 and the n ⁻ drift layer 113 (the forward breakdown voltage of the IGBT) reaches the n ⁺ buffer layer 112. Provide structure. For example, for the withstand voltage 600V system, the thickness of the n ⁻ drift layer 113 is sufficient to be about 70 μm, but when including the p ⁺ substrate 111, the total thickness of the silicon substrate 110 becomes 350 μm to 600 μm. The specific resistance of p ⁺ substrate 111 is a low resistance of 10 mΩcm or less. The specific resistances of the n ⁺ buffer layer 112 and the n ⁻ drift layer 113 are 0.1 Ωcm and 40 Ωcm, respectively. In the PT-IGBT, when a positive high voltage is applied to the collector electrode 109 on the back surface of the substrate in the blocking state, a depletion layer enters the n ⁻ drift layer 113 from the junction between the p base layer 114 and the n ⁻ drift layer 113. spread. When the breakdown voltage is reached, the depletion layer stretches almost at the n ⁺ buffer layer 112. Since this PT-IGBT uses an epitaxial silicon substrate as described above, the chip cost must be relatively high.

Therefore, instead of using the above-described expensive epitaxial silicon substrate, an inexpensive FZ substrate as shown in FIG. 7 is used to reduce the cost of the chip, so that the n ⁻ drift layer 115 thicker than the n ⁻ drift layer 113 is formed on the n ⁻ drift layer 115. A non-punch-through IGBT 116 employing a shallow p ⁺ collector layer 121 with a low dose and a field stop IGBT 117 as shown in FIG. 8 have been developed. The basic structure of the field stop IGBT 117 in FIG. 8 is the same as that of the PT-IGBT, but the total thickness of the substrate is changed according to the withstand voltage using an FZ substrate without using an epitaxial substrate, but it is 100 μm to 200 μm. It is thin to the extent. Like n and the PT-IGBT ^- thickness of the drift layer 118 is Yes in the order of 70μm in breakdown voltage of 600V, n ^- the total area of the drift layer 118 is depleted, to suppress the extension of the depletion layer, n ^- drift layer Under 118, an FS layer (n ⁺ buffer layer) 119 is provided. On the collector side, a shallow p ⁺ collector layer 120 with a low dose is used as the low implantation collector. Thereby, lifetime control becomes unnecessary similarly to NPT-IGBT116.

On the other hand, FIG. 3 is a cross-sectional view of the main part of the reverse blocking IGBT having the separation diffusion layer 130. The basic structure is formed so that the p ⁺ isolation diffusion layer 130 for maintaining the reverse breakdown voltage is connected to the p ⁺ collector layer 131 at the same potential around the chip of the NPT-IGBT in FIG. This reverse blocking IGBT eliminates the need for a series diode for reverse blocking, which had to be connected separately in the conventional forward voltage IGBT, so that the on-loss for the diode can be reduced. It has characteristics that greatly contribute to improvement. The reverse blocking IGBT can be manufactured by combining a technique for forming a separation region having a deep junction of 100 μm or more from the surface of the semiconductor substrate and an ultra-thin wafer manufacturing technique having a thickness of 100 μm or less.

  By the way, as described above, the field stop type (FS type) IGBT as shown in FIG. 5 which is often used as the switching means for the igniter has several collectors in the direction in which the collector is negative with respect to the emitter. A reverse bias of about 10 to 100 V may be applied, in which case the IGBT may be destroyed. This is because the above-mentioned FS-IGBT can maintain the blocking state with high reliability against the forward bias in the direction in which the collector is positive and the emitter is negative, but the emitter is positive and the collector is positive. This is because the voltage can hardly be maintained in a blocking state against a reverse bias having a negative potential.

  On the other hand, as shown in FIG. 3 (FIG. 1 of Patent Document 4), it is designed to properly protect the termination treatment of the collector junction of the IGBT, and an appropriate manufacturing process is applied, so that both forward and reverse bias are highly reliable. A reverse breakdown voltage IGBT (also referred to as a bidirectional IGBT) that can ensure a sufficient breakdown voltage is also known as a device (see Patent Document 4).

Therefore, in consideration of the fact that the IGBT used as the switching element of the inductive load circuit for the igniter is not connected with an anti-parallel FWD (free wheel diode) in the circuit configuration, the IGBT itself prepares for the reverse bias surge voltage. Further, if a blocking function corresponding to the reverse bias surge is secured, it is considered that the above-described reverse bias surge applied to the IGBT is protected, and the inductive load circuit for the igniter can be made highly reliable.
JP 2000-310173 A JP 2002-4991 A JP 2001-153011 A JP 2005-101551 A

However, since the reverse breakdown voltage IGBT (FIG. 3) which is not a field stop type as described in Patent Document 4 can ensure a forward and reverse breakdown voltage with high reliability, it has already been developed. IGBTs are not yet known. This is because, in a field stop type reverse blocking IGBT, since there is a field stop layer adjacent to the p ⁺ collector layer, the expansion of the depletion layer during reverse bias is inevitably suppressed, so the electric field strength is high. This is because the reverse breakdown voltage tends to decrease.

  The present invention has been made in view of the above-described points, and has a low on-voltage characteristic, a low switching loss characteristic, a reverse breakdown voltage characteristic necessary for an igniter circuit, and a high surge voltage withstand capability. An object is to provide an apparatus.

According to the first aspect of the present invention, the one-conductivity-type semiconductor substrate, the other-conductivity-type isolation diffusion region that connects one main surface of the semiconductor substrate to the other main surface, and the isolation The one main surface surrounded by the diffusion region is provided with a MOS gate structure and a breakdown voltage structure portion surrounding the MOS gate structure, and is exposed on the entire surface of the other main surface surrounded by the isolation diffusion region. A reverse breakdown voltage field stop type semiconductor device for an igniter comprising: another conductivity type collector region in contact with an isolation diffusion region; and a one conductivity type field stop layer in contact with the collector region on the semiconductor substrate side, wherein the one conductivity type field stop layer P is formed by the other conductivity type collector region and the one conductivity type field stop layer. An igniter reverse withstand voltage field stop type semiconductor device having a reverse withstand voltage value of the junction having at least 1/10 to 1/3 of the forward withstand voltage value of the igniter reverse withstand voltage field stop type semiconductor device, The object of the invention is achieved.

According to a second aspect of the present invention, the reverse breakdown voltage field for an igniter according to claim 1, further comprising a diode connected between the collector region and the gate region constituting the MOS gate structure. A stop-type semiconductor device can be obtained.

3. The reverse breakdown field stop for an igniter according to claim 2, wherein the diode is a diode deposited in layers on the breakdown voltage structure portion with an insulating film interposed therebetween. It is even more preferable to use a type semiconductor device.

According to a fourth aspect of the present invention, it is preferable that the reverse breakdown voltage field stop type semiconductor device for an igniter according to the second or third aspect is characterized in that the diode is a bidirectional diode. .

According to the invention of claim 5, the igniter according to any one of claims 1 to 4, wherein the semiconductor device for igniter comprises an IC circuit for controlling the semiconductor device on the same semiconductor substrate. It is preferable to use a reverse breakdown voltage field stop type semiconductor device.

  According to the present invention, it is possible to provide an igniter semiconductor device having low on-voltage characteristics, low switching loss characteristics, at least reverse withstand voltage characteristics required for an igniter circuit, and high surge voltage withstand capability.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the examples described below unless it exceeds the gist. FIG. 1 is a cross-sectional view of an igniter reverse breakdown voltage FS-IGBT according to the present invention. FIG. 2 is a plan view of the igniter semiconductor device in which the igniter reverse breakdown voltage FS-IGBT and its control circuit IC are integrated according to the present invention. FIG. 9 is a sectional view of an igniter reverse breakdown voltage FS-IGBT in which a clamp diode according to the present invention is formed.

  First, a conventional IGBT will be described for comparison. As described above, generally known IGBTs include punch-through (hereinafter referred to as PT) type, non-punch-through (hereinafter referred to as NPT) type, and field stop (hereinafter referred to as FS) type 3. There are types.

As shown in FIG. 7, in the conventional NPT-IGBT, the n ⁻ drift layer 115 is made thicker than the n ⁻ drift layer 113 of the PT-IGBT without providing the n ⁺ buffer layer. ^{+ The} depletion layer does not reach the collector layer 121. In the NPT-IGBT, after forming the MOS gate structure 122 on the surface of the FZ wafer to be the n ⁻ drift layer 115, the back surface of the wafer is ground to a thickness of 100 μm, and then boron ion implantation and activity from the back surface of the wafer are performed. The p ⁺ collector layer 121 is formed by performing a chemical heat treatment. The specific resistance of the FZ wafer is about 28 Ωcm when the withstand voltage is 600V. The dose of boron for forming the back surface p ⁺ collector layer is 10 ¹⁵ cm ⁻² . Moreover, the activation process temperature is 350 degreeC. In NPT-IGBT, the hole injection efficiency is about 0.3. There is no lifetime control. The transport efficiency in the n ⁻ drift layer 115 is about 1. By doing so, the carrier distribution is optimized even with the same base ground current gain as the PT-IGBT, and the loss characteristic is improved as compared with the PT-IGBT.

The conventional FS-IGBT shown in FIG. 8 is formed by forming an n-type field stop layer (hereinafter referred to as FS layer) 119 similar to the n ⁺ buffer layer 112 of PT-IGBT on the back surface of the NPT-IGBT. The n ⁻ drift layer 118 can be made thinner than the NPT-IGBT. With such a configuration, the loss characteristics of the FS-IGBT are improved compared to the NPT-IGBT. In the FS-IGBT, the hole injection efficiency and the transport efficiency in the n ⁻ drift layer 118 are approximately the same as those of the NPT-IGBT, or the hole injection efficiency is slightly lower than that of the NPT-IGBT.

Next, a method for manufacturing the reverse breakdown voltage FS-IGBT according to the present invention shown in FIG. 1 will be described. An isolation diffusion layer 2 is formed to a depth of 120 μm by thermal diffusion from the front side of the FZ-n type, specific resistance 28 Ωcm, thickness 500 μm semiconductor substrate 1. A surface MOS gate structure 3 similar to the surface structure 122 of FIG. 7 is formed on the surface surrounded by the annular pattern of the isolation diffusion layer 2 formed on the surface of the semiconductor substrate 1. 7 shows only the central portion of the surface MOS gate structure, but FIG. 1 shows a cross section of the main portion including the surface MOS gate structure, the breakdown voltage structure portion 4 on the outside thereof, and the isolation diffusion layer 2 on the outside thereof. Indicates. The surface MOS gate structure 3 according to the present invention may be the same as the surface MOS gate structure 122 of FIG. The p base layer 5, the n ⁺ emitter layer 6, the gate oxide film 7, the polycrystalline silicon gate electrode 8, the emitter electrode 9 and the like are formed by a known method. The rear surface of the semiconductor substrate 1 is thinned to a thickness of about 100 μm. Thereafter, after the processing strain layer is removed, in order to form the FS layer (n ⁺ layer) 10 and the p ⁺ collector layer 11, ion implantation is performed from the back surface. For example, ions such as phosphorus, selenium, and sulfur are used for forming the FS layer 10. Boron ions are implanted for forming the p ⁺ collector layer 11.

As with NPT-IGBT, the FS layer 10 is made thin by grinding the back surface of the wafer, and then ion-implanted with donor forming impurity ions selected from phosphorus, selenium, sulfur, etc. together with boron from the back surface of the wafer, and activated at a low temperature. By performing the heat treatment, the n-type FS layer 10 is formed at a position deeper than the p collector region 11 from the back surface side. By selecting selenium and sulfur as impurity ions, the FS layer 10 can be made deeper. The reverse breakdown voltage of the reverse breakdown voltage FS-IGBT according to the present invention is adjusted by the impurity concentration and depth of the FS layer 10. According to this reverse withstand voltage adjustment method, the reverse withstand voltage can be reduced to about 200 V even with the FS-IGBT. The thickness of the FS layer 10 is 10 to 100 times the thickness of the p ⁺ collector region 11. The reverse breakdown voltage value of the pn junction between the FS layer 10 and the p ⁺ collector region 11 is set to be 10% or more of the forward breakdown voltage of the reverse breakdown voltage FS-IGBT.

  The p collector region 11 and the FS layer 10 on the back surface are formed by performing an activation process after ion implantation. However, since the process is performed after the aluminum electrode is formed on the MOS gate structure 3, It is necessary to perform the treatment at 500 ° C. or lower so as not to adversely affect the treatment. As such activation treatment, laser annealing treatment is preferable. According to the laser irradiation, only the layer irradiated with the laser can be heated to a high temperature without setting the temperature of the surface aluminum electrode to 500 ° C. or higher. A feature of laser annealing is that only the surface layer of the surface irradiated with laser is annealed at a high temperature of about 1000 ° C., and the temperature of the surface not irradiated with laser can be kept at room temperature. Here, the laser is a YAG third harmonic (YAG3ω) pulse laser (wavelength = 355 nm, full width at half maximum = 100 ns to 500 ns, frequency = 500 Hz, with a single irradiation area of about 1 mm square and 50% to 90% overlap. A deep FS layer of about 10 μm to several tens of μm is formed. In order to obtain a deep FS layer of several tens of μm, it is preferable to use impurity ions having a diffusion coefficient larger than that of phosphorus such as selenium and sulfur.

Moreover, according to the laser annealing of YAG3ω, only the p ⁺ collector layer 11 and the FS layer 10 formed on the surface layer of the wafer can be activated. Also, from YAG second harmonic (YAG2ω) pulse laser (wavelength = 532 nm, half-width = 100 ns to 500 ns, frequency = 1 kHz, one irradiation area is about 1 mm square and irradiated with 50% to 90% overlap) Laser annealing may be performed.

Next, a metal vapor deposition film is formed as the back electrode 13 on the p ⁺ collector layer 11 which has been activated. Here, examples of the metal vapor deposition film include vapor deposition films such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer. This vapor deposition is preferably performed by a low temperature sputtering method. The chip formation is performed by cutting the central portion of the separation diffusion layer 2. In FIG. 1, the cut portion is denoted by reference numeral 12.

  FIG. 9 is a cross-sectional view of a semiconductor device (IGBT) 18 in which means for increasing the avalanche resistance of the forward breakdown voltage is added to the IGBT of FIG. The left end of the figure is an end (cut portion) 12 of the IGBT chip cut at the central portion of the separation diffusion layer 2. A contact region 14 of the same conductivity type is formed on the surface layer of the isolation diffusion layer 2, and an auxiliary electrode 15 having the same potential as the collector electrode 13 is in contact with the contact region 14. A breakdown voltage structure 4 is provided between the auxiliary electrode 15 and the surface MOS gate structure 3 of the IGBT. The pressure-resistant structure 4 is preferably provided with a means for increasing the pressure resistance such as a guard ring structure or a field plate structure.

  The surface of the breakdown voltage structure 4 is protected by a field oxide film 16, and an anti-series Zener diode group 17 is provided on the field oxide film 16 and at least one of them is reversely connected. The auxiliary electrode 14 is connected to one end of the series Zener diode group 17 and the other end is connected to the gate electrode G of the IGBT. In this way, by using the IGBT having the anti-series Zener diode 17 for overvoltage protection, the dielectric breakdown of the oxide film 16 is particularly reduced when a high dv / dt voltage required for the IGBT used in the igniter circuit is applied. It can be suppressed and the destruction resistance can be greatly increased. FIG. 9 shows a cross-sectional view of the main part of a reverse blocking FS-IGBT 18 including a Zener diode 17 formed so as to connect between the collector and the gate according to the present invention.

  As a method for improving the avalanche resistance of the IGBT, the diffusion depth of a part of the p base region is increased. However, increasing the diffusion depth affects other characteristics such as on-resistance. Therefore, the existence of the semiconductor device according to the present invention is significant.

  FIG. 2 shows a semiconductor device in which an igniter circuit IC19 is further integrated in the same substrate as the semiconductor substrate on which the reverse blocking FS-IGBT 18 having the Zener diode 17 shown in FIG. 9 is formed.

It is principal part sectional drawing of FS-IGBT for reverse prevention concerning this invention. It is a top view of the semiconductor device with which FS-IGBT for reverse prevention concerning this invention and its control IC were integrated. It is principal part sectional drawing of the conventional reverse blocking IGBT. It is an igniter circuit diagram. It is principal part sectional drawing of the conventional FS-IGBT. It is principal part sectional drawing of the conventional punch through type IGBT. It is principal part sectional drawing of the conventional non-punch through type IGBT. It is principal part sectional drawing of the conventional field stop type IGBT. It is principal part sectional drawing of reverse blocking FS-IGBT provided with the Zener diode group concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, Semiconductor substrate 2, Separation diffused layer 3, MOS gate structure 4, Withstand voltage structure part 5, p base layer 6, n ⁺ emitter layer 7, Gate oxide film 8, Gate electrode 9, Emitter electrode 10, Field stop layer 11, p collector layer 12, cutting portion 13, collector electrode 14, contact portion 15, auxiliary electrode 16, field oxide film 17, Zener diode group 18, reverse blocking FS-IGBT
19. Igniter circuit IC.

Claims (5)

A semiconductor substrate of one conductivity type, an isolation diffusion region of another conductivity type connecting one main surface and the other main surface of the semiconductor substrate, and a MOS gate structure on the one main surface surrounded by the isolation diffusion region and a pressure-resistant structure portion surrounding the MOS gate structure, wherein the whole surface of the isolation diffusion region and the other main surface surrounded by the opposite conductivity type collector region in contact with the separation diffusion region exposed, said collector region An igniter reverse breakdown field stop type semiconductor device comprising a one-conductivity type field stop layer in contact with the semiconductor substrate side, wherein the thickness of the one-conductivity type field stop layer is 10 to 100 of the thickness of the other-conductivity type collector region. The reverse breakdown voltage value of the pn junction formed by the other conductivity type collector region and the one conductivity type field stop layer is the reverse breakdown voltage for the igniter. Field stop type semiconductor device reverse voltage field-stop type semiconductor device for an igniter, characterized in that at least has less than 1/10 1/3 order breakdown voltage values. 2. The reverse breakdown field stop type semiconductor device for an igniter according to claim 1, further comprising a diode connected between the collector region and a gate region constituting the MOS gate structure. 3. The reverse withstand voltage field stop type semiconductor device for an igniter according to claim 2, wherein the diode is a diode deposited on the withstand voltage structure portion in a layered manner with an insulating film interposed therebetween. 4. The reverse breakdown field stop type semiconductor device for an igniter according to claim 2, wherein the diode is a bidirectional diode. 5. The reverse breakdown field stop for igniter according to claim 1, wherein the reverse breakdown field stop type semiconductor device for igniter includes an IC circuit for controlling the semiconductor device on the same semiconductor substrate. Type semiconductor device.

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