JP5194329B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method for an electro-optical device, a driving circuit for the electro-optical device, an electro-optical device, and an electronic apparatus suitable for use in displaying various types of information.
[0002]
[Background]
An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material, is widely used as a display device in place of a cathode ray tube (CRT) in a display unit of various information processing devices, a liquid crystal television, and the like. Here, the conventional electro-optical device is configured as follows, for example. In other words, a conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It is composed of a counter substrate on which counter electrodes facing each other are formed, and a liquid crystal as an electro-optical material filled between the two substrates.
[0003]
In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. In this conductive state, when an image signal having a voltage corresponding to the gradation is applied to the pixel electrode through the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Accumulated. After the charge accumulation, even if the switching element is turned off, the charge accumulation in the liquid crystal layer is maintained by the capacity of the pixel electrode and the counter electrode, the storage capacity, and the like. As described above, when each switching element is driven and the amount of charge to be stored is controlled according to the gradation, the density at which light is modulated and displayed for each pixel changes. Therefore, it is possible to display gradation.
[0004]
At this time, since charges may be accumulated in the electrodes of each pixel during a part of the period for displaying one screen, first, each scanning line is sequentially arranged by the scanning line driving circuit. In the selection period of the scanning line, secondly, the data line is sequentially selected by the data line driving circuit, and thirdly, an image signal having a voltage corresponding to the gradation is sampled on the selected data line. With this configuration, it is possible to perform time-division multiplex driving in which the scanning line and the data line are shared by a plurality of pixels.
[0005]
However, the image signal applied to the data line is a voltage corresponding to the gradation, that is, an analog signal. For this reason, a D / A conversion circuit, an operational amplifier, and the like are required for the peripheral circuit of the electro-optical device, which increases the cost of the entire device. In addition, display unevenness occurs due to the non-uniformity of these D / A conversion circuits, operational amplifiers, and various wiring resistances, so that high-quality display is extremely difficult. This is particularly noticeable when high-definition display is performed. Furthermore, in an electro-optical material such as liquid crystal, the relationship between the applied voltage and the transmittance varies depending on the type of electro-optical material. For this reason, as a drive circuit for driving the electro-optical device, a general-purpose circuit that can handle various electro-optical devices is desired.
[0006]
Due to the circumstances described above, the present applicant has developed a technique for dividing one frame into a plurality of subfields and turning on / off each pixel for each subfield. According to this technique, the applied voltage when a pixel is turned on / off within each subfield is constant regardless of the gradation, and the duty ratio (or voltage effective value) at which the pixel is turned on within one frame. Determines the gradation of the pixel.
[0007]
Here, when the gradation characteristics of the electro-optical device are observed while changing the duty ratio between 0% and 100%, the gradation does not change in the vicinity of the duty ratio of 0% even though the duty ratio is changed. An area exists. Here, the effective voltage value at the point where the gradation characteristic rises is called a threshold voltage Vth. Although the value of the threshold voltage Vth differs depending on the composition of the liquid crystal, it is necessary to provide a subfield that is always set to the ON state in order to give this threshold voltage Vth regardless of the value of the gradation data.
[0008]
Here, when the number of gradations of the required image is 2N, a method of providing 2N + 1 subfields in one frame and a method of providing N + 1 subfields can be considered. In the former method, each subfield period has substantially the same length, but the subfield period is slightly increased or decreased as necessary in order to compensate for the nonlinear characteristic of the electro-optical device. As a result, the former method is advantageous in that it can accurately compensate for the nonlinear characteristics of the electro-optical device.
[0009]
On the other hand, in the latter method, N out of N + 1 subfield periods are associated with each bit of the gradation data. Here, the subfield period associated with 20 digits is the shortest, and the other subfields have a length of about 2M times the shortest subfield length according to the number of digits M of the corresponding bits. Compared with the former method, the latter method is advantageous in that the number of on / off times of pixels in one frame can be reduced and the power consumption can be suppressed low.
[0010]
[Problems to be solved by the invention]
By the way, in the latter method, N-bit data constituting one pixel of gradation data is once written in a memory and used for on / off control of a corresponding subfield. In this memory, writing by the host device and reading by the drive circuit of the electro-optical device can be executed asynchronously and independently. For this reason, in the moving image, a problem arises that a pseudo contour line of a bag that does not exist originally is displayed.
[0011]
One example will be described with reference to FIGS. These figures are examples of images displayed on the electro-optical device. The gradation data is 16 gradations from “0” to “15”, and the normally black mode where the gradation value is “0” is the darkest. An example using the electro-optical device is assumed. First, FIG. 6A shows a gradation value “7” (binary notation) inside a background image 501 having a gradation value “8” (binary notation “1000”) in a certain frame (n-th frame). Is a state in which a rectangular image 502 of “0111” is displayed.
[0012]
If this rectangular image 502 is an image that gradually moves downward, in the next frame (the (n + 1) th frame), the rectangular image 502 is simply moved downward by several lines as shown in FIG. It should be an image that has been moved to. However, when the gradation data in the memory is rewritten in the middle of the (n + 1) th frame, for example, as shown in FIG. In this case, the white contour portion 504 is displayed.
[0013]
The reason for this will be described below. First, since the area corresponding to the white outline 504 is a part of the rectangular image 502 in the nth frame, “111” of the lower 3 bits is used to realize the gradation data “7” (“0111”). Based on, the corresponding subfield is set to the on state. It is assumed that the gradation data of the next (n + 1) th frame is written in the memory when the control by the lower 3 bits is completed. In the (n + 1) th frame, since the region corresponding to the white outline 504 is a part of the background image 501, in order to realize the gradation data “8” (“1000”), it is based on the most significant bit “1”. Thus, the corresponding subfield is set to the on state.
[0014]
Eventually, in this area, a display equivalent to the case where all the subfields are set to the on state is performed based on the highest gradation data “15” (“1111”), and becomes white as illustrated. is there. On the other hand, in the black contour portion 503, since it is a part of the background image 501 in the nth frame and is a part of the rectangular image 502 in the n + 1th frame, the lower 3 bits “000” of the gradation data “8”. ”And the most significant bit“ 0 ”of the gradation data“ 7 ”, all the subfields are turned off.
[0015]
Since the gradation values of the contour portions 503 and 504 are actually different depending on the gradation values of the background image 501 and the rectangular image 502 and the timing at which the memory is rewritten, the rectangular image 502 in the actual moving image. A pseudo contour line blinking in the upper and lower parts of the screen is generated.
The present invention has been made in view of the above-described circumstances, and a driving method of an electro-optical device, a driving circuit of the electro-optical device, an electro-optical device, and an electronic device that can eliminate or reduce image deterioration due to a pseudo contour line. The purpose is to provide equipment.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized by having the following configuration. The parentheses are examples.
According to one aspect of the present invention, a method of driving an electro-optical device divides one frame into a plurality of subfields, and sets a plurality of pixels arranged in a matrix in an on or off state for each subfield. A method of driving an electro-optical device that performs gradation display by the step of storing gradation data of each pixel in a memory (320 to 323), and each of the pixels based on the gradation data stored in the memory The process of setting each pixel to an on or off state for each subfield, and after the on or off state of each pixel is set in the last subfield (SF4) of each subfield (writing period Tr) After), writing is performed so as to allow rewriting of the contents of the memory (320 to 323) within a period until the last subfield (SF4) is completed. The write enable signal (DW) is set (set to H level) and the write enable signal (in order to prohibit rewriting of the contents of the memory (320 to 323) during at least a part of the other subfields. DW) is set (set to L level).
In the electro-optical device driving method, the last subfield may be the longest subfield among the subfields in the one frame.
[0017]
Further, in another aspect of the present invention, the driving method of the electro-optical device (modified example of FIG. 8B) divides one frame into a plurality of subfields, and a plurality of pixels arranged in a matrix form A method of driving an electro-optical device that performs gradation display by setting an on or off state for each subfield, the step of storing gradation data of each pixel in a memory (320 to 323), and the memory And setting each pixel to an on or off state for each subfield based on the gradation data stored in the first frame (nth frame) and the longest first subfield (nth frame). SF4) is started, the process of setting the on or off state of each pixel (writing period Tr), and after the on or off state of each pixel is set, the memory (320 to 323) The process of setting (setting to H level) the write enable signal (DW) so as to allow the rewriting of the contents, and the second frame ( Starting the second subfield (SF0, or the normally off subfield in the modified example) in which the ON or OFF state is determined regardless of the gradation data, at the beginning of the (n + 1th frame), Setting the write enable signal (DW) so as to allow rewriting of the contents of the memories (320 to 323) during the sub-field period, and setting the first and second sub In order to prohibit the rewriting of the contents of the memory (320 to 323) during at least a part of the subfield other than the field, And having a set of enable signal (DW) (to L level) process.
[0018]
In another aspect of the present invention, the driving method of the electro-optical device (modified example of FIG. 9A) divides one frame into a plurality of subfields, and a plurality of pixels arranged in a matrix form. A method of driving an electro-optical device that performs gradation display by setting an on or off state for each subfield, the step of storing gradation data of each pixel in a memory (320 to 323), and the memory A pixel state setting process for setting each pixel to an on or off state for each subfield based on the gradation data stored in the first subfield, and a first sub provided at the end of the frame among the subfields In the first group of subfields (SF4, SF0, SF1) including the field (SF4) and the other second subfield (SF1), the first subfield The contents of the memories (320 to 323) are allowed to be rewritten (the write enable signal DW is set to the H level) except for a period (write period Tr) in which the on or off state of each pixel is set in the memory. The rewriting of the contents of the memories (320 to 323) is prohibited during the process and at least a part of the second group subfields (SF2, SF3) other than the first group subfield (the write enable signal DW is set). And at least one subfield of the second group of subfields (SF2, SF3) is longer than the second subfield (SF1).
In the electro-optical device driving method, the first group of subfields may include a third subfield (SF0) in which an on or off state is determined regardless of gradation data.
[0019]
In another aspect of the present invention, the driving method of the electro-optical device (modified example of FIG. 9B) divides one frame into a plurality of subfields, and a plurality of pixels arranged in a matrix form. A driving method of an electro-optical device that performs gradation display by setting an on or off state for each subfield, wherein the memories (320 to 322, 402, 404) storing gradation data of each pixel In the process of storing the gradation data of each pixel, for the data of the first group subfield (SF4) including at least the first subfield (SF4) provided at the end of the frame, every frame The process of storing the gradation data of each pixel in a memory composed of two blocks (memory blocks 402 and 404) that are alternately written, and the first group In the subfield (SF4) of FIG. 5, in the process of reading the corresponding data from the non-written side block, and in the second group subfield (subfield SF1 to SF3) other than the first group subfield, A process of reading corresponding data from the memory, a pixel state setting process of setting each pixel to an on or off state based on the read data in each subfield of the first and second groups, A period (writing period) in which the ON or OFF state of each pixel is set in a first subfield (SF3) which is a subfield belonging to two groups and is provided immediately before the subfield of the first group is started. A period excluding (Tr) and a subfield (SF4) belonging to the first group. , The process of allowing rewriting of the contents of the memories (320 to 322, 402, 404) (setting the write enable signal DW to H level) and at least a part of the other subfields belonging to the second group And rewriting the contents of the memories (320 to 322, 402, 404) in the period (SF2, SF3) (setting the write enable signal DW to L level).
[0020]
  In addition, the drive circuit of the electro-optical device according to the present invention divides one frame into a plurality of subfields, and sets a plurality of pixels arranged in a matrix in an on or off state for each subfield. A drive circuit for an electro-optical device that performs gray scale display, which stores gradation data of each pixel and a memory (320 to 323) configured of two blocks for at least some subfields. And a data setting circuit (data line driving circuit 140) for setting each pixel to an on or off state for each subfield based on gradation data stored in the memory, and the two blocks. Complementary switching between the block where the gradation data is written and the block where the written gradation data is read out for the memory Characterized by comprising a that switching circuit (406-416).
According to another electro-optical device driving circuit of the present invention, one frame is divided into a plurality of subfields, and a plurality of pixels provided in a matrix are set to an on or off state for each subfield. A drive circuit for an electro-optical device that performs gradation display, the memory storing gradation data of each pixel, and the pixels for each subfield based on the gradation data stored in the memory A data line driving circuit to be set to an on or off state, and a period from when the on or off state of each pixel is set in the last subfield of each of the subfields until the end of the last subfield The memory contents can be rewritten in the memory, and the memory contents cannot be rewritten in at least a part of the other subfields. Characterized by comprising a timing signal generating circuit for generating a write enable signal for the.
According to another electro-optical device driving circuit of the present invention, one frame is divided into a plurality of subfields, and a plurality of pixels provided in a matrix are set to an on or off state for each subfield. A drive circuit for an electro-optical device that performs gradation display, the memory storing gradation data of each pixel, and the pixels for each subfield based on the gradation data stored in the memory A data line driving circuit that is set to an on or off state, and an on or off state of each pixel is set in the longest first subfield of the subframes provided at the end of the first frame. Data for setting the on or off state regardless of the gradation data in the second subfield provided at the beginning of the second frame following the first frame A drive circuit, allowing rewriting of the contents of the memory after the ON or OFF state of each pixel is set in the first subfield and during the second subfield, and A timing signal generation circuit that generates a write enable signal that prohibits rewriting of the contents of the memory during at least a part of a subfield other than the first and second subfields of a second frame. And
According to another electro-optical device driving circuit of the present invention, one frame is divided into a plurality of subfields, and a plurality of pixels provided in a matrix are set to an on or off state for each subfield. A drive circuit for an electro-optical device that performs gradation display, the memory storing gradation data of each pixel, and the pixels for each subfield based on the gradation data stored in the memory A data line driving circuit that is set to an on or off state, and a second sub-field having a first sub-field provided at the end of the first frame and a shortest period of the second frame following the first frame among the sub-fields. In the first group of subfields composed of successive subfields including the subfield, each pixel in the first subfield Except for the period in which the on or off state is set, rewriting of the contents of the memory is allowed, and at least one of the second group subfields other than the first group subfield in the first and second frames. And a timing signal generation circuit for generating a write enable signal for prohibiting rewriting of the contents of the memory during the period of the section.
According to another electro-optical device driving circuit of the present invention, one frame is divided into a plurality of subfields, and a plurality of pixels provided in a matrix are set to an on or off state for each subfield. A driving circuit of an electro-optical device that performs gradation display, and stores gradation data to be written in each pixel in a first subfield provided at the end of a frame, and writing is performed alternately every frame. A first memory composed of two blocks; a second memory for storing gradation data to be written in each pixel in a subfield other than the first subfield in the frame; and a memory immediately before the first subfield. Each pixel is turned on or off based on the gradation data of the second subfield read from the second memory in the second subfield. In the first subfield, each pixel is turned on or off based on the grayscale data of the first subfield read from the block on which data is not written out of the two blocks of the first memory in the first subfield. In a period excluding a data line driving circuit to be set and a period in which the on / off state of each pixel is set in the second subfield, the contents of the second memory are allowed to be rewritten, and the frame of the frame And a timing signal generation circuit that generates a write enable signal that prohibits rewriting of the contents of the second memory in at least a part of the subfield other than the first and second subfields.
  According to another aspect of the present invention, an electro-optical device includes any one of the electro-optical device driving circuits.
  According to another aspect of the present invention, an electronic apparatus includes the electro-optical device.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
1． Configuration of the embodiment
1.1. overall structure
Next, the configuration of the electro-optical device according to the embodiment of the invention will be described with reference to FIG.
In the figure, the timing signal generation circuit 200 is supplied with a vertical synchronizing signal Vs, a horizontal synchronizing signal Hs and a dot clock signal DCLK of input gradation data D0 to D3 from a host device (not shown). Further, the oscillation circuit 150 supplies the basic clock RCLK of the read timing to the timing signal generation circuit 200. The timing signal generation circuit 200 generates various timing signals and clock signals described below according to these signals. First, the AC signal FR is a signal whose polarity is inverted every frame.
[0022]
The drive signal LCOM is a signal applied to the counter electrode of the counter substrate, and has a constant potential (zero potential) in the present embodiment. In the present embodiment, one frame is divided into a plurality of subfields SF0 to SF4, and gradation display is performed by turning on / off pixels for each subfield. The start pulse DY is a pulse signal that is output first in each subfield. The clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). The latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY is changed (that is, rising and falling). The clock signal CLX is a dot clock signal for display.
[0023]
Here, an outline of the subfield driving will be described with reference to the waveform of the start pulse DY in FIG. First, a subfield SF0 is provided at the beginning of the frame. The length of this subfield is set to a length that provides a boundary at which the liquid crystal transmittance rises from the lowest value (in the case of normally black) near 0%, that is, a length that gives a threshold voltage Vth.
[0024]
The subfields SF1 to SF4 are set to lengths having weights corresponding to the respective bits of the input gradation data D0 to D3. That is, the subfield SF1 corresponds to the gradation data D0 that is the least significant bit, and is set to a length that causes a change in transmittance corresponding to the on / off of the gradation data D0 by the on / off thereof. The subfields SF2, SF3, and SF4 are also set to lengths that cause a change in transmittance corresponding to the on / off of the gradation data D1, D2, and D3 depending on the on / off state. That is, the subfields SF2, SF3, and SF4 have lengths that are about twice, four times, and eight times that of the subfield SF1, respectively.
[0025]
Returning to FIG. 1, the timing signal generation circuit 200 outputs a write enable signal DW to a host device (not shown). The write enable signal DW is a signal that permits the host device to supply the input gradation data D0 to D3, that is, to update the memory blocks 320 to 323. The timing chart is shown in FIG. The write enable signal DW is set to the H level in the second half of the subfield SF4 of each frame, and allows the memory blocks 320 to 323 to be updated only within the period of the H level.
[0026]
Returning to FIG. 1, a plurality of scanning lines 112 are formed in the display region 101 a on the element substrate 101 so as to extend in the X (row) direction in the drawing. A plurality of data lines 114 are formed extending along the Y (column) direction. The pixels 110 are provided corresponding to the intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. Here, the total number of scanning lines 112 is m, and the total number of data lines 114 is n (m and n are integers of 2 or more, respectively).
[0027]
1.2. Pixel configuration
As a specific configuration of the pixel 110, for example, the one shown in FIG. In this configuration, the gate of the thin film transistor (TFT) 116 is connected to the scanning line 112, the source is connected to the data line 114, and the drain is connected to the pixel electrode 118, and the electro-optic is provided between the pixel electrode 118 and the counter electrode 108. A liquid crystal layer is formed by sandwiching a liquid crystal 105 as a material. Here, the counter electrode 108 is a transparent electrode formed on one surface of the counter substrate so as to face the pixel electrode 118. In addition, a storage capacitor 119 is formed in parallel with the pixel electrode 118 and the counter electrode 108 to reduce the influence on display due to leakage of charge from the pixel electrode 118. In this embodiment, one potential of the storage capacitor 119 is set to the same potential as the counter electrode 108, but may be set to the same potential as the ground potential GND or the potential of the gate line.
[0028]
Here, in the configuration shown in FIG. 2A, since only one channel type is used as the transistor 116, an offset voltage is required. However, as shown in FIG. If the channel transistor and the N channel transistor are combined in a complementary manner, the influence of the offset voltage can be canceled. However, in this complementary configuration, it is necessary to supply mutually exclusive levels as scanning signals, so two scanning lines 112a and 112b are required for one row of pixels 110.
[0029]
1.3. Scan line driving circuit 130
The description returns to FIG. 1 again. The scanning line driving circuit 130 transfers the start pulse DY supplied at the beginning of the subfield according to the clock signal CLY, and sequentially supplies each of the scanning lines 112 exclusively as the scanning signals G1, G2, G3,. To do.
[0030]
1.4. Data conversion circuit 300
The data conversion circuit 300 converts the input gradation data D0 to D2 input in synchronization with the dot clock signal DCLK into a data signal Ds that is synchronized with the clock signal CLX and outputs the data signal Ds. Here, the detailed configuration of the data conversion circuit 300 will be described with reference to FIG. In the figure, reference numerals 320 to 323 denote memory blocks, which are provided for storing the gradation data D0 to D3, respectively, and are each an m × n bit memory corresponding to the display area (m rows × n columns) of the element substrate 101. Have a space.
[0031]
The memory blocks 320 to 323 are configured so that write and read operations can be executed asynchronously and independently. A write address control unit 310 supplies the write enable signal WE and the write address WAD to the memory blocks 320 to 323 in synchronization with the vertical synchronization signal Vs, the horizontal synchronization signal Hs, and the dot clock signal DCLK.
[0032]
That is, the write address control unit 310 counts up the dot clock signal DCLK, outputs the count result as the write address WAD, and outputs the write enable signal WE every time the value of the write address WAD is determined. The count result in the write address control unit 310 is reset every time the vertical synchronization signal Vs is input. As a result, the memory block 320 to 323 is supplied with the write address WAD for sequentially accessing the m × n-bit memory space, and the gradation data D0 to D3 is set to an address corresponding to the display position of the corresponding memory block. It will be stored sequentially.
[0033]
The display address controller 330 outputs an address signal RAD for accessing the bit data of the corresponding display row when each of the subfield periods is started. The address signal RAD is incremented “n−1” times in accordance with the number of display columns in synchronization with the clock signal CLX. As a result, an address signal RAD for sequentially accessing the bits in the first column to the n-th column for the corresponding display row is output. Further, the read signal RD0 is always enabled during the subfield SF1. However, read signals RD1, RD2, and RD3 are always turned off in subfield SF1. As a result, only the memory block 320 can be read, and the other memory blocks are in a read-inhibited state. Then, the gradation data D0 of the least significant bit of the gradation data in the first column to the n-th column of the corresponding display row is read from the memory block 320.
[0034]
Further, the read signal RD1 is always enabled during the subfield SF2. However, read signals RD0, RD2, and RD3 are always turned off in subfield SF2. As a result, only the memory block 321 is accessed, and the second bit gradation data D1 is read from the lower order of the gradation data. Similarly, read signals RD2 and RD3 are enabled during subfields SF3 and SF4, respectively, and other read signals are turned off. As a result, the memory blocks 322 and 323 are sequentially accessed, and the gradation data D2 and D3 are sequentially read out. Further, when the subfield SF0 is started, the ON signal S_on is fixed to the H level for the period of n cycles of the clock signal CLX. The OR circuit 332 outputs the logical sum of the gradation data D0 to D3 and the ON signal S_on as the data signal Ds.
[0035]
1.5. Data line driving circuit 140
Next, the data line driving circuit 140 sequentially latches n data signals Ds corresponding to the number of data lines 114 in a certain horizontal scanning period, and then latches the n data signals Ds in the next horizontal scanning period. The data signals d1, d2, d3,... Dn are simultaneously supplied to the corresponding data lines 114 via the potential selection circuit 1440. Here, the specific configuration of the data line driving circuit 140 is as shown in FIG. That is, the data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, a second latch circuit 1430, and a potential selection circuit 1440.
[0036]
Among them, the X shift register 1410 transfers the latch pulse LP supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX, and sequentially supplies the latch signals S1, S2, S3,. . Next, the first latch circuit 1420 sequentially latches the data signal Ds at the falling edge of the latch signals S1, S2, S3,..., Sn. Then, the second latch circuit 1430 latches each of the data signals Ds latched by the first latch circuit 1420 at the falling edge of the latch pulse LP, and transfers the data signals Ds to the potential selection circuit 1440.
[0037]
The potential selection circuit 1440 converts these latched binary signals into potentials based on the alternating signal FR and applies them to the data lines 114 as data signals d1, d2, d3,. That is, if the AC signal FR is at the L level, the H level of the data signals d1, d2, d3,... Dn is converted to the potential V1, and the L level is converted to the zero potential. On the other hand, if the alternating signal FR is at the H level, the H level of the data signals d1, d2, d3,... Dn is converted to the potential -V1, and the L level is converted to the zero potential.
[0038]
1.6. Configuration of liquid crystal device
The structure of the above-described electro-optical device will be described with reference to FIGS. 6 (a) and 6 (b). 1A is a plan view showing the configuration of the electro-optical device 100, and FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG. As shown in these drawings, the electro-optical device 100 includes a device substrate 101 on which a pixel electrode 118 and the like are formed and a counter substrate 102 on which a counter electrode 108 and the like are formed with a certain gap between each other by a sealant 104. And a liquid crystal 105 as an electro-optic material is sandwiched between the gaps. Actually, the sealing material 104 has a cut-out portion, and after the liquid crystal 105 is sealed through this, the sealing material 104 is sealed with a sealing material, but is omitted in these drawings. Here, the element substrate 101 and the counter substrate 102 are amorphous substrates such as glass and quartz. The pixel electrode 118 and the like are formed by TFTs formed by depositing a semiconductor film on the element substrate 101. That is, the electro-optical device 100 is used as a transmission type.
[0039]
Now, in the element substrate 101, a light shielding film 106 is provided inside the sealing material 104 and outside the display area 101a. In the region where the light shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 106 prevents light from entering the drive circuit formed in this region. A drive signal LCOM is applied to the light shielding film 106 together with the counter electrode 108. For this reason, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer is almost zero, so that the display state is the same as the voltage non-application state of the pixel electrode 118.
[0040]
In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed, and the sealant 104 is separated, and control signals and power from the outside are formed. And so on. On the other hand, the counter electrode 108 of the counter substrate 102 is electrically connected to the light-shielding film 106 and the connection terminal in the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. Conduction is achieved. That is, the drive signal LCOM is applied to the light shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.
[0041]
In addition, the counter substrate 102 is first provided with a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the electro-optical device 100, for example, if it is a direct view type. Second, a light shielding film (black matrix) made of, for example, a metal material or resin is provided. In the case of use of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of the direct-view type, the electro-optical device 100 is provided with a front light that emits light from the counter substrate 102 side or a backlight that emits light from the element substrate 101 side as necessary. In addition, the electrode formation surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film (not shown) that is rubbed in a predetermined direction to define the alignment direction of the liquid crystal molecules when no voltage is applied. On the other hand, the element substrate 101 and the counter substrate 102 are provided with polarizing plates (not shown) corresponding to the alignment direction. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizer and the like are not required, so that the light utilization efficiency is increased. This is effective in terms of reducing power consumption.
[0042]
2． Operation of the embodiment
Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 7 is a timing chart for explaining the operation of the electro-optical device. First, the alternating signal FR is a signal whose polarity is inverted every frame (1F). On the other hand, the start pulse DY is supplied at the start of each subfield.
[0043]
Here, when the start pulse DY is supplied in one frame (1F) in which the AC signal FR is at the L level, the scanning signal is transferred by the scanning line driving circuit 130 (see FIG. 1) according to the clock signal CLY. G1, G2, G3,..., Gm are sequentially output exclusively in the writing period Tr. Note that the writing period Tr is set to a period equivalent to or shorter than the shortest subfield SF1.
[0044]
The scanning signals G1, G2, G3,..., Gm each have a pulse width corresponding to a half cycle of the clock signal CLY, and the scanning signal G1 corresponding to the first scanning line 112 counted from above is After the start pulse DY is supplied, the clock signal CLY rises for the first time and is output after being delayed by at least a half cycle of the clock signal CLY. Therefore, one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140 after the start pulse DY is supplied and before the scanning signal G1 is output.
[0045]
Consider a case where one shot (G0) of the latch pulse LP is supplied. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, the latch signals S1, S2, and S2 are transferred by the transfer according to the clock signal CLX in the data line driving circuit 140 (see FIG. 4). S3,..., Sn are sequentially output exclusively in the horizontal scanning period (1H). The latch signals S1, S2, S3,..., Sn each have a pulse width corresponding to a half cycle of the clock signal CLX.
[0046]
At this time, the first latch circuit 1420 in FIG. 4 corresponds to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling edge of the latch signal S1. The data signal Ds to the pixel 110 is latched, and then corresponds to the intersection of the first scanning line 112 counted from the top and the second data line 114 counted from the left at the falling edge of the latch signal S2. The data signal Ds to the pixel 110 is latched. Similarly, the data signal to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the nth data line 114 counted from the left is similarly described below. Latch Ds.
[0047]
Thereby, first, the data signal Ds for one row corresponding to the intersection with the first scanning line 112 from the top in FIG. 1 is latched dot-sequentially by the first latch circuit 1420. Needless to say, the data conversion circuit 300 converts the grayscale data D0 to D3 of each pixel into the data signal Ds and outputs it in accordance with the latch timing of the first latch circuit 1420.
[0048]
Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. 1 is selected, and as a result, the pixel corresponding to the intersection with the scanning line 112 is selected. All 110 transistors 116 are turned on. On the other hand, the latch pulse LP is output at the falling edge of the clock signal CLY. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 receives the data signal Ds latched dot-sequentially by the first latch circuit 1420 via the potential selection circuit 1440. The data signals d1, d2, d3,..., Dn are simultaneously supplied to each of the lines 114. Therefore, the data signals d1, d2, d3,..., Dn are simultaneously written in the pixels 110 in the first row counting from the top.
[0049]
In parallel with this writing, the first latch circuit 1420 latches the data signal Ds for one row corresponding to the intersection with the second scanning line 112 from the top in FIG. Thereafter, the same operation is repeated until the scanning signal Gm corresponding to the mth scanning line 112 is output. That is, in one horizontal scanning period (1H) in which a certain scanning signal Gi (i is an integer satisfying 1 ≦ i ≦ m) is output, data for one row of the pixels 110 corresponding to the i-th scanning line 112. The writing of the signals d1, d2, d3,... Dn and the dot sequential latching of the data signal Ds for one row of the pixels 110 corresponding to the (i + 1) th scanning line 112 are performed in parallel. become. Note that the data signal written to the pixel 110 is held until writing in the next subfield.
[0050]
Thereafter, the same operation is repeated every time the start pulse DY that defines the start of the subfield is supplied. However, in the subfield SF0, the level of the data signal Ds is always H level. Furthermore, even when the AC signal FR is inverted to H level after one frame has elapsed, the same operation is repeated in each subfield.
[0051]
Here, as shown in FIG. 8A, in the subfield SF4, the write enable signal DW rises to the H level in the memory update period Tdw1 from the end of the write period Tr to the end of the subfield SF4. Raised. In other periods, the write enable signal DW is set to L level. Therefore, in this memory update period Tdw1, the gradation data in the memory blocks 320 to 323 is updated as appropriate by the host device.
[0052]
Even if the contents of the memory blocks 320 to 323 are updated within the memory update period Tdw1, since the writing to the pixel 110 has already been completed, there is no influence on the display in the frame. From the next frame, normal display is performed based on the updated gradation data. One feature of this embodiment is that a memory update period Tdw1 is provided after the end of the write period Tr of the longest subfield SF4. A relatively long continuous period is avoided while avoiding the write period Tr of each subfield. Can be assigned to the memory update period Tdw1.
[0053]
3． Specific examples of electronic devices
3.1. projector
Next, some examples in which the above-described electro-optical device is used in a specific electronic apparatus will be described.
First, a projector 5400 that is a projection display device using the electro-optical device according to the above-described embodiment as a light valve will be described.
FIG. 10A is a schematic configuration diagram showing a main part of the projection display device. In the drawing, 5431 is a light source, 5442 and 5444 are dichroic mirrors, 5443, 5448 and 5449 are reflection mirrors, 5445 is an entrance lens, 5446 is a relay lens, 5447 is an exit lens, and 100R, 100G and 100B are liquid crystals by the electro-optical device. An optical modulator, 5451 is a cross dichroic prism, and 5437 is a projection lens. The light source 5431 includes a lamp 5440 such as a metal halide and a reflector 5441 that reflects the light of the lamp. The blue light / green light reflecting dichroic mirror 5442 transmits red light out of the light flux from the light source 5431 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 5443 and is incident on the liquid crystal light modulator for red light 100R. On the other hand, of the color light reflected by the dichroic mirror 5442, green light is reflected by the dichroic mirror 5444 that reflects green light and is incident on the liquid crystal light modulator for green light 100G.
[0054]
On the other hand, the blue light also passes through the second dichroic mirror 5444. For blue light, in order to prevent light loss due to a long optical path, a light guide means including a relay lens system including an incident lens 5445, a relay lens 5446, and an output lens 5447 is provided, through which blue light is converted into blue light. Incident on the liquid crystal light modulation device 100B. The three color lights modulated by the respective light modulation devices are incident on the cross dichroic prism 5451. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. These dielectric multilayer films combine the three color lights to form light representing a color image. The combined light is projected onto the screen 5452 by the projection lens 5437 which is a projection optical system, and the image is enlarged and displayed.
[0055]
3.2. Mobile computer
Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 10B is a front view showing the configuration of this personal computer. In the figure, a mobile computer 5200 includes a main body 5204 having a keyboard 5202 and a display unit 5206. The display unit 5206 is configured by adding a backlight behind the electro-optical device 100 described above.
[0056]
3.3. Mobile phone
Further, an example in which the electro-optical device is applied to a mobile phone will be described. FIG.10 (c) is a front view which shows the structure of this mobile telephone. In the figure, a cellular phone 5300 includes the electro-optical device 100 in addition to a plurality of operation buttons 5302 as well as an earpiece 5304 and a mouthpiece 5306. The electro-optical device 100 is also provided with a backlight behind it as necessary.
[0057]
3.4. Other
In addition to the above-described electronic devices, liquid crystal televisions, viewfinder type, monitor direct-view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, Examples include a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.
[0058]
Four. Modified example
The present invention is not limited to the above-described embodiment, and various modifications can be made as follows, for example.
(1) In the embodiment described above, the period excluding the write period Tr of the longest subfield SF4 is the memory update period Tdw1, but as shown in FIG. 8B, the write period of the subfield SF4 The period Tdw2 from the end of Tr to the end of the first subfield SF0 of the next frame may be set as the memory update period, and the write enable signal DW may be set to the H level. Thereby, a longer memory update period can be secured. As described in FIG. 3, in the subfield SF0, the memory blocks 320 to 323 are not read, and the data signal Ds is uniquely determined by the ON signal S_on. Therefore, it is assumed that the memory blocks 320 to 323 are updated within this period. There will be no trouble.
[0059]
(2) If a longer memory update period is necessary, as shown in FIG. 9A, after the writing period Tr of the subfield SF4 ends, the subfield SF1 of the next frame ends. The period Tdw3 may be a memory update period, and the write enable signal DW may be set to H level. In this modification, the data signal Ds for the subfield SF1 of the next frame is not guaranteed, but since the subfield SF1 is the shortest subfield, the pseudo contour can be made almost inconspicuous.
[0060]
(3) If a longer memory update period is required, as shown in FIG. 9B, after the writing period Tr of the subfield SF3 ends, the subfield SF0 of the next frame ends. The period Tdw4 may be a memory update period, and the write enable signal DW may be set to H level. In this modification, in order to guarantee the data signal Ds in the subfield SF4, it is necessary to use a circuit in which the memory is duplicated as shown in FIG. 5 instead of the memory block 323 in FIG.
[0061]
In FIG. 5, reference numerals 402 and 404 denote memory blocks, which are configured in the same manner as the memory blocks 320 to 323. An AND circuit 406 supplies a logical product of the write enable signal WE and the alternating signal FR to the write enable terminal of the memory block 402. Thus, the gradation data D3 is written in the memory block 402 only in a frame in which the AC signal FR becomes H level. Reference numeral 408 denotes an inverter, and reference numeral 410 denotes an AND circuit. The logical product of the inverted signal / FR of the alternating signal FR and the write enable signal WE is supplied to the write enable terminal of the memory block 404. Thus, the gradation data D3 is written in the memory block 404 only in a frame in which the AC signal FR becomes L level.
[0062]
An AND circuit 412 supplies the logical product of the inverted signal / FR and the read signal RD3 to the read enable terminal of the memory block 402. As a result, stored data is read into the memory block 402 only in a frame in which the AC signal FR is at the L level, that is, a frame in which writing is not performed. Similarly, reference numeral 414 denotes an AND circuit that supplies a logical product of the alternating signal FR and the read signal RD3 to the read enable terminal of the memory block 402. As a result, the memory block 402 reads the stored data only in a frame in which the AC signal FR is at the H level, that is, a frame in which writing is not performed.
[0063]
The read results of the memory blocks 402 and 404 are supplied to the OR circuit 332 (see FIG. 3) via the OR circuit 416 as gradation data D3. As described above, in the present modification, frames in which writing and reading of the memory blocks 402 and 404 are permitted are switched in a complementary manner. Therefore, even if the gradation data D3 is written to one of the memory blocks 402 and 404 within or before the writing period Tr of the subfield SF4, it is understood that there is no influence on the data read from the other. .
[0064]
(4) Further, in the modification according to FIG. 5, the memory is duplicated only for the gradation data D3 which is the most significant bit, but the other gradation data D0 to D2 are similarly replaced with the memory blocks 320 to 322. The circuit may be used. When the memory is duplicated for all gradation data, the write enable signal DW can be set to the H level in almost all periods except for a short period during which the AC signal FR is switched.
[0065]
(5) In the above-described embodiment, the on period in which the pixels are always on is provided once in one frame period as the subfield SF0. However, not only the on period but also the off period in which the pixels are always off is included. May be provided. By providing both the on-section and the off-section in this way, the length of the on-section can be adjusted while the length of one frame period is fixed. Further, when the off period is provided adjacent to subfield SF4 or subfield SF0, the off period can be included in the memory update period.
[0066]
(6) In the above embodiment, the drive signal LCOM applied to the counter electrode 108 is zero potential, but the voltage applied to each pixel is shifted depending on the characteristics of the transistor 116, the storage capacitor 119, the capacitance of the liquid crystal, and the like. There is a case. In such a case, the level of the drive signal LCOM applied to the counter electrode 108 may be shifted according to the voltage shift amount.
[0067]
(7) In the above embodiment, the element substrate 101 constituting the electro-optical device is an amorphous substrate such as glass or quartz, and a semiconductor film is deposited on the element substrate 101 to form a TFT to be a transmission type. However, the present invention is not limited to this. For example, a reflective layer is provided on the element substrate 101 or the counter substrate 102, the element substrate 101 is formed of an opaque semiconductor substrate, the dot electrode 118 is formed of a reflective metal such as aluminum, and the counter substrate 102 is formed. When configured from glass or the like, the electro-optical device 100 can be used as a reflection type.
[0068]
(8) Further, although the above embodiment has described an example in which the present invention is applied to an electro-optical device using liquid crystal, other electro-optical devices, in particular, pixels that perform binary display of on or off are used. Thus, the present invention can be applied to all electro-optical devices that perform gradation display. As such an electro-optical device, an electroluminescence device or a plasma display can be considered. In particular, in the case of an organic electroluminescence device, there is no need to perform AC driving as in liquid crystal, and polarity inversion is not necessary.
[0069]
【Effect of the invention】
As described above, according to the present invention, after the ON or OFF state of each pixel is set in the last subfield, the memory contents can be rewritten within the period until the last subfield is completed. Since measures such as this are taken, image degradation due to pseudo contour lines can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.
FIG. 2 is a diagram illustrating a configuration example of a pixel in the embodiment.
FIG. 3 is a block diagram of a data conversion circuit 300 in the embodiment.
4 is a block diagram of a data line driving circuit 140 in the embodiment. FIG.
FIG. 5 is a circuit diagram of a main part of a data conversion circuit 300 in the modification of FIG. 9B.
FIG. 6 is a structural diagram of the electro-optical device in the embodiment.
FIG. 7 is a timing chart of the electro-optical device according to the embodiment.
FIG. 8 is a timing chart of a write enable signal DW in the embodiment and the modification example.
FIG. 9 is a timing chart of a write enable signal DW in another modified example.
FIG. 10 is a diagram illustrating examples of various electronic devices to which the electro-optical device is applied.
FIG. 11 is a diagram for explaining a problem of a conventional technique.
[Explanation of symbols]
100: Electro-optical device
101: Element substrate
101a ... display area
102. Counter substrate
104 ... Sealing material
105 ... Liquid crystal
106: light shielding film
107 ... area
108 ... Counter electrode
110 ... pixel
112 ... Scanning line
114 ... data line
116: Thin film transistor
118: Pixel electrode
119 ... Storage capacity
130: Scanning line driving circuit
140: Data line driving circuit (data setting circuit)
150: Oscillator circuit
200: Timing signal generation circuit
300: Data conversion circuit
310: Write address control unit
320 to 323 ... memory block
330: Display address control unit
332: OR circuit
402, 404 ... memory block
406 ... AND circuit (switching circuit)
408 ... Inverter (switching circuit)
410: AND circuit (switching circuit)
412 ... AND circuit (switching circuit)
414 ... AND circuit (switching circuit)
416: OR circuit (switching circuit)
501 ... Background image
502 ... rectangular image
503 ... Black contour
504 ... White contour

Claims (8)

A drive circuit for an electro-optical device that performs gradation display by dividing one frame into a plurality of subfields and setting a plurality of pixels provided in a matrix in an on or off state for each subfield,
A memory for storing gradation data of each pixel;
A data line driving circuit for setting each pixel to an on or off state for each subfield based on gradation data stored in the memory;
After the on / off state of each pixel is set in the last subfield among the subfields, the memory contents can be rewritten within a period until the last subfield is completed, A timing signal generation circuit for generating a write enable signal for prohibiting rewriting of the contents of the memory in at least a part of a period of another subfield;
An electro-optical device driving circuit comprising:   2. The electro-optical device driving circuit according to claim 1, wherein the last subfield is a subfield having the longest period among the subfields in the one frame. A drive circuit for an electro-optical device that performs gradation display by dividing one frame into a plurality of subfields and setting a plurality of pixels provided in a matrix in an on or off state for each subfield,
A memory for storing gradation data of each pixel;
A data line driving circuit for setting each pixel to an on or off state for each subfield based on gradation data stored in the memory;
The on / off state of each pixel is set in the longest first subfield of the first frame provided at the end of the first frame, and the first of the second frame following the first frame is set. set the regardless oN or oFF state to the gradation data in a second subfield provided in front Symbol before Symbol after on or off state of each pixel is set within the first subfield a rewriting the contents of the previous SL memory in the duration of the second subfield is allowable, the memory at least part of the period of a subfield other than the first and second sub-fields of the first and second frame A timing signal generation circuit for generating a write enable signal for prohibiting rewriting of the contents of
A drive circuit for an electro-optical device, comprising: A drive circuit for an electro-optical device that performs gradation display by dividing one frame into a plurality of subfields and setting a plurality of pixels provided in a matrix in an on or off state for each subfield,
A memory for storing gradation data of each pixel;
A data line driving circuit for setting each pixel to an on or off state for each subfield based on gradation data stored in the memory;
Of each of the subfields, a first subfield provided at the end of the first frame and a second subfield including a second subfield having the shortest period of the second frame following the first frame are provided. In one group of subfields, the contents of the memory are allowed to be rewritten except for a period during which the on / off state of each pixel is set in the first subfield, and the first and second frames A timing signal generation circuit for generating a write enable signal for prohibiting rewriting of the contents of the memory in a period of at least a part of a subfield of the second group other than the subfield of the first group in
A drive circuit for an electro-optical device, comprising:   5. The drive circuit of an electro-optical device according to claim 4, wherein the first group of subfields includes a third subfield in which an on or off state is determined regardless of gradation data. A drive circuit for an electro-optical device that performs gradation display by dividing one frame into a plurality of subfields and setting a plurality of pixels provided in a matrix in an on or off state for each subfield,
A first memory comprising two blocks in which gradation data to be written to each pixel is stored in a first subfield provided at the end of a frame, and writing is performed alternately every frame;
A second memory for storing gradation data written to each pixel in a subfield other than the first subfield in the frame;
In the second subfield immediately before the first subfield, each pixel is set to an on or off state based on the grayscale data of the second subfield read from the second memory. In the first subfield, A data line driving circuit for setting each of the pixels to an on or off state based on the gradation data of the first subfield read from a block on which data is not written out of the two blocks of the first memory;
In the second subfield, the contents of the second memory are allowed to be rewritten in a period excluding a period in which the on / off state of each pixel is set, and other than the first and second subfields of the frame. A timing signal generation circuit for generating a write enable signal for prohibiting rewriting of the contents of the second memory in at least a part of the subfield of
A drive circuit for an electro-optical device, comprising:   An electro-optical device comprising the drive circuit for the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 7.

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